22 Lucent Technologies Inc.
Data Sheet
March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Functional Description
Four channels of PCM data input and output are
passed through only two ports, D
X
and D
R
, so some
type of time-slot assignment is necessary. The scheme
used here is to utilize timing modes of 32 or 64 time
slots corresponding to master clock frequencies of
either 2.048 MHz or 4.096 MHz, respectively. Each
device has four transmit frame sync (FS
X
) inputs, one
for each channel. During a single 125
µ
s frame, each
transmit frame sync input is supplied a single pulse.
The timing of the pulse indicates the beginning of the
time slot during which the data for that channel is
clocked out of the device. During a frame, transmit
frame sync pulses must be separated from each other
by one or more time slots. A channel is placed in a
standby (lo w-power) mode if its FS
X
input has been low
for 500
µ
s.
There is a single frame sync separation input (FSEP).
The number of negative clock edges minus one that
occurs while FSEP is high is the delay (in clock
periods) that is placed between the rising edge of a
transmit frame sign bit and the falling edge used by the
receiver to sample the sign bit. There must alw a ys be a
pulse on the FSEP input since this input provides the
8 kHz signal required to maintain internal timing. If the
FSEP pulse is one clock period or less, the device
makes the tr ansmit edges and receive sampling edges
one half clock period apart. The entire device is placed
in a powerdown mode if FSEP remains low for 500
µ
s.
Time slot zero is defined as starting on the first rising
MCLK edge after FSEP = 1 is detected by a negative
MCLK edge. In the T7504, MCLK negative-going
edges that detect the start of FSEP and FS
X
N must be
integer multiples of eight MCLK periods apart (zero
multiples are allowed). Since FSEP is assumed to
define time slot 0, the number of multiples separating
FS
X
N and FSEP is the time-slot number. In the T5504,
FS
X
N for time slot 0 nominally starts on the MCLK
positive edge following the negative edge which
detects FSEP.
The frequency of the master clock must be either
2.048 MHz or 4.096 MHz. Internal circuitry determines
the master clock frequency during the powerup reset
interval.
Powerdown is not guaranteed if MCLK is lost unless
the device is already in the powerdown mode due to
FSEP low for at least 500
µ
s.
The analog input section in Figure 2 includes an on-
chip op amp that is used in conjunction with external,
user-supplied resistors to vary encoder passband gain.
The f eedback resistance (R
F
) should range from 10 k
Ω
to 200 k
Ω
and capacitance from GSx to ground should
be kept to less than 50 pF. The input signal at VF
X
IN
should be ac coupled. For best performance, the maxi-
mum gain of this op amp should be limited to 20 dB or
less.
5-3786
Figure 2. Typical Analog Input Section
VF
X
IN TO
CODEC
FILTERS
2.4 V
GAIN= R
X
GS
X
R
I
R
F
–
+
R
I