Document No. 70-0289-05 │www.psemi.com
Page 1 of 10
©2009-2010 Peregrine Semiconductor Corp. All rights reserved.
RF1 RF2
CTRLLS
RFC
50Ω50ΩCMOS
Control
Driver
ESD ESD
The PE42556 RF Switch is designed for use in Test/ATE,
cellular and other wireless applications. This broadband general
purpose switch maintains excellent RF performance and
linearity from 9kHz through 13500 MHz. The PE42556
integrates on-board CMOS control logic driven by a single-pin,
low voltage CMOS control input. It also has a logic select pin
which enables changing the logic definition of the control pin.
Additional features include a novel user defined logic table,
enabled by the on-board CMOS circuitry. The PE42556 also
exhibits excellent isolation of 26 dB at 13500 MHz, fast settling
time, and is offered in a tiny Flip Chip package.
The PE42556 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance of
GaAs with the economy and integration of conventional CMOS.
Product Specification
SPDT UltraCMOS™ RF Switch
9 kHz - 13500 MHz
Product Description
Figure 1. Functional Diagram
PE42556 Flip Chip
Features
• HaRP™-Technology-Enhanced
• Eliminates Gate Lag
• No insertion loss or phase drift
• Fast settling time
• Next Gen 0.25 µm Process Technology
• Single-pin 3.3 V CMOS logic control
• High Isolation: 26 dB@ 13.5 GHz
• Low Insertion Loss: 1.7 dB @ 13.5 GHz
• P1dB: 33 dBm typical
• Return Loss: 13 dB @ 13.5 GHz (typ)
• IIP3: +56 dBm typical
• Exceptional ESD: 4000 V HBM
• Absorptive Switch Design
• Flip Chip packaging
Figure 2. Die Photo (Bumps Up)
Flip Chip Packaging
Product Specification
PE42556
Page 2 of 10
©2009-2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0289-05 │ UltraCMOS™ RFIC Solutions
Table 1. Electrical Specifications: Temp = 25°C, VDD = 3.3V
Parameter Conditions
Min Typical Max Units
Operation Frequency 9 kHz 13500
MHz As shown
Insertion Loss
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
0.85
0.92
0.98
1.07
1.74
0.93
1.06
1.23
1.41
2.65
dB
dB
dB
dB
dB
Isolation – RF1 to RF2
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
76.5
43.5
30.0
24.0
15.5
88.5
46.0
31.5
25.5
17.5
dB
dB
dB
dB
dB
Return Loss
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
22.5
22.0
17.0
16.0
13.0
dB
dB
dB
dB
dB
Switching Time 50% CTRL to 90% or 10% of final value (-40 to +85 °C) 3.3 4.0 µs
Input 1 dB
Compression 1,2 13500 MHz 33 dBm
Input IP3 1 13500 MHz 56 dBm
Isolation – RFC to RF1
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
72.5
39.0
31.5
27.0
21.5
84.0
40.5
33.0
30.5
26.5
dB
dB
dB
dB
dB
Isolation – RFC to RF2
9 kHz - 10 MHz
10 - 3000 MHz
3000 - 7500 MHz
7500 - 10000 MHz
10000 - 13500 MHz
75.5
39.5
31.5
27.5
21.0
87.0
41.0
33.0
30.5
26.0
dB
dB
dB
dB
dB
Settling Time 50% CTRL to 0.05 dB final value (-40 to +85 °C) Rising Edge
50% CTRL to 0.05 dB final value (-40 to +85 °C) Falling Edge 8.5
9.5 10.0
13.5 µs
µs
Input IP2 1 13500 MHz 107.5 dBm
Note: 1. Linearity and power performance are derated at lower frequencies (< 1 MHz)
2. Please refer to Maximum Operating Pin (50Ω) in Table 3
Product Specification
PE42556
Page 3 of 10
Document No. 70-0289-05 │www.psemi.com ©2009-2010 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Bump Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this de vice contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Figure 3. Bump Configuration (Bumps Up)
Bump
No. Bump
Name Description
1 VSS Negative supply voltage or GND
connection (Note 3)
2, 13, 14 D-GND Digital Ground
3, 5, 7, 9 GND Ground
4 RF2 RF Port 2
6 RFC RF Common
8 RF1 RF Port 1
10 LS
Logic Select - Used to determine the
definition for the CTRL pin (see Table 5)
11 VDD Nominal 3.3 V supply connection
12 CTRL CMOS logic level
Table 5. Control Logic Truth Table
Exceeding absolut e maximum ratings m ay cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Table 3. Operating Ranges
Note: 5. Please consult Figures 4 and 5 (low-frequency graphs) for
recommended low-frequency operating power level.
6. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
Note: 3. Use VSS (bump 1, VSS = -VDD) to bypass and disable
internal negative voltage generator. Connect VSS (bump 1) to GND
(VSS = 0V) to enable internal negative voltage generator.
LS CTRL RFC-RF1 RFC-RF2
0 0 off on
0 1 on off
1 0 on off
1 1 off on
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input except
for CTRL and LS inputs -0.3 VDD+
0.3 V
VCTRL Voltage on CTRL input 4.0 V
VLS Voltage on LS input 4.0 V
TST Storage temperature range -65 150 °C
TOP Operating temperature range -40 85 °C
PIN5 (50Ω) 9 kHz ≤ 1 MHz
1 MHz ≤ 13.5 GHz fig. 4,5
30 dBm
dBm
VESD ESD voltage (HBM)6
ESD voltage (Machine Model) 4000
300 V
V
Parameter Min Typ Max Units
VDD Positive Power Supply
Voltage 3.0 3.3 3.6 V
VDD Negative Power Supply
Voltage -3.6 -3.3 -3.0 V
IDD Power Supply Current
(Vss = -3.3V, VDD = 3.0 to
3.6V, -40 to +85 °C) 8.0 12.5 µA
Control Voltage High 0.7xVDD V
Control Voltage Low 0.3xVDD V
PIN RF Power In4 (50Ω):
9 kHz ≤ 1 MHz
1 MHz ≤ 13.5 GHz
fig. 4,5
30
dBm
dBm
IDD Power Supply Current
(Vss = 0V, VDD = 3.0 to 3.6V,
-40 to +85 °C) 21.5 29.0 µA
ISS Negative Power Supply
Current
(Vss = -3.3V, VDD = 3.0 to
3.6V, -40 to +85 °C)
-18.0 -24.0 µA
Vdd Vss
GND
CTRL
LS
RF1 RF2
RFC
D-GND D- GND
DG ND GND
GND GND
1
2
3
4
5
11
10
9
8
7
12
13
14
6
Flip Chip Packaging
Switching Frequency
The PE42556 has a maximum 25 kHz switching rate
when the internal negative voltage gen erator is used
(bump1=GND). The rate at which the PE42556 can be
switched is only limited to the switching time (Table 1) if
an external negative supply is provided (bump1=VSS).
Spurious Performance
The typical spurious performance of the PE42556 is
-116 dBm when VSS=0V (bump 1 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
Note: 4. Please consult Figures 4 and 5 (low-frequency graphs) for
recommended low-frequency operating power level.
Product Specification
PE42556
Page 4 of 10
©2009-2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0289-05 │ UltraCMOS™ RFIC Solutions
Power Handling Scaling with Frequency
0
5
10
15
20
25
30
1 10 100 1000
Freq (kHz)
Operating Power Offset (dB)
-12
-10
-8
-6
-4
-2
0
2
4
6
8
2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Vdd (V)
Input Power (dBm)
Upper Power Limit
Figure 5 shows how the power limit in Figure 4 will
increase with frequency. As the frequency
increases, the contours and Maximum Power
Limit Curve will increase with the increase in
power handling shown on the curve.
Figure 4. Maximum Operating Power Limit
vs. Vdd and Input Power @ 9 KHz Figure 5. Operating Power Offset vs.
Frequency (Normalized to 9kHz)
Figure 4 provides guidelines of how to adjust the
Vdd and Input Power to the PE42556 device. The
upper limit curve represents the maximum Input
Power vs Vdd recommended for this part at low
frequencies only. Please consult Table 3 for the
1 MHz ≤ 13.5 GHz range.
To allow for sustained operation under any load VSWR condition,
max power should be kept 6dB lower than max power in 50 Ohm. Power Handling Examples
Example 1: Maximum power handling at 100 kHz,
Z=50 ohms, VSWR 1:1, and Vdd=3V
• The power handling offset for 100 kHz from
Fig. 5 is 7 dB
• The max power handling at Vdd = 3 V is 5.5
dB from Fig. 4
• Derate power under mismatch conditions
• Total maximum power handling for this
example is 7 dB + 5.5 dB = 12.5 dBm
Low Frequency Power Handling: ZL = 50Ω
Product Specification
PE42556
Page 5 of 10
Document No. 70-0289-05 │www.psemi.com ©2009-2010 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit Figure 6. Evaluation Board Layouts
Peregrine Specification 101/0402
Figure 7. Evaluation Board Schematic
Peregrine Specification 102/0478
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine's PE42556 (dual
use with PE42554). The RF Common port is
connected through a 50ohm transmission line via
the top SMA connector, J1. RF1 and RF2 are
connected through 50ohm transmission lines via
SMA connectors J3, and J2, respectively. A
through 50ohm transmission line is available via
SMA connectors J4 and J5. This transmission
line can be used to estimate the loss of the PCB
over the environmental conditions being
evaluated.
The board is constructed of a four metal layers
with a total thickness of 62 mils. The top and
bottom layers are ROGERS RO4003 material with
an 8 mil core and Er=3.55. The middle layers
provide ground for the transmission lines. The RF
transmission lines were designed using a coplanar
waveguide with ground plane model using a trace
width of 15 mils, and trace gaps of 10 mils.
X
General Comments
--
Transmission lines connected to J1, J2, and J3 should
have exactly the same electrical length.
J4 to J5.
NOTES:
1. USE 101-0402-02 PCB
should have the same length as J4 and J5 and be in parallel to
The path from J2 to J3 including the distance through the part
6RFC
8
RF1
4
RF2
10
LS
11
VDD
12
CTL
1
VSS
2G0
14 G7
13 G6
9G5
7G4
5G2
3G1
U1
PE42554
1CTL
3LS
5NC
7VDD
2
GND
4
GND
6
GND
8
GND
9VSS
11 GND
10
GND
12
GND
J9
HEADER, 12 PIN
1
2
J3
1
2
J2
1
2
J5
1
2
J4
1
2
J1
Product Specification
PE42556
Page 6 of 10
©2009-2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0289-05 │ UltraCMOS™ RFIC Solutions
Figure 11. Isolation: Active Port to
Isolated Port @ 3.3 V
Figure 10. Insertion Loss: RFX @ 25 °C
Figure 8. Nominal Insertion Loss: RF1, RF2 Figure 9. Insertion Loss: RFX @ 3.3 V
Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated
Figure 12. Isolation: Active Port to
Isolated Port @ 25 °C Figure 13. Isolation: RFC to
Isolated Port @ 3.3 V
Product Specification
PE42556
Page 7 of 10
Document No. 70-0289-05 │www.psemi.com ©2009-2010 Peregrine Semiconductor Corp. All rights reserved.
IIP3: Third Order Distortion from 9kHz - 14 GHz
0
10
20
30
40
50
60
70
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
100.0E+9
Frequency [Hz]
Linearity [dBm]
Nominal Perf ormance
Figure 17. IIP3: Third Order Distortion from
9kHz - 14GHz
Figure 16. Return Loss at active port @ 25 °C
Figure 14. Isolation: RFC to
Isolated Port @ 25 °C Figure 15. Return Loss at active port @ 3.3 V
Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated
Product Specification
PE42556
Page 8 of 10
©2009-2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0289-05 │ UltraCMOS™ RFIC Solutions
Figure 18. Pad Layout (Bumps Up)
Vdd Vss
GND
CTRL
LS
RF1
RF2
RFC
D-GND
D-GND
DGND
GND
GND
GND
Singulated Die size: 1.1 X 2.0 mm (400um ball pitch)
Table 6. Mechanical Specifications
Parameter Minimum Typical Maximum Units Test Conditions
Die Size, Drawn (x,y) 996 x 1896 µm As drawn
Die Size, Singulated (x,y) 1080 x 1980 1100 x 2000 1150 x 2050 µm Including excess sapphire, max. tolerance
= -20/+50 µm
Wafer Thickness 180 200 220 µm
Wafer Size 150 mm
Ball Pitch 400 µm
Ball Height 72.25 85 97.75 µm
Ball Diameter 110 µm Typical
UBM Diameter 85 90 95 µm
Table 7. Bump Coordinates
Bump # Bump Name Bump Center (µm)
X Y
1 VSS 400 850
2 DGND 400 450
3 GND4 400 50
4 RF2 400 -350
5 GND3 400 -750
6 RFC 0 -750
7 GND1 -400 -750
8 RF1 -400 -350
9 GND2 -400 50
10 LS -400 450
11 VDD -400 850
12 CTRL 0 850
13 DGND 0 450
14 DGND 0 50
1
2
3
4
5
11
10
9
8
7
12
13
14
6
All bump locations originate from the die center and refer to the
center of the bump.
Ball pitch is 400 µm.
2000 µm
-20/+50 µm
1100 µm
-20/+50 µm
RoHS compliant lead-free solder balls
• Solder ball composition: 95.5%Sn/3.5%Ag/ 1.0%Cu
Product Specification
PE42556
Page 9 of 10
Document No. 70-0289-05 │www.psemi.com ©2009-2010 Peregrine Semiconductor Corp. All rights reserved.
Table 8. Ordering Information
LOGO
Pin
#1
4.00 ± .05
(.157 ± .002)
4.00 ± .05
(.157 ± .002)
1.50 + .10
(.059 + .004) 2.00 ± .05
(.079 ±.002)
3.50 ± .05
(.138 ± .002)
8.00 +.30 -.10
(.315 +.012 - .004)
1.75 ± .10
(.069 ± .004)
Bump 1
Drawing not drawn to scale, Pocket hole diameter 0.6±0.05mm
.229 ± .02
(.009 ± .0008)
Ao 1.2 ± .05
(.047 ± .002)
.45 ± .05
(.018 ± .002)
2.1± .05
(.083 ± .002) AO = 1.2
BO = 2.1
KO = 0.45
KO
Bo
Note: Bumped die are oriented active si de down
Maximum cavity angle 5o
Tape Feed Direction
Figure 19. Tape and Reel Specifications
Device Orientation in Tape
bump
side
down
Bump 1
Order Code Package Specification Shipping Method
PE42556DI Die on cut Tape and Reel 81-0012 Loose or cut tape
PE42556DI-Z Die on full Tape and Reel 81-0012 1,000 Dice / Reel
EK42556-01 Evaluation Kit 1/ box
PE42556DBI Die in waffle pack 81-0015 204 Dice / Waffle pack
Product Specification
PE42556
Page 10 of 10
©2009-2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0289-05 │ UltraCMOS™ RFIC Solutions
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The Americas
Peregrine Semiconductor Corporation
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
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Bâtiment Maine
13-15 rue des Quatre Vents
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Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preli m inary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a CNF
(Customer Notification Form).
The information in this data sheet is beli eved to be reliable.
However, Peregrine assumes no li ability for the use of this
information. Use shall be entirely at the user ’s own risk.
No patent rights or licenses to any circuits describe d in this
data sheet are implied or gran ted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to supp ort or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no li ability for damages, including
consequential or incidental da mages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
High-Reliability and Defense Products
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
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