1 of 2 August 13, 2009
2008 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Device Overview
The IDT Tsi384 is a high-performance bus bridge that connects the
PCI Express (PCIe) protocol to the PCI and PCI-X bus standards.
The Tsi384’s PCIe Interface has superior performance and supports
1, 2, or 4 lanes. This enables the bridge to offer exceptional throughput
performance of up to 1 GBps.
The device’s PCI/X Interface can operate up to 133 MHz in PCI-X
mode, or up to 66 MHz in PCI mode. This interface offers designers
extensive flexibility by supporting three types of addressing modes:
transparent, opaque, and non-transparent.
Low Power Consumption
The Tsi384 has typical power consumption of 1.3W, and incorporates
advanced power management to minimize power consumption during
operation. In addition to supporting D0, D3 hot, and D3 cold power
management modes, the device permits unused PCIe lanes to be
powered off automatically or by configuration.
Tr ansparent, Non-transparent, and Opaque
Bridging
Transparent mode operation is available for efficient, flow-through
configurations, while non-transparent bridging allows isolation between
the Tsi384’s PCIe and the PCI/X domains. Non-transparent bridging also
enables multi-host systems and is used in applications such as storage
adapters. Opaque mode provides semi-transparent operation for multi-
processor configurations and enhanced private device support.
High Performance
The Tsi384 incorporates many advanced PCIe protocols that
increase system performance, including: Lane Reversal and Polarity
Inversion, end-to-end CRC, ASPM L0 link state power management,
and Hot Plug. In addition to low-latency operation, the device supports a
maximum payload size of up to 512 bytes to allow better throughput effi-
ciency.
Figure 1 Tsi384 Block Diagram
Features
•General
–PCI Express to PCI/PCI-X Forward bridge
–Transparent, Non-transparent, and Opaque modes
–Low latency – Superior queuing and buffering architecture
maximize throughput and minimize latency
–Compliant with the following specifications:
• PCI Express Base 1.1
• PCI Express PCI/PCI-X Bridge 1.0
• PCI-to-PCI Bridge Architecture 1.2
• PCI Local Bus 3.0
• PCI-X 2.0 (mode 1 only)
• PCI Bus Power Management Interface 1.2
PCI/X
Arbiter
Error
Handling
Interrupt
Handling
Clocking/
Reset EEPROM
Controller
Power
Mgmt
JTAG
PCI/X Interface
PCIe Interface (x4)
80E1000_BK001_01 (Tsi384)
Posted
Writer
Buffer
Posted
Queue
Mux Logic
Non-
Posted
Buffer
Non-
Posted
Queue
DownstreamDownstream
UpstreamUpstream
Posted
Writer
Buffer
Posted
Queue
Mux Logic
Non-
Posted
Buffer
Non-
Posted
Queue
Config
Registers
Tsi384™ PCIe® to PCI/X Bridge
Product Brief
Tsi384 Evaluation Board Prod uct Brief
2 of 2 August 13, 2009
August 16, 2004August 16, 200
NOT AN OFFER FOR SALE
The information presented herein is subject to a Non-Disclosure Agreement and is for planning purposes only. Nothing contained in this presenta-
tion, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
CORPORATE HE ADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
document: 80E1000_FB001_07
®
•PCI Express
–Configurable as 1, 2, or 4 lanes
–512-byte maximum payload
–Advanced error reporting capability
–Supports Lane Reversal and Lane Polarity Inversion
–End-to-end CRC check and generation
–Up to four outstanding memory reads
–ASPM L0s link state power management
–Legacy interrupt signaling and MSI interrupts
–Hot Plug support
•PCI/PCI-X
–32/64-bit addressing
–32/64-bit data
–PCI-X operation at 50, 66, 100, and 133 MHz
–PCI operation at 25, 33, 50, and 66 MHz
–Up to eight outstanding memory reads
–4K read completion buffer
–Four external PCI/X masters supported through internal
arbiter
–Support for external arbiter
•Other
–Support for Masquerade mode
–JTAG IEEE 1149.1, 1149.6
–Support for D0, D3 hot, D3 cold power management states
–1.2V core power supply
–1.3W typical power consumption (x4 PCIe to 133-MHz PCI-X)
–Packaged in 17x17 mm, 256-pin PBGA
–Package pinout and footprint compatible with PLX8114
compatible with PLX8114
Benefits
–Enhances system performance by delivering high throughput
and low latency across bus interfaces
–Simplifies system design by offering numerous programmable
features
–Minimizes system power consumption by providing compre-
hensive power management
Typical Applications
The Tsi384 is suited to applications that need to bridge from PCIe to
downstream PCI-X and PCI devices. Its flexibility, high performance,
small footprint, and low power consumption, make it ideal for a wide
range of applications, including:
•Storage Area Network (SAN, RAID HBA cards)
•Network Attached Storage, Direct Attached Storage (NAS, DAS)
•Line cards and NICs
•Routers and switches
•Motherboards (server, SBC, industrial PC)
•PC adapter cards (communications, graphics, imaging, and
multimedia)
•Multi-function printers
•Digital video recorders
Figure 2 HBA Card Application
80E1000_TA001_01
PCI-X 133 MHz
PCI-X 133 MHz
PCIe x4
Tsi384
GbE/FC
Controller
GbE/FC
Controller
