March 2012 I
© 2012 Microsemi Corporation
ProASIC3E Flash Family FPGAs
with Optional Sof t ARM Support
Features and Benefits
High Capacity
600 k to 3 Million System Gates
108 to 5 04 kb its of True Dual-Por t SRAM
Up to 620 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
1 kbit of FlashROM with Synchronous Interfacing
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock® Designed to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-S peed, Very-Long-Line Network
High-Per f or ma nce , Lo w-Sk ew Gl oba l Net wor k
Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-V oltage Operation
Bank-Selectable I/O V oltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Cla ss I and II, SSTL3
Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold S p aring I/Os
Programmable Output Slew Rate and Drive S trength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/- Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Comp a tib l e Pack age s ac ro ss t he Pro ASIC ®3E Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, Each with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
Wide Input Frequency Range (1.5 MHz to 200 MHz)
SRAMs and FIFOs
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
T rue Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous Operation
up to 350 MHz
ARM® Processor Support in ProASIC3E FPGAs
M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
with or without Debug
Table 1-1 • Pro ASIC3E Product Family
ProASIC3E Devices A3PE600 A3PE1500 A3PE3000
Cortex-M1 Devices 1M1A3PE1500 M1A3PE3000
System Gates 600,000 1,500,000 3,000,000
VersaTiles (D-flip-flops) 13,824 38,400 75,264
RAM Kbits (1,024 bits) 108 270 504
4,608-Bit Blocks 24 60 112
FlashROM Kbits 11 1
Secure (AES) ISP Yes Yes Yes
CCCs with Integrated PLLs266 6
VersaNet Globals318 18 18
I/O Banks 88 8
Maximum User I/Os 270 444 620
Package Pins
PQFP
FBGA PQ208
FG256, FG484 PQ208
FG484, FG676 PQ208
FG324, FG484, FG896
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. The PQ208 package supports six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet.
Revision 10
ProASIC3E Flash Family FPGAs
II Revision 10
I/Os Per Package1
ProASIC3E Device Status
ProASIC3E Devices A3PE600 A3PE1500 3A3PE3000 3
Cortex-M1 Devices 2M1A3PE1500 M1A3PE3000
Package
I/O Types
Single-Ended I/O1
Differential I/O Pairs
Single-Ended I/O1
Differential I/O Pairs
Single-Ended I/O1
Differential I/O Pairs
PQ208 147 65 147 65 147 65
FG256 16579––––
FG324 ––––221110
FG484 270 135 280 139 341 168
FG676 444 222
FG896 ––––620310
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E FPGA Fabric Users
Guide to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per no rth or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per
minibank (group of I/Os).
6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Orderi ng Information" on page III for the location of the "G"
in the part number.
Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensio ns
Package PQ208 FG256 FG324 FG484 FG676 FG896
Length × Width (mm\mm) 28 × 28 17 × 17 19 × 19 23 × 23 27 × 27 31 × 31
Nominal Area (mm2)784 289 361 529 729 961
Pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0
Height (mm) 3.40 1.60 1.63 2.23 2.23 2.23
ProASIC3E Devices Status M1 ProASIC3E Devices Status
A3PE600 Production
A3PE1500 Production M1A3PE1500 Production
A3PE3000 Production M1A3PE3000 Production
ProASIC3E Flash Family FPGAs
Revision 10 III
ProASIC3E Ordering Information
A3PE3000 FG
_
Part Number
Speed Grade
1
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Package Type
PQ =Plastic Quad Flat Pack (0.5 mm pitch)
FG =Fine Pitch Ball Grid Array (1.0 mm pitch)
896 I
Y
Package Lead Count
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
600,000 System Gates
A3PE600 =
1,500,000 System Gates
A3PE1500 =
3,000,000 System Gates
A3PE3000 =
1,500,000 System Gates
M1A3PE1500 =
3,000,000 System Gates
M1A3PE3000 =
G
Lead-Free Packaging
Blank =Standard Packaging
G =RoHS-Compliant (Green) Packaging
ProASIC3E Devices
ProASIC3E Devices with Cortex-M1
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
ProASIC3E Flash Family FPGAs
IV Revision 10
Temperature Grade Offerings
Speed Grade and Temperature Grade Matrix
References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi SoC Products Group representative for devi c e availability:
http://www.microsemi.com/soc/contact/default.aspx.
Package A3PE600 A3PE1500 A3PE3000
Cortex-M1 Devices M1A3PE1500 M1A3PE3000
PQ208 C, I C, I C, I
FG256 C, I
FG324 C, I
FG484 C, I C, I C, I
FG676 C, I
FG896 C, I
Note: C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Temperature Gr ade Std. –1 –2
C1333
I2333
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
ProASIC3E Flash Family FPGAs
Revision 10 V
Table of Content s
ProASIC3E Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3E DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Package Pin Assignments
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Safety Critical, Life Support, and High -R eliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Revision 10 1-1
1 – ProASIC3E Device Family Overview
General Description
ProASIC3E, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3E
devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU).
ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems using existing ASIC or FPGA design flows and
tools.
ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices have
up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620
user I/Os.
Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have
Microsemi ordering numbers that begin with M1A3PE.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC 3E devices allow all function ality to be live at power-up; no external
boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using
the industry-standard AES algorithm. The ProASIC3E family device architecture mitigates the need for
ASIC migration at higher user volumes. This makes the ProASIC3E family a cost-effective ASIC
replacement solution, especially for applications in the consumer, networking/ communications,
computing, and avionics markets.
Security
The nonvolatile, flash -based ProASIC3 E devices do no t require a boot PROM, so there is no vul nerable
external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock, which provides
a unique combination of reprogrammability and design security without external overhead, advantages
that only an FPGA with nonvolatile flash programming can offer.
ProASIC3E devices utilize a 128-bit flash-based lock and a sep arate AES key to pr ovide the highest level
of protection in the FPGA industry for programmed intellectual property and configuration data. In
addition, all FlashROM data in ProASIC3E devices can be encrypted prior to loading, using the industry-
leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the
National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard.
ProASIC3E devices have a built-in AES decryption engine and a flash-based AES key that make them
the most comprehensive programmable logic device security solution available today. ProASIC3E
devices with AES-based securi ty provide a high level of protection for secu re, remote field updates over
public networks such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. Th e contents of a programmed ProASIC3E device cannot
be read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and AES security, is
unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
with industry-standard security, making remote ISP possible. A ProASIC3E device provides the best
available security for programmable logic designs.
ProASIC3E Device Family Overview
1-2 Revision 10
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structu re, a nd no exte rnal configuratio n data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3E FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Live at Power-Up
Flash-based ProASIC3E devices support Leve l 0 o f the LAPU classi fica tion standard. This fe ature he lps
in system component initialization, execution of critical tasks before the processor wakes up, setup and
configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of
flash-based ProASIC3E devices greatly simplifies total system design and reduces total system cost,
often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a
system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3E device's
flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or complete removal of the configuration PROM,
expensive voltage monitor , brownout detection, and clock generator devices from the PCB design. Flash-
based ProASIC3E devices simplify total system design and reduce cost and design risk while increasing
system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3E device s exhibit power ch aracteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3E devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
ProASIC3E Flash Family FPGAs
Revision 10 1-3
Advanced Architecture
The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on
page 3):
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-fl op/latch with enable allows for efficient use of the FPGA fabric. Th e VersaTile
capability is unique to the ProASIC famil y of third-generation architecture Flash FPGAs. VersaTiles are
connected with an y of the four levels of routing hi erarchy. Flash switches are distribute d throughout the
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
Figure 1-1 ProASIC3E Device Arc hitectu re Overview
4,608-Bit Dual-Port SRAM
or FIFO Block
VersaTile
RAM Block
CCC
Pro I/Os
ISP AES Decryption User Nonvolatile
FlashROM Charge Pumps
4,608-Bit Dual-Port SRAM
or FIFO Block
RAM Block
ProASIC3E Device Family Overview
1-4 Revision 10
VersaTiles
The ProASIC3E core consists of V ersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The ProASIC3E VersaTile supports the following:
All 3-input logic functions—L UT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-2 for VersaTile configurations.
User Nonvolatile FlashROM
ProASIC3E devices have 1 kbit of on-chip, use r-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is w ritten using the standard ProASIC3E IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored i n the FlashROM for a
user design.
The FlashROM can be programmed via the JTAG progr amming interface, and its contents can be read
back either through the JTAG programmin g interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bi ts; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defin es which of the 8 banks
and which of the 16 byte s within that bank are being read. T he three most significa nt bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The ProASIC3E development software solutions, Libero® Integrated Design Environment (IDE) and
Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequenti al
programming files for a pplications requiring a unique seria l number in each part. Another featur e allows
the inclusion of static data for system version control. D ata for the Flash ROM can be generated quickly
and easily using Libero IDE and Designer software tools. Comprehensive programming file support is
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
Figure 1-2 VersaTile Configurations
X1 Y
X2
X3 LUT-3 Data Y
CLK
Enable
CLR
D-FF
Data Y
CLK
CLR D-FF
LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set
ProASIC3E Flash Family FPGAs
Revision 10 1-5
SRAM and FIFO
ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,
1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be
configured with different bit widths on each port. For example, data can be sent through a 4-bit port a nd
read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port
(ROM emulation mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be con figured as a synchro nous FIFO with out using additi onal core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each member of
the ProASIC3E family contains six CCCs, each with an integrated PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides.
To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208
package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay typ es for clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration.
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock per iod peak-to-peak period jitter when single global
network used
Maximum acquisition time = 300 µs
Low power consumption of 5 mW
Exceptional tolerance to input perio d jitter— allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC)
Global Clocking
ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
ProASIC3E Device Family Overview
1-6 Revision 10
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs feat ures a flexible I/O structure, s upporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-ended,
differential, and voltage-referenced. The I/Os are or ganized into banks, with eigh t banks per de vice (two
per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is
subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8
to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given
VREF minibank is configured a s a VREF pin, the remaini ng I/Os in th at miniba nk w ill be a ble to use that
reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)
ProASIC3E banks support M-LVDS with 20 multi-drop points.
Hot-swap (also called hot-pl ug, or hot-insertion ) is t he opera tion of h ot-insertion or hot-remova l of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Specifying I/O States During Programming
You can modi fy the I/O states during programming in FlashPro. In F lashP ro, thi s fea tu re is sup ported for
PDB files generated from Designer v8.5 or greater. See the FlashPro Users Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that head er.
Select the I/Os you wish to modify ( Figure 1-3 on page 1-7).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programmi ng
Z -Tri-State: I/O is tristated
ProASIC3E Flash Family FPGAs
Revision 10 1-7
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
Figure 1- 3 • I/O States During Programming Window
Revision 10 2-1
2 – ProASIC3E DC and Switching Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA
specifications. Some restrictions might be added and will be reflected in future revisions of this
document. The –F speed grade is only suppo rted in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol Parameter Limits Units
VCC DC core supply voltage –0.3 to 1.65 V
VJTAG JTAG DC voltage –0.3 to 3.75 V
VPUMP Programming voltage –0.3 to 3.75 V
VCCPLL Analog power supply (PLL) –0.3 to 1.65 V
VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V
VMV DC I/O input buffer supply voltage 0.3 to 3.75 V
VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, which ever voltage is lower
(when I/O hot-in se rti o n mo de is di sa b le d )
V
TSTG 2Storage temperature –65 to +150 °C
TJ2Junction temperature +125 °C
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-3 on page 2-2.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, re fer to Table 2-2 on page 2-2.
ProASIC3E DC and Switching Characteristics
2-2 Revision 10
Table 2-2 • Recommended Operating Conditions1
Symbol Parameter Commercial Industrial Units
TAAmbient temperature 0 to +70 –40 to +85 °C
TJJunction temperature 0 to +85 –40 to +100 °C
VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V
VJTAG JTAG DC voltage 1.4 to 3.6 1 .4 to 3.6 V
VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V
Operation30 to 3.6 0 to 3.6 V
VCCPLL Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V
VCCI and VMV 21.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V
1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V
2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V
3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V
3.0 V DC supply voltage52.7 to 3.6 2.7 to 3.6 V
LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V
LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-13 on p age 2-17. VMV and VCCI should be at the same volt age within a given I/O bank.
3. VPUMP can be left floating during normal operation (not programming mode).
4. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user fol low best design practices using Microsemi’s timing and power simulati on tools.
5. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation.
Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperat ure 1
Product Gr ade Programming
Cycles Program Retention
(biased/unbiased) Maximum Storage
Temperature TSTG C) 2 Maximum Operating Junction
Temperatur e TJ (°C) 2
Commercial 500 20 years 110 100
Industrial 500 20 years 110 100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolut e limits.
ProASIC3E Flash Family FPGAs
Revision 10 2-3
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC®3E device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principl e is shown in Figure 2-1
on page 2-4.
There are five regions to consider durin g power-up.
ProASIC3E I/Os are activated only if ALL of the following three cond itions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the follow ing:
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Table 2-4 • Overshoot and Undershoot Limits 1
VCCI and VMV
Average VCCI–GND Overshoot or
Undershoot Duration
as a Percentage of Clock Cycle2Maximum Overshoot/
Undershoot2
2.7 V or less 10% 1.4 V
5% 1.49 V
3 V 10% 1.1 V
5% 1.19 V
3.3 V 10% 0.79 V
5% 0.88 V
3.6 V 10% 0.45 V
5% 0.54 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
ProASIC3E DC and Switching Characteristics
2-4 Revision 10
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper
power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed
brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on
page 2-4 for more details).
When PLL power supply voltage and/or VCC le vels dro p below the VCC b rownout level s (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the ProASIC3E FPGA Fabric User’s Guide for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
Figure 2-1 I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
V
a
= 0.85 V ± 0.25 V
Deactivation trip point:
V
d
= 0.75 V ± 0.25 V
Activation trip point:
V
a
= 0.9 V ± 0.3 V
Deactivation trip point:
V
d
= 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCC = VCCI + VT
ProASIC3E Flash Family FPGAs
Revision 10 2-5
Thermal Characteristics
Introduction
The temperature variable in Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction becau se dynamic and static power consumption cause the
chip junction to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA EQ 1
where:
TA = Ambient Temperature
ΔT = Temperature gradient between ju nction (silicon) and ambient ΔT = θja * P
θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and the juncti on-to-ambient air thermal resistivity is
θja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum juncti on
temperature is 110°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for an 896-pin FBGA package at commercial temperature and in still air.
EQ 2
Temperature and Voltage Derating Factors
Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)
θja(°C/W)
--------------------------------------------------------------------------------------------------------------------------------------- 110°C70°C
13.6°C/W
------------------------------------ 5 . 8 8 W===
Table 2-5 • Package Thermal Resistivities
Package Type Pin Count θjc
θja
UnitsStill Air 200 ft./min. 500 ft./min.
Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W
Plastic Quad Flat Package (PQFP) with
embedded heat spreader 208 3.8 16.2 13.3 11.9 C/W
Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W
484 3.2 20.5 17.0 15.9 C/W
676 3.2 16.4 13.0 12.0 C/W
896 2.4 13.6 10.4 9.4 C/W
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ= 70°C, VCC = 1.425 V)
Array Voltage
VCC (V)
Junction Temperature (°C)
–40°C 0°C 25°C 70°C 85°C 100°C
1.425 0.87 0.92 0.95 1.00 1.02 1.04
1.500 0.83 0.88 0.90 0.95 0.97 0.98
1.575 0.80 0.85 0.87 0.92 0.93 0.95
ProASIC3E DC and Switching Characteristics
2-6 Revision 10
Calculating Power Dissipation
Quiescent Supply Current
Power per I/O Pin
Table 2-7 • Quiescent Supply Current Characteristics
A3PE600 A3PE1500 A3PE3000
Typical (25°C) 5 mA 12 mA 25 mA
Maximum (Commercial) 30 mA 70 mA 150 mA
Maximum (Industrial) 45 mA 105 mA 22 5 mA
Notes:
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in
Table 2-8 and Table 2-9 on page 2-8.
2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O
leakage.
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VMV
(V) Static Power
PDC2 (mW)1Dynamic Power
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL /LVCMOS 3.3 17.39
3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 25.51
3.3 V LVTTL/LVCMOS Wide Range33.3 16.34
3.3 V LVTTL/LVCMOS Wide Range – Schmitt trigger33.3 24.49
2.5 V LVCMOS 2.5 5.76
2.5 V LVCMOS – Schmitt trigger 2.5 7.16
1.8 V LVCMOS 1.8 2.72
1.8 V LVCMOS – Schmitt trigger 1.8 2.80
1.5 V LVCMOS (JESD8-11) 1.5 2.08
1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 2.00
3.3 V PCI 3.3 18.82
3.3 V PCI – Schmitt trigger 3.3 20.12
3.3 V PCI-X 3.3 18.82
3.3 V PCI-X – Schmitt trigger 3.3 20.12
Voltage-Referenced
3.3 V GTL 3.3 2.90 8.23
2.5 V GTL 2.5 2.13 4.78
3.3 V GTL+ 3.3 2.81 4.14
2.5 V GTL+ 2.5 2.57 3.71
Notes:
1. PDC2 is the static po wer (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
ProASIC3E Flash Family FPGAs
Revision 10 2-7
HSTL (I) 1.5 0.17 2.03
HSTL (II) 1.5 0.17 2.03
SSTL2 (I) 2.5 1.38 4.48
SSTL2 (II) 2.5 1.38 4.48
SSTL3 (I) 3.3 3.21 9.26
SSTL3 (II) 3.3 3.21 9.26
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)
VMV
(V) Static Power
PDC2 (mW)1Dynamic Power
PAC9 (µW/MHz)2
Notes:
1. PDC2 is the static po wer (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
ProASIC3E DC and Switching Characteristics
2-8 Revision 10
Differential
LVDS/B-LVDS/M-LVDS 2.5 2.26 1.50
LVPECL 3.3 5.71 2.17
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
CLOAD
(pF) VCCI
(V) Static Power
PDC3 (mW)2
Dynamic Pow er
PAC10
(μW/MHz)3
Single-Ended
3.3 V LVT TL /LVCMOS 35 3.3 474.70
3.3 V LVTTL/LVCMOS Wide
Range435 3.3 474.70
2.5 V LVCMOS 35 2.5 270.73
1.8 V LVCMOS 35 1.8 151.78
1.5 V LVCMOS (JESD8-11) 35 1.5 104.55
3.3 V PCI 10 3.3 204.61
3.3 V PCI-X 10 3.3 204.61
Voltage-Referenced
3.3 V GTL 10 3.3 24.08
2.5 V GTL 10 2.5 13.52
3.3 V GTL+ 10 3.3 24.10
2.5 V GTL+ 10 2.5 13.54
HSTL (I) 2 0 1.5 7.08 26.22
HSTL (II) 20 1.5 13.88 27.22
SSTL2 (I) 30 2.5 16.69 105.56
SSTL2 (II) 30 2.5 25.91 116.60
SSTL3 (I) 30 3.3 26.02 114.87
SSTL3 (II) 30 3.3 42.21 131.76
Differential
LVDS/B-LVDS/M-LVDS 2.5 7.70 89.62
LVPECL 3.3 19.42 168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static po wer (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD8-B specification.
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)
VMV
(V) Static Power
PDC2 (mW)1Dynamic Power
PAC9 (µW/MHz)2
Notes:
1. PDC2 is the static po wer (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
ProASIC3E Flash Family FPGAs
Revision 10 2-9
Power Consumption of Va ri ous Internal Resources
Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices
Parameter Definition
Device-Specific Dynamic Contributions
(µW/MHz)
A3PE600 A3PE1500 A3PE3000
PAC1 Clock contribution of a Global Rib 12.77 16.21 19.7
PAC2 Clock contribution of a Global Spine 1.85 3.06 4.16
PAC3 Clock contribution of a VersaTile row 0.88
PAC4 Clock contribution of a VersaTile used as a sequential
module 0.12
PAC5 First contribution of a VersaTile used as a sequential
module 0.07
PAC6 Se cond contribution of a VersaTile used as a sequentia l
module 0.29
PAC7 Contribution of a VersaTile used as a combinatorial
module 0.29
PAC8 Average contribution of a ro uting net 0.70
PAC9 Co ntribution of an I/O input pin (standard-dependent) See Table 2-8 on page 2-6.
PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-9 on page 2-8
PAC11 Average contribution of a RAM block during a read
operation 25.00
PAC12 Average contribution of a RAM block during a write
operation 30.00
PAC13 Static PLL contribution 2.55 mW
PAC14 Dynamic contribution for PLL 2.60
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
calculator or SmartPower in Libero IDE.
ProASIC3E DC and Switching Characteristics
2-10 Revision 10
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial an d sequential cells used in th e design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-11 on
page 2-12.
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-12 on
page 2-12.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-12 on page 2-12. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number o f global spines used in the user design—gu idelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric
User's Guide.
NROW is the number of VersaTile rows used in the design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric
User's Guide.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-12.
FCLK is the global clock signal frequency.
ProASIC3E Flash Family FPGAs
Revision 10 2-11
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-12.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-12.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-12.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-12.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2 -12 on page 2-12.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-12 on
page 2-12.
FWRITE-CLOCK is the memory write clock frequency.
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-12 on
page 2-12.
PLL Contribution—PPLL
PPLL = PA C13 + PAC14 * FCLKOUT
FCLKOUT is the output clock frequency.1
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
ProASIC3E DC and Switching Characteristics
2-12 Revision 10
Guidelines
Toggle Rate Definition
A toggle rate defines the freque ncy of a net or logic elem ent relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock
frequency.
The average toggle rate of an 8-bit counter is 25%:
Bit 0 (LSB) = 100%
Bit 1 = 50%
Bit 2 = 25%
–…
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-11 • Toggle Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
α1Togg le rate of VersaTile outputs 10%
α2I/O buffer toggle rate 10%
Table 2-12 • Enable Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
β1I/O output buffer enable rate 100%
β2RAM enable rate for read operations 12.5%
β3RAM enable rate for write operations 12.5%
ProASIC3E Flash Family FPGAs
Revision 10 2-13
User I/O Characteristics
Timing Model
Figure 2-2 Timi ng Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ= 70°C), Worst-Case
VCC = 1.425 V
DQ
Y
Y
DQ
DQ DQ
Y
Combinational Cell
Combinational Cell
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell Register Cell I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL
LVPECL
LVDS,
BLVDS,
M-LVDS
GTL+ 3.3V
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
t
PD
= 0.56 ns t
PD
= 0.49 ns t
DP
= 1.36 ns
t
PD
= 0.87 ns t
DP
= 2.74 ns
t
PD
= 0.51 ns
t
PD
= 0.47 ns
t
DP
= 2.39 ns
t
DP
= 3.30 ns
t
CLKQ
= 0.59 ns
t
DP
= 1.53 ns
t
SUD
= 0.31 ns
t
PY
= 0.90 ns
t
CLKQ
= 0.55 ns
t
SUD
= 0.43 ns
t
PY
= 0.90 ns
t
PD
= 0.47 ns
t
CLKQ
= 0.55 ns
t
SUD
= 0.43 ns
t
PY
= 1.36 ns
t
PY
= 0.90 ns
t
ICLKQ
= 0.24 ns
t
ISUD
= 0.26 ns
t
PY
= 1.22 ns
ProASIC3E DC and Switching Characteristics
2-14 Revision 10
Figure 2-3 Input Buffer Timing Model an d Del ays (ex amp le )
(R)
PAD
YGND (F)
50%
50%
(R) (F)
(R)
DIN
GND (F)
50%50%
PAD Y
D
CLK
Q
I/O Interface
DIN
To Array
tDIN tDIN
VCC
tPYS
tPY
tPYS
tPY
VCC
Vtrip Vtrip
VIH
VIL
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
tPY tDIN
ProASIC3E Flash Family FPGAs
Revision 10 2-15
Figure 2-4 Output Buffer Model and Delays (example)
tDP
(R)
PAD VOL
tDP
(F)
Vtrip
Vtrip
VOH
VCC
D50% 50%
VCC
0 V
DOUT 50% 50% 0 V
tDOUT
(R) tDOUT
(F)
From Array
PAD
tDP
Std
Load
D
CLK
Q
I/O Interface
DOUT
D
tDOUT
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
ProASIC3E DC and Switching Characteristics
2-16 Revision 10
Figure 2-5 Tris tate Output Buffer Timing Model and Del ays (example)
D
CLK
Q
D
CLK
Q
10% V
CCI
t
ZL
Vtrip
50%
t
HZ
90% VCCI
t
ZH
Vtrip
50% 50% t
LZ
50%
EOUT
PAD
D
E50%
t
EOUT (R)
50%t
EOUT (F)
PAD
DOUT
EOUT
D
I/O Interface
E
t
EOUT
t
ZLS
Vtrip
50%
t
ZHS
Vtrip
50%
EOUT
PAD
D
E50% 50%
t
EOUT (R)
t
EOUT (F)
50%
VCC
VCC
VCC
VCCI
VCC
VCC
VCC
VOH
VOL
VOL
t
ZL
, t
ZH
, t
HZ
, t
LZ
, t
ZLS
, t
ZHS
t
EOUT
= MAX(t
EOUT
(r), t
EOUT
(f))
ProASIC3E Flash Family FPGAs
Revision 10 2-17
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions
I/O Standard Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1Slew
Rate
VIL VIH VOL VOH IOL IOH
Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
3.3V LVTTL/
3.3 V
LVCMOS
12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12
3.3 V
LVCMOS
Wide Range
100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1
2.5 V
LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12
1.8 V
LVCMOS 12 mA 12 mA High 0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12
1.5 V
LVCMOS 12 mA 12 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12
3.3 V PCI Per PCI Specification
3.3 V PCI-X Per PCI-X Specification
3.3 V GTL 25 mA225 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25
2.5 V GTL 25 mA225 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25
3.3 V GTL+ 35 mA 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 51 51
2.5 V GTL+ 33 mA 33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 40 40
HSTL (I) 8 mA 8 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8
HSTL (II) 15 mA215 mA2High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15
SSTL2 (I) 15 mA 15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15
SSTL2 (II) 18 mA 18 mA Hig h –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18
SSTL3 (I) 14 mA 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14
SSTL3 (II) 21 mA 21 mA High 0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displa yed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Output drive strength is below JEDEC specification.
3. Currents are measured at 85°C junction temperature.
4. Output Slew Rates can be extr acted from IBIS Models, located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
ProASIC3E DC and Switching Characteristics
2-18 Revision 10
Table 2-14 • Summary of Maximum and Minimum DC Inp ut Le vels
Applicable to Commercial and Industrial Conditions
DC I/O Sta ndards
Commercial1Industrial2
IIL3IIH4IIL3IIH4
µA µA µA µA
3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15
3.3 V LVCMOS Wide Range 10 10 15 15
2.5 V LVCMOS 10 10 15 15
1.8 V LVCMOS 10 10 15 15
1.5 V LVCMOS 10 10 15 15
3.3 V PCI 10101515
3.3 V PCI-X 10101515
3.3 V GTL 10101515
2.5 V GTL 10101515
3.3 V GTL+ 10 10 15 15
2.5 V GTL+ 10 10 15 15
HSTL (I) 10101515
HSTL (II) 10 10 15 15
SSTL2 (I) 10101515
SSTL2 (II) 10 10 15 15
SSTL3 (I) 10101515
SSTL3 (II) 10 10 15 15
Notes:
1. Commercial range (0°C < TA < 70°C)
2. Industrial range (–40°C < TA < 85°C)
3. IIL is the input leak age current per I/O pin over recommended operation conditions where –0.3 V < VIN <
VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI.
Input current is larger when operating outside recommended ranges.
ProASIC3E Flash Family FPGAs
Revision 10 2-19
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-15 • Summary of AC Measuring Points
Standard Input Reference Voltage
(VREF_TYP) Board Termination
Voltage (VTT_REF) Measuring Trip Point
(Vtrip)
3.3 V LVTTL / 3.3 V
LVCMOS 1.4 V
3.3 V LVCMOS Wide Range 1.4 V
2.5 V LVCMOS 1.2 V
1.8 V LVC MOS 0.90 V
1.5 V LVC MOS 0.75 V
3.3 V PCI 0 .285 * VCCI (RR)
0.615 * VCCI (FF))
3.3 V PCI-X 0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V GTL 0.8 V 1.2 V VREF
2.5 V GTL 0.8 V 1.2 V VREF
3.3 V GTL+ 1.0 V 1.5 V VREF
2.5 V GTL+ 1.0 V 1.5 V VREF
HSTL (I) 0.75 V 0.75 V VREF
HSTL (II) 0.75 V 0.75 V VREF
SSTL2 (I) 1.25 V 1.25 V VREF
SSTL2 (II) 1.25 V 1.25 V VREF
SSTL3 (I) 1.5 V 1.485 V VREF
SSTL3 (II) 1.5 V 1.485 V VREF
LVDS Cross point
LVPECL Cross point
Table 2-16 • I/O AC Parameter Definitions
Parameter Definition
tDP Data to Pad delay through the Output Buffer
tPY Pad to Data delay through the Input Buffer with Schmitt trigger disabled
tDOUT Data to Output Buffer delay through the I/O interface
tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN Input Buffer to Data delay through the I/O interface
tPYS Pad to Data delay through the Input Buffer with Schmitt trigger enabled
tHZ Enable to Pad delay through the Output Buffer—High to Z
tZH Enable to Pad delay through the Output Buffer—Z to High
tLZ Enable to Pad delay through the Output Buffer—Low to Z
tZL Enable to Pad delay through the Output Buffer—Z to Low
tZHS Enable to Pad delay through the Output Buffer with delayed enable —Z to High
tZLS Enable to Pad delay through the Output Buffer with delayed enable —Z to Low
ProASIC3E DC and Switching Characteristics
2-20 Revision 10
Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
I/O Standard
Drive
Strength
(mA)
Equivalent
Software
Default
Drive
Strength
Option)1
Slew Rate
Capacitive Load (pF)
External Resistor (Ω)
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tPYS (ns)
tEOUT (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
tZLS (ns)
tZHS (ns)
3.3 V LVTTL /
3.3 V L V CMOS 12 12 High 35 – 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81
3.3 V LVCMOS
Wide Range2100 µA 12 High 35 0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79
2.5 V LVCMOS 12 12 High 35 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
1.8 V LVCMOS 12 12 High 35 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
1.5 V LVCMOS 12 12 High 35 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
3.3 V PCI Per PCI
spec – High 10 25 3 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V PCI-X Per PCI-X
spec – High 10 253 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V GTL 25 High 10 25 0.45 1.55 0.03 2.19 0.32 1.52 1.55 – – 3.19 3.22
2.5 V GTL 25 High 10 25 0.45 1.59 0.03 1.83 – 0.32 1.61 1.59 – – 3.28 3.26
3.3 V GTL+ 35 High 10 25 0.45 1.53 0.03 1.19 – 0.32 1.56 1.53 – – 3.23 3.20
2.5 V GTL+ 33 High 10 25 0.45 1.65 0.03 1.13 0.32 1.68 1.57 – – 3.35 3.24
HSTL (I) 8 High 20 50 0 .49 2.37 0.03 1.59 0.32 2.42 2.35 – 4.09 4.02
HSTL (II) 15 High 20 25 0.49 2.26 0.03 1.59 0.32 2.30 2.03 – – 3.97 3.70
SSTL2 (I) 15 High 30 50 0.49 1.59 0.03 1.00 – 0.32 1.62 1.38 – 3.29 3.05
SSTL2 (II) 18 High 30 25 0.49 1.62 0.03 1.00 – 0.32 1.65 1.32 – 3.32 2.99
SSTL3 (I) 14 High 30 50 0.49 1.72 0.03 0.93 – 0.32 1.75 1.37 – 3.42 3.04
SSTL3 (II) 21 High 30 25 0.49 1.54 0.03 0.93 – 0.32 1.57 1.25 – 3.24 2.92
LVDS/B-LVDS/
M-LVDS 24 High 0.49 1.40 0.03 1.36 – – – – – – – –
LVPECL 24 High 0.49 1.36 0.03 1.22 – – – – – – – –
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. Fo r a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3V wide range as specified in the JESD8b specification.
3. Resistance is us ed t o measu re I/O pro pagati on del ays as define d in PCI specifi cat ion s. See Figu re 2-11 on page 2-38 for
connectivity. This resistor is not required during no rmal operation.
4. For specific junct ion temperature and voltage supply levels, refer to Table 2-6 on page 2-5..
ProASIC3E Flash Family FPGAs
Revision 10 2-21
Detailed I/O DC Characteristics
Table 2-18 • Input Capacitance
Symbol Definition Conditions Min. Max. Units
CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF
CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF
Table 2-19 • I/O Output Buffer Maximum Resistances1
Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3
3.3 V LVT TL / 3.3 V LVCMOS 4 mA 100 300
8 mA 50 150
12 mA 25 75
16 mA 17 50
24 mA 11 33
3.3 V LVCMOS Wide Range 100 µA Same as regular
3.3 V LVCMOS Same as regular
3.3 V LVCMOS
2.5 V LVCMOS 4 mA 100 200
8 mA 50 100
12 mA 25 50
16 mA 20 40
24 mA 11 22
1.8 V LVCMOS 2 mA 200 225
4 mA 100 112
6 mA 50 56
8 mA 50 56
12 mA 20 22
16 mA 20 22
1.5 V LVCMOS 2 mA 200 224
4 mA 100 112
6 mA 67 75
8 mA 33 37
12 mA 33 37
3.3 V PCI/PCI-X Per PCI/PCI-X
specification 25 75
3.3 V GTL 25 mA 11
2.5 V GTL 25 mA 14
3.3 V GTL+ 35 mA 12
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at http://www.microsemi.com/soc/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
ProASIC3E DC and Switching Characteristics
2-22 Revision 10
2.5 V GTL+ 33 mA 15
HSTL (I) 8 mA 50 50
HSTL (II) 15 mA 25 25
SSTL2 (I) 15 mA 27 31
SSTL2 (II) 18 mA 13 15
SSTL3 (I) 14 mA 44 69
SSTL3 (II) 21 mA 18 32
Table 2-20 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCI
R((WEAK PULL-UP)1
(Ω)R(WEAK PULL-DOWN)2
(Ω)
Min. Max. Min. Max.
3.3 V 10 k 45 k 10 k 45 k
3.3 V (Wide
Range I/Os) 10 k 45 k 10 k 45 k
2.5 V 11 k 55 k 12 k 74 k
1.8 V 18 k 70 k 17 k 110 k
1.5 V 19 k 90 k 19 k 140 k
Notes:
1. R(WEAK PULL-UP -MA X) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-DO W N -MAX) = (VOLspec) / I(WEAK PULL-D O W N -MIN)
Table 2-19 • I/O Output Buffer Maximum Resistances1 (continued)
Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at http://www.microsemi.com/soc/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
ProASIC3E Flash Family FPGAs
Revision 10 2-23
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection, but
such protection would only be needed in extremely prolonged stre ss conditions.
Table 2-21 • I/O Short Currents IOSH/IOSL
Drive Strength IOSH (mA)* IOSL (mA)*
3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27
8 mA 51 54
12 mA 103 109
16 mA 132 127
24 mA 268 181
3.3 V LVCMOS Wide Range 100 µA Same as regular
3.3 V LVCMOS Same as regular
3.3 V LVCMOS
2.5 V LVC MOS 4 mA 16 18
8 mA 32 37
12 mA 65 74
16 mA 83 87
24 mA 169 124
1.8 V LVC MOS 2 mA 9 11
4 mA 17 22
6 mA 35 44
8 mA 45 51
12 mA 91 74
16 mA 91 74
1.5 V LVC MOS 2 mA 13 16
4 mA 25 33
6 mA 32 39
8 mA 66 55
12 mA 66 55
Notes:
1. TJ = 100°C
2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength
selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range as specified in the JESD8b specification.
Table 2-22 • Duration of Short Circuit Event before Failure
Temperature Time before Failure
–40°C > 20 years
0°C > 20 years
25°C > 20 years
70°C 5 years
85°C 2 years
ProASIC3E DC and Switching Characteristics
2-24 Revision 10
100°C 6 months
110°C 3 months
Table 2-23 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration Hysteresis Value (typ.)
3.3 V LVT TL /LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV
2.5 V LVCMOS (Schmitt trigger mode) 140 mV
1.8 V LVCMOS (Schmitt trigger mode) 80 mV
1.5 V LVCMOS (Schmitt trigger mode) 60 mV
Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Buffer Input Rise/Fall Time
(min.) Input Rise/Fall Time (max.) Reliability
LVTTL/LVCMOS
(Schmitt trigger disabled) No requirement 10 ns * 20 years
(110°C)
LVTTL/LVCMOS
(Schmitt trigger enabled) No requirement No requirement, but input noise
voltage cannot exceed Schmitt
hysteresis.
20 years
(110°C)
HSTL/SSTL/GTL No requirement 10 ns * 10 years
(100°C)
LVDS/B-LVDS/M-LVDS/
LVPECL No requirement 10 ns * 10 years
(100°C)
Note: *For clock signals and similar edge-generating signals, refer to the "ProASIC3/E SSO and Pin
Placement Guidelines" chapter of the ProASIC3E FPGA Fabric User’s Guide. The maximum i nput
rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the
rise time and fall time of input buffers ca n be increased beyond the maximum value . The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends
signal integrity evaluation/characterization of the system to ensure that there is no excessive noise
coupling into inp ut sig nals.
Table 2-22 • Duration of Short Circuit Event before Failure
Temperature Time before Failure
ProASIC3E Flash Family FPGAs
Revision 10 2-25
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LV TTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Table 2-25 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2
Drive Strength Min.
VMax.
VMin.,
VMax.
VMax.
VMin.
VmAmAMax.
mA3Max.
mA3µA4µA4
4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10
8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10
12 mA –0.3 0.8 23.6 0.4 2.4 12 12 109 103 10 10
16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10
24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-6 AC Loading
Table 2-26 • 3.3 V LVTTL / 3.3 V LVCMOS AC Waveforms, Measur ing Points, and Capacitive Load s
Input Low (V) Input High (V) M easuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 3.3 1.4 35
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point Test Point
Enable Path
Datapath 35 pF
R = 1 k R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
ProASIC3E DC and Switching Characteristics
2-26 Revision 10
Timing Characteristics
Table 2-27 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3. 0 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.66 7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94 ns
–1 0.56 6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60 ns
–2 0.49 5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67 6.67 ns
8 mA Std. 0.66 5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38 ns
–1 0.56 4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43 ns
–2 0.49 3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53 4.76 ns
12 mA Std. 0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11 ns
–1 0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34 ns
–2 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns
16 mA Std. 0.66 3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84 ns
–1 0.56 2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12 ns
–2 0.49 2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62 ns
24 mA Std. 0.66 3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39 ns
–1 0.56 2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.74 ns
–2 0.49 2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3. 0 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29 ns
–1 0.56 9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60 ns
–2 0.49 8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43 ns
8 mA Std. 0.66 7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68 ns
–1 0.56 6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38 ns
–2 0.49 5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48 ns
12 mA Std. 0.66 6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26 ns
–1 0.56 5.13 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17 ns
–2 0.49 4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.45 2.59 6.25 5.42 ns
16 mA Std. 0.66 5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96 ns
–1 0.56 4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92 ns
–2 0.49 4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20 ns
24 mA Std. 0.66 5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93 ns
–1 0.56 4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89 ns
–2 0.49 3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-27
3.3 V LVCMOS Wide Range
Table 2-29 • Minimum and Maximum DC Input and Output Levels
3.3 V
LVCMOS
Wide
Range
Equivalent
Software
Default
Drive
Strength
Option1
VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2IIH3
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
AµA
Max.
mA4Max.
mA4µA5µA5
100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 27 25 10 10
100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 27 25 10 10
100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 54 51 10 10
100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 54 51 10 10
100 µA 12 mA –0.3 0.8 23.6 0.2 VDD – 0.2 100 100 109 103 10 10
100 µA 16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 127 132 10 10
100 µA 24 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 181 268 10 10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. Fo r a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Figure 2-7 AC Loading
Table 2-30 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) M easuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 3.3 1.4 35
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point Test Point
Enable Path
Datapath 35 pF
R = 1 k R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
ProASIC3E DC and Switching Characteristics
2-28 Revision 10
Timing Characteristics
Table 2-31 • 3.3 V LVCMOS Wide Range High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1 Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
100 µA 4 mA Std. 0.66 12.19 0.04 1.83 2.38 0.43 12.19 10.17 4.16 4.00 15.58 13.57 ns
–1 0.56 10.37 0.04 1.55 2.02 0.36 10.37 8.66 3.54 3.41 13.26 11.54 ns
–2 0.49 9.10 0.03 1.36 1.78 0.32 9.10 7.60 3.11 2.99 11.64 10.13 ns
100 µA 8 mA S td. 0.66 7.85 0.04 1.83 2.38 0.43 7.85 6.29 4.71 4.97 11.24 9.68 ns
–1 0.56 6.68 0.04 1.55 2.02 0.36 6.68 5.35 4.01 4.22 9.57 8.24 ns
–2 0.49 5.86 0.03 1.36 1.78 0.32 5.86 4.70 3.52 3.71 8.40 7.23 ns
100 µA 12 mA Std. 0.66 5.67 0.04 1.83 2.38 0.43 5.67 4.36 5.06 5.59 9.07 7.75 ns
–1 0.56 4.82 0.04 1.55 2.02 0.36 4.82 3.71 4.31 4.75 7.71 6.59 ns
–2 0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79 ns
100 µA 16 mA Std. 0.66 5.35 0.04 1.83 2.38 0.43 5.35 3.96 5.15 5.76 8.75 7.35 ns
–1 0.56 4.55 0.04 1.55 2.02 0.36 4.55 3.36 4.38 4.90 7.44 6.25 ns
–2 0.49 4.00 0.03 1.36 1.78 0.32 4.00 2.95 3.85 4.30 6.53 5.49 ns
100 µA 24 mA Std. 0.66 4.96 0.04 1.83 2.38 0.43 4.96 3.27 5.23 6.38 8.35 6.67 ns
–1 0.56 4.22 0.04 1.55 2.02 0.36 4.22 2.78 4.45 5.43 7.11 5.67 ns
–2 0.49 3.70 0.03 1.36 1.78 0.32 3.70 2.44 3.91 4.76 6.24 4.98 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-29
Table 2-32 • 3.3 V LVCMOS Wide Range Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1 Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
100 µA 4 mA Std. 0.66 17.02 0.04 1.83 2.38 0.43 17.02 13.74 4.16 3.78 20.42 17.14 ns
–1 0.56 14.48 0.04 1.55 2.02 0.36 14.48 11.69 3.54 3.21 17.37 14.58 ns
–2 0.49 12.71 0.03 1.36 1.78 0.32 12.71 10.26 3.11 2.82 15.25 12.80 ns
100 µA 8 mA Std. 0.66 12.16 0.04 1.83 2.38 0.43 12.16 9.78 4.70 4.74 15.55 13.17 ns
–1 0.56 10.34 0.04 1.55 2.02 0.36 10.34 8.32 4.00 4.03 13.23 11.20 ns
–2 0.49 9.08 0.03 1.36 1.78 0.32 9.08 7.30 3.51 3.54 11.61 9.84 ns
100µA 12 mA Std. 0.66 9.32 0.04 1.83 2.38 0.43 9.32 7.62 5.06 5.36 12.71 11.02 ns
–1 0.56 7.93 0.04 1.55 2.02 0.36 7.93 6.48 4.31 4.56 10.81 9.37 ns
–2 0.49 6.96 0.03 1.36 1.78 0.32 6.96 5.69 3.78 4.00 9.49 8.23 ns
100 µA 16 mA Std. 0.66 8.69 0.04 1.83 2.38 0.43 8.69 7.17 5.14 5.53 12.08 10.57 ns
–1 0.56 7.39 0.04 1.55 2.02 0.36 7.39 6.10 4.37 4.71 10.28 8.99 ns
–2 0.49 6.49 0.03 1.36 1.78 0.32 6.49 5.36 3.83 4.13 9.02 7.89 ns
100 µA 24 mA Std. 0.66 8.11 0.04 1.83 2.38 0.43 8.11 7.13 5.23 6.13 11.50 10.52 ns
–1 0.56 6.90 0.04 1.55 2.02 0.36 6.90 6.06 4.45 5.21 9.78 8.95 ns
–2 0.49 6.05 0.03 1.36 1.78 0.32 6.05 5.32 3.91 4.57 8.59 7.86 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-30 Revision 10
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-33 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.,
VMin.
VmAmA Max.
mA3Max.
mA3µA4µA4
4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10
8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10
12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10
16 mA –0.3 0 .7 1.7 3.6 0.7 1.7 16 16 87 83 10 10
24 mA –0.3 0 .7 1.7 3.6 0.7 1.7 24 24 124 169 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-8 AC Loading
Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) M easuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 2.5 1.2 35
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point Test Point
Enable Path
Datapath 35 pF
R = 1 k R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
ProASIC3E Flash Family FPGAs
Revision 10 2-31
Timing Characteristics
Table 2-35 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 2.3 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.66 8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05 ns
–1 0.56 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40 ns
–2 0.49 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25 ns
8 mA Std. 0.66 5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50 7.51 ns
–1 0.56 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38 ns
–2 0.49 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61 ns
12 mA Std. 0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73 ns
–1 0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87 ns
–2 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns
16 mA Std. 0.66 3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83 5.35 ns
–1 0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55 ns
–2 0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00 ns
24 mA Std. 0.66 3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56 4.72 ns
–1 0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01 ns
–2 0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-32 Revision 10
Table 2-36 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 2.3 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.66 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85 ns
–1 0.56 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78 ns
–2 0.49 8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34 ns
8 mA Std. 0.66 8.73 0.04 1.51 1.66 0.43 8.89 8.01 3.10 2.93 11.13 10.25 ns
–1 0.56 7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72 ns
–2 0.49 6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65 ns
12 mA Std. 0.66 6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34 ns
–1 0.56 5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10 ns
–2 0.49 5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23 ns
16 mA Std. 0.66 6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96 ns
–1 0.56 5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77 ns
–2 0.49 4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95 ns
24 mA Std. 0.66 5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94 ns
–1 0.56 5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75 ns
–2 0.49 4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-33
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applica ti ons. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-37 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA3Max.
mA3µA4µA4
2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI 0.45 2 2 11 9 10 10
4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI 0.45 4 4 22 17 10 10
6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10
8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI 0.45 8 8 51 45 10 10
12 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 74 91 10 10
16 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI 0.45 16 16 74 91 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-9 AC Loading
Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) M easuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 1.8 0.9 35
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point Test Point
Enable Path
Datapath 35 pF
R = 1 k R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
ProASIC3E DC and Switching Characteristics
2-34 Revision 10
Timing Characteristics
Table 2-39 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 1.7 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.66 12.10 0.04 1.45 1.91 0.43 9.59 12.10 2.78 1.64 11.83 14.34 ns
–1 0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20 ns
–2 0.49 9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71 ns
4 mA Std. 0.66 7.05 0.04 1.45 1.91 0.43 6.20 7.05 3.25 2.86 8.44 9.29 ns
–1 0.56 6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90 ns
–2 0.49 5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94 ns
6 mA Std. 0.66 4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76 ns
–1 0.56 3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75 ns
–2 0.49 3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05 ns
8 mA Std. 0.66 4.12 0.04 1.45 1.91 0.43 4.20 3.99 3.63 3.62 6.43 6.23 ns
–1 0.56 3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30 ns
–2 0.49 3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65 ns
12 mA Std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns
–1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns
–2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns
16 mA Std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns
–1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns
–2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-35
Table 2-40 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 1.7 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07 ns
–1 0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37 ns
–2 0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50 ns
4 mA Std. 0.66 11.39 0.04 1.4 5 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99 ns
–1 0.56 9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05 ns
–2 0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70 ns
6 mA Std. 0.66 8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33 ns
–1 0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79 ns
–2 0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72 ns
8 mA Std. 0.66 8.35 0.04 1.45 1.91 0.43 8.50 7.59 3.64 3.52 10.74 9.82 ns
–1 0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35 ns
–2 0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33 ns
12 mA Std. 0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80 ns
–1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns
–2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns
16 mA Std. 0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80 ns
–1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns
–2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-36 Revision 10
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applica ti ons. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-41 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA3Max.
mA3µA4µA4
2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10
4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10
6 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 39 32 10 10
8 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 55 66 10 10
12 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 55 66 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-10 • AC Loading
Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) M easuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 1.5 0.75 35
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point Test Point
Enable Path
Datapath 35 pF
R = 1 k R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
ProASIC3E Flash Family FPGAs
Revision 10 2-37
Timing Characteristics
Table 2-43 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 1.4 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.66 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77 ns
–1 0.56 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16 ns
–2 0.49 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04 ns
4 mA Std. 0.66 5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45 7.65 ns
–1 0.56 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50 ns
–2 0.49 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71 ns
6 mA Std. 0.66 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98 ns
–1 0.56 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94 ns
–2 0.49 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21 ns
8 mA Std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns
–1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns
–2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns
12 mA Std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns
–1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns
–2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-44 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 1.4 V
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.66 14 .11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37 ns
–1 0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08 ns
–2 0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48 ns
4 mA Std. 0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10 ns
–1 0.56 9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29 ns
–2 0.49 8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04 ns
6 mA Std. 0.66 10.45 0.04 1.7 0 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48 ns
–1 0.56 8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76 ns
–2 0.49 7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57 ns
8 mA Std. 0.66 10.02 0.04 1.7 0 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47 ns
–1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns
–2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns
12 mA Std. 0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47 ns
–1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns
–2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-38 Revision 10
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
path characterization are described in Figure 2-11.
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is
described in Table 2-46.
Timing Characteristics
Table 2-45 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1IIH2
Drive Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA3Max.
mA3µA4µA4
Per PCI specification P er PCI curves 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Figure 2-11 • AC Loading
Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 3.3 0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
–10
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Table 2-47 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V
Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 2.81 0.04 1.05 1.67 0.43 2.86 2.00 3.28 3.61 5.09 4.23 ns
–1 0.56 2.39 0.04 0.89 1.42 0.36 2.43 1.70 2.79 3.07 4.33 3.60 ns
–2 0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-39
Voltage-Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
Timing Characteristics
Table 2-48 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL VIL VIH VOL VOH IOL IOH IOSL IOSH I IL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
25 mA3–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25 181 268 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Figure 2-12 • AC Loading
Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point 10 pF
25
GTL
VTT
Table 2-50 • 3.3 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.60 2.08 0.04 2.93 0.43 2.04 2.08 4.27 4.31 ns
–1 0.51 1.77 0.04 2.50 0.36 1.73 1.77 3.63 3.67 ns
–2 0.45 1.55 0.03 2.19 0.32 1.52 1.55 3.19 3.22 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-40 Revision 10
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Timing Characteristics
Table 2-51 • Minimum and Maximum DC Input and Output Levels
2.5 GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.,
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
25 mA3–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25 124 169 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Figure 2-13 • AC Loading
Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point 10 pF
25
GTL
VTT
Table 2-53 • 2.5 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.60 2.13 0.04 2.46 0.43 2.16 2.13 4.40 4.36 ns
–1 0.51 1.81 0.04 2.09 0.36 1.84 1.81 3.74 3.71 ns
–2 0.45 1.59 0.03 1.83 0.32 1.61 1.59 3.28 3.26 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-41
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
Timing Characteristics
Table 2-54 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
35 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 3 5 35 181 268 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-14 • AC Loading
Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point 10 pF
25
GTL+
VTT
Table 2-56 • 3.3 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.0 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.60 2.06 0.04 1.59 0.43 2.09 2.06 4.33 4.29 ns
–1 0.51 1.75 0.04 1.35 0.36 1.78 1.75 3.68 3.65 ns
–2 0.45 1.53 0.03 1.19 0.32 1.56 1.53 3.23 3.20 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-42 Revision 10
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Timing Characteristics
Table 2-57 • Minimum and Maximum DC Input and Output Levels
2.5 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
33 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 33 33 124 169 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-15 • AC Loading
Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point 10 pF
25
GTL+
VTT
Table 2-59 • 2.5 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.0 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.60 2.21 0.04 1.51 0.43 2.25 2.10 4.48 4.34 ns
–1 0.51 1.88 0.04 1.29 0.36 1.91 1.79 3.81 3.69 ns
–2 0.45 1.65 0.03 1.13 0.32 1.68 1.57 3.35 3.24 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-43
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Timing Characteristics
Table 2-60 • Minimum and Maximum DC Input and Output Levels
HSTL Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
8 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8 39 32 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-16 • AC Loading
Table 2-61 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point*
(V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.1 VREF + 0.1 0.75 0.75 0.75 20
Note: *Measuri ng poi nt = Vtrip. See Table 2-15 on page 2-19 for a complete table of trip points.
Test Point 20 pF
50
HSTL
Class I
VTT
Table 2-62 • HSTL Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = .4 V, VREF = 0.75 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 3.18 0.04 2.12 0.43 3.24 3.14 5.47 5.38 ns
–1 0.56 2.70 0.04 1.81 0.36 2.75 2.67 4.66 4.58 ns
–2 0.49 2.37 0.03 1.59 0.32 2.42 2.35 4.09 4.02 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-44 Revision 10
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull
output buffer.
Timing Characteristics
Table 2-63 • Minimum and Maximum DC Input and Output Levels
HSTL Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.,
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
15 mA3–0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15 55 66 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Figure 2-17 • AC Loading
Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.1 V REF + 0.1 0.75 0.75 0.75 20
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-19 for a complete table of trip points.
Test Point 20 pF
25
HSTL
Class II
VTT
Table 2-65 • HSTL Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 3.02 0.04 2.12 0.43 3.08 2.71 5.32 4.95 ns
–1 0.56 2.57 0.04 1.81 0.36 2.62 2.31 4.52 4.21 ns
–2 0.49 2.26 0.03 1.59 0.32 2.30 2.03 3.97 3.70 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-45
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-66 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
15 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15 87 83 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-18 • AC Loading
Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.2 VREF + 0.2 1.25 1.25 1.25 30
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point
30 pF
50
25
SSTL2
Class I
VTT
Table 2-68 • SSTL 2 Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 2.13 0.04 1.33 0.43 2.17 1.85 4.40 4.08 ns
–1 0.56 1.81 0.04 1.14 0.36 1.84 1.57 3.74 3.47 ns
–2 0.49 1.59 0.03 1.00 0.32 1.62 1.38 3.29 3.05 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-46 Revision 10
SSTL2 Class II
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-69 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
18 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18 124 169 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-19 • AC Loading
Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.2 V REF + 0.2 1.25 1.25 1.25 30
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point
30 pF
25
25
SSTL2
Class II
VTT
Table 2-71 • SSTL 2 Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 0.66 2.17 0.04 1.33 0.43 2.21 1.77 4.44 ns
–1 0.56 0.56 1.84 0.04 1.14 0.36 1.88 1.51 3.78 ns
–2 0.49 0.49 1.62 0.03 1.00 0.32 1.65 1.32 3.32 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-47
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-72 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I VIL VIH VOL VOH IO L IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
14 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 54 51 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-20 • AC Loading
Table 2-73 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point
30 pF
50
25
SSTL3
Class I
VTT
Table 2-74 • SSTL3 Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 2.31 0.04 1.25 0.43 2.35 1.84 4.59 4.07 ns
–1 0.56 1.96 0.04 1.06 0.36 2.00 1.56 3.90 3.46 ns
–2 0.49 1.72 0.03 0.93 0.32 1.75 1.37 3.42 3.04 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-48 Revision 10
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-75 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
21 mA 0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21 109 103 10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-21 • AC Loading
Table 2-76 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring
Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)
VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
Test Point
30 pF
25
25
SSTL3
Class II
VTT
Table 2-77 • SSTL3 Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.66 2.07 0.04 1.25 0.43 2.10 1.67 4.34 3.91 ns
–1 0.56 1.76 0.04 1.06 0.36 1.79 1.42 3.69 3.32 ns
–2 0.49 1.54 0.03 0.93 0.32 1.57 1.25 3.24 2.92 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-49
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by the Designer software when the user
instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional
I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-22. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3E also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Figure 2-22 • LVDS Circuit Diagram and Board-Level Imple mentation
140 Ω100 Ω
Z
0
= 50 Ω
Z
0
= 50 Ω
165 Ω
165 Ω
+
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA FPGA
Bourns Part Number: CAT16-LV4F12
ProASIC3E DC and Switching Characteristics
2-50 Revision 10
Table 2-78 • LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Typ. Max. Units
VCCI Supply Voltage 2.375 2.5 2.625 V
VOL Output Low Voltage 0.9 1.075 1.25 V
VOH Output High Voltage 1.25 1.425 1.6 V
IOL1 Output Lower Current 0.65 0.91 1.16 mA
IOH1 Output High Current 0.65 0.91 1.16 mA
VI Input Voltage 0 2.925 V
IIH2Input High Leakage Current 10 µA
IIL2Input Low Leakage Current 10 µA
VODIFF Differential Output Voltage 250 350 450 mV
VOCM Output Common Mode Voltage 1.125 1.25 1.375 V
VICM Input Common Mode Voltage 0.05 1.25 2.35 V
VIDIFF Input Differential Vo ltage 2 100 350 mV
Notes:
1. IOL/IOH defined by VODIFF/(Resistor Network).
2. Currents are measured at 85°C junction temperature.
Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V)
1.075 1.325 Cross point
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
ProASIC3E Flash Family FPGAs
Revision 10 2-51
Timing Characteristics
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20
loads. A sample application is given in Figure 2-23. The input and output buffer delays are available in
the LVDS section in Table 2-80.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS=60Ω and
RT=70Ω, given Z0=50Ω (2") and Zstub =50Ω (~1.5").
Table 2-80 • LVDS
Commercial-Case Conditions: TJ = 70°C, Worst-C ase VCC = 1.425 V, Worst-Case
VCCI = 2.3 V
Speed Grade tDOUT tDP tDIN tPY Units
Std. 0.66 1.87 0.04 1.82 ns
–1 0.56 1.59 0.04 1.55 ns
–2 0.49 1.40 0.03 1.36 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for
derating values.
Figure 2-23 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
...
RTRT
BIBUF_LVDS
R
+
-T
+
-R
+
-T
+
-
D
+
-
EN EN EN EN EN
Receiver Transceiver Receiver TransceiverDriver
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
ProASIC3E DC and Switching Characteristics
2-52 Revision 10
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Timing Characteristics
Figure 2-24 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-81 • Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Max. Min. Max. Min. Max. Units
VCCI Supply V o ltage 3.0 3.3 3.6 V
VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V
VOH Outpu t High Vo ltage 1.8 2.11 1.92 2.28 2.13 2.41 V
VIL, VIH Input Low, Input High Voltages 0 3.3 0 3.6 0 3.9 V
VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V
VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V
VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V
VIDIFF Input Differential Voltage 300 300 300 mV
Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V)
1.64 1.94 Cross point
Note: *Measuring point = Vtrip. See Table 2-15 on p a g e 2-19 for a complete table of trip points.
187 W 100 Ω
Z0 = 50 Ω
Z0 = 50 Ω
100 Ω
100 Ω
+
P
N
P
N
INBUF_LVPECL
OUTBUF_LVPECL
FPGA FPGA
Bourns Part Number: CAT16-PC4F12
Table 2-83 • LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade tDOUT tDP tDIN tPY Units
Std. 0.66 1.83 0.04 1.63 ns
–1 0.56 1.55 0.04 1.39 ns
–2 0.49 1.36 0.03 1.22 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-53
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Figure 2-25 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
INBUF INBUF
TRIBUF
CLKBUF
INBUF
INBUF
CLKBUF
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Pad Out
CLK
Enable
Preset
Data_out
Data
EOUT
DOUT
Enable
CLK
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
D_Enable
A
B
C
D
EE
E
EF
G
H
I
J
L
K
YCore
Array
ProASIC3E DC and Switching Characteristics
2-54 Revision 10
Table 2-84 • Parameter Definitio n an d Measuring Nodes
Parameter Name Parameter Definition Measuring Nodes
(from, to)*
tOCLKQ Clock-to-Q of the Output Data Register H, DOUT
tOSUD Data Setup Time for the Output Data Register F, H
tOHD Data Hold Time for the Output Data Register F, H
tOSUE Enable Setup Time for the Output Data Register G, H
tOHE Enable Hold Time for the Output Data Register G, H
tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT
tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H
tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H
tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT
tOESUD Data Setup Time for the Output Enable Register J, H
tOEHD Data Hold Time for the Output Enable Register J, H
tOESUE Enable Setup Time for the Output Enable Register K, H
tOEHE Enable Hold Time for the Output Enable Register K, H
tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Registe r I, EOUT
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Reg ister I, H
tOERECPRE Asynch ronous Preset Recovery Time for the Output Enable Register I, H
tICLKQ Clock-to-Q of the Input Data Register A, E
tISUD Dat a Setup Time for the Input Data Register C, A
tIHD Data Hold Time for the Input Data Register C, A
tISUE Enable Setup Time for the Input Data Register B, A
tIHE Enable Hold Time for the Input Data Register B, A
tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E
tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A
tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A
Note: *See Figure 2-25 on page 2-53 for more information.
ProASIC3E Flash Family FPGAs
Revision 10 2-55
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
Figure 2-26 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronou s Clear
Enable
CLK
Pad Out
CLK
Enable
CLR
Data_out
Data Y
AA
EOUT
DOUT
Core
Array
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
INBUF
TRIBUF
INBUF INBUF CLKBUF
INBUF
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
ProASIC3E DC and Switching Characteristics
2-56 Revision 10
Table 2-85 • Parameter Definitio n an d Measuring Nodes
Parameter Name Parameter Definition Measuring Nodes
(from, to)*
tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT
tOSUD Data Setup Time for the Output Data Register FF, HH
tOHD Data Hold Time for the Output Data Register FF, HH
tOSUE Enable Setup Time for the Output Data Register GG, HH
tOHE Enable Hold Time for the Output Data Register GG, HH
tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT
tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH
tORECCLR Asynchronous Clear Reco very Time for the Output Data Register LL, HH
tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT
tOESUD Data Setup Time for the Output Enable Register JJ, HH
tOEHD Data Hold Time for the Output Enable Register JJ, HH
tOESUE Enable Setup Time for the Output Enable Register KK, HH
tOEHE Enable Hold Time for the Output Enable Register KK, HH
tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Reg ister II, HH
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Regi ster II, HH
tICLKQ Clock-to-Q of the Input Data Register AA, EE
tISUD Data Setu p Time for the Input Data Register CC, AA
tIHD Data Hold Time for the Input Data Register CC, AA
tISUE Enable Setup Time for the Input Data Register BB, AA
tIHE Enable Hold T ime for the Input Data Register BB, AA
tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE
tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA
tIRECCLR Asynchronous Clear Reco very Time for the Input Data Register DD, AA
Note: *See Figure 2-26 on page 2-55 for more information.
ProASIC3E Flash Family FPGAs
Revision 10 2-57
Input Register
Timing Characteristics
Figure 2-27 • Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
t
ISUE
50%
50%
t
ISUD
t
IHD
50% 50%
t
ICLKQ
10
t
IHE
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH
t
ICKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
Table 2-86 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns
tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns
tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns
tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 ns
tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 ns
tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns
tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns
tIREMCLR Asynchronous Clear Remo val Time for the Input Data Register 0.00 0.00 0.00 ns
tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns
tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns
tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns
tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns
tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns
tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.36 0.41 0.48 ns
tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.37 0.43 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-58 Revision 10
Output Register
Timing Characteristics
Figure 2-28 • Output Register Timing Diagram
Preset
Clear
DOUT
CLK
Data_out
Enable
t
OSUE
50%
50%
t
OSUD
t
OHD
50% 50%
t
OCLKQ
10
t
OHE
t
ORECPRE
t
OREMPRE
t
ORECCLR
t
OREMCLR
t
OWCLR
t
OWPRE
t
OPRE2Q
t
OCLR2Q
t
OCKMPWH
t
OCKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
50%
Table 2-87 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns
tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 n s
tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns
tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 ns
tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 ns
tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns
tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns
tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns
tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns
tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns
tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns
tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns
tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.36 0.41 0.48 ns
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.37 0.43 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-59
Output Enable Register
Timing Characteristics
Figure 2-29 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
t
OESUE
50%
50%
t
OESUD
t
OEHD
50% 50%
t
OECLKQ
10
t
OEHE
t
OERECPRE
t
OEREMPRE
t
OERECCLR
t
OEREMCLR
t
OEWCLR
t
OEWPRE
t
OEPRE2Q
t
OECLR2Q
t
OECKMPWH
t
OECKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
Table 2-88 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 ns
tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns
tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns
tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 ns
tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 ns
tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns
tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Regist er 0.67 0.76 0.89 ns
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns
tOERECCLR Asynchronous Cle ar Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns
tOERECPRE Asynchro nous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns
tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns
tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.36 0.41 0.48 ns
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.32 0.37 0.43 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-60 Revision 10
DDR Module Specifications
Input DDR Module
Figure 2-30 • Input DDR Timing Model
Table 2-89 • Parameter Definitions
Parameter Name Parameter Definition Measuring Nodes (from, to)
tDDRICLKQ1 Clock-to-Out Out_QR B, D
tDDRICLKQ2 Clock-to-Out Out_QF B, E
tDDRISUD Data Setup Time of DDR input A, B
tDDRIHD Data Hold Time of DDR input A, B
tDDRICLR2Q1 Clear-to-Out Out_QR C, D
tDDRICLR2Q2 Clear-to-Out Out_QF C, E
tDDRIREMCLR Clear Removal C, B
tDDRIRECCLR Clear Recovery C, B
Input DDR
Data
CLK
CLKBUF
INBUF Out_QF
(to core)
FF2
FF1
INBUF
CLR
DDR_IN
E
A
B
C
D
Out_QR
(to core)
ProASIC3E Flash Family FPGAs
Revision 10 2-61
Timing Characteristics
Figure 2-31 • Input DDR Timing Diagram
t
DDRICLR2Q2
t
DDRIREMCLR
t
DDRIRECCLR
t
DDRICLR2Q1
12 3 4 5 6 7 8 9
CLK
Data
CLR
Out_QR
Out_QF
t
DDRICLKQ1
246
357
t
DDRIHD
t
DDRISUD
t
DDRICLKQ2
Table 2-90 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tDDRICLKQ1 Clock -to-Out Out_QR for Input DDR 0.39 0.44 0.52 ns
tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.27 0.31 0.37 ns
tDDRISUD Data Setup for Input DDR 0.28 0.32 0.38 ns
tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 ns
tDDRICLR2Q1 Asynchronous Clear to Out Out_QR for Input DDR 0.57 0.65 0.76 ns
tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.46 0.53 0.62 ns
tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 0.00 ns
tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.22 0.25 0.30 ns
tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 ns
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 ns
FDDRIMAX Maximum Frequency for Input DDR 1404 1232 1048 MHz
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-62 Revision 10
Output DDR Module
Figure 2-32 • Output DDR Timing Model
Table 2-91 • Parameter Definitions
Parameter Name Parameter Definition Measuring Nodes (from, to)
tDDROCLKQ Clock-to-Out B, E
tDDROCLR2Q Asynchronous Clear-to-Out C, E
tDDROREMCLR Clear Removal C, B
tDDRORECCLR Clear Recovery C, B
tDDROSUD1 Data Setup Data_F A, B
tDDROSUD2 Data Setup Data_R D, B
tDDROHD1 Data Hold Data_F A, B
tDDROHD2 Data Hold Data_R D, B
Data_F
(from core)
CLK CLKBUF
Out
FF2
INBUF
CLR
DDR_OUT
Output DDR
FF1
0
1
X
X
X
X
X
X
X
A
B
D
E
C
C
B
OUTBUF
Data_R
(from core)
ProASIC3E Flash Family FPGAs
Revision 10 2-63
Timing Characteristics
Figure 2-33 • Output DDR Timing Diagram
116
1
7
2
8
3
910
45
28 3 9
t
DDROREMCLR
t
DDROHD1
t
DDROREMCLR
t
DDROHD2
t
DDROSUD2
t
DDROCLKQ
t
DDRORECCLR
CLK
Data_R
Data_F
CLR
Out
t
DDROCLR2Q
7104
Table 2-92 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns
tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns
tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns
tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns
tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns
tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns
tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns
tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns
tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns
tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 0.41 0.48 ns
tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 0.37 0.43 ns
FDDOMAX Maximum Frequency for the Output DDR 1404 1232 1048 MHz
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-64 Revision 10
VersaTile Characteristics
Ve rsaTile Specifications as a Combinatorial Module
The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e,
and ProASIC3/E Macro Library Guide.
Figure 2-34 • Sample of Combinatorial Cells
MAJ3
A
C
BY
MUX2
B
0
1
A
S
Y
AY
B
B
AXOR2 Y
NOR2
B
AY
B
AYOR2
INV
AY
AND2
B
AY
NAND3
B
A
C
XOR3 Y
B
A
C
NAND2
ProASIC3E Flash Family FPGAs
Revision 10 2-65
Figure 2-35 • Timing Mode l and Waveforms
tPD
A
B
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR))
where edges are applicable for the particular
combinatorial cell
Y
NAND2 or
Any Combinatorial
Logic
tPD
tPD
50%
VCC
VCC
VCC
50%
GND
A, B, C 50% 50%
50%
(RR)
(RF) GND
OUT
OUT
GND
50%
(FF)
(FR)
tPD
tPD
ProASIC3E DC and Switching Characteristics
2-66 Revision 10
Timing Characteristics
Ve rsaTile Specifications as a Sequential Module
The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each has
a data input and optional enable, clear, or preset. In this section , timing characteristi cs are p resented for
a representative sample from the library . For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Macro Library Guide.
Table 2-93 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell Equation Parameter –2 –1 Std. Units
INV Y = !A tPD 0.40 0.46 0.54 ns
AND2 Y = A · B tPD 0.47 0.54 0.63 ns
NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 ns
OR2 Y = A + B tPD 0.49 0.55 0.65 ns
NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 ns
XOR2 Y = A Bt
PD 0.74 0.84 0.99 ns
MAJ3 Y = MAJ(A , B, C) tPD 0.70 0.79 0.93 ns
XOR3 Y = A B Ct
PD 0.87 1.00 1.17 ns
MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 ns
AND3 Y = A · B · C tPD 0.56 0.64 0.75 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
Figure 2- 36 Sample of Sequential Cells
DQ
DFN1
Data
CLK
Out
DQ
DFN1C1
Data
CLK
Out
CLR
DQ
DFI1E1P1
Data
CLK
Out
En
PRE
DQ
DFN1E1
Data
CLK
Out
En
ProASIC3E Flash Family FPGAs
Revision 10 2-67
Timing Characteristics
Figure 2-37 • Timing Mode l and Waveforms
PRE
CLR
Out
CLK
Data
EN
t
SUE
50%
50%
t
SUD
t
HD
50% 50%
t
CLKQ
0
t
HE
t
RECPRE
t
REMPRE
t
RECCLR
t
REMCLR
t
WCLR
t
WPRE
t
PRE2Q
t
CLR2Q
t
CKMPWH
t
CKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
50%
Table 2-94 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 ns
tSUD Dat a Set up Time for the Core Register 0.43 0.49 0.57 ns
tHD Data Hold Time for the Core Register 0.00 0.00 0.00 ns
tSUE Enable Setu p Time for the Core Regist er 0.45 0.52 0.61 ns
tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 ns
tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 ns
tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 ns
tREMCLR Asynchronous Clear Removal Time for the Core Registe r 0.00 0.00 0.00 ns
tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 ns
tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 ns
tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 ns
tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns
tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0 .22 0.25 0.30 ns
tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.32 0.37 0.43 ns
tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.36 0.41 0.48 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-68 Revision 10
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-38 is an example of a global tree used for cl ock routing. The
global tree presented in Figure 2-38 is driven by a CCC located on the west side of the A3PE600 device.
It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as th ese are I/O standard–depe nde nt, and th e cl ock may be d riven
and conditioned i nternally by the CCC mo dule. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-70. Table 2-95 on page 2-69, Table 2-96 on
page 2-69, and Tab le 2-97 on page 2-69 present minimum and maximum g lobal clock delays within the
device. Minimum and ma ximum delays are measured with minimum and maximum loading.
Figure 2-38 • Examp le of Global Tree Use in an A3PE600 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
ProASIC3E Flash Family FPGAs
Revision 10 2-69
Timing Characteristics
Table 2-95 • A3PE600 Global Resou rce
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description
–2 –1 Std.
UnitsMin.1Max.2Min.1Max.2Min.1Max.2
tRCKL Input Low Delay for Global Clock 0.83 1.04 0.94 1.18 1.11 1.39 ns
tRCKH Input High Delay for Global Clock 0.81 1.06 0.93 1.21 1.09 1.42 ns
tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns
tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns
tRCKSW Maximum Skew for Global Clock 0.25 0.28 0.33 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflect s maximum lo ad. The del ay is measu red on the cl ock pin of the fart hest seq uential el ement, located i n a full y
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-96 • A3PE1500 Glob al Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description
–2 –1 Std.
UnitsMin.1Max.2Min.1Max.2Min.1Max.2
tRCKL Input Low Delay for Global Clock 1.071.291.221.471.431.72 ns
tRCKH Input High Delay for Global Clock 1.061.321.211.501.421.76 ns
tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns
tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns
tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maxi mum load. The delay is meas ured on the clock pin of the farthest sequenti al element, located in a full y
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-97 • A3PE3000 Glob al Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description
–2 –1 Std.
UnitsMin.1Max.2Min.1Max.2Min.1Max.2
tRCKL Input Low Delay for Global Clock 1.411.621.601.851.882.17 ns
tRCKH Input High Delay for Global Clock 1.401.661.591.891.872.22 ns
tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns
tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns
tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.35 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maxi mum load. The delay is meas ured on the clock pin of the farthest sequenti al element, located in a full y
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-70 Revision 10
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-98 • ProASIC3E CCC/PLL Specification
Parameter Minimum Typical Maximum Units
Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz
Delay Increments in Programmable Delay Blocks1, 2 1603ps
Serial Clock (SCLK) for Dynamic PLL4125 MHz
Number of Programmable Values in Each
Programmable Delay Block 32
Input Period Jitter 1.5 ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter
1 Global
Network Used 3 Gl obal
Networks Used
0.75 MHz to 24 MHz 0.50% 0.70%
24 MHz to 100 MHz 1.00% 1 .20%
100 MHz to 250 MHz 1.75% 2.00%
250 MHz to 350 MHz 2.50% 5.60%
Acquisition Time LockControl = 0 300 µs
LockControl = 1 6.0 ms
Tracking Jitter 5 LockControl = 0 1.6 ns
LockControl = 1 0.8 ns
Output Duty Cycle 48.5 51.5 %
Delay Range in Block: Programmable Delay 11, 2 0.6 5.56 ns
Delay Range in Block: Programmable Delay 2 1,2 0.025 5.56 ns
Delay Range in Block: Fixed Delay1,4 2.2 ns
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings
2. TJ = 25°C, VCC = 1.5 V.
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
ProASIC3E Flash Family FPGAs
Revision 10 2-71
Note: Peak-to-peak jitter measurements are defi ned by T peak-to-peak = Tperiod_max – Tperiod_min.
Figure 2-39 • Peak-to-Peak Jitter Definition
T
period_max
T
period_min
Output Signal
ProASIC3E DC and Switching Characteristics
2-72 Revision 10
Embedded SRAM and FIFO Characteristics
SRAM
Figure 2- 40 RAM Models
ADDRA11 DOUTA8
DOUTA7
DOUTA0
DOUTB8
DOUTB7
DOUTB0
ADDRA10
ADDRA0
DINA8
DINA7
DINA0
WIDTHA1
WIDTHA0
PIPEA
WMODEA
BLKA
WENA
CLKA
ADDRB11
ADDRB10
ADDRB0
DINB8
DINB7
DINB0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
RAM4K9
RADDR8 RD17
RADDR7 RD16
RADDR0 RD0
WD17
WD16
WD0
WW1
WW0
RW1
RW0
PIPE
REN
RCLK
RAM512X18
WADDR8
WADDR7
WADDR0
WEN
WCLK
RESET
RESET
ProASIC3E Flash Family FPGAs
Revision 10 2-73
Timing Waveforms
Figure 2-41 • RAM Read for Pass-Through Output. Applicable to Bo th RAM4K9 and RAM512x18.
Figure 2-42 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
CLK
[R|W]ADDR
BLK
WEN
DOUT|RD
A0A1A2
D0D1D2
tCYC
tCKH tCKL
tAS tAH
tBKS
tENS tENH
tDOH1
tBKH
Dn
tCKQ1
CLK
[R|W]ADDR
BLK
WEN
DOUT|RD
A0A1A2
D0D1
tCYC
tCKH tCKL
tAS tAH
tBKS
tENS tENH
tDOH2
tCKQ2
tBKH
Dn
ProASIC3E DC and Switching Characteristics
2-74 Revision 10
Figure 2-43 • RAM Write, Output Retained . Applicable to Both RAM4K9 and RAM512x18.
Figure 2-44 • RAM Write, Output as Write Data. Applicable to RAM4K9 Only.
tCYC
tCKH tCKL
A0A1A2
DI0DI1
tAS tAH
tBKS
tENS tENH
tDS tDH
CLK
BLK
WEN
[R|W]ADDR
DIN|WD
Dn
DOUT|RD
tBKH
D2
tCYC
tCKH tCKL
A0A1A2
DI0DI1
tAS tAH
tBKS
tENS
tDS tDH
CLK
BLK
WEN
ADDR
DIN
tBKH
DOUT
(pass-through) DI1
DnDI0
DOUT
(pipelined) DI0DI1
Dn
DI2
ProASIC3E Flash Family FPGAs
Revision 10 2-75
Figure 2-45 • RAM Reset. Applicable to Both RAM4K9 and RAM5 12x18.
CLK
RESET
DOUT|RD D
n
t
CYC
t
CKH
t
CKL
t
RSTBQ
D
m
ProASIC3E DC and Switching Characteristics
2-76 Revision 10
Timing Characteristics
Table 2-99 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tAS Address setup time 0.25 0.28 0.33 ns
tAH Address hold time 0.00 0.00 0.00 ns
tENS REN, WEN setup time 0.14 0.16 0.19 ns
tENH REN, WEN hold time 0.10 0.11 0.13 ns
tBKS BLK setup time 0.23 0.27 0.31 ns
tBKH BLK hold time 0.02 0.02 0.02 ns
tDS Input data (DIN) setup time 0.18 0.21 0.25 ns
tDH Input data (DIN) hold time 0.00 0.00 0.00 ns
tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 1.79 2.03 2.39 ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.36 2.68 3.15 ns
tCKQ2 Clock High to new data valid on DOUT (pipelined) 0.89 1.02 1.20 ns
tC2CWWL1Address collision clk-to-clk delay for reliable write after write on same
address—Applicable to Closing Edge 0.33 0.28 0.25 ns
tC2CWWH1Address collision clk-to-clk delay for reliable write after write on same
address—Applicable to Rising Edge 0.30 0.26 0.23 ns
tC2CRWH1Address collision clk-to-clk delay for reliable read access after write on same
address—Applicable to Opening Edge 0.45 0.38 0.34 ns
tC2CWRH1Address collision clk-to-clk delay for relia ble write a ccess after read on same
address— Applicable to Openi ng Edge 0.49 0.42 0.37 ns
tRSTBQ RESET Low to data out Low on DO (flow-through) 0.92 1.05 1.23 ns
RESET Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 ns
tREMRSTB RESET removal 0.29 0.33 0.38 ns
tRECRSTB RESET recovery 1.50 1.71 2.01 ns
tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns
tCYC Clock cycle time 3.23 3.68 4.32 ns
FMAX Maximum frequency 310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E Flash Family FPGAs
Revision 10 2-77
Table 2-100 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tAS Address setup time 0.25 0.28 0.33 ns
tAH Address hold time 0.00 0.00 0.00 ns
tENS REN, WEN setup time 0.18 0.20 0.24 ns
tENH REN, WEN hold time 0.06 0.07 0.08 ns
tDS Input data (WD) setup time 0.18 0.21 0.25 ns
tDH Input data (WD) hold time 0.00 0.00 0.00 ns
tCKQ1 Clock High to new data valid on RD (output retained) 2.16 2.46 2.89 ns
tCKQ2 Clock High to new data valid on RD (pipelined) 0.90 1.02 1.20 ns
tC2CRWH1Address collision clk-to-clk delay for reliable read access after write on same
address—Applicable to Opening Edge 0.50 0.43 0.38 ns
tC2CWRH1Address collision clk-to-clk delay for reliable write access after read on same
address— Applicable to Opening Edge 0.59 0.50 0.44 ns
tRSTBQ RESET Low to data out Low on RD (flow-through) 0.92 1.05 1.23 ns
RESET Low to data out Low on RD (pipelined) 0.92 1.05 1.23 ns
tREMRSTB RESET removal 0.29 0.33 0.38 ns
tRECRSTB RESET recovery 1.50 1.71 2.01 ns
tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns
tCYC Clock cycle time 3.23 3.68 4.32 ns
FMAX Maximum frequency 310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-78 Revision 10
FIFO
Figure 2- 46 FIFO Model
FIFO4K18
RW2
RD17
RW1
RD16
RW0
WW2
WW1
WW0 RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AFVAL11
AEMPTY
AFVAL10
AFVAL0
AEVAL11
AEVAL10
AEVAL0
REN
RBLK
RCLK
WEN
WBLK
WCLK
RPIPE
WD17
WD16
WD0
RESET
ProASIC3E Flash Family FPGAs
Revision 10 2-79
Timing Waveforms
Figure 2-47 • FIF O Rese t
Figure 2-48 • FIF O EMPT Y Fl ag and AEMPTY Flag Assertion
MATCH (A0)
tMPWRSTB
tRSTFG
tRSTCK
tRSTAF
RCLK/
WCLK
RESET
EMPTY
AEMPTY
WA/RA
(Address Counter)
tRSTFG
tRSTAF
FULL
AFULL
RCLK
NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)
tCKAF
tRCKEF
EMPTY
AEMPTY
tCYC
WA/RA
(Address Counter)
ProASIC3E DC and Switching Characteristics
2-80 Revision 10
Figure 2-49 • FIFO FULL Flag and AFULL Flag Assertion
Figure 2-50 • FIF O EMPT Y Flag and AEMPTY Flag Deassertion
Figure 2-51 • FIF O FUL L F la g an d AFULL Flag Deassertion
NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)
tCKAF
tWCKFF
tCYC
WCLK
FULL
AFULL
WA/RA
(Address Counter)
WCLK
WA/RA
(Address Counter) MATCH
(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1
NO MATCH
RCLK
EMPTY
1st Rising
Edge
After 1st
Write
2nd Rising
Edge
After 1st
Write t
RCKEF
t
CKAF
AEMPTY
Dist = AFF_TH – 1
MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH
t
WCKF
t
CKAF
1st Rising
Edge
After 1st
Read
1st Rising
Edge
After 2nd
Read
RCLK
WA/RA
(Address Counter)
WCLK
FULL
AFULL
ProASIC3E Flash Family FPGAs
Revision 10 2-81
Timing Characteristics
Table 2-101 • FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tENS REN, WEN Setup Time 1.38 1.57 1.84 ns
tENH REN, WEN Hold Time 0.02 0.02 0.02 ns
tBKS BLK Setup T ime 0.19 0.22 0.26 ns
tBKH BLK Hold Time 0.00 0.00 0.00 ns
tDS Input Data (WD) Setup Ti me 0.18 0.21 0.25 ns
tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns
tCKQ1 Clock High to New Data Valid on RD (pass-through) 2.36 2.68 3.15 ns
tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.89 1.02 1.20 ns
tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns
tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 n s
tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns
tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns
tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns
tRSTBQ RESET Low to Data Out Low on RD (pass-through) 0.92 1.05 1.23 ns
RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns
tREMRSTB RESET Removal 0.29 0.33 0.38 ns
tRECRSTB RESET Recovery 1.50 1.71 2.01 ns
tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns
tCYC Clock Cycle Time 3.23 3.68 4.32 ns
FMAX Maximum Frequency 310 272 231 MHz
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
ProASIC3E DC and Switching Characteristics
2-82 Revision 10
Embedded FlashROM Characteristics
Timing Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not incl ude JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-13 for more details.
Timing Characteristics
Figure 2-52 • Timing Diagram
A
0
A
1
t
SU
t
HOLD
t
SU
t
HOLD
t
SU
t
HOLD
t
CKQ2
t
CKQ2
t
CKQ2
CLK
Address
Data D
0
D
0
D
1
Table 2-102 • Embedded FlashROM Access Time
Parameter Description –2 –1 Std. Units
tSU Address Setup Time 0.53 0.61 0 .71 ns
tHOLD Address Hold Time 0.00 0.00 0.00 ns
tCK2Q Clock to Out 16.23 18.48 21.73 ns
FMAX Maximum Clock Frequency 15 15 15 MHz
Table 2-103 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description –2 –1 Std. Units
tDISU Test Data Input Setup Time 0.50 0.57 0.67 ns
tDIHD Test Data Input Hold Time 1.00 1.13 1.33 ns
tTMSSU Test Mode Select Setup Time 0.50 0.57 0.67 ns
tTMDHD Test Mode Select Hold Time 1.00 1.13 1.33 ns
tTCK2Q Clock to Q (data out) 6.00 6.80 8.00 n s
tRSTB2Q Reset to Q (data out) 20.00 22.67 26.67 ns
FTCKMAX TCK Maximum Frequency 25.00 22.00 19.00 MHz
tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns
tTRSTREC ResetB Recovery Time 0.20 0.23 0.27 ns
tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 10 3-1
3 – Pin Descriptions and Packaging
Supply Pins
GND Ground
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous sw itching noise orig inated from the outpu t buffer ground domain. This
minimizes the noise transfer within th e package and improves input signal in tegrity. GNDQ must always
be connected to GND on the board.
VCC Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine
in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of intercon nected devices,
both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.
VCCIBx I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied
to GND.
VMVx I/O Supply Volt age (quiet)
Quiet supply voltage to the input b uffers of each I/O bank. x is the bank number. Within the package, the
VMV plane is decoupled from th e simultaneous switching noise originating from the output buffer VCCI
domain. This minimizes the noise transfer within the package and improves input signal integrity. Each
bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank
run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each
I/O b ank . V MV x ca n be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their
corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O
bank. Used VMV pins must be connected to the corre sponding VCCI pins of th e same bank (i.e., VMV0
to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V.
When the PLLs are not used, th e place-and-route tool automatically disable s the unused PLLs to lower
power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi
recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the
PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low
Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide
for a complete board solution for the PLL analog power supply and ground.
There are six VCCPLX pins on ProASIC3E devices.
VCOMPLA/B/C/D/E/F PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool
automatically disables the unused PLLs to lower power consumption. The user should tie unused
VCCPLx and VCOMPLx pins to ground.
There are six VCOMPL pins (PLL ground) on ProASIC3E devices.
VJTAG JTAG Supply Voltage
Low power flash devices ha ve a separate bank for the dedicated JTAG pins. T he JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor plann ed for use, the VJ TAG p in together w ith the TRST pi n could be tied to
Pin Descriptions and Packaging
3-2 Revision 10
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
insufficient. If a device is in a JTAG chain o f interconnected board s, the board containing the device can
be powered down, provided b oth VJTA G and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP Programming Supply Volta ge
For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled u p) to any voltage between 0 V and the VPUMP ma ximum. Programming
power supply voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User-Defined Supply Pins
VREF I/O Voltage Reference
Reference voltage for I/O minibanks. VREF pins are configured by the user from regular I/Os, and any
I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards
require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One
VREF pin can support the numbe r of I/Os available in its minibank.
User Pins
I/O User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide. All
inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an
input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled
GC/GF are direct inputs into the chip-level globals, and th e rest are connected to the quadrant globals.
The inputs to the global network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the ProASIC3E FPGA Fabric User’s Guide for an explanation of the
naming of global pins.
ProASIC3E Flash Family FPGAs
Revision 10 3-3
JTAG Pins
Low power flash devices ha ve a separate bank for the dedicated JTAG pins. T he JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neith er u sed nor pl anned for use , the VJTAG pin together with the T RST
pin could be tied to GND.
TCK Test Clock
Test clock input for JTAG bou ndary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is n ot used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 W to 1 kΩ will satisfy the requirements. Refer to
Table 3-1 for more information.
TDI Test Data Input
Serial input for JTAG bound ary scan, ISP, and UJTAG usag e. There is an internal weak pull-up resistor
on the TDI pin.
TDO Test Data Output
Serial output for JTAG bound ary scan, ISP, and UJTAG usage.
TMS Test Mode Select
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST Boundary Scan Reset Pin
The TRST pin fun ctions as an active-low inpu t to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be include d to ensure the test access port (TAP) is held in reset mode . The resistor
values must be chosen from Table 3-1 and must satisfy the parallel resistance value requirement. The
values in Table 3-1 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circui t could allow en trance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements.
Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG Tie-Off Resistance
VJTAG at 3.3 V 200 Ω to 1 kΩ
VJTAG at 2.5 V 200 Ω to 1 kΩ
VJTAG at 1.8 V 500 Ω to 1 kΩ
VJTAG at 1.5 V 500 Ω to 1 kΩ
Notes:
1. Equivalent parallel resistance if more than one device is on the JTAG chain
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled do wn.
Pin Descriptions and Packaging
3-4 Revision 10
Special Function Pins
NC No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To ena ble next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs wi th large-p in-count Bal l Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Microsemi offers a variety of p ackages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
Related Documents
Users Guides
ProASIC3E FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/PA3E_UG.pdf
Packaging
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 10 4-1
4 – Package Pin Assignment s
PQ208
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Note: This is the top view of the package.
208-Pin PQFP
1208
Package Pin Assignments
4-2 Revision 10
PQ208
Pin Number A3PE600 Function
1GND
2 GNDQ
3VMV7
4 GAB2/IO133PSB7V1
5 GAA2/IO134PDB7V1
6 IO134NDB7V1
7 GAC2/IO132PDB7V1
8 IO132NDB7V1
9 IO130PDB7V1
10 IO130NDB7V1
11 IO127PDB7V1
12 IO127NDB7V1
13 IO126PDB7V0
14 IO126NDB7V0
15 IO124PSB7V0
16 VCC
17 GND
18 VCCIB7
19 IO122PPB7V0
20 IO121PSB7V0
21 IO122NPB7V0
22 GFC1/IO120PSB7V0
23 GFB1/IO119PDB7V0
24 GFB0/IO119NDB7V0
25 VCOMPLF
26 GFA0/IO118NPB6V1
27 VCCPLF
28 GFA1/IO118PPB6V1
29 GND
30 GFA2/IO117PDB6V1
31 IO117NDB6V1
32 GFB2/IO116PPB6V1
33 GFC2/IO115PPB6V1
34 IO116NPB6V1
35 IO115NPB6V1
36 VCC
37 IO112PDB6V1
38 IO112NDB6V1
39 IO108PSB6V0
40 VCCIB6
41 GND
42 IO106PDB6V0
43 IO106NDB6V0
44 GEC1/IO104PDB6V0
45 GEC0/IO104NDB6V
0
46 GEB1/IO103PPB6V0
47 GEA1/IO102PPB6V0
48 GEB0/IO103NPB6V0
49 GEA0/IO102NPB6V0
50 VMV6
51 GNDQ
52 GND
53 VMV5
54 GNDQ
55 IO101NDB5V2
56 GEA2/IO101PDB5V2
57 IO100NDB5V2
58 GEB2/IO100PDB5V2
59 IO99NDB5V2
60 GEC2/IO99PDB5V2
61 IO98PSB5V2
62 VCCIB5
63 IO96PSB5V2
64 IO94NDB5V1
65 GND
66 IO94PDB5V1
67 IO92NDB5V1
68 IO92PDB5V1
69 IO88NDB5V0
70 IO88PDB5V0
71 VCC
PQ208
Pin Number A3PE600 Fu nc tion
72 VCCIB5
73 IO85NPB5V0
74 IO84NPB5V0
75 IO85PPB5V0
76 IO84PPB5V0
77 IO83NPB5V0
78 IO82NPB5V0
79 IO83PPB5V0
80 IO82PPB5V0
81 GND
82 IO80NDB4V1
83 IO80PDB4V1
84 IO79NPB4V1
85 IO78NPB4V1
86 IO79PPB4V1
87 IO78PPB4V1
88 VCC
89 VCCIB4
90 IO76NDB4V1
91 IO76PDB4V1
92 IO72NDB4V0
93 IO72PDB4V0
94 IO70NDB4V0
95 GDC2/IO70PDB4V0
96 IO68NDB4V0
97 GND
98 GDA2/IO68PDB4V0
99 GDB2/IO69PSB4V0
100 GNDQ
101 TCK
102 TDI
103 TMS
104 VMV4
105 GND
106 VPUMP
107 GNDQ
PQ208
Pin Number A3PE600 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-3
108 TDO
109 TRST
110 VJTAG
111 VMV3
112 GDA0/IO67NPB3V1
113 GDB0/IO66NPB3V1
114 GDA1/IO67PPB3V1
115 GDB1/IO66PPB3V1
116 GDC0/IO65NDB3V1
117 GDC1/IO65PDB3V1
118 IO62NDB3V1
119 IO62PDB3V1
120 IO58NDB3V0
121 IO58PDB3V0
122 GND
123 VCCIB3
124 GCC2/IO55PSB3V0
125 GCB2/IO54PSB3V0
126 NC
127 IO53NDB3V0
128 GCA2/IO53PDB3V0
129 GCA1/IO52PPB3V0
130 GND
131 VCCPLC
132 GCA0/IO52NPB3V0
133 VCOMPLC
134 GCB0/IO51NDB2V1
135 GCB1/IO51PDB2V1
136 GCC1/IO50PSB2V1
137 IO49NDB2V1
138 IO49PDB2V1
139 IO48PSB2V1
140 VCCIB2
141 GND
142 VCC
143 IO47NDB2V1
PQ208
Pin Number A3PE600 Function
144 IO47PDB2V1
145 IO44NDB2V1
146 IO44PDB2V1
147 IO43NDB2V0
148 IO43PDB2V0
149 IO40NDB2V0
150 IO40PDB2V0
151 GBC2/IO38PSB2V0
152 GBA2/IO36PSB2V0
153 GBB2/IO37PSB2V0
154 VMV2
155 GNDQ
156 GND
157 VMV1
158 GNDQ
159 GBA1/IO35PDB1V1
160 GBA0/IO35NDB1V1
161 GBB1/IO34PDB1V1
162 GND
163 GBB0/IO34NDB1V1
164 GBC1/IO33PDB1V1
165 GBC0/IO33NDB1V1
166 IO31PDB1V1
167 IO31NDB1V1
168 IO27PDB1V0
169 IO27NDB1V0
170 VCCIB1
171 VCC
172 IO23PPB1V0
173 IO22PSB1V0
174 IO23NPB1V0
175 IO21PDB1V0
176 IO21NDB1V0
177 IO19PPB0V2
178 GND
179 IO18PPB0V2
PQ208
Pin Number A3PE600 Fu nc tion
180 IO19NPB0V2
181 IO18NPB0V2
182 IO17PPB0V2
183 IO16PPB0V2
184 IO17NPB0V2
185 IO16NPB0V2
186 VCCIB0
187 VCC
188 IO15PDB0V2
189 IO15NDB0V2
190 IO13PDB0V2
191 IO13NDB0V2
192 IO11PSB0V1
193 IO09PDB0V1
194 IO09NDB0V1
195 GND
196 IO07PDB0V1
197 IO07NDB0V1
198 IO05PDB0V0
199 IO05NDB0V0
200 VCCIB0
201 GAC1/IO02PDB0V0
202 GAC0/IO02NDB0V0
203 GAB1/IO01PDB0V0
204 GAB0/IO01NDB0V0
205 GAA1/IO00PDB0V0
206 GAA0/IO00NDB0V0
207 GNDQ
208 VMV0
PQ208
Pin Number A3PE600 Function
Package Pin Assignments
4-4 Revision 10
PQ208
Pin Number A3PE1500 Function
1GND
2 GNDQ
3VMV7
4 GAB2/IO220PSB7V3
5 GAA2/IO221PDB7V3
6 IO221NDB7V3
7 GAC2/IO219PDB7V3
8 IO219NDB7V3
9 IO215PDB7V3
10 IO215NDB7V3
11 IO212PDB7V2
12 IO212NDB7V2
13 IO208PDB7V2
14 IO208NDB7V2
15 IO204PSB7V1
16 VCC
17 GND
18 VCCIB7
19 IO200PDB7V1
20 IO200NDB7V1
21 IO196PSB7V0
22 GFC1/IO192PSB7V0
23 GFB1/IO191PDB7V0
24 GFB0/IO191NDB7V0
25 VCOMPLF
26 GFA0/IO190NPB6V2
27 VCCPLF
28 GFA1/IO190PPB6V2
29 GND
30 GFA2/IO189PDB6V2
31 IO189NDB6V2
32 GFB2/IO188PPB6V2
33 GFC2/IO187PPB6V2
34 IO188NPB6V2
35 IO187NPB6V2
36 VCC
37 IO184PDB6V2
38 IO184NDB6V2
39 IO180PSB6V1
40 VCCIB6
41 GND
42 IO176PDB6V1
43 IO176NDB6V1
44 GEC1/IO169PDB6V0
45 GEC0/IO169NDB6V0
46 GEB1/IO168PPB6V0
47 GEA1/IO167PPB6V0
48 GEB0/IO168NPB6V0
49 GEA0/IO167NPB6V0
50 VMV6
51 GNDQ
52 GND
53 VMV5
54 GNDQ
55 IO166NDB5V3
56 GEA2/IO166PDB5V3
57 IO165NDB5V3
58 GEB2/IO165PDB5V3
59 IO164NDB5V3
60 GEC2/IO164PDB5V3
61 IO163PSB5V3
62 VCCIB5
63 IO161PSB5V3
64 IO157NDB5V2
65 GND
66 IO157PDB5V2
67 IO153NDB5V2
68 IO153PDB5V2
69 IO149NDB5V1
70 IO149PDB5V1
71 VCC
72 VCCIB5
PQ208
Pin Number A3PE1500 Function
73 IO145NDB5V1
74 IO145PDB5V1
75 IO143NDB5V1
76 IO143PDB5V1
77 IO137NDB5V0
78 IO137PDB5V0
79 IO135NDB5V0
80 IO135PDB5V0
81 GND
82 IO131NDB4V2
83 IO131PDB4V2
84 IO129NDB4V2
85 IO129PDB4V2
86 IO127NDB4V2
87 IO127PDB4V2
88 VCC
89 VCCIB4
90 IO121NDB4V1
91 IO121PDB4V1
92 IO119NDB4V1
93 IO119PDB4V1
94 IO113NDB4V0
95 GDC2/IO113PDB4V0
96 IO112NDB4V0
97 GND
98 GDB2/IO112PDB4V0
99 GDA2/IO111PSB4V0
100 GNDQ
101 TCK
102 TDI
103 TMS
104 VMV4
105 GND
106 VPUMP
107 GNDQ
108 TDO
PQ208
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-5
109 TRST
110 VJTAG
111 VMV3
112 GDA0/IO110NPB3V2
113 GDB0/IO109NPB3V2
114 GDA1/IO110PPB3V2
115 GDB1/IO109PPB3V2
116 GDC0/IO108NDB3V2
117 GDC1/IO108PDB3V2
118 IO105NDB3V2
119 IO105PDB3V2
120 IO101NDB3V1
121 IO101PDB3V1
122 GND
123 VCCIB3
124 GCC2/IO90PSB3V0
125 GCB2/IO89PSB3V0
126 NC
127 IO88NDB3V0
128 GCA2/IO88PDB3V0
129 GCA1/IO87PPB3V0
130 GND
131 VCCPLC
132 GCA0/IO87NPB3V0
133 VCOMPLC
134 GCB0/IO86NDB2V3
135 GCB1/IO86PDB2V3
136 GCC1/IO85PSB2V3
137 IO83NDB2V3
138 IO83PDB2V3
139 IO81PSB2V3
140 VCCIB2
141 GND
142 VCC
143 IO73NDB2V2
144 IO73PDB2V2
PQ208
Pin Number A3PE1500 Function
145 IO71NDB2V2
146 IO71PDB2V2
147 IO67NDB2V1
148 IO67PDB2V1
149 IO65NDB2V1
150 IO65PDB2V1
151 GBC2/IO60PSB2V0
152 GBA2/IO58PSB2V0
153 GBB2/IO59PSB2V0
154 VMV2
155 GNDQ
156 GND
157 VMV1
158 GNDQ
159 GBA1/IO57PDB1V3
160 GBA0/IO57NDB1V3
161 GBB1/IO56PDB1V3
162 GND
163 GBB0/IO56NDB1V3
164 GBC1/IO55PDB1V3
165 GBC0/IO55NDB1V3
166 IO51PDB1V2
167 IO51NDB1V2
168 IO47PDB1V1
169 IO47NDB1V1
170 VCCIB1
171 VCC
172 IO43PSB1V1
173 IO41PDB1V1
174 IO41NDB1V1
175 IO35PDB1V0
176 IO35NDB1V0
177 IO31PDB0V3
178 GND
179 IO31NDB0V3
180 IO29PDB0V3
PQ208
Pin Number A3PE1500 Function
181 IO29NDB0V3
182 IO27PDB0V3
183 IO27NDB0V3
184 IO23PDB0V2
185 IO23NDB0V2
186 VCCIB0
187 VCC
188 IO18PDB0V2
189 IO18NDB0V2
190 IO15PDB0V1
191 IO15NDB0V1
192 IO12PSB0V1
193 IO11PDB0V1
194 IO11NDB0V1
195 GND
196 IO08PDB0V1
197 IO08NDB0V1
198 IO05PDB0V0
199 IO05NDB0V0
200 VCCIB0
201 GAC1/IO02PDB0V0
202 GAC0/IO02NDB0V0
203 GAB1/IO01PDB0V0
204 GAB0/IO01NDB0V0
205 GAA1/IO00PDB0V0
206 GAA0/IO00NDB0V0
207 GNDQ
208 VMV0
PQ208
Pin Number A3PE1500 Function
Package Pin Assignments
4-6 Revision 10
PQ208
Pin Number A3PE3000 Functio n
1GND
2 GNDQ
3VMV7
4 GAB2/IO308PSB7V4
5 GAA2/IO309PDB7V4
6 IO309NDB7V4
7 GAC2/IO307PDB7V4
8 IO307NDB7V4
9 IO303PDB7V3
10 IO303NDB7V3
11 IO299PDB7V3
12 IO299NDB7V3
13 IO295PDB7V2
14 IO295NDB7V2
15 IO291PSB7V2
16 VCC
17 GND
18 VCCIB7
19 IO285PDB7V1
20 IO285NDB7V1
21 IO279PSB7V0
22 GFC1/IO275PSB7V0
23 GFB1/IO274PDB7V0
24 GFB0/IO274NDB7V0
25 VCOMPLF
26 GFA0/IO273NPB6V4
27 VCCPLF
28 GFA1/IO273PPB6V4
29 GND
30 GFA2/IO272PDB6V4
31 IO272NDB6V4
32 GFB2/IO271PPB6V4
33 GFC2/IO270PPB6V4
34 IO271NPB6V4
35 IO270NPB6V4
36 VCC
37 IO252PDB6V2
38 IO252NDB6V2
39 IO248PSB6V1
40 VCCIB6
41 GND
42 IO244PDB6V1
43 IO244NDB6V1
44 GEC1/IO236PDB6V0
45 GEC0/IO236NDB6V0
46 GEB1/IO235PPB6V0
47 GEA1/IO234PPB6V0
48 GEB0/IO235NPB6V0
49 GEA0/IO234NPB6V0
50 VMV6
51 GNDQ
52 GND
53 VMV5
54 GNDQ
55 IO233NDB5V4
56 GEA2/IO233PDB5V4
57 IO232NDB5V4
58 GEB2/IO232PDB5V4
59 IO231NDB5V4
60 GEC2/IO231PDB5V4
61 IO230PSB5V4
62 VCCIB5
63 IO218NDB5V3
64 IO218PDB5V3
65 GND
66 IO214PSB5V2
67 IO212NDB5V2
68 IO212PDB5V2
69 IO208NDB5V1
70 IO208PDB5V1
71 VCC
72 VCCIB5
73 IO202NDB5V1
74 IO202PDB5V1
75 IO198NDB5V0
76 IO198PDB5V0
77 IO197NDB5V0
78 IO197PDB5V0
PQ208
Pin Number A3PE3000 Function
79 IO194NDB5V0
80 IO194PDB5V0
81 GND
82 IO184NDB4V3
83 IO184PDB4V3
84 IO180NDB4V3
85 IO180PDB4V3
86 IO176NDB4V2
87 IO176PDB4V2
88 VCC
89 VCCIB4
90 IO170NDB4V2
91 IO170PDB4V2
92 IO166NDB4V1
93 IO166PDB4V1
94 IO156NDB4V0
95 GDC2/IO156PDB4V0
96 IO154NPB4V0
97 GND
98 GDB2/IO155PSB4V0
99 GDA2/IO154PPB4V0
100 GNDQ
101 TCK
102 TDI
103 TMS
104 VMV4
105 GND
106 VPUMP
107 GNDQ
108 TDO
109 TRST
110 VJTAG
111 VMV3
112 GDA0/IO153NPB3V4
113 GDB0/IO152NPB3V4
114 GDA1/IO153PPB3V4
115 GDB1/IO152PPB3V4
116 GDC0/IO151NDB3V4
117 GDC1/IO151PDB3V4
PQ208
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-7
118 IO134NDB3V2
119 IO134PDB3V2
120 IO132NDB3V2
121 IO132PDB3V2
122 GND
123 VCCIB3
124 GCC2/IO117PSB3V0
125 GCB2/IO116PSB3V0
126 NC
127 IO115NDB3V0
128 GCA2/IO115PDB3V0
129 GCA1/IO114PPB3V0
130 GND
131 VCCPLC
132 GCA0/IO114NPB3V0
133 VCOMPLC
134 GCB0/IO113NDB2V3
135 GCB1/IO113PDB2V3
136 GCC1/IO112PSB2V3
137 IO110NDB2V3
138 IO110PDB2V3
139 IO106PSB2V3
140 VCCIB2
141 GND
142 VCC
143 IO99NDB2V2
144 IO99PDB2V2
145 IO96NDB2V1
146 IO96PDB2V1
147 IO91NDB2V1
148 IO91PDB2V1
149 IO88NDB2V0
150 IO88PDB2V0
151 GBC2/IO84PSB2V0
152 GBA2/IO82PSB2V0
153 GBB2/IO83PSB2V0
154 VMV2
155 GNDQ
156 GND
PQ208
Pin Number A3PE3000 Functio n
157 VMV1
158 GNDQ
159 GBA1/IO81PDB1V4
160 GBA0/IO81NDB1V4
161 GBB1/IO80PDB1V4
162 GND
163 GBB0/IO80NDB1V4
164 GBC1/IO79PDB1V4
165 GBC0/IO79NDB1V4
166 IO74PDB1V4
167 IO74NDB1V4
168 IO70PDB1V3
169 IO70NDB1V3
170 VCCIB1
171 VCC
172 IO56PSB1V1
173 IO55PDB1V1
174 IO55NDB1V1
175 IO54PDB1V1
176 IO54NDB1V1
177 IO40PDB0V4
178 GND
179 IO40NDB0V4
180 IO37PDB0V4
181 IO37NDB0V4
182 IO35PDB0V4
183 IO35NDB0V4
184 IO32PDB0V3
185 IO32NDB0V3
186 VCCIB0
187 VCC
188 IO28PDB0V3
189 IO28NDB0V3
190 IO24PDB0V2
191 IO24NDB0V2
192 IO21PSB0V2
193 IO16PDB0V1
194 IO16NDB0V1
195 GND
PQ208
Pin Number A3PE3000 Function
196 IO11PDB0V1
197 IO11NDB0V1
198 IO08PDB0V0
199 IO08NDB0V0
200 VCCIB0
201 GAC1/IO02PDB0V0
202 GAC0/IO02NDB0V0
203 GAB1/IO01PDB0V0
204 GAB0/IO01NDB0V0
205 GAA1/IO00PDB0V0
206 GAA0/IO00NDB0V0
207 GNDQ
208 VMV0
PQ208
Pin Number A3PE3000 Function
Package Pin Assignments
4-8 Revision 10
FG256
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Note: This is the bottom view of the package.
13579111315 246810121416
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A1 Ball Pad Corner
ProASIC3E Flash Family FPGAs
Revision 10 4-9
FG256
Pin Number A3PE600 Function
A1 GND
A2 GAA0/IO00NDB0V0
A3 GAA1/IO00PDB0V0
A4 GAB0/IO01NDB0V0
A5 IO05PDB0V0
A6 IO10PDB0V1
A7 IO12PDB0V2
A8 IO16NDB0V2
A9 IO23NDB1V0
A10 IO23PDB1V0
A11 IO28NDB1V1
A12 IO28PDB1V1
A13 GBB1/IO34PDB1V1
A14 GBA0/IO35NDB1V1
A15 GBA1/IO35PDB1V1
A16 GND
B1 GAB2/IO133PDB7V1
B2 GAA2/IO134PDB7V1
B3 GNDQ
B4 GAB1/IO01PDB0V0
B5 IO05NDB0V0
B6 IO10NDB0V1
B7 IO12NDB0V2
B8 IO16PDB0V2
B9 IO20NDB1V0
B10 IO24NDB1V0
B11 IO24PDB1V0
B12 GBC1/IO33PDB1V1
B13 GBB0/IO34NDB1V1
B14 GNDQ
B15 GBA2/IO36PDB2V0
B16 IO42NDB2V0
C1 IO133NDB7V1
C2 IO134NDB7V1
C3 VMV7
C4 VCCPLA
C5 GAC0/IO02NDB0V0
C6 GAC1/IO02PDB0V0
C7 IO15NDB0V2
C8 IO15PDB0V2
C9 IO20PDB1V0
C10 IO25NDB1V0
C11 IO27PDB1V0
C12 GBC0/IO33NDB1V1
C13 VCCPLB
C14 VMV2
C15 IO36NDB2V0
C16 IO42PDB2V0
D1 IO128PDB7V1
D2 IO129PDB7V1
D3 GAC2/IO132PDB7V1
D4 VCOMPLA
D5 GNDQ
D6 IO09NDB0V1
D7 IO09PDB0V1
D8 IO13PDB0V2
D9 IO21PDB1V0
D10 IO25PDB1V0
D11 IO27NDB1V0
D12 GNDQ
D13 VCOMPLB
D14 GBB2/IO37PDB2V0
D15 IO39PDB2V0
D16 IO39NDB2V0
E1 IO128NDB7V1
E2 IO129NDB7V1
E3 IO132NDB7V1
E4 IO130PDB7V1
E5 VMV0
E6 VCCIB0
E7 VCCIB0
E8 IO13NDB0V2
FG256
Pin Number A3PE600 Function
E9 IO21NDB1V0
E10 VCCIB1
E11 VCCIB1
E12 VMV1
E13 GBC2/IO38PDB2V0
E14 IO37NDB2V0
E15 IO41NDB2V0
E16 IO41PDB2V0
F1 IO124PDB7V0
F2 IO125PDB7V0
F3 IO126PDB7V0
F4 IO130NDB7V1
F5 VCCIB7
F6 GND
F7 VCC
F8 VCC
F9 VCC
F10 VCC
F11 GND
F12 VCCIB2
F13 IO38NDB2V0
F14 IO40NDB2V0
F15 IO40PDB2V0
F16 IO45PSB2V1
G1 IO124NDB7V0
G2 IO125NDB7V0
G3 IO126NDB7V0
G4 GFC1/IO120PPB7V0
G5 VCCIB7
G6 VCC
G7 GND
G8 GND
G9 GND
G10 GND
G11 VCC
G12 VCCIB2
FG256
Pin Number A3PE600 Function
Package Pin Assignments
4-10 Revision 10
G13 GCC1/IO50PPB2V1
G14 IO44NDB2V1
G15 IO44PDB2V1
G16 IO49NSB2V1
H1 GFB0/IO119NPB7V0
H2 GFA0/IO118NDB6V1
H3 GFB1/IO119PPB7V0
H4 VCOMPLF
H5 GFC0/IO120NPB7V0
H6 VCC
H7 GND
H8 GND
H9 GND
H10 GND
H11 VCC
H12 GCC0/IO50NPB2V1
H13 GCB1/IO51PPB2V1
H14 GCA0/IO52NPB3V0
H15 VCOMPLC
H16 GCB0/IO51NPB2V1
J1 GFA2/IO117PSB6V1
J2 GFA1/IO118PDB6V1
J3 VCCPLF
J4 IO116NDB6V1
J5 GFB2/IO116PDB6V1
J6 VCC
J7 GND
J8 GND
J9 GND
J10 GND
J11 VCC
J12 GCB2/IO54PPB3V0
J13 GCA1/IO52PPB3V0
J14 GCC2/IO55PPB3V0
J15 VCCPLC
J16 GCA2/IO53PSB3V0
FG256
Pin Number A3PE600 Function
K1 GFC2/IO115PSB6V1
K2 IO113PPB6V1
K3 IO112PDB6V1
K4 IO112NDB6V1
K5 VCCIB6
K6 VCC
K7 GND
K8 GND
K9 GND
K10 GND
K11 VCC
K12 VCCIB3
K13 IO54NPB3V0
K14 IO57NPB3V0
K15 IO55NPB3V0
K16 IO57PPB3V0
L1 IO113NPB6V1
L2 IO109PPB6V0
L3 IO108PDB6V0
L4 IO108NDB6V0
L5 VCCIB6
L6 GND
L7 VCC
L8 VCC
L9 VCC
L10 VCC
L11 GND
L12 VCCIB3
L13 GDB0/IO66NPB3V1
L14 IO60NDB3V1
L15 IO60PDB3V1
L16 IO61PDB3V1
M1 IO109NPB6V0
M2 IO106NDB6V0
M3 IO106PDB6V0
M4 GEC0/IO104NPB6V0
FG256
Pin Number A3PE600 Function
M5 VMV5
M6 VCCIB5
M7 VCCIB5
M8 IO84NDB5V0
M9 IO84PDB5V0
M10 VCCIB4
M11 VCCIB4
M12 VMV3
M13 VCCPLD
M14 GDB1/IO66PPB3V1
M15 GDC1/IO65PDB3V1
M16 IO61NDB3V1
N1 IO105PDB6V0
N2 IO105NDB6V0
N3 GEC1/IO104PPB6V0
N4 VCOMPLE
N5 GNDQ
N6 GEA2/IO101PPB5V2
N7 IO92NDB5V1
N8 IO90NDB5V1
N9 IO82NDB5V0
N10 IO74NDB4V1
N11 IO74PDB4V1
N12 GNDQ
N13 VCOMPLD
N14 VJTAG
N15 GDC0/IO65NDB3V1
N16 GDA1/IO67PDB3V1
P1 GEB1/IO103PDB6V0
P2 GEB0/IO103NDB6V0
P3 VMV6
P4 VCCPLE
P5 IO101NPB5V2
P6 IO95PPB5V1
P7 IO92PDB5V1
P8 IO90PDB5V1
FG256
Pin Number A3PE600 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-11
P9 IO82PDB5V0
P10 IO76NDB4V1
P11 IO76PDB4V1
P12 VMV4
P13 TCK
P14 VPUMP
P15 TRST
P16 GDA0/IO67NDB3V1
R1 GEA1/IO102PDB6V0
R2 GEA0/IO102NDB6V0
R3 GNDQ
R4 GEC2/IO99PDB5V2
R5 IO95NPB5V1
R6 IO91NDB5V1
R7 IO91PDB5V1
R8 IO83NDB5V0
R9 IO83PDB5V0
R10 IO77NDB4V1
R11 IO77PDB4V1
R12 IO69NDB4V0
R13 GDB2/IO69PDB4V0
R14 TDI
R15 GNDQ
R16 TDO
T1 GND
T2 IO100NDB5V2
T3 GEB2/IO100PDB5V2
T4 IO99NDB5V2
T5 IO88NDB5V0
T6 IO88PDB5V0
T7 IO89NSB5V0
T8 IO80NSB4V1
T9 IO81NDB4V1
T10 IO81PDB4V1
T11 IO70NDB4V0
T12 GDC2/IO70PDB4V0
FG256
Pin Number A3PE600 Function
T13 IO68NDB4V0
T14 GDA2/IO68PDB4V0
T15 TMS
T16 GND
FG256
Pin Number A3PE600 Function
Package Pin Assignments
4-12 Revision 10
FG324
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Note: This is the bottom view of the package.
1
3
5
791113
15 246
8
101214
16
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A1 Ball Pad Corner
ProASIC3E Flash Family FPGAs
Revision 10 4-13
FG324
Pin Number A3PE3000 FBGA
A1 GND
A2 IO08NDB0V0
A3 IO08PDB0V0
A4 IO10NDB0V1
A5 IO10PDB0V1
A6 IO12PDB0V1
A7 GND
A8 IO32NDB0V3
A9 IO32PDB0V3
A10 IO42PPB1V0
A11 IO52NPB1V1
A12 GND
A13 IO66NDB1V3
A14 IO72NDB1V3
A15 IO72PDB1V3
A16 IO74NDB1V4
A17 IO74PDB1V4
A18 GND
B1 IO305PDB7V3
B2 GAB2/IO308PDB7V4
B3 GAA0/IO00NPB0V0
B4 VCCIB0
B5 GNDQ
B6 IO12NDB0V1
B7 IO18NDB0V2
B8 VCCIB0
B9 IO42NPB1V0
B10 IO44NDB1V0
B11 VCCIB1
B12 IO52PPB1V1
B13 IO66PDB1V3
B14 GNDQ
B15 VCCIB1
B16 GBA0/IO81NDB1V4
B17 GBA1/IO81PDB1V4
B18 IO88PDB2V0
C1 IO305NDB7V3
C2 IO308NDB7V4
C3 GAA2/IO309PPB7V4
C4 GAA1/IO00PPB0V0
C5 VMV0
C6 IO14NDB0V1
C7 IO18PDB0V2
C8 IO40NDB0V4
C9 IO40PDB0V4
C10 IO44PDB1V0
C11 IO56NDB1V1
C12 IO64NDB1V2
C13 IO64PDB1V2
C14 VMV1
C15 GBC0/IO79NDB1V4
C16 GBC1/IO79PDB1V4
C17 GBB2/IO83PPB2V0
C18 IO88NDB2V0
D1 IO303PDB7V3
D2 VCCIB7
D3 GAC2/IO307PPB7V4
D4 IO309NPB7V4
D5 GAB1/IO01PPB0V0
D6 IO14PDB0V1
D7 IO24NDB0V2
D8 IO24PDB0V2
D9 IO28PDB0V3
D10 IO48NDB1V0
D11 IO56PDB1V1
D12 IO60PPB1V2
D13 GBB0/IO80NDB1V4
D14 GBB1/IO80PDB1V4
D15 GBA2/IO82PDB2V0
D16 IO83NPB2V0
D17 VCCIB2
D18 IO90PDB2V1
FG324
Pin Number A3PE3000 FBGA
E1 IO303NDB7V3
E2 GNDQ
E3 VMV7
E4 IO307NPB7V4
E5 VCCPLA
E6 GAB0/IO01NPB0V0
E7 VCCIB0
E8 GND
E9 IO28NDB0V3
E10 IO48PDB1V0
E11 GND
E12 VCCIB1
E13 IO60NPB1V2
E14 VCCPLB
E15 IO82NDB2V0
E16 VMV2
E17 GNDQ
E18 IO90NDB2V1
F1 IO299NDB7V3
F2 IO299PDB7V3
F3 IO295PDB7V2
F4 IO295NDB7V2
F5 VCOMPLA
F6 IO291PPB7V2
F7 GAC0/IO02NDB0V0
F8 GAC1/IO02PDB0V0
F9 IO26PDB0V3
F10 IO34PDB0V4
F11 IO58NDB1V2
F12 IO58PDB1V2
F13 IO94PPB2V1
F14 VCOMPLB
F15 GBC2/IO84PDB2V0
F16 IO84NDB2V0
F17 IO92NDB2V1
F18 IO92PDB2V1
FG324
Pin Number A3PE3000 FBGA
Package Pin Assignments
4-14 Revision 10
G1 GND
G2 IO287PDB7V1
G3 IO287NDB7V1
G4 IO283PPB7V1
G5 VCCIB7
G6 IO279PDB7V0
G7 IO291NPB7V2
G8 VCC
G9 IO26NDB0V3
G10 IO34NDB0V4
G11 VCC
G12 IO94NPB2V1
G13 IO98PDB2V2
G14 VCCIB2
G15 GCC0/IO112NPB2V3
G16 IO104PDB2V2
G17 IO104NDB2V2
G18 GND
H1 IO267PDB6V4
H2 VCCIB7
H3 IO283NPB7V1
H4 GFB1/IO274PPB7V0
H5 GND
H6 IO279NDB7V0
H7 VCC
H8 VCC
H9 GND
H10 GND
H11 VCC
H12 VCC
H13 IO98NDB2V2
H14 GND
H15 GCB1/IO113PDB2V3
H16 GCC1/IO112PPB2V3
H17 VCCIB2
H18 IO108PDB2V3
FG324
Pin Number A3PE3000 FBGA
J1 IO267NDB6V4
J2 GFA0/IO273NDB6V4
J3 VCOMPLF
J4 GFA2/IO272PDB6V4
J5 GFB0/IO274NPB7V0
J6 GFC0/IO275NDB7V0
J7 GFC1/IO275PDB7V0
J8 GND
J9 GND
J10 GND
J11 GND
J12 GCA2/IO115PDB3V0
J13 GCA1/IO114PDB3V0
J14 GCA0/IO114NDB3V0
J15 GCB0/IO113NDB2V3
J16 VCOMPLC
J17 IO120NPB3V0
J18 IO108NDB2V3
K1 IO263PDB6V3
K2 GFA1/IO273PDB6V4
K3 VCCPLF
K4 IO272NDB6V4
K5 GFC2/IO270PPB6V4
K6 GFB2/IO271PDB6V4
K7 IO271NDB6V4
K8 GND
K9 GND
K10 GND
K11 GND
K12 IO115NDB3V0
K13 GCB2/IO116PDB3V0
K14 IO116NDB3V0
K15 GCC2/IO117PDB3V0
K16 VCCPLC
K17 IO124NPB3V1
K18 IO120PPB3V0
FG324
Pin Number A3PE3000 FBGA
L1 IO263NDB6V3
L2 VCCIB6
L3 IO259PDB6V3
L4 IO259NDB6V3
L5 GND
L6 IO270NPB6V4
L7 VCC
L8 VCC
L9 GND
L10 GND
L11 VCC
L12 VCC
L13 IO132PDB3V2
L14 GND
L15 IO117NDB3V0
L16 IO128NPB3V1
L17 VCCIB3
L18 IO124PPB3V1
M1 GND
M2 IO255PDB6V2
M3 IO255NDB6V2
M4 IO251PPB6V2
M5 VCCIB6
M6 GEB0/IO235NDB6V0
M7 GEB1/IO235PDB6V0
M8 VCC
M9 IO192PPB4V4
M10 IO154NPB4V0
M11 VCC
M12 GDA0/IO153NPB3V4
M13 IO132NDB3V2
M14 VCCIB3
M15 IO134NDB3V2
M16 IO134PDB3V2
M17 IO128PPB3V1
M18 GND
FG324
Pin Number A3PE3000 FBGA
ProASIC3E Flash Family FPGAs
Revision 10 4-15
N1 IO247NDB6V1
N2 IO247PDB6V1
N3 IO251NPB6V2
N4 GEC0/IO236NDB6V0
N5 VCOMPLE
N6 IO212NDB5V2
N7 IO212PDB5V2
N8 IO192NPB4V4
N9 IO174PDB4V2
N10 IO170PDB4V2
N11 GDA2/IO154PPB4V0
N12 GDB2/IO155PPB4V0
N13 GDA1/IO153PPB3V4
N14 VCOMPLD
N15 GDB0/IO152NDB3V4
N16 GDB1/IO152PDB3V4
N17 IO138NDB3V3
N18 IO138PDB3V3
P1 IO245PDB6V1
P2 GNDQ
P3 VMV6
P4 GEC1/IO236PDB6V0
P5 VCCPLE
P6 IO214PDB5V2
P7 VCCIB5
P8 GND
P9 IO174NDB4V2
P10 IO170NDB4V2
P11 GND
P12 VCCIB4
P13 IO155NPB4V0
P14 VCCPLD
P15 VJTAG
P16 GDC0/IO151NDB3V4
P17 GDC1/IO151PDB3V4
P18 IO142PDB3V3
FG324
Pin Number A3PE3000 FBGA
R1 IO245NDB6V1
R2 VCCIB6
R3 GEA1/IO234PPB6V0
R4 IO232NDB5V4
R5 GEB2/IO232PDB5V4
R6 IO214NDB5V2
R7 IO202PDB5V1
R8 IO194PDB5V0
R9 IO186PDB4V4
R10 IO178PDB4V3
R11 IO168NSB4V1
R12 IO164PDB4V1
R13 GDC2/IO156PDB4V0
R14 TCK
R15 VPUMP
R16 TRST
R17 VCCIB3
R18 IO142NDB3V3
T1 IO241PDB6V0
T2 GEA0/IO234NPB6V0
T3 IO233NPB5V4
T4 IO231NPB5V4
T5 VMV5
T6 IO208NDB5V1
T7 IO202NDB5V1
T8 IO194NDB5V0
T9 IO186NDB4V4
T10 IO178NDB4V3
T11 IO166NPB4V1
T12 IO164NDB4V1
T13 IO156NDB4V0
T14 VMV4
T15 TDI
T16 GNDQ
T17 TDO
T18 IO146PDB3V4
FG324
Pin Number A3PE3000 FBGA
U1 IO241NDB6V0
U2 GEA2/IO233PPB5V4
U3 GEC2/IO231PPB5V4
U4 VCCIB5
U5 GNDQ
U6 IO208PDB5V1
U7 IO198PPB5V0
U8 VCCIB5
U9 IO182NPB4V3
U10 IO180NPB4V3
U11 VCCIB4
U12 IO166PPB4V1
U13 IO162PDB4V1
U14 GNDQ
U15 VCCIB4
U16 TMS
U17 VMV3
U18 IO146NDB3V4
V1 GND
V2 IO218NDB5V3
V3 IO218PDB5V3
V4 IO206NDB5V1
V5 IO206PDB5V1
V6 IO198NPB5V0
V7 GND
V8 IO190NDB4V4
V9 IO190PDB4V4
V10 IO182PPB4V3
V11 IO180PPB4V3
V12 GND
V13 IO162NDB4V1
V14 IO160NDB4V0
V15 IO160PDB4V0
V16 IO158NDB4V0
V17 IO158PDB4V0
V18 GND
FG324
Pin Number A3PE3000 FBGA
Package Pin Assignments
4-16 Revision 10
FG484
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Note: This is the bottom view of the package.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
12345678910111213141516171819202122 A1 Ball Pad Corner
ProASIC3E Flash Family FPGAs
Revision 10 4-17
FG484
Pin Number A3PE600 Function
A1 GND
A2 GND
A3 VCCIB0
A4 IO06NDB0V1
A5 IO06PDB0V1
A6 IO08NDB0V1
A7 IO08PDB0V1
A8 IO11PDB0V1
A9 IO17PDB0V2
A10 IO18NDB0V2
A11 IO18PDB0V2
A12 IO22PDB1V0
A13 IO26PDB1V0
A14 IO29NDB1V1
A15 IO29PDB1V1
A16 IO31NDB1V1
A17 IO31PDB1V1
A18 IO32NDB1V1
A19 NC
A20 VCCIB1
A21 GND
A22 GND
AA1 GND
AA2 VCCIB6
AA3 NC
AA4 IO98PDB5V2
AA5 IO96NDB5V2
AA6 IO96PDB5V2
AA7 IO86NDB5V0
AA8 IO86PDB5V0
AA9 IO85PDB5V0
AA10 IO85NDB5V0
AA11 IO78PPB4V1
AA12 IO79NDB4V1
AA13 IO79PDB4V1
AA14 NC
AA15 NC
AA16 IO71NDB4V0
AA17 IO71PDB4V0
AA18 NC
AA19 NC
AA20 NC
AA21 VCCIB3
AA22 GND
AB1 GND
AB2 GND
AB3 VCCIB5
AB4 IO97NDB5V2
AB5 IO97PDB5V2
AB6 IO93NDB5V1
AB7 IO93PDB5V1
AB8 IO87NDB5V0
AB9 IO87PDB5V0
AB10 NC
AB11 NC
AB12 IO75NDB4V1
AB13 IO75PDB4V1
AB14 IO72NDB4V0
AB15 IO72PDB4V0
AB16 IO73NDB4V0
AB17 IO73PDB4V0
AB18 NC
AB19 NC
AB20 VCCIB4
AB21 GND
AB22 GND
B1 GND
B2 VCCIB7
B3 NC
B4 IO03NDB0V0
B5 IO03PDB0V0
B6 IO07NDB0V1
FG484
Pin Number A3PE600 Function
B7 IO07PDB0V1
B8 IO11NDB0V1
B9 IO17NDB0V2
B10 IO14PDB0V2
B11 IO19PDB0V2
B12 IO22NDB1V0
B13 IO26NDB1V0
B14 NC
B15 NC
B16 IO30NDB1V1
B17 IO30PDB1V1
B18 IO32PDB1V1
B19 NC
B20 NC
B21 VCCIB2
B22 GND
C1 VCCIB7
C2 NC
C3 NC
C4 NC
C5 GND
C6 IO04NDB0V0
C7 IO04PDB0V0
C8 VCC
C9 VCC
C10 IO14NDB0V2
C11 IO19NDB0V2
C12 NC
C13 NC
C14 VCC
C15 VCC
C16 NC
C17 NC
C18 GND
C19 NC
C20 NC
FG484
Pin Number A3PE600 Func tio n
Package Pin Assignments
4-18 Revision 10
C21 NC
C22 VCCIB2
D1 NC
D2 NC
D3 NC
D4 GND
D5 GAA0/IO00NDB0V0
D6 GAA1/IO00PDB0V0
D7 GAB0/IO01NDB0V0
D8 IO05PDB0V0
D9 IO10PDB0V1
D10 IO12PDB0V2
D11 IO16NDB0V2
D12 IO23NDB1V0
D13 IO23PDB1V0
D14 IO28NDB1V1
D15 IO28PDB1V1
D16 GBB1/IO34PDB1V1
D17 GBA0/IO35NDB1V1
D18 GBA1/IO35PDB1V1
D19 GND
D20 NC
D21 NC
D22 NC
E1 NC
E2 NC
E3 GND
E4 GAB2/IO133PDB7V1
E5 GAA2/IO134PDB7V1
E6 GNDQ
E7 GAB1/IO01PDB0V0
E8 IO05NDB0V0
E9 IO10NDB0V1
E10 IO12NDB0V2
E11 IO16PDB0V2
E12 IO20NDB1V0
FG484
Pin Number A3PE600 Function
E13 IO24NDB1V0
E14 IO24PDB1V0
E15 GBC1/IO33PDB1V1
E16 GBB0/IO34NDB1V1
E17 GNDQ
E18 GBA2/IO36PDB2V0
E19 IO42NDB2V0
E20 GND
E21 NC
E22 NC
F1 NC
F2 IO131NDB7V1
F3 IO131PDB7V1
F4 IO133NDB7V1
F5 IO134NDB7V1
F6 VMV7
F7 VCCPLA
F8 GAC0/IO02NDB0V0
F9 GAC1/IO02PDB0V0
F10 IO15NDB0V2
F11 IO15PDB0V2
F12 IO20PDB1V0
F13 IO25NDB1V0
F14 IO27PDB1V0
F15 GBC0/IO33NDB1V1
F16 VCCPLB
F17 VMV2
F18 IO36NDB2V0
F19 IO42PDB2V0
F20 NC
F21 NC
F22 NC
G1 IO127NDB7V1
G2 IO127PDB7V1
G3 NC
G4 IO128PDB7V1
FG484
Pin Number A3PE600 Function
G5 IO129PDB7V1
G6 GAC2/IO132PDB7V1
G7 VCOMPLA
G8 GNDQ
G9 IO09NDB0V1
G10 IO09PDB0V1
G11 IO13PDB0V2
G12 IO21PDB1V0
G13 IO25PDB1V0
G14 IO27NDB1V0
G15 GNDQ
G16 VCOMPLB
G17 GBB2/IO37PDB2V0
G18 IO39PDB2V0
G19 IO39NDB2V0
G20 IO43PDB2V0
G21 IO43NDB2V0
G22 NC
H1 NC
H2 NC
H3 VCC
H4 IO128NDB7V1
H5 IO129NDB7V1
H6 IO132NDB7V1
H7 IO130PDB7V1
H8 VMV0
H9 VCCIB0
H10 VCCIB0
H11 IO13NDB0V2
H12 IO21NDB1V0
H13 VCCIB1
H14 VCCIB1
H15 VMV1
H16 GBC2/IO38PDB2V0
H17 IO37NDB2V0
H18 IO41NDB2V0
FG484
Pin Number A3PE600 Func tio n
ProASIC3E Flash Family FPGAs
Revision 10 4-19
H19 IO41PDB2V0
H20 VCC
H21 NC
H22 NC
J1 IO123NDB7V0
J2 IO123PDB7V0
J3 NC
J4 IO124PDB7V0
J5 IO125PDB7V0
J6 IO126PDB7V0
J7 IO130NDB7V1
J8 VCCIB7
J9 GND
J10 VCC
J11 VCC
J12 VCC
J13 VCC
J14 GND
J15 VCCIB2
J16 IO38NDB2V0
J17 IO40NDB2V0
J18 IO40PDB2V0
J19 IO45PPB2V1
J20 NC
J21 IO48PDB2V1
J22 IO46PDB2V1
K1 IO121NDB7V0
K2 IO121PDB7V0
K3 NC
K4 IO124NDB7V0
K5 IO125NDB7V0
K6 IO126NDB7V0
K7 GFC1/IO120PPB7V0
K8 VCCIB7
K9 VCC
K10 GND
FG484
Pin Number A3PE600 Function
K11 GND
K12 GND
K13 GND
K14 VCC
K15 VCCIB2
K16 GCC1/IO50PPB2V1
K17 IO44NDB2V1
K18 IO44PDB2V1
K19 IO49NPB2V1
K20 IO45NPB2V1
K21 IO48NDB2V1
K22 IO46NDB2V1
L1 NC
L2 IO122PDB7V0
L3 IO122NDB7V0
L4 GFB0/IO119NPB7V0
L5 GFA0/IO118NDB6V1
L6 GFB1/IO119PPB7V0
L7 VCOMPLF
L8 GFC0/IO120NPB7V0
L9 VCC
L10 GND
L11 GND
L12 GND
L13 GND
L14 VCC
L15 GCC0/IO50NPB2V1
L16 GCB1/IO51PPB2V1
L17 GCA0/IO52NPB3V0
L18 VCOMPLC
L19 GCB0/IO51NPB2V1
L20 IO49PPB2V1
L21 IO47NDB2V1
L22 IO47PDB2V1
M1 NC
M2 IO114NPB6V1
FG484
Pin Number A3PE600 Function
M3 IO117NDB6V1
M4 GFA2/IO117PDB6V1
M5 GFA1/IO118PDB6V1
M6 VCCPLF
M7 IO116NDB6V1
M8 GFB2/IO116PDB6V1
M9 VCC
M10 GND
M11 GND
M12 GND
M13 GND
M14 VCC
M15 GCB2/IO54PPB3V0
M16 GCA1/IO52PPB3V0
M17 GCC2/IO55PPB3V0
M18 VCCPLC
M19 GCA2/IO53PDB3V0
M20 IO53NDB3V0
M21 IO56PDB3V0
M22 NC
N1 IO114PPB6V1
N2 IO111NDB6V1
N3 NC
N4 GFC2/IO115PPB6V1
N5 IO113PPB6V1
N6 IO112PDB6V1
N7 IO112NDB6V1
N8 VCCIB6
N9 VCC
N10 GND
N11 GND
N12 GND
N13 GND
N14 VCC
N15 VCCIB3
N16 IO54NPB3V0
FG484
Pin Number A3PE600 Func tio n
Package Pin Assignments
4-20 Revision 10
N17 IO57NPB3V0
N18 IO55NPB3V0
N19 IO57PPB3V0
N20 NC
N21 IO56NDB3V0
N22 IO58PDB3V0
P1 NC
P2 IO111PDB6V1
P3 IO115NPB6V1
P4 IO113NPB6V1
P5 IO109PPB6V0
P6 IO108PDB6V0
P7 IO108NDB6V0
P8 VCCIB6
P9 GND
P10 VCC
P11 VCC
P12 VCC
P13 VCC
P14 GND
P15 VCCIB3
P16 GDB0/IO66NPB3V1
P17 IO60NDB3V1
P18 IO60PDB3V1
P19 IO61PDB3V1
P20 NC
P21 IO59PDB3V0
P22 IO58NDB3V0
R1 NC
R2 IO110PDB6V0
R3 VCC
R4 IO109NPB6V0
R5 IO106NDB6V0
R6 IO106PDB6V0
R7 GEC0/IO104NPB6V0
R8 VMV5
FG484
Pin Number A3PE600 Function
R9 VCCIB5
R10 VCCIB5
R11 IO84NDB5V0
R12 IO84PDB5V0
R13 VCCIB4
R14 VCCIB4
R15 VMV3
R16 VCCPLD
R17 GDB1/IO66PPB3V1
R18 GDC1/IO65PDB3V1
R19 IO61NDB3V1
R20 VCC
R21 IO59NDB3V0
R22 IO62PDB3V1
T1 NC
T2 IO110NDB6V0
T3 NC
T4 IO105PDB6V0
T5 IO105NDB6V0
T6 GEC1/IO104PPB6V0
T7 VCOMPLE
T8 GNDQ
T9 GEA2/IO101PPB5V2
T10 IO92NDB5V1
T11 IO90NDB5V1
T12 IO82NDB5V0
T13 IO74NDB4V1
T14 IO74PDB4V1
T15 GNDQ
T16 VCOMPLD
T17 VJTAG
T18 GDC0/IO65NDB3V1
T19 GDA1/IO67PDB3V1
T20 NC
T21 IO64PDB3V1
T22 IO62NDB3V1
FG484
Pin Number A3PE600 Function
U1 NC
U2 IO107PDB6V0
U3 IO107NDB6V0
U4 GEB1/IO103PDB6V0
U5 GEB0/IO103NDB6V0
U6 VMV6
U7 VCCPLE
U8 IO101NPB5V2
U9 IO95PPB5V1
U10 IO92PDB5V1
U11 IO90PDB5V1
U12 IO82PDB5V0
U13 IO76NDB4V1
U14 IO76PDB4V1
U15 VMV4
U16 TCK
U17 VPUMP
U18 TRST
U19 GDA0/IO67NDB3V1
U20 NC
U21 IO64NDB3V1
U22 IO63PDB3V1
V1 NC
V2 NC
V3 GND
V4 GEA1/IO102PDB6V0
V5 GEA0/IO102NDB6V0
V6 GNDQ
V7 GEC2/IO99PDB5V2
V8 IO95NPB5V1
V9 IO91NDB5V1
V10 IO91PDB5V1
V11 IO83NDB5V0
V12 IO83PDB5V0
V13 IO77NDB4V1
V14 IO77PDB4V1
FG484
Pin Number A3PE600 Func tio n
ProASIC3E Flash Family FPGAs
Revision 10 4-21
V15 IO69NDB4V0
V16 GDB2/IO69PDB4V0
V17 TDI
V18 GNDQ
V19 TDO
V20 GND
V21 NC
V22 IO63NDB3V1
W1 NC
W2 NC
W3 NC
W4 GND
W5 IO100NDB5V2
W6 GEB2/IO100PDB5V2
W7 IO99NDB5V2
W8 IO88NDB5V0
W9 IO88PDB5V0
W10 IO89NDB5V0
W11 IO80NDB4V1
W12 IO81NDB4V1
W13 IO81PDB4V1
W14 IO70NDB4V0
W15 GDC2/IO70PDB4V0
W16 IO68NDB4V0
W17 GDA2/IO68PDB4V0
W18 TMS
W19 GND
W20 NC
W21 NC
W22 NC
Y1 VCCIB6
Y2 NC
Y3 NC
Y4 IO98NDB5V2
Y5 GND
Y6 IO94NDB5V1
FG484
Pin Number A3PE600 Function
Y7 IO94PDB5V1
Y8 VCC
Y9 VCC
Y10 IO89PDB5V0
Y11 IO80PDB4V1
Y12 IO78NPB4V1
Y13 NC
Y14 VCC
Y15 VCC
Y16 NC
Y17 NC
Y18 GND
Y19 NC
Y20 NC
Y21 NC
Y22 VCCIB3
FG484
Pin Number A3PE600 Function
Package Pin Assignments
4-22 Revision 10
FG484
Pin Number A3PE1500 Function
A1 GND
A2 GND
A3 VCCIB0
A4 IO05NDB0V0
A5 IO05PDB0V0
A6 IO11NDB0V1
A7 IO11PDB0V1
A8 IO15PDB0V1
A9 IO17PDB0V2
A10 IO27NDB0V3
A11 IO27PDB0V3
A12 IO32PDB1V0
A13 IO43PDB1V1
A14 IO47NDB1V1
A15 IO47PDB1V1
A16 IO51NDB1V2
A17 IO51PDB1V2
A18 IO54NDB1V3
A19 NC
A20 VCCIB1
A21 GND
A22 GND
AA1 GND
AA2 VCCIB6
AA3 NC
AA4 IO161PDB5V3
AA5 IO155NDB5V2
AA6 IO155PDB5V2
AA7 IO154NDB5V2
AA8 IO154PDB5V2
AA9 IO143PDB5V1
AA10 IO143NDB5V1
AA11 IO131PPB4V2
AA12 IO129NDB4V2
AA13 IO129PDB4V2
AA14 NC
AA15 NC
AA16 IO117NDB4V0
AA17 IO117PDB4V0
AA18 IO115NDB4V0
AA19 IO115PDB4V0
AA20 NC
AA21 VCCIB3
AA22 GND
AB1 GND
AB2 GND
AB3 VCCIB5
AB4 IO159NDB5V3
AB5 IO159PDB5V3
AB6 IO149NDB5V1
AB7 IO149PDB5V1
AB8 IO138NDB5V0
AB9 IO138PDB5V0
AB10 NC
AB11 NC
AB12 IO127NDB4V2
AB13 IO127PDB4V2
AB14 IO125NDB4V1
AB15 IO125PDB4V1
AB16 IO122NDB4V1
AB17 IO122PDB4V1
AB18 NC
AB19 NC
AB20 VCCIB4
AB21 GND
AB22 GND
B1 GND
B2 VCCIB7
B3 NC
B4 IO03NDB0V0
B5 IO03PDB0V0
B6 IO10NDB0V1
FG484
Pin Number A3PE1500 Function
B7 IO10PDB0V1
B8 IO15NDB0V1
B9 IO17NDB0V2
B10 IO20PDB0V2
B11 IO29PDB0V3
B12 IO32NDB1V0
B13 IO43NDB1V1
B14 NC
B15 NC
B16 IO53NDB1V2
B17 IO53PDB1V2
B18 IO54PDB1V3
B19 NC
B20 NC
B21 VCCIB2
B22 GND
C1 VCCIB7
C2 NC
C3 NC
C4 NC
C5 GND
C6 IO07NDB0V0
C7 IO07PDB0V0
C8 VCC
C9 VCC
C10 IO20NDB0V2
C11 IO29NDB0V3
C12 NC
C13 NC
C14 VCC
C15 VCC
C16 NC
C17 NC
C18 GND
C19 NC
C20 NC
FG484
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-23
C21 NC
C22 VCCIB2
D1 NC
D2 NC
D3 NC
D4 GND
D5 GAA0/IO00NDB0V0
D6 GAA1/IO00PDB0V0
D7 GAB0/IO01NDB0V0
D8 IO09PDB0V1
D9 IO13PDB0V1
D10 IO21PDB0V2
D11 IO31NDB0V3
D12 IO37NDB1V0
D13 IO37PDB1V0
D14 IO49NDB1V2
D15 IO49PDB1V2
D16 GBB1/IO56PDB1V3
D17 GBA0/IO57NDB1V3
D18 GBA1/IO57PDB1V3
D19 GND
D20 NC
D21 IO69PDB2V1
D22 NC
E1 NC
E2 IO218PPB7V3
E3 GND
E4 GAB2/IO220PDB7V3
E5 GAA2/IO221PDB7V3
E6 GNDQ
E7 GAB1/IO01PDB0V0
E8 IO09NDB0V1
E9 IO13NDB0V1
E10 IO21NDB0V2
E11 IO31PDB0V3
E12 IO35NDB1V0
FG484
Pin Number A3PE1500 Function
E13 IO41NDB1V1
E14 IO41PDB1V1
E15 GBC1/IO55PDB1V3
E16 GBB0/IO56NDB1V3
E17 GNDQ
E18 GBA2/IO58PDB2V0
E19 IO63NDB2V0
E20 GND
E21 IO69NDB2V1
E22 NC
F1 IO218NPB7V3
F2 IO216NDB7V3
F3 IO216PDB7V3
F4 IO220NDB7V3
F5 IO221NDB7V3
F6 VMV7
F7 VCCPLA
F8 GAC0/IO02NDB0V0
F9 GAC1/IO02PDB0V0
F10 IO23NDB0V2
F11 IO23PDB0V2
F12 IO35PDB1V0
F13 IO39NDB1V0
F14 IO45PDB1V1
F15 GBC0/IO55NDB1V3
F16 VCCPLB
F17 VMV2
F18 IO58NDB2V0
F19 IO63PDB2V0
F20 NC
F21 NC
F22 NC
G1 IO211NDB7V2
G2 IO211PDB7V2
G3 NC
G4 IO214PDB7V3
FG484
Pin Number A3PE1500 Function
G5 IO217PDB7V3
G6 GAC2/IO219PDB7V3
G7 VCOMPLA
G8 GNDQ
G9 IO19NDB0V2
G10 IO19PDB0V2
G11 IO25PDB0V3
G12 IO33PDB1V0
G13 IO39PDB1V0
G14 IO45NDB1V1
G15 GNDQ
G16 VCOMPLB
G17 GBB2/IO59PDB2V0
G18 IO62PDB2V0
G19 IO62NDB2V0
G20 IO71PDB2V2
G21 IO71NDB2V2
G22 NC
H1 IO209PSB7V2
H2 NC
H3 VCC
H4 IO214NDB7V3
H5 IO217NDB7V3
H6 IO219NDB7V3
H7 IO215PDB7V3
H8 VMV0
H9 VCCIB0
H10 VCCIB0
H11 IO25NDB0V3
H12 IO33NDB1V0
H13 VCCIB1
H14 VCCIB1
H15 VMV1
H16 GBC2/IO60PDB2V0
H17 IO59NDB2V0
H18 IO67NDB2V1
FG484
Pin Number A3PE1500 Function
Package Pin Assignments
4-24 Revision 10
H19 IO67PDB2V1
H20 VCC
H21 VMV2
H22 IO74PSB2V2
J1 IO212NDB7V2
J2 IO212PDB7V2
J3 VMV7
J4 IO206PDB7V1
J5 IO204PDB7V1
J6 IO210PDB7V2
J7 IO215NDB7V3
J8 VCCIB7
J9 GND
J10 VCC
J11 VCC
J12 VCC
J13 VCC
J14 GND
J15 VCCIB2
J16 IO60NDB2V0
J17 IO65NDB2V1
J18 IO65PDB2V1
J19 IO75PPB2V2
J20 GNDQ
J21 IO77PDB2V2
J22 IO79PDB2V3
K1 IO200NDB7V1
K2 IO200PDB7V1
K3 GNDQ
K4 IO206NDB7V1
K5 IO204NDB7V1
K6 IO210NDB7V2
K7 GFC1/IO192PPB7V0
K8 VCCIB7
K9 VCC
K10 GND
FG484
Pin Number A3PE1500 Function
K11 GND
K12 GND
K13 GND
K14 VCC
K15 VCCIB2
K16 GCC1/IO85PPB2V3
K17 IO73NDB2V2
K18 IO73PDB2V2
K19 IO81NPB2V3
K20 IO75NPB2V2
K21 IO77NDB2V2
K22 IO79NDB2V3
L1 NC
L2 IO196PDB7V0
L3 IO196NDB7V0
L4 GFB0/IO191NPB7V0
L5 GFA0/IO190NDB6V2
L6 GFB1/IO191PPB7V0
L7 VCOMPLF
L8 GFC0/IO192NPB7V0
L9 VCC
L10 GND
L11 GND
L12 GND
L13 GND
L14 VCC
L15 GCC0/IO85NPB2V3
L16 GCB1/IO86PPB2V3
L17 GCA0/IO87NPB3V0
L18 VCOMPLC
L19 GCB0/IO86NPB2V3
L20 IO81PPB2V3
L21 IO83NDB2V3
L22 IO83PDB2V3
M1 GNDQ
M2 IO185NPB6V2
FG484
Pin Number A3PE1500 Function
M3 IO189NDB6V2
M4 GFA2/IO189PDB6V2
M5 GFA1/IO190PDB6V2
M6 VCCPLF
M7 IO188NDB6V2
M8 GFB2/IO188PDB6V2
M9 VCC
M10 GND
M11 GND
M12 GND
M13 GND
M14 VCC
M15 GCB2/IO89PPB3V0
M16 GCA1/IO87PPB3V0
M17 GCC2/IO90PPB3V0
M18 VCCPLC
M19 GCA2/IO88PDB3V0
M20 IO88NDB3V0
M21 IO93PDB3V0
M22 NC
N1 IO185PPB6V2
N2 IO183NDB6V2
N3 VMV6
N4 GFC2/IO187PPB6V2
N5 IO184PPB6V2
N6 IO186PDB6V2
N7 IO186NDB6V2
N8 VCCIB6
N9 VCC
N10 GND
N11 GND
N12 GND
N13 GND
N14 VCC
N15 VCCIB3
N16 IO89NPB3V0
FG484
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-25
N17 IO91NPB3V0
N18 IO90NPB3V0
N19 IO91PPB3V0
N20 GNDQ
N21 IO93NDB3V0
N22 IO95PDB3V1
P1 NC
P2 IO183PDB6V2
P3 IO187NPB6V2
P4 IO184NPB6V2
P5 IO176PPB6V1
P6 IO182PDB6V1
P7 IO182NDB6V1
P8 VCCIB6
P9 GND
P10 VCC
P11 VCC
P12 VCC
P13 VCC
P14 GND
P15 VCCIB3
P16 GDB0/IO109NPB3V2
P17 IO97NDB3V1
P18 IO97PDB3V1
P19 IO99PDB3V1
P20 VMV3
P21 IO98PDB3V1
P22 IO95NDB3V1
R1 NC
R2 IO177PDB6V1
R3 VCC
R4 IO176NPB6V1
R5 IO174NDB6V0
R6 IO174PDB6V0
R7 GEC0/IO169NPB6V0
R8 VMV5
FG484
Pin Number A3PE1500 Function
R9 VCCIB5
R10 VCCIB5
R11 IO135NDB5V0
R12 IO135PDB5V0
R13 VCCIB4
R14 VCCIB4
R15 VMV3
R16 VCCPLD
R17 GDB1/IO109PPB3V2
R18 GDC1/IO108PDB3V2
R19 IO99NDB3V1
R20 VCC
R21 IO98NDB3V1
R22 IO101PDB3V1
T1 NC
T2 IO177NDB6V1
T3 NC
T4 IO171PDB6V0
T5 IO171NDB6V0
T6 GEC1/IO169PPB6V0
T7 VCOMPLE
T8 GNDQ
T9 GEA2/IO166PPB5V3
T10 IO145NDB5V1
T11 IO141NDB5V0
T12 IO139NDB5V0
T13 IO119NDB4V1
T14 IO119PDB4V1
T15 GNDQ
T16 VCOMPLD
T17 VJTAG
T18 GDC0/IO108NDB3V2
T19 GDA1/IO110PDB3V2
T20 NC
T21 IO103PDB3V2
T22 IO101NDB3V1
FG484
Pin Number A3PE1500 Function
U1 IO175PPB6V1
U2 IO173PDB6V0
U3 IO173NDB6V0
U4 GEB1/IO168PDB6V0
U5 GEB0/IO168NDB6V0
U6 VMV6
U7 VCCPLE
U8 IO166NPB5V3
U9 IO157PPB5V2
U10 IO145PDB5V1
U11 IO141PDB5V0
U12 IO139PDB5V0
U13 IO121NDB4V1
U14 IO121PDB4V1
U15 VMV4
U16 TCK
U17 VPUMP
U18 TRST
U19 GDA0/IO110NDB3V2
U20 NC
U21 IO103NDB3V2
U22 IO105PDB3V2
V1 NC
V2 IO175NPB6V1
V3 GND
V4 GEA1/IO167PDB6V0
V5 GEA0/IO167NDB6V0
V6 GNDQ
V7 GEC2/IO164PDB5V3
V8 IO157NPB5V2
V9 IO151NDB5V2
V10 IO151PDB5V2
V11 IO137NDB5V0
V12 IO137PDB5V0
V13 IO123NDB4V1
V14 IO123PDB4V1
FG484
Pin Number A3PE1500 Function
Package Pin Assignments
4-26 Revision 10
V15 IO112NDB4V0
V16 GDB2/IO112PDB4V0
V17 TDI
V18 GNDQ
V19 TDO
V20 GND
V21 NC
V22 IO105NDB3V2
W1 NC
W2 NC
W3 NC
W4 GND
W5 IO165NDB5V3
W6 GEB2/IO165PDB5V3
W7 IO164NDB5V3
W8 IO153NDB5V2
W9 IO153PDB5V2
W10 IO147NDB5V1
W11 IO133NDB4V2
W12 IO130NDB4V2
W13 IO130PDB4V2
W14 IO113NDB4V0
W15 GDC2/IO113PDB4V0
W16 IO111NDB4V0
W17 GDA2/IO111PDB4V0
W18 TMS
W19 GND
W20 NC
W21 NC
W22 NC
Y1 VCCIB6
Y2 NC
Y3 NC
Y4 IO161NDB5V3
Y5 GND
Y6 IO163NDB5V3
FG484
Pin Number A3PE1500 Function
Y7 IO163PDB5V3
Y8 VCC
Y9 VCC
Y10 IO147PDB5V1
Y11 IO133PDB4V2
Y12 IO131NPB4V2
Y13 NC
Y14 VCC
Y15 VCC
Y16 NC
Y17 NC
Y18 GND
Y19 NC
Y20 NC
Y21 NC
Y22 VCCIB3
FG484
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-27
FG484
Pin Number A3PE3000 Function
A1 GND
A2 GND
A3 VCCIB0
A4 IO10NDB0V1
A5 IO10PDB0V1
A6 IO16NDB0V1
A7 IO16PDB0V1
A8 IO18PDB0V2
A9 IO24PDB0V2
A10 IO28NDB0V3
A11 IO28PDB0V3
A12 IO46PDB1V0
A13 IO54PDB1V1
A14 IO56NDB1V1
A15 IO56PDB1V1
A16 IO64NDB1V2
A17 IO64PDB1V2
A18 IO72NDB1V3
A19 IO74NDB1V4
A20 VCCIB1
A21 GND
A22 GND
AA1 GND
AA2 VCCIB6
AA3 IO228PDB5V4
AA4 IO224PDB5V3
AA5 IO218NDB5V3
AA6 IO218PDB5V3
AA7 IO212NDB5V2
AA8 IO212PDB5V2
AA9 IO198PDB5V0
AA10 IO198NDB5V0
AA11 IO188PPB4V4
AA12 IO180NDB4V3
AA13 IO180PDB4V3
AA14 IO170NDB4V2
AA15 IO170PDB4V2
AA16 IO166NDB4V1
AA17 IO166PDB4V1
AA18 IO160NDB4V0
AA19 IO160PDB4V0
AA20 IO158NPB4V0
AA21 VCCIB3
AA22 GND
AB1 GND
AB2 GND
AB3 VCCIB5
AB4 IO216NDB5V2
AB5 IO216PDB5V2
AB6 IO210NDB5V2
AB7 IO210PDB5V2
AB8 IO208NDB5V1
AB9 IO208PDB5V1
AB10 IO197NDB5V0
AB11 IO197PDB5V0
AB12 IO174NDB4V2
AB13 IO174PDB4V2
AB14 IO172NDB4V2
AB15 IO172PDB4V2
AB16 IO168NDB4V1
AB17 IO168PDB4V1
AB18 IO162NDB4V1
AB19 IO162PDB4V1
AB20 VCCIB4
AB21 GND
AB22 GND
B1 GND
B2 VCCIB7
B3 IO06PPB0V0
B4 IO08NDB0V0
B5 IO08PDB0V0
B6 IO14NDB0V1
FG484
Pin Number A3PE3000 Function
B7 IO14PDB0V1
B8 IO18NDB0V2
B9 IO24NDB0V2
B10 IO34PDB0V4
B11 IO40PDB0V4
B12 IO46NDB1V0
B13 IO54NDB1V1
B14 IO62NDB1V2
B15 IO62PDB1V2
B16 IO68NDB1V3
B17 IO68PDB1V3
B18 IO72PDB1V3
B19 IO74PDB1V4
B20 IO76NPB1V4
B21 VCCIB2
B22 GND
C1 VCCIB7
C2 IO303PDB7V3
C3 IO305PDB7V3
C4 IO06NPB0V0
C5 GND
C6 IO12NDB0V1
C7 IO12PDB0V1
C8 VCC
C9 VCC
C10 IO34NDB0V4
C11 IO40NDB0V4
C12 IO48NDB1V0
C13 IO48PDB1V0
C14 VCC
C15 VCC
C16 IO70NDB1V3
C17 IO70PDB1V3
C18 GND
C19 IO76PPB1V4
C20 IO88NDB2V0
FG484
Pin Number A3PE3000 Function
Package Pin Assignments
4-28 Revision 10
C21 IO94PPB2V1
C22 VCCIB2
D1 IO293PDB7V2
D2 IO303NDB7V3
D3 IO305NDB7V3
D4 GND
D5 GAA0/IO00NDB0V0
D6 GAA1/IO00PDB0V0
D7 GAB0/IO01NDB0V0
D8 IO20PDB0V2
D9 IO22PDB0V2
D10 IO30PDB0V3
D11 IO38NDB0V4
D12 IO52NDB1V1
D13 IO52PDB1V1
D14 IO66NDB1V3
D15 IO66PDB1V3
D16 GBB1/IO80PDB1V4
D17 GBA0/IO81NDB1V4
D18 GBA1/IO81PDB1V4
D19 GND
D20 IO88PDB2V0
D21 IO90PDB2V1
D22 IO94NPB2V1
E1 IO293NDB7V2
E2 IO299PPB7V3
E3 GND
E4 GAB2/IO308PDB7V4
E5 GAA2/IO309PDB7V4
E6 GNDQ
E7 GAB1/IO01PDB0V0
E8 IO20NDB0V2
E9 IO22NDB0V2
E10 IO30NDB0V3
E11 IO38PDB0V4
E12 IO44NDB1V0
FG484
Pin Number A3PE3000 Function
E13 IO58NDB1V2
E14 IO58PDB1V2
E15 GBC1/IO79PDB1V4
E16 GBB0/IO80NDB1V4
E17 GNDQ
E18 GBA2/IO82PDB2V0
E19 IO86NDB2V0
E20 GND
E21 IO90NDB2V1
E22 IO98PDB2V2
F1 IO299NPB7V3
F2 IO301NDB7V3
F3 IO301PDB7V3
F4 IO308NDB7V4
F5 IO309NDB7V4
F6 VMV7
F7 VCCPLA
F8 GAC0/IO02NDB0V0
F9 GAC1/IO02PDB0V0
F10 IO32NDB0V3
F11 IO32PDB0V3
F12 IO44PDB1V0
F13 IO50NDB1V1
F14 IO60PDB1V2
F15 GBC0/IO79NDB1V4
F16 VCCPLB
F17 VMV2
F18 IO82NDB2V0
F19 IO86PDB2V0
F20 IO96PDB2V1
F21 IO96NDB2V1
F22 IO98NDB2V2
G1 IO289NDB7V1
G2 IO289PDB7V1
G3 IO291PPB7V2
G4 IO295PDB7V2
FG484
Pin Number A3PE3000 Function
G5 IO297PDB7V2
G6 GAC2/IO307PDB7V4
G7 VCOMPLA
G8 GNDQ
G9 IO26NDB0V3
G10 IO26PDB0V3
G11 IO36PDB0V4
G12 IO42PDB1V0
G13 IO50PDB1V1
G14 IO60NDB1V2
G15 GNDQ
G16 VCOMPLB
G17 GBB2/IO83PDB2V0
G18 IO92PDB2V1
G19 IO92NDB2V1
G20 IO102PDB2V2
G21 IO102NDB2V2
G22 IO105NDB2V2
H1 IO286PSB7V1
H2 IO291NPB7V2
H3 VCC
H4 IO295NDB7V2
H5 IO297NDB7V2
H6 IO307NDB7V4
H7 IO287PDB7V1
H8 VMV0
H9 VCCIB0
H10 VCCIB0
H11 IO36NDB0V4
H12 IO42NDB1V0
H13 VCCIB1
H14 VCCIB1
H15 VMV1
H16 GBC2/IO84PDB2V0
H17 IO83NDB2V0
H18 IO100NDB2V2
FG484
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-29
H19 IO100PDB2V2
H20 VCC
H21 VMV2
H22 IO105PDB2V2
J1 IO285NDB7V1
J2 IO285PDB7V1
J3 VMV7
J4 IO279PDB7V0
J5 IO283PDB7V1
J6 IO281PDB7V0
J7 IO287NDB7V1
J8 VCCIB7
J9 GND
J10 VCC
J11 VCC
J12 VCC
J13 VCC
J14 GND
J15 VCCIB2
J16 IO84NDB2V0
J17 IO104NDB2V2
J18 IO104PDB2V2
J19 IO106PPB2V3
J20 GNDQ
J21 IO109PDB2V3
J22 IO107PDB2V3
K1 IO277NDB7V0
K2 IO277PDB7V0
K3 GNDQ
K4 IO279NDB7V0
K5 IO283NDB7V1
K6 IO281NDB7V0
K7 GFC1/IO275PPB7V0
K8 VCCIB7
K9 VCC
K10 GND
FG484
Pin Number A3PE3000 Function
K11 GND
K12 GND
K13 GND
K14 VCC
K15 VCCIB2
K16 GCC1/IO112PPB2V3
K17 IO108NDB2V3
K18 IO108PDB2V3
K19 IO110NPB2V3
K20 IO106NPB2V3
K21 IO109NDB2V3
K22 IO107NDB2V3
L1 IO257PSB6V2
L2 IO276PDB7V0
L3 IO276NDB7V0
L4 GFB0/IO274NPB7V0
L5 GFA0/IO273NDB6V4
L6 GFB1/IO274PPB7V0
L7 VCOMPLF
L8 GFC0/IO275NPB7V0
L9 VCC
L10 GND
L11 GND
L12 GND
L13 GND
L14 VCC
L15 GCC0/IO112NPB2V3
L16 GCB1/IO113PPB2V3
L17 GCA0/IO114NPB3V0
L18 VCOMPLC
L19 GCB0/IO113NPB2V3
L20 IO110PPB2V3
L21 IO111NDB2V3
L22 IO111PDB2V3
M1 GNDQ
M2 IO255NPB6V2
FG484
Pin Number A3PE3000 Function
M3 IO272NDB6V4
M4 GFA2/IO272PDB6V4
M5 GFA1/IO273PDB6V4
M6 VCCPLF
M7 IO271NDB6V4
M8 GFB2/IO271PDB6V4
M9 VCC
M10 GND
M11 GND
M12 GND
M13 GND
M14 VCC
M15 GCB2/IO116PPB3V0
M16 GCA1/IO114PPB3V0
M17 GCC2/IO117PPB3V0
M18 VCCPLC
M19 GCA2/IO115PDB3V0
M20 IO115NDB3V0
M21 IO126PDB3V1
M22 IO124PSB3V1
N1 IO255PPB6V2
N2 IO253NDB6V2
N3 VMV6
N4 GFC2/IO270PPB6V4
N5 IO261PPB6V3
N6 IO263PDB6V3
N7 IO263NDB6V3
N8 VCCIB6
N9 VCC
N10 GND
N11 GND
N12 GND
N13 GND
N14 VCC
N15 VCCIB3
N16 IO116NPB3V0
FG484
Pin Number A3PE3000 Function
Package Pin Assignments
4-30 Revision 10
N17 IO132NPB3V2
N18 IO117NPB3V0
N19 IO132PPB3V2
N20 GNDQ
N21 IO126NDB3V1
N22 IO128PDB3V1
P1 IO247PDB6V1
P2 IO253PDB6V2
P3 IO270NPB6V4
P4 IO261NPB6V3
P5 IO249PPB6V1
P6 IO259PDB6V3
P7 IO259NDB6V3
P8 VCCIB6
P9 GND
P10 VCC
P11 VCC
P12 VCC
P13 VCC
P14 GND
P15 VCCIB3
P16 GDB0/IO152NPB3V4
P17 IO136NDB3V2
P18 IO136PDB3V2
P19 IO138PDB3V3
P20 VMV3
P21 IO130PDB3V2
P22 IO128NDB3V1
R1 IO247NDB6V1
R2 IO245PDB6V1
R3 VCC
R4 IO249NPB6V1
R5 IO251NDB6V2
R6 IO251PDB6V2
R7 GEC0/IO236NPB6V0
R8 VMV5
FG484
Pin Number A3PE3000 Function
R9 VCCIB5
R10 VCCIB5
R11 IO196NDB5V0
R12 IO196PDB5V0
R13 VCCIB4
R14 VCCIB4
R15 VMV3
R16 VCCPLD
R17 GDB1/IO152PPB3V4
R18 GDC1/IO151PDB3V4
R19 IO138NDB3V3
R20 VCC
R21 IO130NDB3V2
R22 IO134PDB3V2
T1 IO243PPB6V1
T2 IO245NDB6V1
T3 IO243NPB6V1
T4 IO241PDB6V0
T5 IO241NDB6V0
T6 GEC1/IO236PPB6V0
T7 VCOMPLE
T8 GNDQ
T9 GEA2/IO233PPB5V4
T10 IO206NDB5V1
T11 IO202NDB5V1
T12 IO194NDB5V0
T13 IO186NDB4V4
T14 IO186PDB4V4
T15 GNDQ
T16 VCOMPLD
T17 VJTAG
T18 GDC0/IO151NDB3V4
T19 GDA1/IO153PDB3V4
T20 IO144PDB3V3
T21 IO140PDB3V3
T22 IO134NDB3V2
FG484
Pin Number A3PE3000 Function
U1 IO240PPB6V0
U2 IO238PDB6V0
U3 IO238NDB6V0
U4 GEB1/IO235PDB6V0
U5 GEB0/IO235NDB6V0
U6 VMV6
U7 VCCPLE
U8 IO233NPB5V4
U9 IO222PPB5V3
U10 IO206PDB5V1
U11 IO202PDB5V1
U12 IO194PDB5V0
U13 IO176NDB4V2
U14 IO176PDB4V2
U15 VMV4
U16 TCK
U17 VPUMP
U18 TRST
U19 GDA0/IO153NDB3V4
U20 IO144NDB3V3
U21 IO140NDB3V3
U22 IO142PDB3V3
V1 IO239PDB6V0
V2 IO240NPB6V0
V3 GND
V4 GEA1/IO234PDB6V0
V5 GEA0/IO234NDB6V0
V6 GNDQ
V7 GEC2/IO231PDB5V4
V8 IO222NPB5V3
V9 IO204NDB5V1
V10 IO204PDB5V1
V11 IO195NDB5V0
V12 IO195PDB5V0
V13 IO178NDB4V3
V14 IO178PDB4V3
FG484
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-31
V15 IO155NDB4V0
V16 GDB2/IO155PDB4V0
V17 TDI
V18 GNDQ
V19 TDO
V20 GND
V21 IO146PDB3V4
V22 IO142NDB3V3
W1 IO239NDB6V0
W2 IO237PDB6V0
W3 IO230PSB5V4
W4 GND
W5 IO232NDB5V4
W6 GEB2/IO232PDB5V4
W7 IO231NDB5V4
W8 IO214NDB5V2
W9 IO214PDB5V2
W10 IO200NDB5V0
W11 IO192NDB4V4
W12 IO184NDB4V3
W13 IO184PDB4V3
W14 IO156NDB4V0
W15 GDC2/IO156PDB4V0
W16 IO154NDB4V0
W17 GDA2/IO154PDB4V0
W18 TMS
W19 GND
W20 IO150NDB3V4
W21 IO146NDB3V4
W22 IO148PPB3V4
Y1 VCCIB6
Y2 IO237NDB6V0
Y3 IO228NDB5V4
Y4 IO224NDB5V3
Y5 GND
Y6 IO220NDB5V3
FG484
Pin Number A3PE3000 Function
Y7 IO220PDB5V3
Y8 VCC
Y9 VCC
Y10 IO200PDB5V0
Y11 IO192PDB4V4
Y12 IO188NPB4V4
Y13 IO187PSB4V4
Y14 VCC
Y15 VCC
Y16 IO164NDB4V1
Y17 IO164PDB4V1
Y18 GND
Y19 IO158PPB4V0
Y20 IO150PDB3V4
Y21 IO148NPB3V4
Y22 VCCIB3
FG484
Pin Number A3PE3000 Function
Package Pin Assignments
4-32 Revision 10
FG676
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Note: This is the bottom view of the package.
A1 Ball Pad Corner
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1234567891011121314151617181920212223242526
ProASIC3E Flash Family FPGAs
Revision 10 4-33
FG676
Pin Number A3PE1500 Function
A1 GND
A2 GND
A3 GAA0/IO00NDB0V0
A4 GAA1/IO00PDB0V0
A5 IO06NDB0V0
A6 IO09NDB0V1
A7 IO09PDB0V1
A8 IO14NDB0V1
A9 IO14PDB0V1
A10 IO22NDB0V2
A11 IO22PDB0V2
A12 IO26NDB0V3
A13 IO26PDB0V3
A14 IO30NDB0V3
A15 IO30PDB0V3
A16 IO34NDB1V0
A17 IO34PDB1V0
A18 IO38NDB1V0
A19 IO38PDB1V0
A20 IO41PDB1V1
A21 IO44PDB1V1
A22 IO49PDB1V2
A23 IO50PDB1V2
A24 GBC1/IO55PDB1V3
A25 GND
A26 GND
AA1 IO174PDB6V0
AA2 IO171PDB6V0
AA3 GEA1/IO167PPB6V0
AA4 GEC0/IO169NPB6V0
AA5 VCOMPLE
AA6 GND
AA7 IO165NDB5V3
AA8 GEB2/IO165PDB5V3
AA9 IO163PDB5V3
AA10 IO159NDB5V3
AA11 IO153NDB5V2
AA12 IO147NDB5V1
AA13 IO139NDB5V0
AA14 IO137NDB5V0
AA15 IO123NDB4V1
AA16 IO123PDB4V1
AA17 IO117NDB4V0
AA18 IO117PDB4V0
AA19 GDB2/IO112PDB4V0
AA20 GNDQ
AA21 TDO
AA22 GND
AA23 GND
AA24 IO102NDB3V1
AA25 IO102PDB3V1
AA26 IO98NDB3V1
AB1 IO174NDB6V0
AB2 IO171NDB6V0
AB3 GEB1/IO168PPB6V0
AB4 GEA0/IO167NPB6V0
AB5 VCCPLE
AB6 GND
AB7 GND
AB8 IO156NDB5V2
AB9 IO156PDB5V2
AB10 IO150PDB5V1
AB11 IO155PDB5V2
AB12 IO142PDB5V0
AB13 IO135NDB5V0
AB14 IO135PDB5V0
AB15 IO132PDB4V2
AB16 IO129PDB4V2
AB17 IO121PDB4V1
AB18 IO119NDB4V1
AB19 IO112NDB4V0
AB20 VMV4
FG676
Pin Number A3PE1500 Function
AB21 TCK
AB22 TRST
AB23 GDC0/IO108NDB3V2
AB24 GDC1/IO108PDB3V2
AB25 IO104NDB3V2
AB26 IO104PDB3V2
AC1 IO170PDB6V0
AC2 GEB0/IO168NPB6V0
AC3 IO166NPB5V3
AC4 GNDQ
AC5 GND
AC6 IO160PDB5V3
AC7 IO161PDB5V3
AC8 IO154PDB5V2
AC9 GND
AC10 IO150NDB5V1
AC11 IO155NDB5V2
AC12 IO142NDB5V0
AC13 IO138NDB5V0
AC14 IO138PDB5V0
AC15 IO132NDB4V2
AC16 IO129NDB4V2
AC17 IO121NDB4V1
AC18 IO119PDB4V1
AC19 IO118NDB4V0
AC20 IO118PDB4V0
AC21 IO114PPB4V0
AC22 TMS
AC23 VJTAG
AC24 VMV3
AC25 IO106NDB3V2
AC26 IO106PDB3V2
AD1 IO170NDB6V0
AD2 GEA2/IO166PPB5V3
AD3 VMV5
AD4 GEC2/IO164PDB5V3
FG676
Pin Number A3PE1500 Function
Package Pin Assignments
4-34 Revision 10
AD5 IO162PDB5V3
AD6 IO160NDB5V3
AD7 IO161NDB5V3
AD8 IO154NDB5V2
AD9 IO148PDB5V1
AD10 IO151PDB5V2
AD11 IO144PDB5V1
AD12 IO140PDB5V0
AD13 IO143PDB5V1
AD14 IO141PDB5V0
AD15 IO134PDB4V2
AD16 IO133PDB4V2
AD17 IO127PDB4V2
AD18 IO130PDB4V2
AD19 IO126PDB4V1
AD20 IO124PDB4V1
AD21 IO120PDB4V1
AD22 IO114NPB4V0
AD23 TDI
AD24 GNDQ
AD25 GDA0/IO110NDB3V2
AD26 GDA1/IO110PDB3V2
AE1 GND
AE2 GND
AE3 GND
AE4 IO164NDB5V3
AE5 IO162NDB5V3
AE6 IO158PPB5V2
AE7 IO157PPB5V2
AE8 IO152PPB5V2
AE9 IO148NDB5V1
AE10 IO151NDB5V2
AE11 IO144NDB5V1
AE12 IO140NDB5V0
AE13 IO143NDB5V1
AE14 IO141NDB5V0
FG676
Pin Number A3PE1500 Function
AE15 IO134NDB4V2
AE16 IO133NDB4V2
AE17 IO127NDB4V2
AE18 IO130NDB4V2
AE19 IO126NDB4V1
AE20 IO124NDB4V1
AE21 IO120NDB4V1
AE22 IO116PDB4V0
AE23 GDC2/IO113PDB4V0
AE24 GDA2/IO111PDB4V0
AE25 GND
AE26 GND
AF1 GND
AF2 GND
AF3 GND
AF4 GND
AF5 IO158NPB5V2
AF6 IO157NPB5V2
AF7 IO152NPB5V2
AF8 IO146NDB5V1
AF9 IO146PDB5V1
AF10 IO149NDB5V1
AF11 IO149PDB5V1
AF12 IO145NDB5V1
AF13 IO145PDB5V1
AF14 IO136NDB5V0
AF15 IO136PDB5V0
AF16 IO131NDB4V2
AF17 IO131PDB4V2
AF18 IO128NDB4V2
AF19 IO128PDB4V2
AF20 IO122NDB4V1
AF21 IO122PDB4V1
AF22 IO116NDB4V0
AF23 IO113NDB4V0
AF24 IO111NDB4V0
FG676
Pin Number A3PE1500 Function
AF25 GND
AF26 GND
B1 GND
B2 GND
B3 GND
B4 GND
B5 IO06PDB0V0
B6 IO04NDB0V0
B7 IO07NDB0V0
B8 IO11NDB0V1
B9 IO10NDB0V1
B10 IO16NDB0V2
B11 IO20NDB0V2
B12 IO24NDB0V3
B13 IO23NDB0V2
B14 IO28NDB0V3
B15 IO31NDB0V3
B16 IO32PDB1V0
B17 IO36PDB1V0
B18 IO37PDB1V0
B19 IO42NPB1V1
B20 IO41NDB1V1
B21 IO44NDB1V1
B22 IO49NDB1V2
B23 IO50NDB1V2
B24 GBC0/IO55NDB1V3
B25 GND
B26 GND
C1 GND
C2 GND
C3 GND
C4 GND
C5 GAA2/IO221PDB7V3
C6 IO04PDB0V0
C7 IO07PDB0V0
C8 IO11PDB0V1
FG676
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-35
C9 IO10PDB0V1
C10 IO16PDB0V2
C11 IO20PDB0V2
C12 IO24PDB0V3
C13 IO23PDB0V2
C14 IO28PDB0V3
C15 IO31PDB0V3
C16 IO32NDB1V0
C17 IO36NDB1V0
C18 IO37NDB1V0
C19 IO45NDB1V1
C20 IO42PPB1V1
C21 IO46NPB1V1
C22 IO48NPB1V2
C23 GBB0/IO56NPB1V3
C24 VMV1
C25 GBC2/IO60PDB2V0
C26 IO60NDB2V0
D1 IO218NDB7V3
D2 IO218PDB7V3
D3 GND
D4 VMV7
D5 IO221NDB7V3
D6 GAC0/IO02NDB0V0
D7 GAC1/IO02PDB0V0
D8 IO05NDB0V0
D9 IO08PDB0V1
D10 IO12NDB0V1
D11 IO18NDB0V2
D12 IO17NDB0V2
D13 IO25NDB0V3
D14 IO29NDB0V3
D15 IO33NDB1V0
D16 IO40PDB1V1
D17 IO43NDB1V1
D18 IO47PDB1V1
FG676
Pin Number A3PE1500 Function
D19 IO45PDB1V1
D20 IO46PPB1V1
D21 IO48PPB1V2
D22 GBA0/IO57NPB1V3
D23 GNDQ
D24 GBB1/IO56PPB1V3
D25 GBB2/IO59PDB2V0
D26 IO59NDB2V0
E1 IO212PDB7V2
E2 IO211NDB7V2
E3 IO211PDB7V2
E4 IO220NPB7V3
E5 GNDQ
E6 GAB2/IO220PPB7V3
E7 GAB1/IO01PDB0V0
E8 IO05PDB0V0
E9 IO08NDB0V1
E10 IO12PDB0V1
E11 IO18PDB0V2
E12 IO17PDB0V2
E13 IO25PDB0V3
E14 IO29PDB0V3
E15 IO33PDB1V0
E16 IO40NDB1V1
E17 IO43PDB1V1
E18 IO47NDB1V1
E19 IO54NDB1V3
E20 IO52NDB1V2
E21 IO52PDB1V2
E22 VCCPLB
E23 GBA1/IO57PPB1V3
E24 IO63PDB2V0
E25 IO63NDB2V0
E26 IO68PDB2V1
F1 IO212NDB7V2
F2 IO203PPB7V1
FG676
Pin Number A3PE1500 Function
F3 IO213NDB7V2
F4 IO213PDB7V2
F5 GND
F6 VCCPLA
F7 GAB0/IO01NDB0V0
F8 GNDQ
F9 IO03PDB0V0
F10 IO13PDB0V1
F11 IO15PDB0V1
F12 IO19PDB0V2
F13 IO21PDB0V2
F14 IO27NDB0V3
F15 IO35PDB1V0
F16 IO39NDB1V0
F17 IO51PDB1V2
F18 IO53PDB1V2
F19 IO54PDB1V3
F20 VMV2
F21 VCOMPLB
F22 IO61PDB2V0
F23 IO61NDB2V0
F24 IO66PDB2V1
F25 IO66NDB2V1
F26 IO68NDB2V1
G1 IO203NPB7V1
G2 IO207NDB7V2
G3 IO207PDB7V2
G4 IO216NDB7V3
G5 IO216PDB7V3
G6 VCOMPLA
G7 VMV0
G8 VCC
G9 IO03NDB0V0
G10 IO13NDB0V1
G11 IO15NDB0V1
G12 IO19NDB0V2
FG676
Pin Number A3PE1500 Function
Package Pin Assignments
4-36 Revision 10
G13 IO21NDB0V2
G14 IO27PDB0V3
G15 IO35NDB1V0
G16 IO39PDB1V0
G17 IO51NDB1V2
G18 IO53NDB1V2
G19 VCCIB1
G20 GBA2/IO58PPB2V0
G21 GNDQ
G22 IO64NDB2V1
G23 IO64PDB2V1
G24 IO72PDB2V2
G25 IO72NDB2V2
G26 IO78PDB2V2
H1 IO208NDB7V2
H2 IO208PDB7V2
H3 IO209NDB7V2
H4 IO209PDB7V2
H5 IO219NDB7V3
H6 GAC2/IO219PDB7V3
H7 VCCIB7
H8 VCC
H9 VCCIB0
H10 VCCIB0
H11 VCCIB0
H12 VCCIB0
H13 VCCIB0
H14 VCCIB1
H15 VCCIB1
H16 VCCIB1
H17 VCCIB1
H18 VCCIB1
H19 VCC
H20 VCC
H21 IO58NPB2V0
H22 IO70PDB2V1
FG676
Pin Number A3PE1500 Function
H23 IO69PDB2V1
H24 IO76PDB2V2
H25 IO76NDB2V2
H26 IO78NDB2V2
J1 IO197NDB7V0
J2 IO197PDB7V0
J3 VMV7
J4 IO215NDB7V3
J5 IO215PDB7V3
J6 IO214PDB7V3
J7 IO214NDB7V3
J8 VCCIB7
J9 VCC
J10 VCC
J11 VCC
J12 VCC
J13 VCC
J14 VCC
J15 VCC
J16 VCC
J17 VCC
J18 VCC
J19 VCCIB2
J20 IO62PDB2V0
J21 IO62NDB2V0
J22 IO70NDB2V1
J23 IO69NDB2V1
J24 VMV2
J25 IO80PDB2V3
J26 IO80NDB2V3
K1 IO195PDB7V0
K2 IO199NDB7V1
K3 IO199PDB7V1
K4 IO205NDB7V1
K5 IO205PDB7V1
K6 IO217PDB7V3
FG676
Pin Number A3PE1500 Function
K7 IO217NDB7V3
K8 VCCIB7
K9 VCC
K10 GND
K11 GND
K12 GND
K13 GND
K14 GND
K15 GND
K16 GND
K17 GND
K18 VCC
K19 VCCIB2
K20 IO65PDB2V1
K21 IO65NDB2V1
K22 IO74PDB2V2
K23 IO74NDB2V2
K24 IO75PDB2V2
K25 IO75NDB2V2
K26 IO84PDB2V3
L1 IO195NDB7V0
L2 IO198PPB7V0
L3 GNDQ
L4 IO201PDB7V1
L5 IO201NDB7V1
L6 IO210NDB7V2
L7 IO210PDB7V2
L8 VCCIB7
L9 VCC
L10 GND
L11 GND
L12 GND
L13 GND
L14 GND
L15 GND
L16 GND
FG676
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-37
L17 GND
L18 VCC
L19 VCCIB2
L20 IO67PDB2V1
L21 IO67NDB2V1
L22 IO71PDB2V2
L23 IO71NDB2V2
L24 GNDQ
L25 IO82PDB2V3
L26 IO84NDB2V3
M1 IO198NPB7V0
M2 IO202PDB7V1
M3 IO202NDB7V1
M4 IO206NDB7V1
M5 IO206PDB7V1
M6 IO204NDB7V1
M7 IO204PDB7V1
M8 VCCIB7
M9 VCC
M10 GND
M11 GND
M12 GND
M13 GND
M14 GND
M15 GND
M16 GND
M17 GND
M18 VCC
M19 VCCIB2
M20 IO73NDB2V2
M21 IO73PDB2V2
M22 IO81PPB2V3
M23 IO77PDB2V2
M24 IO77NDB2V2
M25 IO82NDB2V3
M26 IO83PDB2V3
FG676
Pin Number A3PE1500 Function
N1 GFB0/IO191NPB7V0
N2 VCOMPLF
N3 GFB1/IO191PPB7V0
N4 IO196PDB7V0
N5 GFA0/IO190NDB6V2
N6 IO200PDB7V1
N7 IO200NDB7V1
N8 VCCIB7
N9 VCC
N10 GND
N11 GND
N12 GND
N13 GND
N14 GND
N15 GND
N16 GND
N17 GND
N18 VCC
N19 VCCIB2
N20 IO79PDB2V3
N21 IO79NDB2V3
N22 GCA2/IO88PPB3V0
N23 IO81NPB2V3
N24 GCA0/IO87NDB3V0
N25 GCB0/IO86NPB2V3
N26 IO83NDB2V3
P1 GFA2/IO189PDB6V2
P2 VCCPLF
P3 IO193PPB7V0
P4 IO196NDB7V0
P5 GFA1/IO190PDB6V2
P6 IO194PDB7V0
P7 IO194NDB7V0
P8 VCCIB6
P9 VCC
P10 GND
FG676
Pin Number A3PE1500 Function
P11 GND
P12 GND
P13 GND
P14 GND
P15 GND
P16 GND
P17 GND
P18 VCC
P19 VCCIB3
P20 GCC0/IO85NDB2V3
P21 GCC1/IO85PDB2V3
P22 GCB1/IO86PPB2V3
P23 IO88NPB3V0
P24 GCA1/IO87PDB3V0
P25 VCCPLC
P26 VCOMPLC
R1 IO189NDB6V2
R2 IO185PDB6V2
R3 IO187NPB6V2
R4 IO193NPB7V0
R5 GFC2/IO187PPB6V2
R6 GFC1/IO192PDB7V0
R7 GFC0/IO192NDB7V0
R8 VCCIB6
R9 VCC
R10 GND
R11 GND
R12 GND
R13 GND
R14 GND
R15 GND
R16 GND
R17 GND
R18 VCC
R19 VCCIB3
R20 NC
FG676
Pin Number A3PE1500 Function
Package Pin Assignments
4-38 Revision 10
R21 IO89NDB3V0
R22 GCB2/IO89PDB3V0
R23 IO90NDB3V0
R24 GCC2/IO90PDB3V0
R25 IO91PDB3V0
R26 IO91NDB3V0
T1 IO186PDB6V2
T2 IO185NDB6V2
T3 GNDQ
T4 IO180PDB6V1
T5 IO180NDB6V1
T6 IO188NDB6V2
T7 GFB2/IO188PDB6V2
T8 VCCIB6
T9 VCC
T10 GND
T11 GND
T12 GND
T13 GND
T14 GND
T15 GND
T16 GND
T17 GND
T18 VCC
T19 VCCIB3
T20 IO99PDB3V1
T21 IO99NDB3V1
T22 IO97PDB3V1
T23 IO97NDB3V1
T24 GNDQ
T25 IO93PPB3V0
T26 NC
U1 IO186NDB6V2
U2 IO184NDB6V2
U3 IO184PDB6V2
U4 IO182NDB6V1
FG676
Pin Number A3PE1500 Function
U5 IO182PDB6V1
U6 IO178PDB6V1
U7 IO178NDB6V1
U8 VCCIB6
U9 VCC
U10 GND
U11 GND
U12 GND
U13 GND
U14 GND
U15 GND
U16 GND
U17 GND
U18 VCC
U19 VCCIB3
U20 NC
U21 IO101NDB3V1
U22 IO101PDB3V1
U23 IO92NDB3V0
U24 IO92PDB3V0
U25 IO95PDB3V1
U26 IO93NPB3V0
V1 IO183PDB6V2
V2 IO183NDB6V2
V3 VMV6
V4 IO181PDB6V1
V5 IO181NDB6V1
V6 IO176PDB6V1
V7 IO176NDB6V1
V8 VCCIB6
V9 VCC
V10 VCC
V11 VCC
V12 VCC
V13 VCC
V14 VCC
FG676
Pin Number A3PE1500 Function
V15 VCC
V16 VCC
V17 VCC
V18 VCC
V19 VCCIB3
V20 IO107PDB3V2
V21 IO107NDB3V2
V22 IO103NDB3V2
V23 IO103PDB3V2
V24 VMV3
V25 IO95NDB3V1
V26 IO94PDB3V0
W1 IO179NDB6V1
W2 IO179PDB6V1
W3 IO177NDB6V1
W4 IO177PDB6V1
W5 IO172PDB6V0
W6 IO172NDB6V0
W7 VCC
W8 VCC
W9 VCCIB5
W10 VCCIB5
W11 VCCIB5
W12 VCCIB5
W13 VCCIB5
W14 VCCIB4
W15 VCCIB4
W16 VCCIB4
W17 VCCIB4
W18 VCCIB4
W19 VCC
W20 VCCIB3
W21 GDB0/IO109NDB3V2
W22 GDB1/IO109PDB3V2
W23 IO105NDB3V2
W24 IO105PDB3V2
FG676
Pin Number A3PE1500 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-39
W25 IO96PDB3V1
W26 IO94NDB3V0
Y1 IO175NDB6V1
Y2 IO175PDB6V1
Y3 IO173NDB6V0
Y4 IO173PDB6V0
Y5 GEC1/IO169PPB6V0
Y6 GNDQ
Y7 VMV6
Y8 VCCIB5
Y9 IO163NDB5V3
Y10 IO159PDB5V3
Y11 IO153PDB5V2
Y12 IO147PDB5V1
Y13 IO139PDB5V0
Y14 IO137PDB5V0
Y15 IO125NDB4V1
Y16 IO125PDB4V1
Y17 IO115NDB4V0
Y18 IO115PDB4V0
Y19 VCC
Y20 VPUMP
Y21 VCOMPLD
Y22 VCCPLD
Y23 IO100NDB3V1
Y24 IO100PDB3V1
Y25 IO96NDB3V1
Y26 IO98PDB3V1
FG676
Pin Number A3PE1500 Function
Package Pin Assignments
4-40 Revision 10
FG896
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Note: This is the bottom view of the package.
A1 Ball Pad Corner
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
123456789101112131415161718192021222324252627282930
AG
AH
AJ
AK
ProASIC3E Flash Family FPGAs
Revision 10 4-41
FG896
Pin Number A3PE3000 Function
A2 GND
A3 GND
A4 IO14NPB0V1
A5 GND
A6 IO07NPB0V0
A7 GND
A8 IO09NDB0V1
A9 IO17NDB0V2
A10 IO17PDB0V2
A11 IO21NDB0V2
A12 IO21PDB0V2
A13 IO33NDB0V4
A14 IO33PDB0V4
A15 IO35NDB0V4
A16 IO35PDB0V4
A17 IO41NDB1V0
A18 IO43NDB1V0
A19 IO43PDB1V0
A20 IO45NDB1V0
A21 IO45PDB1V0
A22 IO57NDB1V2
A23 IO57PDB1V2
A24 GND
A25 IO69PPB1V3
A26 GND
A27 GBC1/IO79PPB1V4
A28 GND
A29 GND
AA1 IO256PDB6V2
AA2 IO248PDB6V1
AA3 IO248NDB6V1
AA4 IO246NDB6V1
AA5 GEA1/IO234PDB6V0
AA6 GEA0/IO234NDB6V0
AA7 IO243PPB6V1
AA8 IO245NDB6V1
AA9 GEB1/IO235PPB6V0
AA10 VCC
AA11 IO226PPB5V4
AA12 VCCIB5
AA13 VCCIB5
AA14 VCCIB5
AA15 VCCIB5
AA16 VCCIB4
AA17 VCCIB4
AA18 VCCIB4
AA19 VCCIB4
AA20 IO174PDB4V2
AA21 VCC
AA22 IO142NPB3V3
AA23 IO144NDB3V3
AA24 IO144PDB3V3
AA25 IO146NDB3V4
AA26 IO146PDB3V4
AA27 IO147PDB3V4
AA28 IO139NDB3V3
AA29 IO139PDB3V3
AA30 IO133NDB3V2
AB1 IO256NDB6V2
AB2 IO244PDB6V1
AB3 IO244NDB6V1
AB4 IO241PDB6V0
AB5 IO241NDB6V0
AB6 IO243NPB6V1
AB7 VCCIB6
AB8 VCCPLE
AB9 VCC
AB10 IO222PDB5V3
AB11 IO218PPB5V3
AB12 IO206NDB5V1
AB13 IO206PDB5V1
AB14 IO198NDB5V0
FG896
Pin Number A3PE3000 Function
AB15 IO198PDB5V0
AB16 IO192NDB4V4
AB17 IO192PDB4V4
AB18 IO178NDB4V3
AB19 IO178PDB4V3
AB20 IO174NDB4V2
AB21 IO162NPB4V1
AB22 VCC
AB23 VCCPLD
AB24 VCCIB3
AB25 IO150PDB3V4
AB26 IO148PDB3V4
AB27 IO147NDB3V4
AB28 IO145PDB3V3
AB29 IO143PDB3V3
AB30 IO137PDB3V2
AC1 IO254PDB6V2
AC2 IO254NDB6V2
AC3 IO240PDB6V0
AC4 GEC1/IO236PDB6V0
AC5 IO237PDB6V0
AC6 IO237NDB6V0
AC7 VCOMPLE
AC8 GND
AC9 IO226NPB5V4
AC10 IO222NDB5V3
AC11 IO216NPB5V2
AC12 IO210NPB5V2
AC13 IO204NDB5V1
AC14 IO204PDB5V1
AC15 IO194NDB5V0
AC16 IO188NDB4V4
AC17 IO188PDB4V4
AC18 IO182PPB4V3
AC19 IO170NPB4V2
AC20 IO164NDB4V1
FG896
Pin Number A3PE3000 Function
Package Pin Assignments
4-42 Revision 10
AC21 IO164PDB4V1
AC22 IO162PPB4V1
AC23 GND
AC24 VCOMPLD
AC25 IO150NDB3V4
AC26 IO148NDB3V4
AC27 GDA1/IO153PDB3V4
AC28 IO145NDB3V3
AC29 IO143NDB3V3
AC30 IO137NDB3V2
AD1 GND
AD2 IO242NPB6V1
AD3 IO240NDB6V0
AD4 GEC0/IO236NDB6V0
AD5 VCCIB6
AD6 GNDQ
AD7 VCC
AD8 VMV5
AD9 VCCIB5
AD10 IO224PPB5V3
AD11 IO218NPB5V3
AD12 IO216PPB5V2
AD13 IO210PPB5V2
AD14 IO202PPB5V1
AD15 IO194PDB5V0
AD16 IO190PDB4V4
AD17 IO182NPB4V3
AD18 IO176NDB4V2
AD19 IO176PDB4V2
AD20 IO170PPB4V2
AD21 IO166PDB4V1
AD22 VCCIB4
AD23 TCK
AD24 VCC
AD25 TRST
AD26 VCCIB3
FG896
Pin Number A3PE3000 Function
AD27 GDA0/IO153NDB3V4
AD28 GDC0/IO151NDB3V4
AD29 GDC1/IO151PDB3V4
AD30 GND
AE1 IO242PPB6V1
AE2 VCC
AE3 IO239PDB6V0
AE4 IO239NDB6V0
AE5 VMV6
AE6 GND
AE7 GNDQ
AE8 IO230NDB5V4
AE9 IO224NPB5V3
AE10 IO214NPB5V2
AE11 IO212NDB5V2
AE12 IO212PDB5V2
AE13 IO202NPB5V1
AE14 IO200NDB5V0
AE15 IO196PDB5V0
AE16 IO190NDB4V4
AE17 IO184PDB4V3
AE18 IO184NDB4V3
AE19 IO172PDB4V2
AE20 IO172NDB4V2
AE21 IO166NDB4V1
AE22 IO160PDB4V0
AE23 GNDQ
AE24 VMV4
AE25 GND
AE26 GDB0/IO152NDB3V4
AE27 GDB1/IO152PDB3V4
AE28 VMV3
AE29 VCC
AE30 IO149PDB3V4
AF1 GND
AF2 IO238PPB6V0
FG896
Pin Number A3PE3000 Function
AF3 VCCIB6
AF4 IO220NPB5V3
AF5 VCC
AF6 IO228NDB5V4
AF7 VCCIB5
AF8 IO230PDB5V4
AF9 IO229NDB5V4
AF10 IO229PDB5V4
AF11 IO214PPB5V2
AF12 IO208NDB5V1
AF13 IO208PDB5V1
AF14 IO200PDB5V0
AF15 IO196NDB5V0
AF16 IO186NDB4V4
AF17 IO186PDB4V4
AF18 IO180NDB4V3
AF19 IO180PDB4V3
AF20 IO168NDB4V1
AF21 IO168PDB4V1
AF22 IO160NDB4V0
AF23 IO158NPB4V0
AF24 VCCIB4
AF25 IO154NPB4V0
AF26 VCC
AF27 TDO
AF28 VCCIB3
AF29 GNDQ
AF30 GND
AG1 IO238NPB6V0
AG2 VCC
AG3 IO232NPB5V4
AG4 GND
AG5 IO220PPB5V3
AG6 IO228PDB5V4
AG7 IO231NDB5V4
AG8 GEC2/IO231PDB5V4
FG896
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-43
AG9 IO225NPB5V3
AG10 IO223NPB5V3
AG11 IO221PDB5V3
AG12 IO221NDB5V3
AG13 IO205NPB5V1
AG14 IO199NDB5V0
AG15 IO199PDB5V0
AG16 IO187NDB4V4
AG17 IO187PDB4V4
AG18 IO181NDB4V3
AG19 IO171PPB4V2
AG20 IO165NPB4V1
AG21 IO161NPB4V0
AG22 IO159NDB4V0
AG23 IO159PDB4V0
AG24 IO158PPB4V0
AG25 GDB2/IO155PDB4V0
AG26 GDA2/IO154PPB4V0
AG27 GND
AG28 VJTAG
AG29 VCC
AG30 IO149NDB3V4
AH1 GND
AH2 IO233NPB5V4
AH3 VCC
AH4 GEB2/IO232PPB5V4
AH5 VCCIB5
AH6 IO219NDB5V3
AH7 IO219PDB5V3
AH8 IO227NDB5V4
AH9 IO227PDB5V4
AH10 IO225PPB5V3
AH11 IO223PPB5V3
AH12 IO211NDB5V2
AH13 IO211PDB5V2
AH14 IO205PPB5V1
FG896
Pin Number A3PE3000 Function
AH15 IO195NDB5V0
AH16 IO185NDB4V3
AH17 IO185PDB4V3
AH18 IO181PDB4V3
AH19 IO177NDB4V2
AH20 IO171NPB4V2
AH21 IO165PPB4V1
AH22 IO161PPB4V0
AH23 IO157NDB4V0
AH24 IO157PDB4V0
AH25 IO155NDB4V0
AH26 VCCIB4
AH27 TDI
AH28 VCC
AH29 VPUMP
AH30 GND
AJ1 GND
AJ2 GND
AJ3 GEA2/IO233PPB5V4
AJ4 VCC
AJ5 IO217NPB5V2
AJ6 VCC
AJ7 IO215NPB5V2
AJ8 IO213NDB5V2
AJ9 IO213PDB5V2
AJ10 IO209NDB5V1
AJ11 IO209PDB5V1
AJ12 IO203NDB5V1
AJ13 IO203PDB5V1
AJ14 IO197NDB5V0
AJ15 IO195PDB5V0
AJ16 IO183NDB4V3
AJ17 IO183PDB4V3
AJ18 IO179NPB4V3
AJ19 IO177PDB4V2
AJ20 IO173NDB4V2
FG896
Pin Number A3PE3000 Function
AJ21 IO173PDB4V2
AJ22 IO163NDB4V1
AJ23 IO163PDB4V1
AJ24 IO167NPB4V1
AJ25 VCC
AJ26 IO156NPB4V0
AJ27 VCC
AJ28 TMS
AJ29 GND
AJ30 GND
AK2 GND
AK3 GND
AK4 IO217PPB5V2
AK5 GND
AK6 IO215PPB5V2
AK7 GND
AK8 IO207NDB5V1
AK9 IO207PDB5V1
AK10 IO201NDB5V0
AK11 IO201PDB5V0
AK12 IO193NDB4V4
AK13 IO193PDB4V4
AK14 IO197PDB5V0
AK15 IO191NDB4V4
AK16 IO191PDB4V4
AK17 IO189NDB4V4
AK18 IO189PDB4V4
AK19 IO179PPB4V3
AK20 IO175NDB4V2
AK21 IO175PDB4V2
AK22 IO169NDB4V1
AK23 IO169PDB4V1
AK24 GND
AK25 IO167PPB4V1
AK26 GND
AK27 GDC2/IO156PPB4V0
FG896
Pin Number A3PE3000 Function
Package Pin Assignments
4-44 Revision 10
AK28 GND
AK29 GND
B1 GND
B2 GND
B3 GAA2/IO309PPB7V4
B4 VCC
B5 IO14PPB0V1
B6 VCC
B7 IO07PPB0V0
B8 IO09PDB0V1
B9 IO15PPB0V1
B10 IO19NDB0V2
B11 IO19PDB0V2
B12 IO29NDB0V3
B13 IO29PDB0V3
B14 IO31PPB0V3
B15 IO37NDB0V4
B16 IO37PDB0V4
B17 IO41PDB1V0
B18 IO51NDB1V1
B19 IO59PDB1V2
B20 IO53PDB1V1
B21 IO53NDB1V1
B22 IO61NDB1V2
B23 IO61PDB1V2
B24 IO69NPB1V3
B25 VCC
B26 GBC0/IO79NPB1V4
B27 VCC
B28 IO64NPB1V2
B29 GND
B30 GND
C1 GND
C2 IO309NPB7V4
C3 VCC
C4 GAA0/IO00NPB0V0
FG896
Pin Number A3PE3000 Function
C5 VCCIB0
C6 IO03PDB0V0
C7 IO03NDB0V0
C8 GAB1/IO01PDB0V0
C9 IO05PDB0V0
C10 IO15NPB0V1
C11 IO25NDB0V3
C12 IO25PDB0V3
C13 IO31NPB0V3
C14 IO27NDB0V3
C15 IO39NDB0V4
C16 IO39PDB0V4
C17 IO55PPB1V1
C18 IO51PDB1V1
C19 IO59NDB1V2
C20 IO63NDB1V2
C21 IO63PDB1V2
C22 IO67NDB1V3
C23 IO67PDB1V3
C24 IO75NDB1V4
C25 IO75PDB1V4
C26 VCCIB1
C27 IO64PPB1V2
C28 VCC
C29 GBA1/IO81PPB1V4
C30 GND
D1 IO303PPB7V3
D2 VCC
D3 IO305NPB7V3
D4 GND
D5 GAA1/IO00PPB0V0
D6 GAC1/IO02PDB0V0
D7 IO06NPB0V0
D8 GAB0/IO01NDB0V0
D9 IO05NDB0V0
D10 IO11NDB0V1
FG896
Pin Number A3PE3000 Function
D11 IO11PDB0V1
D12 IO23NDB0V2
D13 IO23PDB0V2
D14 IO27PDB0V3
D15 IO40PDB0V4
D16 IO47NDB1V0
D17 IO47PDB1V0
D18 IO55NPB1V1
D19 IO65NDB1V3
D20 IO65PDB1V3
D21 IO71NDB1V3
D22 IO71PDB1V3
D23 IO73NDB1V4
D24 IO73PDB1V4
D25 IO74NDB1V4
D26 GBB0/IO80NPB1V4
D27 GND
D28 GBA0/IO81NPB1V4
D29 VCC
D30 GBA2/IO82PPB2V0
E1 GND
E2 IO303NPB7V3
E3 VCCIB7
E4 IO305PPB7V3
E5 VCC
E6 GAC0/IO02NDB0V0
E7 VCCIB0
E8 IO06PPB0V0
E9 IO24NDB0V2
E10 IO24PDB0V2
E11 IO13NDB0V1
E12 IO13PDB0V1
E13 IO34NDB0V4
E14 IO34PDB0V4
E15 IO40NDB0V4
E16 IO49NDB1V1
FG896
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-45
E17 IO49PDB1V1
E18 IO50PDB1V1
E19 IO58PDB1V2
E20 IO60NDB1V2
E21 IO77PDB1V4
E22 IO68NDB1V3
E23 IO68PDB1V3
E24 VCCIB1
E25 IO74PDB1V4
E26 VCC
E27 GBB1/IO80PPB1V4
E28 VCCIB2
E29 IO82NPB2V0
E30 GND
F1 IO296PPB7V2
F2 VCC
F3 IO306PDB7V4
F4 IO297PDB7V2
F5 VMV7
F6 GND
F7 GNDQ
F8 IO12NDB0V1
F9 IO12PDB0V1
F10 IO10PDB0V1
F11 IO16PDB0V1
F12 IO22NDB0V2
F13 IO30NDB0V3
F14 IO30PDB0V3
F15 IO36PDB0V4
F16 IO48NDB1V0
F17 IO48PDB1V0
F18 IO50NDB1V1
F19 IO58NDB1V2
F20 IO60PDB1V2
F21 IO77NDB1V4
F22 IO72NDB1V3
FG896
Pin Number A3PE3000 Function
F23 IO72PDB1V3
F24 GNDQ
F25 GND
F26 VMV2
F27 IO86PDB2V0
F28 IO92PDB2V1
F29 VCC
F30 IO100NPB2V2
G1 GND
G2 IO296NPB7V2
G3 IO306NDB7V4
G4 IO297NDB7V2
G5 VCCIB7
G6 GNDQ
G7 VCC
G8 VMV0
G9 VCCIB0
G10 IO10NDB0V1
G11 IO16NDB0V1
G12 IO22PDB0V2
G13 IO26PPB0V3
G14 IO38NPB0V4
G15 IO36NDB0V4
G16 IO46NDB1V0
G17 IO46PDB1V0
G18 IO56NDB1V1
G19 IO56PDB1V1
G20 IO66NDB1V3
G21 IO66PDB1V3
G22 VCCIB1
G23 VMV1
G24 VCC
G25 GNDQ
G26 VCCIB2
G27 IO86NDB2V0
G28 IO92NDB2V1
FG896
Pin Number A3PE3000 Function
G29 IO100PPB2V2
G30 GND
H1 IO294PDB7V2
H2 IO294NDB7V2
H3 IO300NDB7V3
H4 IO300PDB7V3
H5 IO295PDB7V2
H6 IO299PDB7V3
H7 VCOMPLA
H8 GND
H9 IO08NDB0V0
H10 IO08PDB0V0
H11 IO18PDB0V2
H12 IO26NPB0V3
H13 IO28NDB0V3
H14 IO28PDB0V3
H15 IO38PPB0V4
H16 IO42NDB1V0
H17 IO52NDB1V1
H18 IO52PDB1V1
H19 IO62NDB1V2
H20 IO62PDB1V2
H21 IO70NDB1V3
H22 IO70PDB1V3
H23 GND
H24 VCOMPLB
H25 GBC2/IO84PDB2V0
H26 IO84NDB2V0
H27 IO96PDB2V1
H28 IO96NDB2V1
H29 IO89PDB2V0
H30 IO89NDB2V0
J1 IO290NDB7V2
J2 IO290PDB7V2
J3 IO302NDB7V3
J4 IO302PDB7V3
FG896
Pin Number A3PE3000 Function
Package Pin Assignments
4-46 Revision 10
J5 IO295NDB7V2
J6 IO299NDB7V3
J7 VCCIB7
J8 VCCPLA
J9 VCC
J10 IO04NPB0V0
J11 IO18NDB0V2
J12 IO20NDB0V2
J13 IO20PDB0V2
J14 IO32NDB0V3
J15 IO32PDB0V3
J16 IO42PDB1V0
J17 IO44NDB1V0
J18 IO44PDB1V0
J19 IO54NDB1V1
J20 IO54PDB1V1
J21 IO76NPB1V4
J22 VCC
J23 VCCPLB
J24 VCCIB2
J25 IO90PDB2V1
J26 IO90NDB2V1
J27 GBB2/IO83PDB2V0
J28 IO83NDB2V0
J29 IO91PDB2V1
J30 IO91NDB2V1
K1 IO288NDB7V1
K2 IO288PDB7V1
K3 IO304NDB7V3
K4 IO304PDB7V3
K5 GAB2/IO308PDB7V4
K6 IO308NDB7V4
K7 IO301PDB7V3
K8 IO301NDB7V3
K9 GAC2/IO307PPB7V4
K10 VCC
FG896
Pin Number A3PE3000 Function
K11 IO04PPB0V0
K12 VCCIB0
K13 VCCIB0
K14 VCCIB0
K15 VCCIB0
K16 VCCIB1
K17 VCCIB1
K18 VCCIB1
K19 VCCIB1
K20 IO76PPB1V4
K21 VCC
K22 IO78PPB1V4
K23 IO88NDB2V0
K24 IO88PDB2V0
K25 IO94PDB2V1
K26 IO94NDB2V1
K27 IO85PDB2V0
K28 IO85NDB2V0
K29 IO93PDB2V1
K30 IO93NDB2V1
L1 IO286NDB7V1
L2 IO286PDB7V1
L3 IO298NDB7V3
L4 IO298PDB7V3
L5 IO283PDB7V1
L6 IO291NDB7V2
L7 IO291PDB7V2
L8 IO293PDB7V2
L9 IO293NDB7V2
L10 IO307NPB7V4
L11 VCC
L12 VCC
L13 VCC
L14 VCC
L15 VCC
L16 VCC
FG896
Pin Number A3PE3000 Function
L17 VCC
L18 VCC
L19 VCC
L20 VCC
L21 IO78NPB1V4
L22 IO104NPB2V2
L23 IO98NDB2V2
L24 IO98PDB2V2
L25 IO87PDB2V0
L26 IO87NDB2V0
L27 IO97PDB2V1
L28 IO101PDB2V2
L29 IO103PDB2V2
L30 IO119NDB3V0
M1 IO282NDB7V1
M2 IO282PDB7V1
M3 IO292NDB7V2
M4 IO292PDB7V2
M5 IO283NDB7V1
M6 IO285PDB7V1
M7 IO287PDB7V1
M8 IO289PDB7V1
M9 IO289NDB7V1
M10 VCCIB7
M11 VCC
M12 GND
M13 GND
M14 GND
M15 GND
M16 GND
M17 GND
M18 GND
M19 GND
M20 VCC
M21 VCCIB2
M22 NC
FG896
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-47
M23 IO104PPB2V2
M24 IO102PDB2V2
M25 IO102NDB2V2
M26 IO95PDB2V1
M27 IO97NDB2V1
M28 IO101NDB2V2
M29 IO103NDB2V2
M30 IO119PDB3V0
N1 IO276PDB7V0
N2 IO278PDB7V0
N3 IO280PDB7V0
N4 IO284PDB7V1
N5 IO279PDB7V0
N6 IO285NDB7V1
N7 IO287NDB7V1
N8 IO281NDB7V0
N9 IO281PDB7V0
N10 VCCIB7
N11 VCC
N12 GND
N13 GND
N14 GND
N15 GND
N16 GND
N17 GND
N18 GND
N19 GND
N20 VCC
N21 VCCIB2
N22 IO106NDB2V3
N23 IO106PDB2V3
N24 IO108PDB2V3
N25 IO108NDB2V3
N26 IO95NDB2V1
N27 IO99NDB2V2
N28 IO99PDB2V2
FG896
Pin Number A3PE3000 Function
N29 IO107PDB2V3
N30 IO107NDB2V3
P1 IO276NDB7V0
P2 IO278NDB7V0
P3 IO280NDB7V0
P4 IO284NDB7V1
P5 IO279NDB7V0
P6 GFC1/IO275PDB7V0
P7 GFC0/IO275NDB7V0
P8 IO277PDB7V0
P9 IO277NDB7V0
P10 VCCIB7
P11 VCC
P12 GND
P13 GND
P14 GND
P15 GND
P16 GND
P17 GND
P18 GND
P19 GND
P20 VCC
P21 VCCIB2
P22 GCC1/IO112PDB2V3
P23 IO110PDB2V3
P24 IO110NDB2V3
P25 IO109PPB2V3
P26 IO111NPB2V3
P27 IO105PDB2V2
P28 IO105NDB2V2
P29 GCC2/IO117PDB3V0
P30 IO117NDB3V0
R1 GFC2/IO270PDB6V4
R2 GFB1/IO274PPB7V0
R3 VCOMPLF
R4 GFA0/IO273NDB6V4
FG896
Pin Number A3PE3000 Function
R5 GFB0/IO274NPB7V0
R6 IO271NDB6V4
R7 GFB2/IO271PDB6V4
R8 IO269PDB6V4
R9 IO269NDB6V4
R10 VCCIB7
R11 VCC
R12 GND
R13 GND
R14 GND
R15 GND
R16 GND
R17 GND
R18 GND
R19 GND
R20 VCC
R21 VCCIB2
R22 GCC0/IO112NDB2V3
R23 GCB2/IO116PDB3V0
R24 IO118PDB3V0
R25 IO111PPB2V3
R26 IO122PPB3V1
R27 GCA0/IO114NPB3V0
R28 VCOMPLC
R29 GCB1/IO113PPB2V3
R30 IO115NPB3V0
T1 IO270NDB6V4
T2 VCCPLF
T3 GFA2/IO272PPB6V4
T4 GFA1/IO273PDB6V4
T5 IO272NPB6V4
T6 IO267NDB6V4
T7 IO267PDB6V4
T8 IO265PDB6V3
T9 IO263PDB6V3
T10 VCCIB6
FG896
Pin Number A3PE3000 Function
Package Pin Assignments
4-48 Revision 10
T11 VCC
T12 GND
T13 GND
T14 GND
T15 GND
T16 GND
T17 GND
T18 GND
T19 GND
T20 VCC
T21 VCCIB3
T22 IO109NPB2V3
T23 IO116NDB3V0
T24 IO118NDB3V0
T25 IO122NPB3V1
T26 GCA1/IO114PPB3V0
T27 GCB0/IO113NPB2V3
T28 GCA2/IO115PPB3V0
T29 VCCPLC
T30 IO121PDB3V0
U1 IO268PDB6V4
U2 IO264NDB6V3
U3 IO264PDB6V3
U4 IO258PDB6V3
U5 IO258NDB6V3
U6 IO257PPB6V2
U7 IO261PPB6V3
U8 IO265NDB6V3
U9 IO263NDB6V3
U10 VCCIB6
U11 VCC
U12 GND
U13 GND
U14 GND
U15 GND
U16 GND
FG896
Pin Number A3PE3000 Function
U17 GND
U18 GND
U19 GND
U20 VCC
U21 VCCIB3
U22 IO120PDB3V0
U23 IO128PDB3V1
U24 IO124PDB3V1
U25 IO124NDB3V1
U26 IO126PDB3V1
U27 IO129PDB3V1
U28 IO127PDB3V1
U29 IO125PDB3V1
U30 IO121NDB3V0
V1 IO268NDB6V4
V2 IO262PDB6V3
V3 IO260PDB6V3
V4 IO252PDB6V2
V5 IO257NPB6V2
V6 IO261NPB6V3
V7 IO255PDB6V2
V8 IO259PDB6V3
V9 IO259NDB6V3
V10 VCCIB6
V11 VCC
V12 GND
V13 GND
V14 GND
V15 GND
V16 GND
V17 GND
V18 GND
V19 GND
V20 VCC
V21 VCCIB3
V22 IO120NDB3V0
FG896
Pin Number A3PE3000 Function
V23 IO128NDB3V1
V24 IO132PDB3V2
V25 IO130PPB3V2
V26 IO126NDB3V1
V27 IO129NDB3V1
V28 IO127NDB3V1
V29 IO125NDB3V1
V30 IO123PDB3V1
W1 IO266NDB6V4
W2 IO262NDB6V3
W3 IO260NDB6V3
W4 IO252NDB6V2
W5 IO251NDB6V2
W6 IO251PDB6V2
W7 IO255NDB6V2
W8 IO249PPB6V1
W9 IO253PDB6V2
W10 VCCIB6
W11 VCC
W12 GND
W13 GND
W14 GND
W15 GND
W16 GND
W17 GND
W18 GND
W19 GND
W20 VCC
W21 VCCIB3
W22 IO134PDB3V2
W23 IO138PDB3V3
W24 IO132NDB3V2
W25 IO136NPB3V2
W26 IO130NPB3V2
W27 IO141PDB3V3
W28 IO135PDB3V2
FG896
Pin Number A3PE3000 Function
ProASIC3E Flash Family FPGAs
Revision 10 4-49
W29 IO131PDB3V2
W30 IO123NDB3V1
Y1 IO266PDB6V4
Y2 IO250PDB6V2
Y3 IO250NDB6V2
Y4 IO246PDB6V1
Y5 IO247NDB6V1
Y6 IO247PDB6V1
Y7 IO249NPB6V1
Y8 IO245PDB6V1
Y9 IO253NDB6V2
Y10 GEB0/IO235NPB6V0
Y11 VCC
Y12 VCC
Y13 VCC
Y14 VCC
Y15 VCC
Y16 VCC
Y17 VCC
Y18 VCC
Y19 VCC
Y20 VCC
Y21 IO142PPB3V3
Y22 IO134NDB3V2
Y23 IO138NDB3V3
Y24 IO140NDB3V3
Y25 IO140PDB3V3
Y26 IO136PPB3V2
Y27 IO141NDB3V3
Y28 IO135NDB3V2
Y29 IO131NDB3V2
Y30 IO133PDB3V2
FG896
Pin Number A3PE3000 Function
Revision 10 5-1
5 – Dat asheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3E datasheet.
Revision Changes Page
Revision 10
(March 2012) The "In-System Programming (ISP) and Security" section and "Security" section
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in
the industry (SAR 34669).
I, 1-1
The Y security option and Licensed DPA Logo were added to the "ProASIC3E
Ordering Information" section. The trademarked Licensed DPA Logo identifies
that a product is covered by a DPA counter-measures license from Cryptog raphy
Research (SAR 34727).
III
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-
voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG
interface" (SAR 34689).
1-3
The "Specifying I/O States During Programming" section is new (SAR 34699). 1-6
VCCPLL in Table 2-2 • Recommended Operating Conditions 1 was corrected
from "1.4 to 1.6 V" to "1.425 to 1.575 V" (SAR 33851).
The TJ symbol was added to the table and notes regarding TA and TJ were
removed. The second of two parameters in the VCCI and VMV row, called "3.3 V
DC supply voltage," was corrected to "3.0 V DC supply voltage" (SAR 37227).
2-2
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3E
FPGA Fabric User's Guide (SAR 34735).
2-10
tDOUT was corrected to tDIN in Figure 2 -3 • Input Buffer Timing Model and Delays
(example) (SAR 37109). 2-14
The typo related to the values for 3.3 V LVCMOS Wide Range in Table 2-17
Summary of I/O Timing Characteristics—Software Default Settings was
corrected (SAR 37227).
2-20
The notes regarding drive strength in the "Summary of I/O Timing Characteristics
– Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range"
section and tables were revised for clarification. They now state that the minimum
drive strength for the default software configuration when run in wide range is
±100 µA. The drive strength displayed in software is supported in normal range
only. For a detailed I/V curve, refer to the IBIS models (SAR 34763).
2-19, 2-27
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-19 • I/O Output Buffer Maximum
Resistances1 and Table 2-21 • I/O Short Currents IOSH/IOSL was replaced by
"Same as regular 3.3 V LVCMOS" (SAR 33853).
3.3 V LVCMOS Wide Range information was separated from regular 3.3 V
LVCMOS and placed into its own new section, "3.3 V LVCMOS Wide Range".
Values of IOSH and IOSL were added in Table 2-29 • Minimum and Maximum DC
Input and Output Levels (SAR 33853).
2-21,
2-23
Datasheet Information
5-2 Revision 10
Revision 10
(continued) The formulas in the table notes for Table 2-20 • I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 34755). 2-22
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default
I/O Software Settings" section (SAR 34889).
2-25
The titles and subtitles for Table 2-31 • 3.3 V LVCMOS Wide Range High Slew
and Table 2-32 • 3.3 V LVCMOS Wide Range Low Slew were corrected (SAR
37227).
2-28, 2-29
The following notes were removed from Table 2-78 • LVDS Minimum and
Maximum DC Input and Output Levels (SAR 34812):
±5%
Differential input voltage = ±350 mV
2-50
Minimum pulse width High and Low values were added to the tables in the
"Global Tree Timing Characteristics" section. The maximum frequency for global
clock parameter was removed from these tables because a frequency on the
global is only an indication of what the global network can do. There are other
limiters such as the SRAM, I/Os, and PLL. SmartTime sof tware should be used to
determine the design frequency (SAR 36957).
2-68
A note was added to Table 2-98 • ProASIC3E CCC/PLL Specification indicating
that when the CCC/PLL core is generated by Microsemi core generator software,
not all delay values of the specified del ay increments are available (SAR 34824).
2-70
The following figures were deleted. Reference was made to a new application
note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based
cSoCs and FPGAs, which covers these cases in detail (SAR 34872).
Figure 2-44 • Write Access after Write onto Same Address
Figure 2-45 • Read Access after Write onto Same Address
Figure 2-46 • Write Access after Read onto Same Address
The port names in the SRAM "Timing Waveforms", SRAM "Timing
Characteristics" tables, Figure 2-47 • FIFO Reset, and the FIFO "Timing
Characteristics" tables were revised to ensure consistency with the software
names (SAR 35750).
2-73,
2-76,
2-79,
2-81
The "Pin Descriptions and Packaging" chapter is new (SAR 34771). 3-1
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 34771). 4-1
Pin E6 for the FG256 package was corrected from VvB0 to VCCIB0 (SARs
30364, 31597, 26243). 4-9
July 2010 The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The "ProASIC3E Device Status" table on page II indicates the status for each
device in the device family.
N/A
Revision Changes Page
ProASIC3E Flash Family FPGAs
Revision 10 5-3
Revision Changes Page
Revision 9 (Aug 2009)
Product Brief v1.2 All references to speed grade –F have been removed from this document. N/A
The "Pro I/Os with Advanced I/O Standards" section was revised to add
definitions of hot-swap and cold-sparing. 1-6
DC and Switching
Characteristics v1.3 3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
N/A
IIL and IIH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables. N/A
–F was removed from the datasheet. The speed grade is no longer supported. N/A
In the Table 2-2 • Recommended Operating Conditions 1 "3.0 V DC supply
voltage" and note 4 are new. 2-2
The Table 2-4 • Overshoot and Unde rshoot Limits 1 table was updated. 2-3
The Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
table was updated. 2-5
There are new parameters and data was updated in the Table 2-99 • RAM4K9
table. 2-76
There are new parameters and data was updated in the Table 2-100
RAM512X18 ta bl e. 2-77
Revision 8 (Feb 2008)
Product Brief v1.1 Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions is new. 1-II
Revision 7 (Jun 2008)
DC and Switching
Characteristics v1.2
The title of Table 2-4 • Overshoot and Undershoot Limits 1 was modified to
remove "as measured on quiet I/Os." Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted.
2-3
Table 2-78 • LVDS Minimum and Maximum DC Input and Output Levels was
updated. 2-50
Revision 6 (Jun 2008) The A3PE600 "FG484" table was missing G22. The pin and its function were
added to the table. 4-17
Revision 5 (Jun 2008)
Packaging v1.4 The naming conventions changed for the following pins in the "FG484" for the
A3PE600:
Pin Number New Function Name
J19 IO45PPB2V1
K20 IO45NPB2V1
M2 IO114NPB6V1
N1 IO114PPB6V1
N4 GFC2/IO115PPB6V1
P3 IO115NPB6V1
4-17
Revision 4 (Apr 2008)
Product Brief v1.0 The product brief portion of the datasheet was divided into two sections and given
a version number, starting at v1.0. The first section of the document includes
features, benefits, ordering information, and temperature and speed grade
offerings. The second section is a device family overview.
N/A
Packaging v1.3 The "FG324" package di a gr am w as repl a ce d. 4-12
Datasheet Information
5-4 Revision 10
Revision 3 (Apr 2008)
Packaging v1.2 The following pins had duplicates and the extra pins were deleted from the
"PQ208" A3PE3000 table:
36, 62, 171
Note: There were no pin function changes in this update.
4-6
The following pins had duplicates and the extra pins were deleted from the
"FG324" table:
E2, E3, E16, E17, P2, P3, T16, U17
Note: There were no pin function changes in this update.
4-12
The "FG256" pin table was updated for the A3PE600 device because the old PAT
were based on the IFX die, and this is the final UMC die version. 4-9
The "FG484" was updated for the A3PE600 device because the old PAT were
based on the IFX die, and this is the final UMC die version. 4-17
The following pins had duplicates and the extra pins were deleted from the
"FG896" table:
AD6, AE5, AE28, AF29, F5, F26, G6, G25
Note: There were no pin function changes in this update.
4-41
Revision 2 (Mar 2008)
Product Brief rev. 1 The FG324 package was added to the "ProASIC3E Product Family" table, the
"I/Os Per Package1" table, and the "Temperature Grade Offerings" table for
A3PE3000.
I, II, IV
Revision 1 (Feb 2008)
DC and Switching
Characteristics v1.1
In Table 2-3 Flash Programming Limits – Retention, Storage and Operating
Temperature 1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
2-2
The "PLL Behavior at Brownout Condition" section is new. 2-4
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency. 2-11
In Table 2-14 • Summary of Maximum and Minimum DC Input Levels, the note
was incorrect. It previously said TJ and it was corrected and changed to TA.2-18
In Table 2-98 • ProASIC3E CCC/PLL S pecification, the SCLK parameter and note
1 are new. 2-70
Tab le 2-103 • JTAG 1532 was populated with the parameter data, w hich was not
in the previous version of the document. 2-82
Revision 1 (cont’d)
Packaging v1.1 The "PQ208" pin table for A3PE3000 was updated. 4-6
The "FG324" pin table for A3PE3000 is new. 4-13
The "FG484" pin table for A3PE3000 is new. 4-27
The "FG896" pin table for A3PE3000 is new. 4-41
Revision 0 (Jan 2008) This document was previously in datasheet v2.1. As a result of moving to the
handbook format, Actel has restarted the version numbers. The new version
number is 51700098-001-0.
N/A
v2.1
(July 2007) Core MP7 information was removed from the "Features and Benefits" secti on. i
The M1 device part numbers have been updated in Table 4 ProASIC3E
Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed
Grade and Temperature Grade Matrix", and "Speed Grade and Temperature
Grade Matrix".
ii, iii,
iv, iv
Revision Changes Page
ProASIC3E Flash Family FPGAs
Revision 10 5-5
v2.1
(continued) The words "ambient temperature" were added to the temperature range in the
"Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix",
and "Speed Grade and Temperature Grade Matrix" sections.
iii, iv, iv
The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i
The caption "Main (chip)" in Figure 2-9 Overview of Automotive ProASIC3
VersaNet Global Network was changed to "Chip (main)." 2-9
The TJ parameter in Table 3-2 Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added. 3-2
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up. 2-15
v2.0
(April 2007) In th e "Temperature Grade Offerings" section, Ambient was deleted. iii
Ambient was deleted from "Temperature Grade Offerings". iii
Ambient was deleted from the "Speed Grade and Temperature Grade Ma trix". iv
The "PLL Macro" section was updated to include power-up information. 2-15
Table 2-13 ProASIC3E CCC/PLL Specification was updated. 2-30
Figure 2-19 Peak-to-Peak Jitter Definition is new. 2-18
The "SRAM and FIFO" section was updated with operation and timing
requirement information. 2-21
The "RESET" section was updated with read and write information. 2-25
The "RESET" section was updated with read and write information. 2-25
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled. 2-28
In the Table 2-15 Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for level s 3 an d 4. 2-34
Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated. 2-64
Notes 3, 4, and 5 were added to Table 2-17 Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated. 2-50
The "VPUMP Programming Supply Voltage" section was updated. 2-50
The "GL Globals" section was updated to include information about direct input
into quadrant clocks. 2-51
VJTAG was deleted from the "TCK Test Clock" section. 2-51
In Ta ble 2-22 Recommended Tie-Off Values fo r the TCK and TRST Pin s, TSK
was changed to TCK in note 2. Note 3 was also updated . 2-51
Ambient was deleted from Table 3-2 Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45". 3-2
Note 3 is new in Tab le 3-4 Overshoot and Undershoot Limits (as measured on
quiet I/Os). 3-2
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88. 3-5
Revision Changes Page
Datasheet Information
5-6 Revision 10
v2.0
(continued) Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated. 3-5
Table 3-5 Package Thermal Resistivities was updated. 3-5
Table 3-10 Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated. 3-8
tWRO and tCCKH were added to Table 3-94 RAM4K9 and Table
3-95 RAM512X18. 3-74 to
3-74
The note in Table 3-24 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated. 3-23
Figure 3-43 Write Access After Write onto Same Address, Figure 3-44 Read
Access After Write onto Same Address, and Figure 3-45 Write Access After
Read onto Same Address are new.
3-71 to 3-
73
Figure 3-53 Timing Diagram was updated. 3-80
Notes were added to the package diagrams identifying if they were to p or bottom
view. N/A
The A3PE1500 "208-Pin PQFP " table is new. 4-4
The A3PE1500 "484-Pin FBGA" table is new. 4-18
The A3PE1500 "A3PE1500 Function" table is new. 4-24
Advance v0.6
(January 2007) In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was
changed for the FG484 and FG676 packages. ii
Advance v0.5
(April 2006) B-LV DS and M-LDVS are new I/O standards added to the datasheet. N/A
The term flow-through was changed to pass-through. N/A
Figure 2-8 Very-Long-Line Resources was updated. 2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated. 2-28
The Delay Increments in the Programmable Del ay Blocks specification in Figure
2-24 ProASIC3E CCC Options. 2-24
The "SRAM and FIFO" section was updated. 2-21
The "RESET" section was updated. 2-25
The "WCLK and RCLK" section was updated. 2-25
The "RESET" section was updated. 2-25
The "RESET" section was updated. 2-27
B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A
The term flow-through was changed to pass-through. N/A
Figure 2-8 Very-Long-Line Resources was updated. 2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated. 2-28
The Delay Increments in the Programmable Del ay Blocks specification in Figure
2-24 ProASIC3E CCC Options. 2-24
The "SRAM and FIFO" section was updated. 2-21
The "RESET" section was updated. 2-25
The "WCLK and RCLK" section was updated. 2-25
Revision Changes Page
ProASIC3E Flash Family FPGAs
Revision 10 5-7
Advance v0.5
(continued) The "RESET" section was updated. 2-25
The "RESET" section was updated. 2-27
The "Introduction" of the "Introduction" section was updated. 2-28
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 VCCI Voltages and Compatible Standards 2-29
Table 2-35 ProASIC3E I/O Features was updated. 2-54
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature. 2-32
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information. 2-35
Level 3 and 4 descriptions were updated in Table 2-43 I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices. 2-64
The notes in Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3E Devices were updated. 2-64
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new. 2-41
A footnote was added to Table 2-37 Maximum I/O Frequency for Single-End ed
and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength
and high slew selected).
2-55
Tab le 2-48 ProASIC3 E I/O Attribute s vs. I/O Standard Applications 2-81
Table 2-55 ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE)
Settings 2-85
The "x" was updated in the "Pin Descriptions" section. 2-50
The "VCC Core Supply Voltage" pin description was updated. 2-50
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected. 2-50
EXTFB was removed from Figure 2-24 ProASIC3E CCC Options. 2-24
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table
2-13 ProASIC3E CCC/PLL Specificatio n. 2-30
EXTFB was removed from Figure 2-27 CCC/PLL Macro. 2-28
The LVPECL specification in Table 2-45 I/O Hot-Swap and 5 V Input Tole rance
Capabilities in ProASIC3E Devices was updated. 2-64
Tab le 2-15 Levels of Hot-Swap Support was updated. 2-34
The "Cold-Sparing Support" section was updated. 2-34
"Electrostatic Discharge (ESD) Protection" section was updated. 2-35
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section. 2-50
The "VJTAG JTAG Supply Voltage" pin description was updated. 2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground. 2-50
Revision Changes Page
Datasheet Information
5-8 Revision 10
Advance v0.5
(continued) The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused. 2-50
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused. 2-51
The "Programming" section was updated to include information concerning
serialization. 2-53
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information. 2-54
The "DC and Switching Characteristics" chapter was updated with new
information. Starting
on page
3-1
Tab le 3-6 was updated. 3-5
In Table 3-1 0, PA C4 was updated. 3-8
Table 3-19 was updated. 3-20
The note in Table 3-24 was updated. 3-23
All Timing Characteristics tables were updated from LVTTL to Register Delays 3-26 to
3-64
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. 3-74 to
3-79
FTCKMAX was updated in Table 3-98. 3-80
Advance v0.4
(October 2005) The "Packaging Tables" table was updated. ii
Advance v0.3 Figure 2-11 was updated. 2-9
The "Clock Resources (VersaNets)" section was updated. 2-9
The "VersaNet Global Networks and Spine Access" secti on was updated. 2-9
The "PLL Macro" section was updated. 2-15
Figure 2-27 was updated. 2-28
Figure 2-20 was updated. 2-19
Tab le 2-5 was updated. 2-25
Tab le 2-6 was updated. 2-25
The "FIFO Flag Usage Considerations" section was updated. 2-27
Table 2-33 was updated. 2-51
Figure 2-24 was updated. 2-31
The "Cold-Sparing Support" section is new. 2-34
Table 2-45 was updated. 2-64
Table 2-48 was updated. 2-81
Pin descriptions in the "JTAG Pins" section were updated. 2-51
The "Pin Descriptions" section wa s updated. 2-50
Tab le 3-7 was updated. 3-6
Revision Changes Page
ProASIC3E Flash Family FPGAs
Revision 10 5-9
Advance v0.3
(continued) The "Methodology" section was updated. 3-9
The A3PE3000 "208-Pin PQF P " pin table was up dated. 4-6
Revision Changes Page
Datasheet Information
5-10 Revision 10
Datasheet Categories
Categories
In order to provide the latest information to des igners, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "ProASIC3E Device Status" table on page II, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categori es are as follows:
Product Brief
The product brief is a summarized versi on of a datasheet (ad vance or producti on) and contains general
product information. This document gives an overvie w of specific de vice and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This info rmation can b e used as estimates, bu t not for production. This label only appl ies to the
DC and Switching Characteristics chapter of the da tasheet and will only be use d when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-supp ort, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliabili ty information.
51700098-10/3.12
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; en terprise and communications; and in dustrial
and alternative energy markets. Products include high-p erformance, high-relia bility an alog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Ali so Viejo CA 92656 USA
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