11640-823 - ON Semiconductor L.L.C.

This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. 2.27.02

FS6146

FS6146FS6146

FS6146

VCXO Clock Generator IC

VCXO Clock Generator ICVCXO Clock Generator IC

VCXO Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

1.0 Features

• On-chip tunable voltage-controlled crystal oscillator

circuitry (VCXO) allows precise system frequency

tuning (pull range typically 300ppm)

• VCXO tuning range: 0-3V

• Uses inexpensive fundamental-mode crystals

• Integrated phase-locked loop (PLL) multiplies VCXO

frequency to the higher system frequencies needed

• 5V core supply voltage (contact factory for 3.3V)

• 3.3V / 5V output supply voltage

• Small circuit board footprint (8-pin 0.150″ SOIC)

• Custom frequency selections available - contact your

local AMI Sales Representative for more information

Figure 1: Pin Configuration

116

XIN

XOUT

VDD

XTUNE

VSS

n/c

CLKA n/c

n/c

CLKB

VSS

VDDO

n/c

FS6146

16-pin (0.150″) SOIC

2.0 Description

The FS6146 is a monolithic CMOS clock generator IC

designed to m inim ize cost a nd com ponen t count in digi tal

video/audio systems.

At the core of the FS6146 is circuitry that implements a

voltage-controlled crystal oscillator when an external

resonator is attached. The VCXO allows device frequen-

cies to b e prec isel y adjust ed for us e in s ystem s that hav e

frequenc y m atching r equir em ents, s uch as digit al s atel lite

receivers.

A high-res olution phase-loc ked lo op generates the outpu t

clock frequencies (CLKA and CLKB). These frequencies

are phas e-locked an d frequenc y-lock ed to the VCXO fre-

quency.

Table 1: Crystal / Output Frequencies

DEVICE fXIN (MHz) CLKA (MHz) CLKB (MHz)

FS6146-01 10.000 40.000 80.000

NOTE: Contact AMI for custom PLL frequencies

Figure 2: Block Diagram

VCXO

FS6146

PLL

XOUT

XIN CLKA

XTUNE

Divider

Array

CLKB

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Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN TYPE NAME DESCRIPTION

1 AI XIN VCXO Crystal Feedback

2 AO XOUT / FREF VCXO Crystal Drive / External Ref erence Clock Input

3 P VDD Core Power Supply

4 AI XTUNE VCXO Tune Input

5 P VSS Ground

6 - N/C No Connection

7DI

UOE Output Enable

8DOCLKAClock Output “A”

9 - N/C No Connection

10 - N/C No Connection

11 DO CLKB Clock Output “B”

12 P VSS Ground

13 P VDDO Output Power Supply (must be les s than or equal to VDD)

14 - N/C No Connection

15 - N/C No Connection

16 - N/C No Connection

3.0 Functional Bl ock Descripti on

3.1 Phase-Locked Loop (PLL)

The on-chip PLL is a standard frequency- and phase-

lock ed loop archi tec tur e. The PLL multiplies the refer enc e

oscillator to the desired frequency by a ratio of integers.

The frequency multiplication is exact with a zero synthe-

sis error.

3.2 Voltage-Controlled Crystal

Oscillator (VCXO)

The VCXO provides a tunable, low-jitter frequency refer-

ence for the rest of the FS6146 system components.

Loading capacitance for the crystal is internal to the

FS6146. No external components (other than the crystal

resonator itself) are required for operation of the VCXO.

Continuous fine-tuning of the VCXO frequency is accom-

plished by varying the voltage on the XTUNE pin.

The oscillator operates the crystal resonator in the paral-

lel-reso nant mode. Cr ystal warpin g, or the “pul ling” of the

crystal oscillation frequency, is accomplished by altering

the eff ective load ca pacitance presented to the crystal b y

the oscillator circuit. T he actual amount that changin g the

load capacitance alters the oscillator frequency will be

dependent o n the charac teristics of the cr ystal as well as

the oscillator circuit itself.

Specifically, the m otional capacitance of the cr ystal (usu-

ally referr ed to by cr ystal m anufactur ers as C1), the st atic

capacitance of the crystal (C0), and the load capacitance

(CL) of the oscillator determine the “warping” or “pulling”

capability of the crystal in the oscillator circuit.

A simple formula to obtain the warping capability of a

crystal oscillator is:

()

()()

CCCC CCC

ppmf LL

1020

121

210

)( +×+× ×−×

=∆

where CL1 and CL2 are the two extremes of the applied

load capacitance.

EXAMPLE: A crystal with the following parameters is

used. With C1 = 0.02 pF, C0 = 5pF , CL1 = 10pF, a nd CL2 =

22.66pF, the tuning range is

()

()()

ppm

f305

105662252 106

106622020 =

+×+× ×−×

=∆ .

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4.0 Electrical Specifications

Table 3: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER SYMBOL MIN. MAX. UNITS

Supply Voltage (VSS = ground) VDD VSS-0.5 7 V

Input Voltage, dc VIVSS-0.5 VDD+0.5 V

Output Voltage, dc VOVSS-0.5 VDD+0.5 V

Input Clamp Current, dc (V I < 0 or VI > VDD)I

IK -50 50 mA

Output Clamp Current, dc (VI < 0 or VI > VDD)I

OK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ125 °C

Lead Temperature (soldering, 10s) 260 °C

Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage res ulting in a loss of functi onality or performance may occur if this devi ce is subjected to a high-energy elec-

trostatic discharge.

Table 4: Operating Conditions

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Supply Voltage VDD 5V ± 5% 4.75 5 5.25 V

Ambient Operating Temperature Range TA070°C

Crystal Resonator Frequency fXTAL Fundamental Mode 5 13.5 18 MHz

Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF

Crystal Loadi ng Capaci tance CL(xtal) AT cut 14 pF

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Table 5: DC Electrical Specifications

Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data

and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Supply Current, Dynamic, with Loaded

Outputs IDD fXTAL = 13.5MHz; CL = 10pF 20 mA

Voltage Controlled Crystal Oscillator - VDD=5.0V

Crystal Loadi ng Capaci tance CL(xtal) As seen by a crystal connected to XIN and

XOUT (@ VXTUNE = 1.65V) 14 pF

Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF

VCXO Tuning Range fXTAL = 13.5MHz; CL(xtal) = 14pF; C1(xtal) = 25fF 300 ppm

VCXO Tuning Characterist ic Note: positive ∆F for positive ∆V100 ppm/V

Crystal Dri ve Level RXTAL=20Ω; CL(xtal) = 14pF 200 uW

Clock Outputs (CLK A, CLKB) - VDDO=3.3V

High-Level Output Sourc e Current * IOH VO = 2.0V -40 mA

Low-Level Output Sink Current * IOL VO = 0.4V 17 mA

zOH VO = 0.1VDD; output drivi ng hi gh 25

Output Impedance * zOL VO = 0.1VDD; output dri ving l ow 25 Ω

Short Circuit S ource Current * IOSH VO = 0V; shorted for 30s, max. -55 mA

Short Circuit S i nk Current * IOSL VO = 5V; shorted for 30s, max. 55 mA

Table 6: AC Timing Specifications

Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data

and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK

(MHz) MIN. TYP. MAX. UNITS

Overall

VCXO Stabilization Time * tVCXOSTB From power valid 10 ms

PLL Stabilization Time * tPLLSTB From V CXO stable 500 us

Output Frequency Synthesis Error (unless otherwise noted in Frequency Table) 0 ppm

Clock Output (CLK)

Duty Cycle * Ratio of high pulse width (as measured from rising edge

to next falling edge at VDD/2) to one clock period 45 55 %

Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at

VDD/2, CL = 10pF 300 ps

Jitter, Long Term (σy(τ)) * tj(LT) From 0-500µs at VDD/2, CL = 10pF

compared to ideal clock source 150 ps

Rise Time * trVDD = 5V; VO = 0.5V to 4.5V; CL = 10pF ns

Fall Time * tfVDD = 5V; VO = 4.5V to 0.5V; CL = 10pF ns

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VCXO Clock Generator IC

VCXO Clock Generator ICVCXO Clock Generator IC

VCXO Clock Generator IC

ISO9001

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5.0 Package Information

Table 7: 16-pin SOIC (0.150") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

MIN. MAX. MIN. MAX.

A 0.061 0.068 1.55 1.73

A1 0.004 0.0098 0.102 0.249

A2 0.055 0.061 1.40 1.55

B 0.013 0.019 0.33 0.49

C 0.0075 0.0098 0.191 0.249

D 0.386 0.393 9.80 9.98

E 0.150 0.157 3.81 3.99

e 0.050 BSC 1.27 BSC

H 0.230 0.244 5.84 6.20

h 0.010 0.016 0.25 0.41

L 0.016 0.035 0.41 0.89

Θ0°8°0°8°

SEATING PLANE

1ALL RADII:

0.005" TO 0.01"

BASE PLANE

7° typ.h x 45°

AMERICAN MICROSYSTEMS, INC.

Table 8: 16-pin SOIC (0.150") Package Characteristics

PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS

Thermal Impedance, Junction to Free-Air

16-pin 0.150” SOIC ΘJA Air flow = 0 m/s 109 °C/W

Corner lead 4.0

Lead Inductanc e, Self L11 Center lead 3.0 nH

Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH

Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF

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6.0 Ordering Information

Table 9: Device Ordering Codes

ORDERING CODE DEVICE NUM BER PACK AGE TYPE OPERATING

TEM PERATURE R ANGE SHIPPING

CONFIGURATION

11640-823 FS6146-01 8-pin (0.150”) S OIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tape and Reel

11640-833 FS6146-01 8-pin (0.150”) S OIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tubes

7.0 Revision Information

DATE PAGE DESCRIPTION

4/26/00 2 Fixed formatting errors

7/31/00 3 Changed “5V ± 10%” to “5V±5%”

Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI

makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom

of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-

serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are

intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-

ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-

mended without additional processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Address: http://www.amis.com E-mail: tgp@amis.com