Final datasheet Please read the Important Notice and Warnings at the end of this document Rev. 2.5
www.infineon.com 2020-03-17
EiceDRIVER™ 2EDi product family
Fast, robust, dual-channel, functional and reinforced isolated
MOSFET gate-driver with accurate and stable timing
Description
The EiceDRIVER™ 2EDi is a family of fast dual-channel isolated MOSFET gate-driver ICs providing functional
(2EDFx) or reinforced (2EDSx) input-to-output isolation by means of coreless transformer (CT) technology. Due
to high driving current, excellent common-mode rejection and fast signal propagation, 2EDi is particularly well
suited for driving medium- to high-voltage MOSFETs (CoolMOS™, OptiMOS™, CoolSIC™) in fast-switching power
systems.
Features
• 4 A / 8 A or 1 A / 2 A source / sink output current
• Up to 10 MHz PWM switching frequency
• PWM signal propagation delay typ. 37 ns with
– 3 ns channel-to-channel mismatch
– +7/-6 ns propagation delay variance
• Resistor-programmable Dead Time Control (DTC) ranging from 15 ns to 250 ns
• Common Mode Transient Immunity CMTI >150 V/ns
• Fast safety turn-off in case of input side Undervoltage Lockout (UVLO)
• Output supply voltage from 4.5 V to 20V with 4V or 8V UVLO threshold
• Wide temperature operating range TJ = -40°C to +150°C
• RoHS compliant wide /narrow-body (WB/NB) DSO16 and 5 mm x 5 mm LGA packages
• Fully qualified according to JEDEC for Industrial Applications
Isolation and safety certificates
•2EDSx with reinforced isolation:
– DIN V VDE V 0884-10 (2006-12) compliant with VIOTM = 8 kVpk and VIOSM = 6.25 kVpk (tested at 10kVpk)
– certified according to UL1577 (Ed. 5) opto-coupler component isolation standard with VISO = 5700 VRMS
– certified according to DIN EN 62368-1 and DIN EN 60950-1 and corresponding CQC certificates
– certified according to EN 61010-1 (reinforced isolation, 300 Vrms mains voltage, overvoltage category III)
•2EDFx with functional isolation: Production test with 1.5 kVDC for 10 ms
DISABLE
GNDI
VDDI
(3.3V)
VDDB
OUTB
GNDB
VDDA
OUTA
GNDA
INA
Rg1
Rg2
M
1
M
2
D
boot
VBus
PGND
Controller
GND
PWM1
3
8
GPIOx 8
VDD 8
CVDDI
DTC
RDTC
SLDON
INB
UVLO
Control
Logic
UVLO
RX
Input-to-Output
Isolation
UVLO
SLDO
Channel-to-Channel
Isolation
Dead Time
Control
PWM2 8
RVDDI
VDD > 3.5V
Aux Power
(12V)
Logic
Logic
CVDDA
CVDDB
Vsw
RX
TX
TX
Final datasheet 2 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Potential Applications
• Server, telecom and industrial SMPS
• Synchronous rectification, brick converters, UPS and battery storage
• EV charging industry automation, motor drives and power tools
Final datasheet 3 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 EiceDRIVER™ 2EDi product family device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Input-to-output isolation testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Channel-to-channel isolation testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Application overview and system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin configurations by device type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Pin configuration for dual-channel input mode with (with DISABLE, SLDON) . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin configuration for dual-channel input mode (with DISABLE, SLDOP, DTC) . . . . . . . . . . . . . . . . . . . . . . 8
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Input-to-output isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 Typical applications by isolation type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1 Input-side power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2 Output-side power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.1 Input-side UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.2 Output-side UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Data transmission input-side to output-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Functional and reinforced isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1 Functional isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1.1 Functional isolation of devices in PG-TFLGA-13-1 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1.2 Functional isolation of devices in NB PG-DSO-16-11 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5.2 Reinforced isolation of devices in WB PG-DSO-16-30 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5.3 Safety-limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 Package PG-DSO-16-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 Package PG-DSO-16-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4 Package PG-TFLGA-13-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents
Final datasheet 4 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Description
1 Description
The gate drivers of the EiceDRIVER™ 2EDi product family are designed for fast-switching, medium to high power
systems with MOSFET switches. They are optimized for high timing accuracy over temperature and production
spread. The reliable accurate timing simplifies system design and provides better power conversion efficiency.
The 2EDSx, 2EDFx dual-channel reinforced (safe) and functional isolated product variants are available with
different drive strengths: 4 A/8 A for low-ohmic power MOSFETs, 1 A/2 A for higher Ron MOSFETs or slower
switching transients (EMI). The 1 A/2 A reinforced isolation driver can also be used as a PWM Data Coupler in
combination with a non-isolated boost gate driver such as 1EDNx 4 A/8 A placed in closest proximity to the
Superjunction power switches.
Two independent and galvanically isolated gate driver channels ensure that all 2EDi versions can be used in any
possible configuration of low- and high-side switches.
Improved system robustness is supported by min. 150 V/ns Common Mode Transient Immunity (CMTI), PWM
inputs with 18 ns noise filter, UVLO on output side including a safety self-lock-down of driver outputs in case of
input UVLO (VDDI < 3 V), PWM outputs with up to 5 A peak reverse current capability and an intrinsically robust
gate driver design.
1.1 EiceDRIVER™ 2EDi product family device overview
The 2EDi product table is provided as a first quick device selection guide; more detailed specifications are
provided in the product features, package dimension and testing chapters of this datasheet.
Find current information on configurations and application notes under www.infineon.com/2EDi
Table 1 EiceDRIVER™ 2EDi product family device overview
Part
number1)
1) for device ordering information and device marking see Chapter 7.1, Table 31
Package Source/
sink
current
UVLO
Input-to-output isolation
DTC
Isolation
class Rating Surge testing
Safety
certification2)
2) CSA Component Acceptance Notice 5A IEC60950 planned and CQC per GB4943.1-2011 pending. For 2EDS9265H, all
certifications are planned.
2EDF7275F
NB-DSO16
10mm x 6mm
4A/8A 4V
Functional VIO = 1.5 kVDC n.a n.a
no
2EDF9275F 13 V no
2EDF7175F 1 A/ 2 A 4 V no
2EDF7275K LGA13
5mm x 5mm
4A/8A 4 V no
2EDF7235K yes
2EDS8265H WB-DSO16
10.3mm x
10.3mm
4A/8A 8 V
Reinforced
VIOTM = 8 kVpk
(VDE0884-10 3))
VISO = 5.7 kVrms
(UL1577)
VIOSM = 10 kVpk
(IEC60065)
VDE0884-10 3)
UL1577
EN 60950-1,
EN 62368-1,
EN 61010-1
3) tested according to VDE0884-10 specifications with certification no longer available due to standard expiration
no
2EDS9265H 13 V no
2EDS8165H 1 A/2 A 8 V no
Final datasheet 5 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Description
1.2 Input-to-output isolation testing
• 2EDSx Reinforced isolation (2EDSx in WB PG-DSO-16-30 package), for details see Table 26 to Table 29.
–8kV
pk transient isolation voltage applied according to DIN V VDE V 0884-10 (2006-12)
–10kVpk surge isolation tested with 25 positive and 25 negative pulses according to VDE-0884-10
• Functional isolation (2EDFx in NB PG-DSO-16-11 and PG-TFLGA-13-1 packages), for details see Table 21 to
Table 23
– Production test with 1.5 kVDC for 10 ms
1.3 Channel-to-channel isolation testing
• The functional isolation between the two channels are verified by the following tests
– sample test with 1.5 kVDC for 10 ms (NB PG-DSO-16-11, WB PG-DSO-16-30)
– sample test with 0.65 kVDC for 10 ms (PG-TFLGA-13-1)
1.4 Application overview and system block diagram
2EDi gate drivers are perfectly suited to substitute bulky pulse transformers and drive power MOSFETs in half-
bridge configuration as depicted in Figure 1.
The input side is usually powered by the same power supply as the PWM controllers (VDDI = 3.3 V or VDDI > 3.5 V
if SLDO is activated). The output-side gate driver voltages VDDA, VDDB are generated by separate isolated
auxiliary supplies. In some topologies like LLC, the high side driver supply VDDA can be generated via a
bootstrapping circuitry.
For further application implementation guidance please refer to dedicated application notes.
Figure 1 Typical application with 5 V controller and bootstrapped high-side VDDA
DISABLE
GNDI
VDDI
(3.3V)
VDDB
OUTB
GNDB
VDDA
OUTA
GNDA
INA
R
g1
R
g2
M1
M
2
Dboot
V
Bus
PGND
Controller
GND
PWM1
3
8
GPIOx
8
VDD
8
C
VDDI
DTC
R
DTC
SLDON
INB
UVLO
Control
Logic
UVLO
RX
Input-to-Output
Isolation
UVLO
SLDO
Channel-to-Channel
Isolation
Dead Time
Control
PWM2
8
R
VDDI
VDD > 3.5V
Aux Power
(12V)
Logic
Logic
C
VDDA
C
VDDB
V
sw
RX
TX
TX
Final datasheet 6 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
INA
DSO-16
1
narrow-body
2EDF7275F
2EDF9275F
2EDF7175F
wide-body
2EDS8265H
2EDS9265H
2EDS8165H
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INB
VDDI
GNDI
DISABLE
N.C.
N.C.
SLDON
VDDA
OUTA
GNDA
N.C.
N.C.
VDDB
OUTB
GNDB
13
2
1
GNDI
12
LGA-13 (5 x 5 mm)
11
4
3
10
6
5
9
87
2EDF7275K
INA
INB
VDDI
DISABLE
N.C.
SLDON
VDDA
OUTA
GNDA
VDDB
OUTB
GNDB
2 Pin configurations by device type
Functional behavior and electrical characteristics are independent of package configuration
2.1 Pin configuration for dual-channel input mode with (with DISABLE, SLDON)
The pin configurations for the different package variants 2EDFxx75F, 2EDF7x75K and 2EDSxx65H are outlined in
Figure 2.
Figure 2 Pin configuration DSO-16 and LGA-13 packages (2EDF7x75F, 2EDF7x75K and 2EDF8x65H)
(Top view, figure is not to scale)
Final datasheet 7 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
For package drawing details see Chapter 7 Package outline dimensions.
Table 2 Pin description for dual-channel input mode (with DISABLE, SLDON)
Pin#
DSO
Pin#
LGA
Symbol Description
1 2 INA Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to
GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
2 3 INB Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to
GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
3 7 VDDI Supply voltage (input side) 3.3 V (Internal SLDO available)
It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1)
4 1 GNDI Ground input side (all signals on input side are referenced to this pin)
(see Chapter 3.3.1)
5 5 DISABLE Digital CMOS / TTL logic input for both channels A and B; logic input high disables both
output channels
Internal pull-down resistor (see Chapter 3.4)
6 6 N.C. Not connected; keep pin floating
7 - N.C. Not connected; keep pin floating
8 4 SLDON Default 3.3 V supply selected, if N.C. or connected to VDDI
If SLDON pin is connected to GNDI, SLDO is activated and a supply voltage higher than
3.5 V can be used (see Chapter 3.3.1)
Internal pull-up resistor to VDDI; hard-wired PCB connection recommended
9 8 GNDB Ground for output channel B
10 9 OUTB Output gate driver for channel B
11 10 VDDB Supply voltage for output channel B
It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2)
12 N.P. N.C. Not present; not connected; for channel-to-channel isolation
13 - N.C. Not connected; for channel-to-channel isolation
14 11 GNDA Ground for output channel A
15 12 OUTA Output gate driver for channel A
16 13 VDDA Supply voltage for output channel A
It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2)
Final datasheet 8 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
2.2 Pin configuration for dual-channel input mode (with DISABLE, SLDOP, DTC)
The pin configuration for the LGA-version with Dead Time Control (2EDF7235K) is outlined in Figure 3
Figure 3 Pin configuration dual-channel input mode (with DISABLE, SLDOP, DTC) for 2EDF7235K
(Top view, Figure is not to scale)
13
2
1
12
LGA-13 (5 x 5 mm)
11
4
3
10
6
5
9
87
2EDF7235K
GNDI
INA
INB
VDDI
DISABLE
DTC
SLDOP
VDDA
OUTA
GNDA
VDDB
OUTB
GNDB
Final datasheet 9 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Pin configurations by device type
For package drawing details see Chapter 7 Package outline dimensions.
Table 3 Pin description for dual-channel input mode (with DISABLE, SLDOP, DTC)
Pin#
LGA
Symbol Description
2 INA Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
3 INB Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to GNDI
If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)
7 VDDI Supply voltage (input side) 3.3 V (Internal SLDO available)
It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1)
1 GNDI Ground input side (all signals on input side are referenced to this pin)
(see Chapter 3.3.1)
5 DISABLE Digital CMOS / TTL logic input for both channels A and B
Logic input high disables both output channels
Internal pull-down resistor (see Chapter 3.4)
6DTC Dead time control
Programmable from 15 ns to 350 ns via resistor to GNDI see Chapter 3.8 Dead Time Control
Internal pull-up resistor; no connection or connection to VDDI disables DTC functionality
4 SLDOP Default mode: supply voltage > 3.5V (with external shunt resistor), if pin N.C. or connected to
VDDI
If SLDOP pin is connected to GNDI SLDO Operation is deactivated, for use with 3.3 V supply on
VDDI(see Chapter 3.3.1)
Internal pull-up resistor to VDDI; hard-wired PCB connection recommended
8 GNDB Ground for output channel B
9 OUTB Output gate driver for channel B
10 VDDB Supply voltage for output channel B
It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2)
- N.P. Not present; for channel-to-channel isolation creepage requirements
11 GNDA Ground for output channel A
12 OUTA Output gate driver for channel A
13 VDDA Supply voltage for output channel A
It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2)
Final datasheet 10 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3 Functional description
3.1 Block diagram
A simplified functional block diagram for the the EiceDRIVER™ 2EDi gate-driver family is given in Figure 4.
Figure 4 EiceDRIVER™ 2EDi product family block diagram
3.2 Input-to-output isolation
All EiceDRIVER™ 2EDi dual-channel isolated products are tested in accordance with their respective isolation
class.
•2EDFx for functional isolation, typically used as primary-side controlled galvanically isolated driver.
Device part numbers: 2EDFxxxxK (2EDF7275K, 2EDF7235K) and 2EDFxxxxF (2EDF7275F, 2EDF9275F,
2EDF7175F)
•2EDSx for reinforced safe isolation, typically used as secondary-side controlled isolated gate driver.
Device part numbers: 2EDSxxxxH (2EDS8165H, 2EDS9265H, 2EDS8265H)
In combination with the different package dimensions and material characteristics, e.g. WB DSO-16 wide-body
(PG-DSO-16-30), NB DSO-16 narrow-body (PG-DSO-16-11) or LGA - 13 at 5mm x 5mm (PG-TFLGA-13-1) the
maximum input-to-output and channel-to-channel creepage and clearance distances and the possible working
voltages of the IC as a semiconductor component are defined (see Table 18 to Table 29)
Note: The achievable system isolation depends on PCB design, materials, manufacturing- and working
environment. It is the customer’s obligation to verify that the outlined semiconductor component
isolation of the 2EDSx, 2EDFx device fits to application, manufacturing, working environment and end
system saftey requirement standards.
INB
GNDI
VDDI
VDDB
OUTB
GNDB
Tx
UVLO
Input-to-Output
Isolation
VDDA
OUTA
GNDA
UVLO
Tx
INA
SLDON
SLDOP SLDO
NC
DTC
Channel-to-Channel
Isolation
Dead Time
Control
DISABLE
ENABLE
UVLO
Control
Logic
Rx
Rx
Logic
Logic
Final datasheet 11 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3.2.1 Typical applications by isolation type
Isolated gate drivers are typically deployed in the following applications.
3.3 Supply voltages
Three different power domains with independent internal power management are utilized to supply the input
chip and the two output drivers. An undervoltage lockout functionality (UVLO) in each domain enables a defined
startup and ensures a robust operation under all conditions.
3.3.1 Input-side power supply
The input side is powered via VDDI with nominal 3.3 V. For using the device with a supply voltage > 3.5 V the on-
chip switched low-dropout regulator (SLDO) must be activated and an external shunt resistor RVDDI has to be
connected to VDDI.
It is recommended to use a ceramic bypass capacitor (10 nF - 22 nF) between VDDI and GNDI.
The SLDO is activated, if the pin SLDON is connected to GNDI. In devices with the inverted pin SLDOP (e.g.
2EDF7235K) the SLDO is active by default and will be deactivated if connected to GNDI. A hard-wired connection
is recommended.
The SLDO regulates the current through an external resistor RVDDI connected between the external supply voltage
VDD and pin VDDI as depicted in Figure 1 to generate the required voltage drop. For proper operation it has to be
ensured that the current through RVDDI always exceeds the maximum supply current IVDD of the input chip (see
Figure 8).
Thus, RVDDI has to fulfill:
RVDDI < (VDD -3.3)/IVDD, max
A typical choice for VDD = 12 V is RVDDI = 3 kΩ, resulting in sufficient margin between resistor current and VDDI
operating current. Dynamic current peaks are eliminated by a blocking cap (10 to 22 nF) between VDDI and GNDI.
The total power consumption of 2EDi is dominated by the output side and depends on switching frequency, gate
resistor and gate charge, while for typical switching frequencies the input supply current stays relatively constant
(see Figure 7 to Figure 8)
3.3.2 Output-side power supply
Each gate driver channel has to be powered separately. It is recommended to use a ceramic bypass capacitor
(minimum value 20 x Ciss of MOSFET) from VDDA to GNDA and from VDDB to GNDB in close proximity to the
device.
The operating supply voltage can range from 4.5 V to 20 V for each gate drive channel.
The minimum gate driver turn-on voltage is set by the device Undervoltage Lockout (UVLO) to protect the power
MOSFETs from operating in the saturation region.
Devices with 4 V, 8 V and 13 V UVLO thresholds for the output supply are currently available (see Chapter 1.1.)
Table 4
Isolation type Potential applications
Functional • High-power hard-switching high-voltage PFC, Vienna Rectifier, Totem Pole PFC or
Synchronous Rectification
• Driving switches with Kelvin source connection (4-pin package)
• Secondary-side control in low voltage isolated DC/DC topologies and brick converters
Reinforced • Secondary-side control of high voltage SJ-MOSFETs in LLC or PS-ZVS
• Primary-side controlled synchronous rectification
• 1 A / 2 A PWM data- / signal-coupler for local boost gate drivers
Final datasheet 12 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3.4 Input configurations
The inputs INA and INB control two independent PWM channels. The input signal is transferred non-inverted to
the corresponding gate driver outputs OUTA and OUTB. All inputs are compatible with LV-TTL threshold levels
and provide a hysteresis of typ. 0.8 V. The hysteresis is independent of the supply voltage VDDI.
The PWM inputs are internally pulled down to a logic low voltage level (GNDI). In case the PWM-controller signals
have an undefined state during the power-up sequence, the gate driver outputs are forced to the "off"-state
(low).
If the DISABLE input is “high”, this unconditionally drives both channel outputs to “low” regardless of the state of
INA or INB.
3.5 Driver outputs
The two rail-to-rail output stages, realized with complementary PMOS, NMOS transistors, are able to provide the
necessary sourcing and sinking current and shoot-through protection and active current limitation have been
implemented with a very low on-resistance (see Table 15). The use of a p-channel sourcing transistor PMOS is
crucial for achieving true rail-to-rail behavior without any source follower voltage drop.
Gate Drive Outputs OUTA, OUTB are held actively low in case of floating inputs or during startup or power down
as long as the UVLO thresholds are not exceeded.
Table 5 Logic table
Inputs Gate Drive Output
DISABLE INA INB UVLO
input side1)
1) “inactive” means that VDD is above UVLO threshold voltage (normal operation)
“active” means that UVLO disables the gate driver output stages
UVLO
output side1)
OUTA OUTB
xxxactive x L L
xxxx ch A/B active L L
L x L inactive ch A activ, ch B inactive L L
L x H inactive ch A active, ch B inactive L H
L L x inactive ch A inactive, ch B active L L
L H x inactive ch A inactive, ch B active H L
Hxxinactive ch A/B inactive L L
LLLinactive ch A/B inactive L L
LLHinactive ch A/B inactive L H
LHHinactive ch A/B inactive H H
Final datasheet 13 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Functional description
3.6 Undervoltage Lockout
3.6.1 Input-side UVLO
During startup (rise of the input-side supply), as long as VDDI is below UVLO, no data is transferred to the output
side. All gate driver outputs are held low (Safety Lock-down at startup).
When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output side is
ready (not in UVLO condition), the output reacts according to the logic input. At any time, if the VDDI voltage
drops below the UVLO threshold, an immediate “switch-to-low” command is sent to all output channels. The
gate driver outputs are held low (Safety Lock-down is active at missing VDDI supply).
3.6.2 Output-side UVLO
The Undervoltage Lockout function (UVLO) ensures that the output can be switched to its high level only if the
gate driver supply voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the power switch
transistors always stay within their Safe Operating Area (SOA). Otherwise a too low driving voltage could cause
the power MOSFET to enter its saturation (ohmic) region with potentially destructive power dissipation.
The UVLO of each channel VDDA/VDDB is controlled independently. There is no feedback to the input side.
3.7 Data transmission input-side to output-side
Coreless Transformer (CT) based communication modules situated on the input die are used for signal transfer
between input and output devices. A proven high-resolution pulse repetition scheme in the transmitter
combined with a watchdog time-out at the receiver side enables recovery from communication fails and ensures
safe system shutdown in failure cases.
3.8 Dead Time Control
Dead Time Control function (DTC) increases the propagation delay of the rising output voltage by a time tDT. This
feature is used in half-bridge applications to prevent the switches from a shoot-through current due to
overlapping or jitter on the PWM signals.
If the DTC feature is available, it can be enabled by connecting a resistor from DTC to GND. If this pin is not
connected or set to VDDI, DTC is disabled.
Recommended DTC resistor (RDTC) values are between 4.7 kΩ and 150 kΩ .
RDTC is related to tDT by the formula: RDTC [kΩ] = (tDT[ns] - 3) / 1.8
The resistor values and dead time delays are shown in Table 17 and Figure 15.
Final datasheet 14 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4 Device characteristics
The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4.1 Absolute maximum ratings
Table 6 Absolute maximum ratings
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input supply voltage VDDI -0.3 – 4.0 V SLDO inactive (N.C. or
connected to VDDI)
Output supply voltage VDDO -0.3 – 22 V –
Voltage at pins PWM and
DISABLE
VIN -0.3 – 17 V –
-5 – – V < 50 ns for transient 1)
1) parameter verified by design, not tested in production
Voltage at pins DTC and
TEST/SLDO
VDTC /
VTEST/SLDO
-0.3 – VDDI + 0.3 V –
Voltage at pins OUTA, OUTB VOUTA/B -0.3 – VDDO + 0.3 V –
-2 – VDDO+ 1.5 V < 200 ns 1)
Reverse current peak at pins
OUTA, OUTB
ISRC_rev -5 – – Apk < 500 ns 1)
ISNK_rev –– 5Apk
Non-destructive Common
Mode Transient Immunity
CMTI 400 – – V/ns input to each output
channel
Junction temperature TJ-40 – 150 °C –
Storage temperature TSTG -65 – 150 °C –
Soldering temperature TSOL – – 260 °C reflow / wave soldering 2)
2) according to JESD22A111
ESD capability VESD_CDM – – 0.5 kV Charged Device Model
(CDM) 3)
3) according to JESD22-002
ESD capability VESD_HBM – – 2 kV Human Body Model
(HBM) 4)
4) according to JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor)
Final datasheet 15 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.2 Thermal characteristics
Table 7 Thermal characteristics at Tamb= 25°C
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
PG-TFLGA-13-1
Thermal resistance junction-
ambient 1)
1) obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in
JESD51-2a.
RthJA25 – 112 – K/W –
Thermal resistance junction-case
(top) 2)
2) obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close
description can be found in the ANSI SEMI standard G30-88.
RthJC25 –44–K/W–
Thermal resistance junction-board 3)
3) obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in
JESD51-8.
RthJB25 –66–K/W–
Characterization parameter
junction-top 4)
4) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining
Rth, using a procedure described in JESD51-2a (sections 6 and 7).
ΨthJT25 –7.7–K/W–
Characterization parameter
junction-board 4)
ΨthJB25 –5.6–K/W–
PG-DSO-16-11
Thermal resistance junction-
ambient 1)
RthJA25 –51–K/W–
Thermal resistance junction-case
(top) 2)
RthJC25 –25–K/W–
Thermal resistance junction-board 3) RthJB25 –36–K/W–
Characterization parameter
junction-top 4)
ΨthJT25 –4.4–K/W–
Characterization parameter
junction-board 4)
ΨthJB25 –5.4–K/W–
PG-DSO-16-30
Thermal resistance junction-
ambient 1)
RthJA25 –59–K/W–
Thermal resistance junction-case
(top) 2)
RthJC25 –32–K/W–
Thermal resistance junction-board 3) RthJB25 –33–K/W–
Characterization parameter
junction-top 4)
ΨthJT25 –8.9–K/W–
Characterization parameter
junction-board 4)
ΨthJB25 –7.7–K/W–
Final datasheet 16 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.3 Operating range
4.4 Electrical characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, respectively. They are
valid within the full operating range. The supply voltage is VDDA, VDDB=12V and VDDI= 3.3 V. Typical values are given
at TJ = 25°C.
Table 8 Operating range
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input supply voltage VDDI 3.0 – 3.5 V Min. defined by UVLO
Output supply voltage VDDA /
VDDB
4.5 – 20 V Min. defined by UVLO
Logic input voltage at pins INA,
INB, DISABLE
VIN 0–15V–
Voltage at pins DTC and SLDO VDTC /
VTEST/SLDO
0–3.5V–
Junction temperature TJ-40 – 150 °C 1)
1) continuous operation above 125°C may reduce lifetime.
Ambient temperature Tamb -40 – 125 °C –
Table 9 Power supply (see Figure 7, Figure 8 and Figure 9)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
IVDDI quiescent current IVDDIqu1 – 1.4 – mA no switching
IVDDA , IVDDB quiescent current IVDDAqu2 /
IVDDBqu2
– 0.6 – mA Outx = low, no switching
(4 V, 8 V UVLO options)
–0.7–mAOutx = low, no
switching, VDDA/B= 15 V >
UVLO_ CMon (13 V UVLO
options)
Table 10 Undervoltage Lockout VDDI (See Figure 11)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO)
turn-on threshold VDDI
UVLOon 2.75 2.85 2.95 V –
Undervoltage Lockout (UVLO)
turn-off threshold VVDDI
UVLOoff –2.70–V–
UVLO threshold hysteresis VDDI UVLOhys 0.1 0.15 0.2 V –
Final datasheet 17 Rev. 2.5
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2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 11 Undervoltage Lockout VDDA, VDDB 13 V-versions for SiC MOSFETs (see Figure 13)
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO) turn-on
threshold VDDA, VDDB
UVLO_
CMon
13.0 13.7 14.2 V –
Undervoltage Lockout (UVLO) turn-off
threshold VDDA , VDDB
UVLO_
CMoff
– 12.9 – V –
UVLO threshold hysteresis VDDA, VDDB UVLO_
CMhys
0.4 0.8 1.2 V –
Table 12 Undervoltage Lockout VDDA, VDDB 8 V-versions for standard MOSFETs (see Figure 12)
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO) turn-on
threshold VDDA, VDDB
UVLO_
CMon
7.6 8.0 8.4 V –
Undervoltage Lockout (UVLO) turn-off
threshold VDDA , VDDB
UVLO_
CMoff
–7.0–V–
UVLO threshold hysteresis VDDA,
VDDB
UVLO_
CMhys
0.711.3V–
Table 13 Undervoltage Lockout VDDA, VDDB 4 V-versions for logic-level MOSFETs (see Figure 12)
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO) turn on
threshold VDDA , VDDB
UVLO_
CMon
4.0 4.2 4.4 V –
Undervoltage Lockout (UVLO) turn off
threshold VDDA, VDDB
UVLO_
CMoff
–3.9–V–
UVLO threshold hysteresis
VDDA , VDDB
UVLO_
CMhys
0.2 0.3 0.4 V –
Table 14 Logic inputs INA, INB and DISABLE (see Figure 11)
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
Input voltage threshold for transition
LH
VINH 1.7 2.0 2.3 V –
Input voltage threshold for transition
HL
VINL –1.2–V–
Input voltage threshold hysteresis VIN_hys 0.4 0.8 1.2 V –
Input pull-down resistor RIN – 150 – kΩ –
Final datasheet 18 Rev. 2.5
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2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 15 Static output characteristics 4 A/8 A devices (see Figure 10)
Parameter Symbol Values Unit Note or
Test Condition
Min. Typ. Max.
High-level (Sourcing) Output
Resistance
Ron_SRC 0.42 0.85 1.6 Ω ISNK = 50 mA
Peak Sourcing Output Current ISRC_pk –41)
1) actively limited by design at approx. 5.2 Apk, parameter is not subject to production test - verified by design /
characterization
A–
Low-level (Sinking) Output Resistance Ron_SNK 0.18 0.35 0.75 Ω ISRC = 50 mA
Peak Sinking Output Current ISNK_pk
2)
2) actively limited by design at approx. -10.2 Apk, parameter is not subject to production test - verified by design /
characterization
-8 – A –
Table 16 Static output characteristics 1 A / 2 A devices (see Figure 10)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
High-level (Sourcing) Output
Resistance
Ron_SRC 1.4 3.1 5.8 Ω ISNK = 50 mA
Peak Sourcing Output Current ISRC_pk –11)
1) actively limited by design at approx. 1.3 Apk, parameter is not subject to production test - verified by design /
characterization
A–
Low-level (Sinking) Output
Resistance
Ron_SNK 0.6 1.2 2.5 Ω ISRC = 50 mA
Peak Sinking Output Current ISNK_pk
2)
2) actively limited by design at approx. -2.6 Apk, parameter is not subject to production test - verified by design /
characterization
-2 – A –
Table 17 Dynamic characteristics (see Figure 5 and Figure 14)
TJ,max = 125°C, CLOAD = 1.8 nF for 4 A / 8 A version, CLOAD = 0.47 nF for 1 A / 2 A version
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
INA- /INB-to-output turn-on /
turn-off propagation delay
tPDon,
tPDoff
31 37 44 ns 4 A/8 A version
INA- /INB-to-output turn-on
propagation delay
tPDon 31 37 44 ns 1 A/2 A version
INA- /INB-to-output turn-off
propagation delay
tPDoff 29 35 44 ns 1 A/2 A version
DISABLE-to-output turn-on/
-off propagation delay
tPDDISoff,
tPDDISoff
– – 100 ns –
Output turn-on propagation
delay mismatch between
channels
∆tPDon – – 3 ns INA, INB shorted
Rise time trise –6.512
1) ns –
Final datasheet 19 Rev. 2.5
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2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Fall time tfall –4.58
1) ns –
Minimum input pulse width
that changes output state
tPW –18–ns–
Programmable dead time tDT – 115 – ns with RDTC = 62 kΩ
1) parameter verified by design, not tested in production
Table 17 Dynamic characteristics (see Figure 5 and Figure 14) (cont’d)
TJ,max = 125°C, CLOAD = 1.8 nF for 4 A / 8 A version, CLOAD = 0.47 nF for 1 A / 2 A version
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Final datasheet 20 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.5 Functional and reinforced isolation specifications
Each individual part number and package variant has its own safety isolation characteristic due to package
dimension and respective isolation test voltages and methods applied. The table heading references each unique
part number.
For reinforced safety, the regulatory tests described in the component and system standards are applied by
Infineon. For functional isolation, the outlined in-house test methods have been applied.
As soon as the regulatory certificates are available, the reference and or documents will become available for
public download on the Infineon website www.infineon.com/2EDi
Note: Final creepage and clearance of component, must be verified in conjunction with PCB design layout
and manufacturing choice like PCB material (CTI), stubs, graves, lacquer which might increase or
reduce safety distances. Meeting the isolation requirements on system level is therefore the
responsibility of the application owner.
4.5.1 Functional isolation specifications
4.5.1.1 Functional isolation of devices in PG-TFLGA-13-1 package
The PG-TFLGA-13-1 package is available for 2EDF7275K and 2EDF7235K. The isolation related parameters are
shown in Table 18, Table 19 and Table 20; for a component with basic or reinforced safety approval, choose a
different part number (e.g. Chapter 4.5.2: 2EDS8265H, 2EDS9265H and 2EDS8165H)
Table 18 Functional isolation input-to-output (PG-TFLGA-13-1)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation test
voltage
VIO 1500 – – VDC Impulse test >10 ms,
production tested
Maximum isolation working
voltage
VIOWM 460 – – VRMS according to IEC 60664-1
(PD 2; MG II)
Package clearance CLR – 3.4 – mm Shortest distance over
air, from any input pin to
any output pin
Package creepage CPG – 3.4 – mm Shortest distance over
surface, from any input
pin to any output pin
Common Mode Transient
Immunity
CMTI 150 – – V/ns according to DIN V VDE
V0884-10, static and
dynamic test
Capacitance input-to-output CIO –2–pF
1)
1) parameter verified by design, not tested in production
Resistance input-to-output RIO – >1000 – MΩ1)
Final datasheet 21 Rev. 2.5
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EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.5.1.2 Functional isolation of devices in NB PG-DSO-16-11 package
The PG-DSO-16-11 package is available for 2EDF7175F, 2EDF9275Fand 2EDF7275F. The isolation related
parameters are shown in Table 21, Table 22 and Table 23
Table 19 Package characteristics (PG-TFLGA-13-1)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Comparative Tracking Index of
package mold
CTI 400 – 600 V according to DIN EN
60112 (VDE 0303-11)
Material group – – II – – according to IEC 60112
Table 20 Functional isolation channel-to-channel (PG-TFLGA-13-1)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation test
voltage
VCh2Ch-DC-
Test
650 – – VDC Impulse Test > 10 ms;
sample tested
Package creepage CPG – 1.0 – mm Shortest distance over
surface, from output pin
Ch1-GND to output pin
Ch2-VDD
Table 21 Input-to-output isolation specification (NB PG-DSO-16-11)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation test
voltage
VIO 1500 – – VDC Impulse test > 10 ms,
sample tested
Maximum isolation working
voltage
VIOWM 510 – – VRMS according to IEC 60664-1
(PD2; MG II)
Package clearance CLR – 4.0 – mm Shortest distance over air,
from any input pin to any
output pin
Package creepage CPG – 4.0 – mm Shortest distance over
surface, from any input
pin to any output pin
Common Mode Transient
Immunity
CMTI 150 – – V/ns according to DIN V VDE
V0884-10, static and
dynamic test
Capacitance input-to-output CIO –2–pF
1)
1) parameter verified by design, not tested in production
Resistance input-to-output RIO – >1000 – MΩ1)
Final datasheet 22 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.5.2 Reinforced isolation of devices in WB PG-DSO-16-30 package
The PG-DSO-16-30 package is available for 2EDS8265H, 2EDS9265H and 2EDS8165H. The safety related
certifications are listed in Table 24, Table 25 and the isolation related parameters are shown in Table 26 to
Table 30
Table 22 Package characteristics (NB PG-DSO-16-11)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Comparative Tracking Index
of package mold
CTI 400 – 600 V according to DIN EN 60112
(VDE 0303-11)
Material group – – II – – according to IEC 60112
Table 23 Channel-to-channel isolation (NB PG-DSO-16-11)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation test
voltage
VCh2Ch-DC-
Test
1500 – – VDC Impulse Test >10 ms;
sample tested
Package Creepage CPG – 2.5 – mm Shortest distance over
surface, from Output pin
Ch1-GND to output pin
Ch2-VDD
Table 24 Component safety-related certificates for WB PG-DSO-16-301)
1) certifications planned for 2EDS9265H
Certification Issuing certification body Certification status Certification number
DIN V VDE V 0884-10 VDE Certified 2)
2) certification no longer available due to standard expiration
40043864
UL 1577 UL Certified E311313
Table 25 Sistem safety-related certifications for WB PG-DSO-16-30 1)
1) certifications planned for 2EDS9265H
Certification Issuing certification body Certification status Certification number
DIN EN 62368-1 (VDE 0868-1),
DIN 60950-1 (VDE 0805-1) VDE Certified 40050289
EN 61010-1 VDE Certified 40051533
EN 60601-1 VDE Certification pending –
GB 4943.1-2011 CQC Certification pending –
CSA C22.2 No. 62368-1 CSA Certification planned –
Final datasheet 23 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
Table 26 Input-to-output isolation specification according to DIN V, VDE0884-10 (2016-06)1)
in WB PG-DSO-16-30
1) VDE encompasses former VDE0884-10, IEC60747-5-5 (opto-coupler standard)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Maximum transient isolation
voltage
VIOTM 8000 – – Vpk qualification for t = 60 s;
production test with
VIOTM > 10 kVpk for t =1 s
Maximum repetitive peak
isolation voltage
VIORM 1420 – – Vpk Time Dependent Dielectric
Breakdown test method
Maximum isolation working
voltage
VIOWM 1420 – – VDC
1000 – – VRMS
Partial discharge voltage VPD 4500 – – Vpk Test sequence: 10.2 kVpk for
t=1s followed by partial
discharge 4.5 kVpk > 1.875 x
VIOWM , QPD < 5 pC; production
test
Maximum surge isolation
voltage
VIOSM 6250 – – Vpk VIOSM_test = 1.6 x VIOSM >10 kVpk;
sample tested 2)
2) Surge pulse tests applied according to IEC60065-10.1 (Ed 8.0 2014), 61000-4-5, 60060-1; waveforms (1.2 µs slope,
50 µs decay)
Package clearance CLR – 8.0 – mm from any input pin to any
output pin
Package creepage CPG – 8.0 – mm from any input pin to any
output pin
Overvoltage category per
IEC 60664-1 table F.1
– I – IV Rated mains voltage
≤ 150 VRMS
I–III ≤ 300 VRMS
I–II ≤ 600 VRMS
Capacitance input-to-output CIO –2 –pF–
Resistance input-to-output RIO – >1000 – MΩ–
Common Mode Transient
Immunity
CMTI 150 – – V/ns input to each output channel;
static & dynamic; sample test
Table 27 Reinforced isolation package characteristics (in WB PG-DSO-16-30)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Comparative Tracking Index
of package mold
CTI 400 – 600 V according to DIN EN 60112
(VDE 0303-11)
Material group – – II – – according to IEC 60112
Pollution degree – – 2 – – –
Climatic category – – 40/125/
21
–– –
Final datasheet 24 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Device characteristics
4.5.3 Safety-limiting values
According to VDE0884-10 and UL1577, safety-limiting values define the operating conditions under which the
isolation barrier can be guaranteed to stay unaffected. This corresponds with the maximum allowed junction
temperature, as temperature-induced failures might cause significant overheating and eventually damage the
isolation barrier.
Table 28 Reinforced input-to-output isolation according to UL1577 Ed 5 (in WB PG-DSO-16-30)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Withstand isolation voltage VISO 5700 – – VRMS VISO= 5700 VRMS for
t = 60 s (qualification);
VISO > 1.2 x VRMS = 6840 V for
t = 1 s
Table 29 Functional isolation channel-to-channel (in WB PG-DSO-16-30)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Functional isolation
test voltage
VCh2Ch-DC-
test
1500 – – VDC Impulse Test >10 ms; sample tested
Package creepage CPG 2.4 2.5 2.7 mm Shortest distance over surface, from
Output pin Ch1-GND to output pin
Ch2-VDD
Table 30 Reinforced isolation safety-limiting values as outlined in VDE-0884-10 (WB PG-DSO-16-30)
Parameter Side Values Unit Note or Test Condition
Min. Typ. Max.
Safety supply power Input chip – – 20.0 mW RthJA = 59 K/W1),
Tamb = 25°C,
TJ = 150°C
1) calculated with the Rth of WB PG-DSO-16-30 package (see Table 7)
Output A – – 1050 mW
Output B – – 1050 mW
Total – – 2120 mW
Safety supply
currents
Output A – – 87.5 mA RthJA = 59 K/W1),
VDDA/VDDB = 12 V,
Tamb = 25°C, TJ = 150°C
Output B – – 87.5 mA
Output A – – 53.5 mA RthJA = 59 K/W,
VDDA/VDDB = 20 V,
Tamb = 25°C, TJ = 150°C
Output B – – 53.5 mA
Safety temperature Ts– – 150 °C Ts = TJ,max
Final datasheet 25 Rev. 2.5
Timing_diag.fm 2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Timing diagrams
5 Timing diagrams
Figure 5 depicts rise, fall and delay times for 2EDi 4 A/8 A. Besides, the effect of an activated dead time control
(resistor connected to pin DTC) is indicated.
Figure 5 Propagation delays, rise, fall and dead time
Figure 6 illustrates the Undervoltage Lockout function for the output supplies.
Figure 6 Output UVLO behavior (output state high)
INA/B
OUTA/B
tPDon
VINH
90%
tPDoff
10%
90%
trise tfall
10%
VINL
tdt
OUTA/B - GNDA/B
VDDA/B - GNDA/B
UVLO
on
UVLO
off
Final datasheet 26 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
6 Typical characteristics
VDDA = VDDB = 12 V, VDDI = 3.3 V, Tamb = 25°C, 2EDF7235K (PG-TFLGA-13-1) and no load unless otherwise noted.
Figure 7 Supply current VDDI
Figure 8 Supply current VDDA, VDDB
I
VDDI
[mA]
T
J
[°C]
Typical VDDI quiescent
current vs. temperature
0
1.0
2.0
3.0
4.0
5.0
6.0
I
VDDI
[mA]
T
J
[°C]
Typical VDDI current vs.
temperature and frequency
1.0
1.2
1.4
1.6
-50 0 50 100 150 -50 0 50 100 150
100kHz
1MHz
3MHz
0.4
0.6
0.8
1.0
-50 0 50 100 150
OUT High
OUT Low
TJ[°C]
IVDDA/B [mA]
Typical VDDA/B quiescent
currents vs. temperature
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
VDDA/B [V]
OUT High
OUT Low
IVDDA/B [mA]
Typical VDDA/B quiescent
currents vs. supply voltage
Final datasheet 27 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
Figure 9 Supply current VDDA, VDDB (with / without load)
Figure 10 Output resistance
Typical VDDA/B current vs.
temperature and frequency, no load
IVDDA/B [mA]
T
J
[°C]
0
10
20
30
40
50
0 200 400 600 800 1000
frequency [kHz]
VDD 4.5V
VDD 12V
VDD 20V
Duty Cycle 50%
CLoad = 1.8nF
IVDDA/B [mA]
Typical VDDA/B current consumption with
capacitive load vs frequency
0
2
4
6
8
10
12
14
-50 0 50 100 150
50kHz
1MHz
3MHz
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 0 50 100 150
R
on
[Ω]
Ron_src
Ron_snk
TJ[°C]
Typical output resistance vs.
temperature (4A/8A version)
0
1
2
3
4
5
6
-50 0 50 100 150
Ron_src
Ron_snk
R
on
[Ω]
TJ[°C]
Typical output resistance vs.
temperature (1A/2A version)
Final datasheet 28 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
Figure 11 Logic input thresholds and VDDI UVLO
Figure 12 VDDA/B UVLO (4 V and 8 V)
0.5
1.0
1.5
2.0
2.5
-50 0 50 100 150
ON threshold
OFF threshold
TJ[°C]
V
VIN
[V]
Typical input voltage
thresholds vs. temperature
2.5
2.7
2.9
-50 0 50 100 150
VDD [V]
UVLO on
UVLO off
TJ[°C]
Typical Undervoltage Lockout
threshold VDDI vs. temperature
VDD [V]
3.7
3.9
4.1
4.3
4.5
-50 0 50 100 150
UVLO on
UVLO off
TJ[°C]
6.4
6.8
7.2
7.6
8.0
8.4
8.8
-50 0 50 100 150
VDD [V]
UVLO on
UVLO off
TJ[°C]
Typical Undervoltage Lockout threshold
VDDA/B vs. temperature (8V-versions)
Typical Undervoltage Lockout threshold
VDDA/B vs. temperature (4V-versions)
Final datasheet 29 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
12.4
12.8
13.2
13.6
14.0
-50 0 50 100 150
VDD [V]
T
j
[°C]
UVLO on
UVLO off
Typical Under Voltage Lockout threshold
VDDA/B vs. temperature (13V-version)
Figure 13 VDDA/B UVLO (13 V)
Figure 14 Propagation delay and rise / fall time
30
35
40
45
-50 0 50 100 150
TJ[°C]
t
PDon,off
[ns]
Typical propagation
delay vs. temperature
3
4
5
6
7
8
-50 0 50 100 150
turn-on
turn-off
VDD=12V
Cload=1.8n
TJ[°C]
t
rise/fall
[ns]
Typical rise and fall time
vs. temperature
Final datasheet 30 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Typical characteristics
Figure 15 Dead time control: rising edge delay vs RDTC
Figure 16 Thermal derating curves
0
50
100
150
200
250
300
0 50 100 150 200
R
DTC
[kΩ]
t
DTC
[ns]
0
500
1000
1500
2000
2500
-50 0 50 100 150
Safety limiting power per channel [mW]
Tamb [°C]
VDDI = 3.3 V
(Current in each channel with both
channels running simultaneously)
0
25
50
75
100
-50 0 50 100 150
Safety limiting current per output [mA]
Tamb [°C]
I_VDDA, VDDB for VDD=12 V
I_VDDA, VDDB for VDD=20 V
VDDI = 3.3 V
(Current in each channel with both
channels running simultaneously)
Thermal derating for safety-
related limiting current Thermal derating for safety-
related limiting power
Final datasheet 31 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
7 Package outline dimensions
The following package versions are available.
• an NB PG-DSO-16-11 package with typ. 4 mm creepage input to output
• an area optimized 5 x 5 mm2 PG-TFLGA-13-1
• a WB PG-DSO-16-30 package with typ. 8 mm creepage input to output
Note: For further information on package types, recommendation for board assembly, please go to:
www.infineon.com/2EDi
7.1 Device numbers and markings
7.2 Package PG-DSO-16-11
Figure 17 PG-DSO-16-11 outline
Table 31 Device numbers and markings
Part number Orderable part number (OPN) Device marking
2EDF7275F 2EDF7275FXUMA2 2F7275B
2EDF9275F 2EDF9275FXUMA1 2F9275B
2EDF7175F 2EDF7175FXUMA2 2F7175B
2EDF7275K 2EDF7275KXUMA2 2F7275B
2EDF7235K 2EDF7235KXUMA1 2F7235A
2EDS8265H 2EDS8265HXUMA2 2S8265B
2EDS9265H 2EDS9265HXUMA1 2S9265B
2EDS8165H 2EDS8165HXUMA2 2S8165B
0.1 C
SEATING
PLANE
0.25 D C 16x
STAND OFF
C
8
COPLANARITY
16x
1.75 MAX.
0.1 MIN.
0.33
+0.17
-0.08
x45°
0.2
+0.05
-0.01
8°M
AX.
0.64
±0.25
6
±0.2
1
9
16
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.25 MAX. PER SIDE
1)
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ]
INDEX
MARKING
BOTTOM VIEW
0.25
GAUGE
PLANE
4
0.0
-0.2
0.41
+0.08
-0.06
D
10
0.0
-0.2
1.27
1)
1
8
916
Final datasheet 32 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
Figure 18 PG-DSO-16-11 footprint
Figure 19 PG-DSO-16-11 packaging
$// ',0(16,216 $5( ,1 81,76 00
7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62 352-(&7,21 0(7+2' > @
,1'(; 0$5.,1*
3,1
Final datasheet 33 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
7.3 Package PG-DSO-16-30
Figure 20 PG-DSO-16-30 outline
Figure 21 PG-DSO-16-30 footprint
'2(6 127 ,1&/8'( 3/$67,& 25 0(7$/ 3527586,21 2) 0$; 3(5 6,'(
$// ',0(16,216 $5( ,1 81,76 00
7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62 352-(&7,21 0(7+2' > @
,1'(;0$5.,1*
%27720 9,(:
'2(6 127 ,1&/8'( '$0%$5 3527586,21 2) 0$;
s
$% &[
0$;
67$1' 2))
s
' & [
rr
*$8*(
3/$1(
&
6($7,1*
3/$1(
&
&23/$1$5,7<
[
$
%
s
[
&$% '[
[ r
'
%$// 6+$3(
(-(&725 0$5.
)/$7 6+$3(
723 9,(:
Final datasheet 34 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
Figure 22 PG-DSO-16-30 packaging
7.4 Package PG-TFLGA-13-1
Figure 23 PG-TFLGA-13-1 outline
24
11
10.8
16
4
3.2
2.7
PIN 1
INDEX MARKING
The drawing is in compliance with ISO 128-30, Projection Method 1 [ ]
All dimensions are in units mm
0.3
Final datasheet 35 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Package outline dimensions
Figure 24 PG-TFLGA-13-1 footprint
Figure 25 PG-TFLGA-13-1 packaging
Final datasheet 36 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Revision history
Page or Item Subjects (major changes since previous revision)
Rev. 2.5 Datasheet, 2020-03-17
Page 1 “certified according to DIN V VDE V0884-10” changed in “DIN V VDE V0884-10
compliant” due to standard expiration on 2019.12.31
Whole document added references to 2EDF9275F and 2EDS9265H (13 V UVLO options for SiC
MOSFETs driving)
Page 1, Table 1 added reference to EN 61010-1 certification
Page 1 update of term DIN EN 62368-1 and DIN EN 60950-1
Table 1 CQC removed from Table 1 due to presence of footnote 2)
Table 1 added footnote 3) due to expiration of VDE0884-10 certification
Table 1, Table 31 added 2EDF9275F and 2EDS9265H products
Table 1 removed OPN for better readability; OPN shown in Table 31
Table 13 VIN max. value 6.5 V→ 15 V
Table 9 added IVDDA, IVDDBquiescient current for 2EDF9275F and 2EDS9265H
Table 11 added VDDA, VDDB Undervoltage Lockout table for 2EDF9275F and 2EDS9265H
Table 13 added “UVLO threshold vs temperature” for the 13 V UVLO options
(2EDF9275F, 2EDS9265H)
Table 24, Table 25 added tables for overview on safety-related certifications of PG-DSO-16-30
Table 26 “see VDE certificate” footnote removed due to certification expiration
Table 28 fixed typo in the test condition: 5700 kVRMS → 5700 VRMS
Table 31 new OPN and “B” marking: improved secondary-side clamping performance
Rev 2.4 Datasheet, 2019-02-08
Table 6 max. VDDI: 3.7 V → 4.0 V
Rev. 2.3 Datasheet, 2019-01-31
Whole document removed “certification pending” because certification has been issued (see
Table 1)
Chapter 7 latest footprints, outlines and packaging for PG-DSO-16-11 and
PG-DSO-16-30
Figure 7 adjusted values
Page 1 propagation delay variance in “Features” updated
Table 1 and Table 31 OPN inserted for 2EDF7235K
Table 6 reference to max. value → VDDO for voltage at pins OUTA and OUTB
Table 6 removed footnote 1 from parameter “Non-destructive Common Mode
Transient Immunity”
Table 8 Tamb max. value 85°C → 125°C
Table 17 CLOAD in "Note or test condition" moved to table description
Table 18, Table 21 and Table 26 Non-destructive Common Mode Transient Immunity transferred to Table 6,
Absolute maximum ratings
Table 18 added footnote to “Capacitance” and “Resistance” parameters
Final datasheet 37 Rev. 2.5
2020-03-17
EiceDRIVER™ 2EDi product family
2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers
Table 21 footnotes assignation patched
Rev. 2.2 Datasheet, 2018-11-07
Chapter 3.2 Update device part numbers
Chapter 4 Update of term “DIN V, VDE V0884-10”
Page 1 Update product validation in “Features”
Table 1, Table 31 Update of OPN
Table 6 Removed typos
Rev. 2.1 Datasheet, 2018-10-24
Table 1, Table 6, Table 31 Updates
Rev. 2.0 Datasheet, 2018-06-04
Initial data sheet available
Page or Item Subjects (major changes since previous revision)
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All referenced product or service names and trademarks are the property of their respective owners.
Edition 2020-03-17
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
Email: erratum@infineon.com
Document reference
EiceDRIVER™ 2EDi Rev.2.4
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