intel. 28F010 1024K (128K x 8) CMOS FLASH MEMORY @ Flash Electrical Chip-Erase m Command Register Architecture for 1 Second Typical Chip-Erase Microprocessor/Microcontroller m Quick Pulse Programming Algorithm Compatible Write Intertace 10 us Typical Byte-Program @ Noise immunity Features 2 Second Chip-Program +10% Vcc Tolerance @ 100,000 Erase/Program Cycles Maximum Latch-Up Immunity through EPI Processing A + m 12.0V 5% Vpp @ ETOX Nonvolatile Flash Technology a High-Performance Read EPROM-Compatible Process Base 65 ns Maximum Access Time ~ High-Volume Manufacturing m CMOS Low Power Consumption Experience 10 mA Typical Active Current @ JEDEC-Standard Pinouts 50 2A Typical Standby Current 32-Pin Plastic Dip 0 Watts Data Retention Power 32-Lead PLCC w Integrated Program/Erase Stop Timer 32-Lead TSOP (See Packaging Spec., Order #231369) m Extended Temperature Options Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on- board during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases memory flexibility, while contributing to time and cost savings. The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel's 28F010 is offered in 32-pin plastic dip or 32-lead PLCC and TSOP Packages. Pin assignments conform to JEDEC standards for byte-wide EPROMs. Extended erase and program cycling capability is designed into Intels ETOX (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F010 performs 100,000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase algorithms. Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low power consumption, and immunity to noise. Its 65 nanosecond access time provides no-WAIT-state perform- ance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 pA trans- lates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address and data pins, from 1V to Voc + 1V. With Intels ETOX process base, the 28F010 levers years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness. October 1993 Order Number: 290207-009 5-33a 28F010 intel. DQy -00, Yoo > \ss > Vpp ERASE VOLT INPUT/OUTPUT SWITCH BUFFERS TO ARRAY SOURCE STATE CONTROL WE# COMMAND REGISTER INTEGRATED PGM VOLTAGE STOP TIMER SWITCH CHIP ENABLE ce# LOGIC OE# Y-DECODER Y-GATING roms 5 B | cocoon | 3 | eitarne 290207-1 Figure 1. 28F010 Block Diagram _ Table 1. Pin Description Symbol Type Name and Function Ao-Ai6 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. DQo-DQ7 | INPUT/OUTPUT | DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data during memory read cycles. The data pins are active high and float to tri-state OFF when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CE# {INPUT CHIP ENABLE: Activates the devices control logic, input buffers, decoders and sense amplifiers. CE # is active low; CE # high deselects the memory device and reduces power consumption to standby levels. OE# INPUT OUTPUT ENABLE: Gates the devices output through the data buffers during a read cycle. OE # is active iow. WE# INPUT WRITE ENABLE: Controls writes to the control register and the array. Write enable is active low. Addresses are latched on the falling edge and data is latched on the rising edge of the WE # pulse. Note: With Vpp < 6.5V, memory contents cannot be altered. Vpp ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing the entire array, or programming bytes in the array. Voc DEVICE POWER SUPPLY (5V + 10%) Vss GROUND NC NO INTERNAL CONNECTION to device. Pin may be driven or left floating. 5-34a intel 28F010 28F010 ar Vpp Ct 32) Voc an oe of A, C2 3110) wee t<aicds>ret Avs O13 30 FAnc 1 3231 50 Ay, C4 29 Ay, A, EJ5 oO 29 A, A, C5 28EI A, 4, C6 284; Che 270A A, C47 27004 *s cl7 P2801 2. 8 5 N28F010 FAs As 32-LeaD 26PlAy A,C}8 =32-Leap pice = 26 FE Ag HPS Org 29M se sexes 2B, . xl. 4,049 top view 24 PA OE# A, Eyt0 24 oc# A, Ty10 230 Ay A, C911 23D AG A, G11 221 ce# Ay C412 22;ce# Ay Fiz 21,)ba, DQ, C413 21-100, pa, C413 20 (Fp 14 15 16 17 18 19 20 Q5 26 pa, Cyi4 19171 De, Ju pa, C415 18100, gg#ge@sgses Vg C416 17 F100, 290207-8 290207-2 4,1 O 32 I oF # ca: noo Ye; 30 or 43 ods 23-1, I STANDARD PINOUT ss wee (77 26-Ip, E28F010 29, Vpp C49 32-LEAD TSOP 24 V5 a i 0.31" x 0.72" ae a Di TOP VIEW = 4, C15 20 J 45 4, 14 ua, A, C15 18 A, a, C16 174; 290207-17 oc# C1 V O32 Da, Ag Co] 2 soa ce# C3 sco4 pb, C4 245 =: REVERSE PINOUT ea 0, Cy? F28F010 26 3 wee CS 32-LEAD TSOP 24S vos i 0.31" x 0.72" | 2 TOP VIEW 21 a, 4c aE aa, 4c 3s & A, 15 18a a; 16 17 A, 290207-18 Figure 2. 28F010 Pin Configurations 5-3528F010 APPLICATIONS The 28F010 flash memory provides nonvolatility along with the capability to perform over 100,000 electrical chip-erasure/reprogram cycles. These fea- tures make the 28F010 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and data-tables are required, the 28F010s reprogrammability and non- volatility make it the obvious and ideal replacement for EPROM. Primary applications and operating systems stored in flash eliminate the slow disk-to-DRAM download process. This results in dramatic enhancement of performance and substantial reduction of power consumption a consideration particularly impor- tant in portable equipment. Flash memory increases flexibility with electrical chip erasure and in-system update capability of operating systems and applica- tion code. With updatable code, system manufactur- ers can easily accommodate last-minute changes as revisions are made. in diskless workstations and terminals, network traf- fic reduces to a minimum and systems are instant- on. Reliability exceeds that of electromechanical media. Often in these environments, power interrup-_ - tions force extended re-boot periods for ali net- worked terminals. This mishap is no longer an issue if boot code, operating systems, communication pro- tocols and primary applications are flash-resident in each terminal. For embedded systems that rely on dynamic RAM/ disk for main system memory or nonvolatite backup storage, the 28F010 flash memory offers a solid state alternative in a minimal form factor. The 28F010 provides higher performance, lower power consumption, instant-on capability, and allows an execute in place memory hierarchy for code and data table reading. Additionally, the flash memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail. The need for code updates pervades all phases of a systems life from prototyping to system manufac- ture to after-sale service. The electrical chip-erasure and reprogramming ability of the 28F010 allows in- circuit alterability; this eliminates unnecessary han- dling and less-reliable socketed connections, while adding greater test, manufacture, and update flexi- bility. 5-36 a intel. Material and labor costs associated with code changes increases at higher levels of system inte- gration the most costly being code updates after sale. Code bugs, or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM-based code requires the re- moval of EPROM components or entire boards. With the 28F010, code updates are implemented locally via an edge-connector, or remotely over a commun- cation link. For systems currently using a high-density static RAM/battery configuration for data accumulation, flash memorys inherent nonvolatility eliminates the need for battery backup. The concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. In addition, flash memory offers a considerable cost advantage over static RAM. Flash memorys electrical chip erasure, byte pro- grammability and complete nonvolatility fit well with data accumulation and recording needs. Electrical chip-erasure gives the designer a blank slate in which to log or record data. Data can be periodically off-loaded for analysis and the flash memory erased producing a new blank slate. A high degree of on-chip feature integration simpli- fies memory-to-processor interfacing. Figure 4 de- picts two 28F010s tied to the 80C186 system bus. The 28F010s architecture minimizes interface cir- Ccuitry needed for complete in-circuit updates of memory contents. The outstanding feature of the TSOP (Thin Small Outline Package) is the 1.2 mm thickness. With stan- dard and reverse pin configurations, TSOP reduces the number of board layers and overall volume nec- essary to layout multiple 28F010s. TSOP is particu- larly suited for portable equipment and applications requiring large amounts of flash memory. Figure 3 illustrates the TSOP Serpentine layout. With cost-effective in-system reprogramming, ex- tended cycling capability, and true nonvolatility, the 28F010 offers advantages to the alternatives: EPROMs, EEPROMs, battery backed static RAM, or disk. EPROM-compatible read specifications, straight-forward interfacing, and in-circuit alterability offers designers unlimited flexibility to meet the high standards of todays designs.28F010 42-202062 0404874 E28F010 01048724 E28FO010 0103823 F28F010 0t04824 F28F010 Figure 3. TSOP Serpentine Layout 5-37. 28F010 in Yee Vpp 1 Yee 80C 186 SYSTEM BUS Vec Vpp Yep Vee I rr Ay~Arg PL AQ-Ag DQg-DQ5 ____________f p9,-pa, DQ)-00, qq____ dt >} DQ, -Da, 28F010 28F010 MCS1# AND MCS 23 rey cE# > CE# BHE# my WEF WR# Dl WE# Ag WE RO rel oE# PT OF# 290207 -4 Figure 4. 28F010 in a 80C 186 System PRINCIPLES OF OPERATION Flash-memory augments EPROM functionality with in-circuit electrical erasure and reprogramming. The 28F010 introduces a command register to manage this new functionality. The command register allows for: 100% TTL-level control inputs; fixed power sup- plies during erasure and programming; and maxi- mum EPROM compatibility. In the absence of high voltage on the Vpp pin, the 28F010 is a read-only memory. Manipulation of the external memory-control pins yields the standard EPROM read, standby, output disable, and Intelli- gent Identifier operations. The same EPROM read, standby, and output disable operations are available when high voltage is ap- plied to the Vpp pin. In addition, high voltage on Vpp enables erasure and programming of the device. All functions associated with altering memory con- tentsIntelligent Identifier, erase, erase verify, pro- gram, and program verifyare accessed via the command register. Commands are written to the register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data 5-38 needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the Intelligent Identifier codes, or out- put data for erase and program verification. Integrated Stop Timer Successive command write cycles define the dura- tions of program and erase operations; specifically, the program or erase time durations are normally terminated by associated program or erase verify commands. An integrated stop timer provides simpli- fied timing control over these operations; thus elimi- nating the need for maximum program/erase timing specifications. Programming and erase pulse dura- tions are minimums only. When the stop timer termi- nates a program or erase operation, the device en- ters an inactive state and remains inactive until re- ceiving the appropriate verify or reset command. Write Protection The command register is only active when Vpp is at high voltage. Depending upon the application, the system designer may choose to make the Vpp pow- er supply switchableavailable only when memory updates are desired. When Vpp = Vpp,, the con-a intel 28F010 Table 2. 28F010 Bus Operations Pins | Vep(t)| Ag | Ag | CE#| OE# | WE#| DQo-DQ, Operation Read VeppL | Ao Ag VIL VIL Vin | Data Out Output Disable Vpp_ | X xX Vir | Vin Vin | Tri-State READ-ONLY | Standby VepL | X xX Vi X X Tri-State Intelligent Identifier (Mfr) (2) VepL | Vit | Vio@)} Vir | Vic | Vin, | Data = 89H Intelligent identifier (Device)(2) | VepL | Vin | Vip@) | Vic | Vic | Vin | Data = B4H Read VppH | Ao Ag VIL VIL Vin | Data Out(4) READ/WRITE Output Disable VppyH | X X Vir | Vin Vin | Tri-State Standby(5) VppH | X X Vin X xX Tri-State Write VppH | Ao Ag Vic | Vin Vit | Data In(6) NOTES: 1. Refer to DC Characteristics. When Vpp = Vpp_ memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other addresses low. 3. Vip is the Intelligent Identifier high voltage. Refer to DC Characteristics. 4. Read operations with Vpp = Vppy may access array data or the Intelligent identifier codes. 5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby). 6. Refer to Table 3 for valid Data-In during a write operation. 7. X can be Vi. or Vin. tents of the register default to the read command, making the 28F010 a read-only memory. In this mode, the memory contents cannot be altered. Or, the system designer may choose to hardwire Vpp, making the high voltage supply constantly available. In this case, all Command Register func- tions are inhibited whenever Vcc is below the write lockout voltage Vi Ko. (See Power Up/Down Protec- tion) The 28F010 is designed to accommodate ei- ther design practice, and to encourage optimization of the processor-memory interface. The two-step program/erase write sequence to the Command Register provides additional software write protections. BUS OPERATIONS Read The 28F010 has two control functions, both of which must be logically active, to obtain data at the out- puts. Chip-Enable (CE #) is the power control and should be used for device selection. Output-Enable (OE #) is the output control and should be used to gate data from the output pins, independent of de- vice selection. Refer to AC read timing waveforms. When Vpp is high (Vpp}), the read operation can be used to access array data, to output the Intelligent Identifier codes, and to access data for program/ erase verification. When Vpp is low (Vpp_), the read operation can only access the array data. Output Disable With Output-Enable at a logic-high level (V)4), output from the device is disabled. Output pins are placed in a high-impedance state. Standby With Chip-Enable at a logic-high level, the standby operation disables most of the 28F010s circuitry and substantially reduces device power consump- tion. The outputs are placed in a high-impedance state, independent of the Output-Enable signal. If the 28F010 is deselected during erasure, pro- gramming, or program/erase verification, the device draws active current until the operation is terminated. Intelligent Identifier Operation The Intelligent identifier operation outputs the manu- facturer code (89H) and device code (B4H). Pro- gramming equipment automatically matches the de- vice with its proper erase and programming algo- rithms. 5-3928F010 With Chip-Enabie and Output-Enable at a logic low level, raising A9 to high voltage Vip (see DC Charac- teristics) activates the operation. Data read from fo- cations OOOOH and 0001H represent the manufac- turer's code and the device code, respectively. The manufacturer- and device-codes can also be read via the command register, for instances where the 28F010 is erased and reprogrammed in the tar- get system. Following a write of 90H to the com- mand register, a read from address location 0OCOOH outputs the manufacturer code (89H). A read from address 0001H outputs the device code (B4H). Write Device erasure and programming are accomplished via the command register, when high voltage is ap- plied to the Vpp pin. The contents of the register serve as input to the internal state-machine. The state-machine outputs dictate the function of the device. The command register itself does not occupy an ad- dressable memory location. The register is a latch a intel. used to store the command, along with address and data information needed to execute the command. The command register is written by bringing Write- Enable to a logic-low level (V;,_), while Chip-Enable is low. Addresses are latched on the falling edge of Write-Enable, while data is latched on the rising edge of the Write-Enable pulse. Standard microproc- essor write timings are used. Refer to AC Write Characteristics and the Erase/ Programming Waveforms for specific timing parameters. COMMAND DEFINITIONS When low voltage is applied to the Vpp pin, the con- tents of the command register default to 00H, en- abling read-only operations. Placing high voltage on the Vpp pin enables read/ write operations. Device operations are selected by writing specific data patterns into the command reg- ister. Table 3 defines these 28F010 register commands. Table 3. Command Definitions Bus First Bus Cycle Second Bus Cycle Command Cycles Req'd | Operation(1) | Address(2)| Data(3) | Operation(1)| Address(2)| Data(3) Read Memory 1 Write Xx 00H Read Intelligent Identifier 3 Write x 90H Read (4) (4) Codes(4) Set-up Erase/Erase(5) 2 Write X 20H Write X 20H Erase Verify(5) 2 Write EA AOH Read 4 EVD Set-up Program/Program(6)| 2 Write X 40H Write PA PD Program Verify(6) 2 Write X COH Read X PVD Reset(7) 2 Write X FFH Write X FFH NOTES: 1. Bus operations are defined in Table 2. 2. 1A = Identifier address: OOH for manufacturer code, 01H for device code. EA = Address of memory location to be read during erase verify. PA = Address of memory location to be programmed. Addresses are latched on the falling edge of the Write-Enable pulse. 3. 1D = Data read from location JA during device identification (Mfr = 89H, Device = B4H). EVD = Data read from location EA during erase verify. PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Enable. PVD = Data read from location PA during program verify. PA is latched on the Program command. . Figure 6 illustrates the Quick Erase Algorithm. NOah 5-40 . Figure 5 illustrates the Quick Pulse Programming Aigorithm. . The second bus cycle must be followed by the desired command register write. . Following the Read intgligent ID command, two read operations access manufacturer and device codes.intel. Read Command While Vpp is high, for erasure and programming, memory contents can be accessed via the read command. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register con- tents are altered. The default contents of the register upon Vpp pow- er-up is OOH. This default value ensures that no spu- rious alteration of memory contents occurs during the Vpp power transition. Where the Vpp supply is hard-wired to the 28F010, the device powers-up and remains enabled for reads until the command-regis- ter contents are changed. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Intelligent Identifier Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer- and device-codes must be ac- cessible while the device resides in the target sys- tem. PROM programmers typically access signature codes by raising AQ to a high voltage. However, mul- tiplexing high voltage onto address lines is not a de- sired system-design practice. The 28F010 contains an Intelligent Identifier opera- tion to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the command register. Following the com- mand write, a read cycle from address OOOOH re- trieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of B4H. To terminate the operation, it is necessary to write another valid command into the register. Set-up Erase/Erase Commands Set-up Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing 20H to the command register. To commence chip-erasure, the erase command (20H) must again be written to the register. The erase operation begins with the rising edge of the Write-Enable pulse and terminates with the rising edge of the next Write-Enable pulse (i.e., Erase-Veri- fy Command). This two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. Also, chip-erasure can only occur when high voltage is applied to the Vpp pin. in the absence 28F010 of this high voltage, memory contents are protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Erase-Verify Command The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing AOH into the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the Write-Enable pulse. The register write terminates the erase opera- tion with the rising edge of its Write-Enable pulse. The 28F010 applies an internally-generated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The erase-verify command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. In the case where the data read is not FFH, another erase operation is performed. (Refer to Set-up Erase/Erase). Verification then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is com- plete. The device can be programmed. At this point, the verify operation is terminated by writing a valid command (e.g. Program Set-up) to the command register. Figure 6, the Quick Erase algorithm, illus- trates how commands and bus operations are com- bined to perform electrical erasure of the 28F010. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Set-up Program/Program Commands Set-up program is a command-only operation that stages the device for byte programming. Writing 40H into the command register performs the set-up operation. Once the program set-up operation is performed, the next Write-Enable pulse causes a transition to an active programming operation. Addresses are in- ternally latched on the falling edge of the Write-En- able pulse. Data is internally latched on the rising edge of the Write-Enable pulse. The rising edge of Write-Enable also begins the programming opera- tion. The programming operation terminates with the next rising edge of Write-Enable, used to write the program-verify command. Refer to AC Programming Characteristics and Waveforms for specific timing parameters. 5-4128F010 Program-Verify Command The 28F010 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at ran- dom. Following each programming operation, the byte just programmed must be verified. The program-verify operation is initiated by writing COH into the command register. The register write terminates the programming operation with the ris- ing edge of its Write-Enable pulse. The program-ver- ify operation stages the device for verification of the byte last programmed. No new address information is latched. The 28F010 applies an internally-generated margin voltage to the byte. A microprocessor read cycle outputs the data. A successful comparison between the programmed byte and true data means that the byte is successfully programmed. Programming then proceeds to the next desired byte location. Figure 5, the 28F010 Quick Pulse Programming algorithm, il- lustrates how commands are combined with bus op- erations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specific timing parameters. Reset Command A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. A valid command must then be written to place the device in the desired state. EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. Howev- er, redundancy requires that cell size be doubled an expensive solution. Intel has designed extended cycling capability into its ETOX flash memory technology. Resulting im- provements in cycling reliability come without in- creasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric field is one-tenth that of common EEPROMs, minimizing the probabili- ty of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 MV/cm lower than EEPROM. The lower electric 5-42 intel. field greatly reduces oxide stress and the probability of failureincreasing time to wearout by a factor of 100,000,000. The 28F010 is capable or 100,000 program/erase cycles. The device is programmed and erased using intels Quick Pulse Programming and Quick Erase algorithms. Intels algorithmic approach uses a se- ries of operations (pulses), along with byte verifica- tion, to completely and reliably erase and program the device. For further information, see Reliability Report RR-60. QUICK PULSE PROGRAMMING ALGORITHM The Quick Pulse Programming algorithm uses pro- gramming operations of 10 js duration. Each opera- tion is followed by a byte verification to determine when the addressed byte has been successfully pro- grammed. The algorithm aliows for up to 25 pro- gramming operations per byte, although most bytes verify on the first or second operation. The entire sequence of programming and byte verification is performed with Vpp at high voltage. Figure 5 illus- trates the Quick Pulse Programming algorithm. QUICK ERASE ALGORITHM Intels Quick Erase algorithm yields fast and reliable electrical erasure of memory contents. The algo- rithm employs a closed-loop flow, similar to the Quick Pulse Programming algorithm, to simulta- neously remove charge from all bits in the array. Erasure begins with a read of memory contents. The 28F010 is erased when shipped from the factory. Reading FFH data from the device would immedi- ately be followed by device programming. For devices being erased and reprogrammed, uni- form and reliable erasure is ensured by first pro- gramming all bits in the device to their charged state (Data = 00H). This is accomplished, using the Quick Pulse Programming algorithm, in approximately two seconds. Erase execution then continues with an initial erase operation. Erase verification (data = FFH) begins at address 0000H and continues through the array to the last address, or until data other than FFH is en- countered. With each erase operation, an increasing number of bytes verify to the erased state. Erase efficiency may be improved by storing the address of the last byte verified in a register. Following the next erase operation, verification starts at that stored ad- dress location. Erasure typically occurs in one sec- ond. Figure 6 illustrates the Quick Erase algorithm.28F010 Operation Command Comments Apply Vepu [1] Standby Wait for Vpp Ramp to Vppp(1) tnitialize Pulse-Count Vv - WRITE Set- Program cmd Write Set-up Data = 40H Program Write Program Valid Address/Data Standby Duration of Program Operation (twHwH1) Write Program(2) | Data = COH; Stops Program Verify Operation(3) Standby tWHGL Read Read Byte to Verify Programming Standby Compare Data Output to Data Expected Y Increment Lost Address Address Y Write . Write Read Data = 00H, Resets the Register for Read Operations Appl Appl . Vpn it | | Von tt Standby Wait for Vpp Ramp to Vep; (1) Programming Completed 290207-5 NOTES: 3. Refer to principles of operation. 1. See DC Characteristics for the value of Vppy and Vpp. 4. CAUTION: The algorithm MUST BE FOLLOWED 2. Program Verify is only performed after byte program- to ensure proper and reliable operation of the de- ming. A final read/compare may be performed (option- vice. al) after the register is written with the Read command. Figure 5. 28F010 Quick Pulse Programming Algorithm 5-4328F010 intel. (4) Start Erosure N Program All Bytes to OOH ADDR = 00H PLSCNT = 0 Write Erase Set-up Cmd Time Out 10 ms > Write Erase Verify Cmd Time Out 6 us Read Data from Device Increment Address Apply Veet [t] Erasure Completed 290207-6 1. See DC Characteristics for the value of Vppy and VPPL- 2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is written with the read command. Apply Vopy [1] Bus Operation Command Comments Entire Memory Must = 00H Before Erasure Use Quick Pulse Programming Algorithm (Figure 5) Standby Wait for Vpp Ramp to Vppy(1) Initialize Addresses and Pulse-Count Write Set-up Data = 20H Erase Write Erase Data = 20H Standby Duration of Erase Operation (twHwHe) Write Erase(2) Addr = Byte to Verify; Verify Data = AOH; Stops Erase Operation(3) Standby tWHGL Read Read Byte to Verify Erasure Standby Compare Output to FFH increment Pulse-Count Write Read Data = OOH, Resets the Register for Read Operations Standby Wait for Vpp Ramp to Vpp;(1) 3. Refer to principles of operation. 4. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the de- vice. Figure 6. 28F010 Quick Erase Algorithm 5-44intel. DESIGN CONSIDERATIONS Two-Line Output Control! Flash-memories are often used in larger memory ar- rays. Intel provides two read-control inputs to ac- commodate multiple memory connections. Two-line control provides for: a. the lowest possible memory power dissipation and, b. complete assurance that output bus contention will not occur. To efficiently use these two control inputs, an ad- dress-decoder output should drive chip-enable, while the systems read signal controls all flash- memories and other paralle! memories. This assures that only enabled memory devices have active out- puts, while deselected devices maintain the low power standby condition. Power Supply Decoupling Flash-memory power-switching characteristics re- quire careful device decoupling. System designers are interested in three supply current (Icc) issues standby, active, and transient current peaks pro- duced by falling and rising edges of chip-enable. The capacitive and inductive loads on the device outputs determine the magnitudes of these peaks. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between Vcc and Vsg, and between Vpp and Vss. . Place the high-frequency, low-inherent-inductance capacitors as close as possible to the devices. Also, for every eight devices, a 4.7 wF electrolytic capaci- tor should be placed at the arrays power supply connection, between Voc and Vgg. The bulk capaci- tor will overcome voltage slumps caused by printed- 28F010 circuit-board trace inductance, and will supply charge to the smaller capacitors as needed. Vpp Trace on Printed Circuit Boards Programming flash-memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the Vpp power sup- ply trace. The Vpp pin supplies the memory cell cur- rent for programming. Use similar trace widths and layout considerations given the Vcc power bus. Ad- equate Vpp supply traces and decoupling will de- crease Vpp voltage spikes and overshoots. Power Up/Down Protection The 28F010 is designed to offer protection against accidental erasure or programming during power transitions. Upon power-up, the 28F010 is indifferent as to which power supply, Vpp or Vcc, powers up first. Power supply sequencing is not required. Inter- nal circuitry in the 28F010 ensures that the com- mand register is reset to the read mode on power up. A system designer must guard against active writes for Vcc voltages above Vixo when Vpp is active. Since both WE# and CE# must be low for a com- mand write, driving either to V4 will inhibit writes. The control register architecture provides an added level of protection since alteration of memory con- tents only occurs after successful completion of the two-step command sequences. 28F010 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases the usable battery life of your system because the 28F010 does not consume any power to retain code or data when the system is off. Table 4 illustrates the power dissipated when updating the 28F010. Table 4. 28F010 Typical Update Power Dissipation(4) Operation Notes Watt Seccade). Array Program/Program Verify 1 0.171 Array Erase/Erase Verify 0.136 One Complete Cycle 3 0.478 NOTES: 1. Formula to calculate typical Program/Program Verity Power = [Vpp x # Bytes x typical # Prog Pulses (twHwH1 X Ipp2 typical + twHat x Ipp4 typical)] + [Vcc x # Bytes x typical # Prog Pulses (twHwH1 X Ioce typical + twHet X 'Icc4 typical]. 2. Formula to calculate typical Erase/Erase Verify Power = [Vpp (Vpp3 typical x terase typical + Ipps typical x twHGgL X # Bytes)} + [Vcc (locs typical x terase typical + Iocs typical < twHgL < # Bytes)]. 3. One Complete Cycie = Array Preprogram + Array Erase + Program. 4. Typicals are not guaranteed, but based on a limited number of samples from production lots. 5-4528F010 ABSOLUTE MAXIMUM RATINGS Operating Temperature During Read .................. 0C to +70C(1) During Erase/Program ......... oC to +70C(1) Operating Temperature During Read ............... 40C to + 85C(2) During Erase/Program ...... 40C to + 85C(2) Temperature Under Bias....... 10C to +80C(1) Temperature Under Bias....... 50C to +95C(2) Storage Temperature .......... 65C to + 125C Voltage on Any Pin with Respect to Ground.......... 2.0V to + 7.0V(3) Voltage on Pin Ag with Respect to Ground....... 2.0V to +13.5V03, 4) Vpp Supply Voltage with Respect to Ground During Erase/Program ....2.0V to + 14.0V%, 4) Voc Supply Voltage with Respect to Ground.......... 2,0V to + 7.0V(8) Output Short Circuit Current............. 100 mA(5) NOTES: intel. NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. 1. Operating Temperature is for commercial product as defined by this specification. 2. Operating Temperature is for extended temperature products as defined by this specification. 3. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods less than 20 ns. Maximum DC voitage on output pins is Voc + 0.5V, which may overshoot to Vcc + 2.0V for periods less than 20 ns. 4. Maximum DC voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. 6. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics. OPERATING CONDITIONS Symbol Parameter Limits Unit Min Max Ta Operating Temperature 0 70 C Ta Operating Temperature 40 +85 C Voc Voc Supply Voltage (10%) 4.50 5.50 v Voc Voc Supply Voltage (5%) 4.75 .25 Vv DC CHARACTERISTICSTTL/NMOS COMPATIBLECommercial Products Symbol Parameter Notes Limits Unit Test Conditions Min | Typical(4) | Max lo Input Leakage Current 1 1.0 | pA | Voc = Voc Max Vin = Voc or Vss lLo Output Leakage Current 1 +10 | pA | Voc = Voc Max Vout = Vcc or Vss locs Voc Standby Current 1 0.3 1.0 mA | Voc = Voc Max CE# = Vin loci Voc Active Read Current 1 10 30 mA | Voc = Voc Max, CE# = Vit f = 6 MHz, lout = OMA 5-46intel e 28F010 DC CHARACTERISTICSTTL/NMOS COMPATIBLECommercial Products (Continued) Symbol Parameter Notes Limits Unit Test Conditions Min |Typical(4)| Max loce Voc Programming Current 1,2 1.0 10 mA |Programming in Progress loos Voc Erase Current 1,2 5.0 15 mA |Erasure in Progress loca Voc Program Verify Current 1,2 5.0 15 mA |Vpp = Vppp, Program Verify in Progress locos Voc Erase Verify Current 1,2 5.0 16 mA |Vpp = Vppy;, Erase Verify in Progress lpps Vpp Leakage Current 1 +10 pA |Vpp < Voc lppy VppRead Current 1 90 200 pA |Vpp > Voc or Standby Current +100 Vpp < Voc Ippe Vpp Programming Current 1,2 8.0 30 MA |Vpp = VppH Programming in Progress Ipp3 Vpp Erase Current 1,2 6.0 30 MA |Vpp = VppH Erasure in Progress Ipp4 Vpp Program Verify Current 1,2 2.0 5.0 mA |Vpp = Vppp, Program ; Verify in Progress Ipps Vpp Erase Verify Current 1,2 2.0 5.0. MA |Vpp = Vppx, Erase Verify in Progress ViL Input Low Voltage -0.5 0.8 Vv Vi Input High Voltage 2.0 Voc + 0.5] V VoL Output Low Voitage 0.45 V jlo: = 5.8 mA Voc = Voc Min Vou1 {Output High Voltage 2.4 V jlon = 2.5mA Voc = Voc Min Vip Ag Intelligent Identifer Voltage 11.50 13.00 Vv lip Ag Intelligent Identifier Current| 1, 2 90 200 BA |Ag = Vip Vpp_ | Vpp during Read-Only 0.00 6.5 V_|NOTE: Erase/Program are Operations Inhibited when Vpp = Vpp,| VepH |Vpp during Read/Write 11.40 12.60 Vv Operations Viko {Voc Erase/Write Lock Voltage 2.5 Vv DC CHARACTERISTICSCMOS COMPATIBLECommercial Products Symbol Parameter Notes Limits Unit Test Conditions Min | Typical(4) | Max tu Input Leakage Current 1 +1.0] pA | Voc = Voc Max Vin = Voc or Vgg ILo Output Leakage Current 1 +10] pA } Voc = Voc Max Vout = Voc or Vss locs Voc Standby Current 1 50 100 | pA | Voc = Voc Max CE# = Voc +0.2V loc1 Voc Active Read Current 1 10 30 | MA | Voc = Voc Max, CE# = Vic f = 6 MHz, lout = OMA | 5-4728F010 intel : DC CHARACTERISTICSCMOS COMPATIBLECommercial Products (Continued) Symbol Parameter Not Limits Unit Test Conditions Min Typical(4) Max loca Voc Programming Current 1,2 1.0 10 mA | Programming in Progress locs Voc Erase Current 1,2 5.0 15 mA | Erasure in Progress loca Voc Program Verify Current} 1,2 5.0 15 MA | Vpp = Vepy, Program Verify in Progress loos Voc Erase Verify Current 1,2 5.0 16 mA | Vpp = Vppp, Erase Verify in Progress Ipps Vpp Leakage Current 1 +10 pA | Vpp < Voc tpp;__| Vpp Read Current, ID 1 90 200 | pA | Vpp > Voc Current or Standby Current #410 Vpp < Voc Ippe Vpp Programming 1,2 8.0 30 MA | Vpp = VppH Current Programming in Progress Ipp3 Vpp Erase Current 1,2 6.0 30 mA | Vpp = VppH | Erasure in Progress Ipp4 Vpp Program Verify 1,2 2.0 5.0 MA | Vpp = Vppx, Program Current . Verify in Progress Ipps Vpp Erase Verify i,2 2.0 5.0 MA | Vep = Vppp, Erase Current Verify in Progress ViL Input Low Voltage -0.5 0.8 Vin Input High Voltage 0.7 Voc Voc + 0.5 Vor Output Low Voltage 0.45 V jlo, = 5.8mA Voc = Vcc Min vi 0.85 V, lon = 2: : =V, i Ont Output High Voltage ce vy [OH 2.5 mA, Voc ce Min Von2 Voc 0.4 lou = 100 nA, Voc = Voc Min Vip Ag Intelligent Identifer 11.50 13.00 Vv Voltage lip Ag Intelligent Identifier 1,2 90 200 BA | Ag = Vip Current VPPL Vpp during Read-Only 0.00 6.5 V_ | NOTE: Erase/Programs are Operations Inhibited when Vpp = Vpp, VPPH Vpp during Read/Write 11.40 12.60 Vv Operations VLKO Voc Erase/Write Lock 2.5 v Voltage 5-48intel 28F010 De CHARACTERISTICSTTL/NMOS COMPATIBLEExtended Temperature roducts Symbol Parameter Notes Limits Unit Test Conditions Min |Typical(4| Max lu Input Leakage Current 4 +1.0 | pA Voc = Voc Max Vin = Voc or Vsg lLo Output Leakage Current 1 10 | wA|Voc = Voc Max Vout = Vcc or Vss locs Voc Standby Current 1 0.3 1.0 mA |Vcc = Voc Max CE# = Vin loci Vcc Active Read Current 1 10 30 mA |Vcc = Voc Max, CE# = Vi, f = 6 MHz, lout = OMA loce Voc Programming Current 1,2 1.0 30 mA {Programming in Progress Icc3 _|Voc Erase Current 1,2 5.0 30 mA |Erasure in Progress loca [Voc Program Verify Current 1,2 5.0 30 mA |Vpp = Vppy, Program Verify in Progress Iccs _|Voc Erase Verify Current 1,2 5.0 30 mA |Vpp = Vppy, Erase Verify in Progress lpps Vpp Leakage Current 1 +10 | pA|Vpp < Voc Ippy Vpp Read Current 1 90 200 pA |Vpp > Voc or Standby Current +10.0 Vpp < Voc Ippo Vpp Programming Current 1,2 8.0 30 mA |Vpp = Vppy Programming in Progress lppg Vpp Erase Current 1,2 6.0 30 MA |Vpp = Vppy Erasure in Progress Ipp4 Vep Program Verify Current 1,2 2.0 5.0 mA |Vpp = Vppx, Program Verify in Progress Ipps Vpp Erase Verify Current 1,2 2.0 5.0 MA |Vpp = Vppy, Erase ; Verify in Progress Mit Input Low Voltage 0.5 0.8 Vv Vin Input High Voitage 2.0 Voc + 0.5] V VoL Output Low Voltage 0.45 V flo. = 5.8mA Voc = Voc Min Vou1 |Output High Voltage 2.4 V jlo = 2.5mA Voc = Vcc Min MID Ag Intelligent Identifer Voltage 11.50 13.00 v lio Ag Intelligent Identifier Current] 1, 2 90 500 pA IAg = Vip VppL__|Vpp during Read-Only 0.00 6.5 V_ |NOTE: Erase/Program are Operations Inhibited when Vpp = Vppy VppH_ |Vpp during Read/Write 11.40 12.60 Vv Operations ViKo |Vcc Erase/Write Lock Voltage 2.5 Vv | 5-4928F010 intel. DC CHARACTERISTICSCMOS COMPATIBLEExtended Temperature Products Symbol] Parameter _| Notes Limits Unit} Test Conditions Min | Typical(4)) Max Iu Input Leakage 1 +1.0 BA |Voc = Voc Max Current Vin = Voc or Vss ILo Output Leakage 1 +10 pA |Voc = Voc Max Current Vout = Voc or Vss locs Voc Standby 1 50 100 BA |Voco = Voc Max Current CE# = Vcc 0.2V loc Voc Active Read 1 10 30 mA |Voc = Voc Max, CE# = Vit Current f = 10 MHz, Iloyy = OMA loc2 Voc Programming 1,2 1.0 10 mA | Programming in Progress Current locs Voc Erase Current 1,2 5.0 30 mA | Erasure in Progress loca Voc Program Verify 1,2 5.0 30 MA |Vpp = Vppx, Program Current Verify in Progress locs Voc Erase Verify 1,2 5.0 30 mA |Vpp = Vppp, Erase Current Verify in Progress Ipps Vpp Leakage Current 1 +10 BA |Vpp < Voc Ipp4 Vpp Read Current, 1 90 200 pA |Vpp > Voc ID Current or Standby Current +10 Vep < Voc Ippo Vpp Programming 1,2 8.0 30 MA | Vpp = Vppy Current Programming in Progress Ippa Vpp Erase Current 1,2 6.0 30 mA |Vpp = VppH Erasure in Progress Ippa Vpp Program Verify 1,2 2.0 5.0 mA |Vpp = Vppx, Program Current Verify in Progress Ipps Vpp Erase Verify 1,2 2.0 5.0 mA |Vpp = Vpp, Erase Current Verify in Progress VIL Input Low Voltage -0.5 0.8 Vv Vin Input High Voltage 0.7 Voc Voc + 0.5] V VoL Output Low Voltage . 0.45 V flot = 5.8mA Voc = Voc Min VoH1 : 0.85 Voc lon = 2.5 mA, Output High Voltage V Voc = Veo Min VoH2 Voc 0.4 loo = 100 pA, Voc = Vcc Min Vio Ag Intelligent Identifer | 11.50 13.00 Vv Voltage lio Ag Intelligent Identifier| 1,2 90 500 pA |Ag = Vip Current 5-50intl : 28F010 DC CHARACTERISTICSCMOS COMPATIBLEExtended Temperature Products (Continued) Symbol Parameter Notes Limits Unit Test Conditions Min | Typical(4) | Max VepPL Vpp during Read-Only 0.00 6.5 V_ | NOTE: Erase/Programs are Operations Inhibited when Vpp = Vpp. VpPH Vpp during Read/Write 11.40 12.60} V Operations ViKo Voc Erase/Write Lock 2.6 v Voltage CAPACITANCE Ta = 25C, f = 1.0 MHz Symbol Parameter Notes Limits Unit Conditions Min Max Cin Address/Control Capacitance 3 8 pF Vin = OV Cout Output Capacitance 3 12 pF Vout = OV NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, Vpp = 12.0V, T = 25C. These currents are valid for alt product versions (packages and speeds). 2. Not 100% tested: characterization data available. 3. Sampied, not 100% tested. 4. Typicals are not guaranteed, but based on a limited number of samples from production lots. 5-5128F010 AC TESTING INPUT/OUTPUT intel. HIGH SPEED AC TESTING INPUT/OUTPUT WAVEFORM(1) WAVEFORM(2) | 24 ss 3.0 ts wwPut oe PonTS < Ke QUTPUT rut X1.5 TEST POINTS >1.5 OUTPUT 0.45 : i$ : 0.0 ss 290207-7 AC test inputs are driven at Von (2.4 Vr7,) for a Logic 41 and Voz (0.45 Vt.) for a Logic 0. Input timing begins at Vjy (2.0 VrtL) and Viz (0.8 Vrt_). Output tim- ing ends at Viy and Vi,. Input rise and fall times (10% to 90%) <10 ns. 280207-8 AC test inputs are driven at 3.0V for a Logic 1 and 0.0V for a Logic 0. Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. AC TESTING LOAD CIRCUIT(!) HIGH SPEED AC TESTING LOAD CIRCUIT(2) INS14 INS14 RX RR DEVICE DEVICE UNDER out UNDER out TEST TEST q q C, = 100 pF T C, = 30 pF Tt C, includes Jig Capacitance ~ 290207-22 C_ includes Jig Capacitance ~ 290207-~23 RL = 33 KN RL = 3.3 KN AC TEST CONDITIONS(1) HIGH-SPEED AC TEST CONDITIONS(2) Input Rise and Fall Times (10% to 90%)...... 10 ns Input Rise and Fail Times (10% to 90%)...... 10 ns Input Pulse Levels ................ 0.45V and 2.4V Input Pulse Levels ................- 0.0V and 3.0V Input Timing Reference Level ....... 0.8V and 2.0V Input Timing Reference Level ................ 1.5V Output Timing Reference Level ...... 0.8V and 2.0V Output Timing Reference Level .............. 1.5V Capacitive Load.......... 00... cece eee ee 100 pF Capacitive Load................. cece eee ee 30 pF NOTES: 1. Testing characteristics for 28F010-65 in standard configuration, and 28F010-90, 28F010-120, and 28F010-150. 2. Testing characteristics for 28F010-65 in high speed configuration. 5-5228F010 sonsue}oesey Buse} 10) synoutg peo? Buyse| Oy pue SUUOJeAeM BoUELEJe: INd\INC/NdU| OV e9S Ss sonsueye7eYyo Bugse} 40J synd19 peo? Bunse, Oy peeds YBi} pue SUOJEARAA BOUElEJ01 indinosindu Oy peeds yBiy ees -y uBisep Aq peeyueseny pe}se1 % 00} 10u pejdues Zz YSUly SINDDO JOABYSIYM *| sCommercial and Extended & YY 2 'S3.LON g peey si0jeq gS si 9 9 9 9 9 eu) Ai@Aooey CW, OHM, ebueyd #30 10 #39 = su 0 0 0 zh sSeJpply WO PjOH INdjnC, HO} 6 Z UBIY s su se oe ~ 0 oe oe Zz indynE oO} e1qesiq yndyng ; 4Mj/ZOHO, o Z M07 Ul Su 0 0 0 2 indyno 0} ejqeuz yndyno | 710,/XO1D) oe Z UBIH UI 2 su ss ss Sy Ov Se Zz ndjno 0} eiqesiq dup 20H3; - 3 su 0 0 Z Z MO7] 0} efqeug diyn | 2/XO13; 2 3 su ss 0S se ez Sz OUI, SSED0y e/qeUy IndinO | _30,/ADT, Wa | | ost 021 06 od s9 Sul, S8eddy SseIppy | SOY) /ADAY) 5 su Ost Oz} 06 OL g9 eull| ssesoy eiqeug diyp | 30,/A0 13) og <s su OSI ozt 06 OZ so QU, @JOAD peay | DH} /AVAV, c+ i < 5 xen UIIN xew UIA xew UII XBW UlIN xeW UI S9}ON ONSHe}esBYD joquiAg @ | yun | (0st-o1r0s9z (s)0Z1-010282 ()06-01.0482 (g)S9-010482 %OL + FDA Oo E (v)S9-0L0487 %S F IDA SUO|S10A <E 5-5328F010 6- 402062 Lal Z HOIH AN QP) ADAV, ______.-eof (Zhy x07, - Je (210) x09, GY) Ad1a, >} (2%) ~y Z HOIH cr (3%) f+ 20H) = pe 20H, ene OHM, PX AVAY, a NMOG-4IMOd 9A ASGNYLS a1evis ssauaov \ __) ONnvA viva Q318N3 S1INdiNo NOILD313S SS3Hd0 ONY DIA: 30 ALLS AGONVLS dn-wamod 29 AO 2D, AOS (od) viva (#4) #3M (#9) #30 (#3) #39 $3ss3ydav Figure 7. AC Waveforms for Read Operations 5-5428F010 yonpoud eunyesedwe) pepueyxg 410) UoVBoYyIoeds WNUIUI 9 sonsue}oBseyo Buyse} 10) synoutg peo7 Bunse; oy pue suuojenem BoUGJE}E) yndyngsindu| oy ees s sonsue}BIeYS Buyse) 104 SyNdIID peo? Buses Dy peeds YB pue SUUOJEABMA GOUBJE}O: nding sindu; oy peeds yBiy ees y uoneoyioeds wnuwIxe 8 10) peeu ey) Buneuiuje snuy suolpesedo eseie/BuiuwesBo1d eyy SeyBUILUE} Jew doys peyesBequl eu, uBisep Aq peejuBeny Zz suoesedO AJUC-Peey 404 SONSUE}OBIeUD Oy 0} Jejey sUCHesedo AjUO-peed Buunp se ewes oy) ese suOHeedo eymM/peal Bunp sonsueyoeseyo Buin peel | /Program Only Operations(1) *S3.LON M07 e1qBUR dIYUD svt l L I I i zZ 0} ew) dr-jeg ddp, TadAy uoneedQ sw G6 s6 s'6 6 S'6 esesg JO uOnBING cHMHMy uonsledC, sv ol ol Ol ol Ol Buxuwes6org Jo uoNesng LHMHMy su ir 02 oz 02 oz UBIH UIPIAA easing eA | Hd) MANY Sg 9 sv 09 09 OF Or Ov UIPIM 88iNg BUA, | oMy/HM TINY su o 0 0 0 0 BULL PIOH eqeuy diyo | HOy/HSHMy SIUM 810}0q su cor Sl Sl Sl Sk eu, dr-yeg ejqeuz diyy SO)/1M1Ay BAA 810JOq su 0 0 0 0 0 2 aul) Aeacoey peey MHD} PeeY e10jeq sv 9 9 9 9 9 eu] AIGA0DEY OMA TOHM, su Ol Ot Ol OL ol OWL PIO ByeQ | HOy,/XAHMy ss 9 * OF Or Or Ov Ov ew, dr-leg eye@q | S0)/HMAC, SS 9 * Or or Or Or OF el) PiOH SSeuppy Hy XV IMy su 0 0 0 0 0 oul, d/)-18g ssezppy SV) IMAVy su OSL Oz 06 OL $9 BUI, BFAD OM | IM) /AVAY) xeW UW XEW UW XeVW UIN xew UW Xew UW Sa)ON WISaeswyD joquiAs wun | (s)0St-010482z ()0Z}-01.0482 ()06-01. 0192 (s)S9-01.0482 %O1 F IDA eucjesoa ()S9-01.0482 %S F 99K Commercial and Extended Temperature Products AC CHARACTERISTICSWrite/Erase 5-5528F010 99.9 CUM . PROB. 2 #25 3 35 4455 10 15 Chip Program Time (Sec) 12V; 10 ke; 23C 202 11.4; 10 ke: 70C e-- 12V; 100 ke; 23C 20 290207 -13 Figure 8. Typical Programming Capability CHIP PROGRAM TIME SEC 2 0 10 2 WD 53 DW MO WM 10 110 10 TEMP (Cc) 1k Cycles omme 10k Cycles women 100k Cycles 19 290207-14 5-56 Figure 9. Typical Program Time at 12V28F010 CUM . PROB. 28F010~120/150 28F010-200 05 07 1 2 3 45678910 20 30 CHIP ERASE TIME (SEC) 12V;10 ke; 23C womemoe =$1.4V510 ke 3 0C ewnwmee 123100 ke; 23C 290207-15 Figure 10. Typical Erase Capability 32 30 28 26 24 a "v ws Z 22 = a < = 20 a oa 18 1.6 14 12 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 TEMP (C) o tk Cycles : = 10k Cycles mome= 100k Cycles 290207~16 Figure 11. Typical Erase Time at 12V 5-5728F010 OL~L0Z062 \ Tddy ddy Ag? AQ Wp AO'S (0a) viva (#M) #3 (#9) #30 (#3) #39 s3ss3udav dA, >) Ie- aora, | (ZA) O73, Ut viva , N Hoo = NIVivd Hoy _ | NIVLVO NIVLVG NK atv f (71) Z HOIH xXD19, HAA 70, (#44) O xOHM, HATA (20) ADT, 3 Son OHM, HAHA, VL 4 i)) (4) at ZDH3, (SA) (49) wT, H3HM, 13, i 13, H3HMy t+ \ L cy x0, cy 0m _/f TAY, > TAAY, >| | JL (thy AVA, (My) AVAY, ot (2M) AVAY, be (My) AVAYY NMOO-43M0d 27A NOILVOUdIH3A CNVYANWOD ONINNVEDONd =v1Vd # SS3udav HOLT GNVNNOO AGQNVLS / ABONVES Wwvud0dd ASIMIA GNVAWOD WYYSOd WVU90Ud dN-13S dN-y3MOd 24 WV490ud Figure 12. AC Waveforms for Programming Operations 5-5828F010 LL-20z062 Tddy ddy AOTI ECL AO 294 AO'S Cr) Je ora, > (Zh) %013, K HOz = Hoz = / (70) NI Viva Ni Viva THO (0a) viva xOT HMAQ, xaHm, xGHA, XGHM, } HIM, HATH, (20) Ad19, 3 (#4) #3M J 4) T9Hm, ZHAHM, ZOHD, (Ham) THM, WHO, be (#9) #30 St af 5 (*y) (Sy (A) a) HOHM, (SY) (4) TAT, HaHM#, TW, 1 1a13, HIHM, ro : (#3) #30 (HY) TH, (S%) HAY, } (Oty AVAY, gt 1 (2M,) AVAY, Om) AvAY, Om) AvaY, sassayqay NMOO-YaMOd 7%, NOILVOISIN3A ONVAWOD ONISVYR ONVNAOS 3SVu3 GNVYANOS ASONViS NVLS asvaz AdIaA 3Svaa dN-13S dN-W3MOd 2% 3asvaz 5-59 Figure 13. AC Waveforms for Erase Operations28F010 AC CHARACTERISTICSAlternative CE #-Controlied WritesCommercial and Extended Temperature suonesede AjuQ-peey 104 SoNSUE}OBIeYD OV 0} 48}0H suonesedo Aju0-pee, Bi sosuejoRseYyo Buse} 10} SYNIO peo? Buyse| Ov pue sonsuejoeseyo Bugse} 10) syNdIg peo) Bunse) Oy peeds uoneoytoeds uinwew 8 JO} peeu e4) BuyeuIUe snuyy suoHes onpoid eunyesedwe | pepusyxg 40) uoHeoyloeds WNWIUIW, 9 BiH pue SULOJOABM SUUOJOABNA EQUGIEJOI INGNO/Ndu OV ees S eouesajes INNO Indu} Oy peeds yBIH 9eg Py edo eseie/buiwuesBosd ey) SeyBUIWIE} soLUN doys peyesBeyu! oul uBisep Aq peayuBsend 2 UUNp SB ewes ey) Gue SUCNBsEdO B}UM/PROl Buunp sonsuejoeseyo Bury peey | *3.LON MO7 8/QBUy se b b L b \ z diug oy ew, dn-ieg ddq | T3dAy uoyesedQ su s s6 s s6 s'6 eseiq jo uoyeing | @HaHs) uoyesedQ sv or Ol ol ol ol Bulwwes601g jo uoNeINg | +H3H3 su oz oz 02 oz 02 UBIH UIPIM 8SINd O1UM 1AHAy su 09 9 o OL Sv St op UIPIM 8SINd 1M H313} su 0 0 0 0 0 OUI, PIOH eIqeuy awM | HMH=) ajqeuz diyd eiojeq su 0 0 0 0 0 owls d-1eg eiqeuz eM Tay elu 210304 su 0 0 0 0 0 2 ew Mieacoey peey | IMHD) peey o10jeq su 9 9 9 9 9 aul Ai@AOdeY OHM 79H3; su ol OL or oL OL awl PIOH Bed XH; su os 9 Sy Sy ce se se ew! dr-leg e1eq H3AG, su 09 9 SS gs SP SY Sv ell) PJOH SSeuppy XVv1Ay su 0 0 0 0 0 ely dn-1eS sseuppy TAY} su oSt oet 06 04 s9 BUI, @fOAD OUAA AVAYY xe ul xeW UI xeW UII xew UI XBW uN SO]ON ONsa}BIeYD joquids wun | (s)0Sb-0 0492 (g)0Z4-01.0482 (g)06-010482 (g)S9-010482 %OL F FFA SUOISIOA (yzso-0r0sez | %S + 9A 5-60a ] ntel 28F010 ERASE AND PROGRAMMING PERFORMANCE Parameter Notes Min Typical Max Unit Chip Erase Time 1,3,4 2 30 Sec 1,2,4 4 25 * Sec NOTES: 1. Typicals are not guaranteed, but based on samples from production lots. Data taken at 25C, 12.0V Vpp. 2. Minimum byte programming time excluding system overhead is 16 usec (10 psec program + 6 psec write recovery), while maximum is 400 usec/byte (16 wsec x 25 loops allowed by algorithm). Max chip Programming time is specified lower than the worst case allowed by the programming algorithm since most bytes Program significantly faster than the worst case byte. 3. Excludes 00H programming prior to erasure. 4. Excludes system level overhead. | 5-6128F010 61- 202062 Addy dd, A0'Zh le 1adA, / AO AO'S >) A013, (ZR) X07) ino 4 f N HOO = Hor = onwa Niviva Niviva NiVLva aon (0a) viva NIN Z (71%) x01, HAAG, HO, XH3, XH3, ZOHR, | (30) ADT | 1373, +| 4373, | \ / (#M) #39 (3%) 19H, HaHa, ZOHO) 1aHO, >] (#9) #30 <5 L __ 5 ,, HAH3, | 73a, HAH, j=! Ly aim, HMH3, io baal ~| >| J \ J \ / (#3) #4M xv73, Taav, >| | (0%) AVAY, (2M) AVAV, ef AVA, y sass3yaqyv K NMOG-43MOd 9A NOLLVOISIS3A GNVNWOD ONINNVEOONd == VIVO SSJNGOV HOLVT GNVNNOO ABONVLS /ABONVLS Wvua0"d AaNIBA GNVWNOD WYY9OUd WYY90"d dN-L3S dN-y3aMod 2A WYeS0ud Figure 14. Alternate AC Waveforms for Programming Operations Alternative CE #-Controlled Write Timings also apply to erase operations. NOTE 5-62intel 28F010 ORDERING INFORMATION CTePefel lel Tel-[]zle TEMPERATURE en PACKAGE | ACCESS SPEED (ns) T = EXTENDED (-40C to +85C) P = 32-PIN PLASTIC DIP BLANK = COMMERCIAL (0C to +70C) N= 32-LEAD PLCC 120ns E = STANDARD 32~LEAD TSOP 150 ns F = REVERSE 32-LEAD TSOP 290207-20 VALID COMBINATIONS: P28F010-65 N28F010-65 TN28F010-90 P28F010-90 N28F010-90 P28F010-120 N28F010-120 P28F010-150 N28F010-150 E28F010-65 F28F010-65 TE28F010-90 E28F010-90 F28F010-90 TF28F010-90 E28F010-120 F28F010-120 E28F010-150 F28F010-150 ADDITIONAL INFORMATION Order Number ER-20, ETOX Flash Memory 294005 Technology ER-24, Intel Flash Memory 294008 ER-28, ETOX Ill Flash Memory 294012 Technology RR-60, ETOX Flash Memory 293002 Reliability Data Summary AP-316, Using Flash Memory for 292046 In-System Reprogrammable Nonvolatile Storage AP-325 Guide to Flash Memory 292059 Reprogramming REVISION HISTORY Number Description 007 Removed 200 ns Speed Bin Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000 Clarified AC and DC Test Conditions Added dimple to F TSOP Package Corrected Serpentine Layout 008 Corrected AC Waveforms Added Extended Temperature Options 009 Added 28F010-65 and 28F010-90 speeds Revised Symbols, i.e., CE, OE, etc. to CE#, OE#, etc.