DPD Demodulator for PA Linearization 550MHz to 1150MHz
IDT Zero-DistortionTM, Glitch-FreeTM DPD Receiver 1 Rev4 January 2014
IDTF1320NBGI
Datasheet
ARY DATASHEET
GENERAL DESCRIPTION
This document describes the specification for the
IDTF1320 Digital Pre-Distortion Demodulator for PA
linearization. This device is one of 2 variants to cover
common UTRA bands. See the Part# Matrix below for
details.
COMPETITIVE ADVANTAGE
In typical basestation transmitters a digital pre-distortion
loop is employed to improve the Transmitter
performance. The signal coming out of the PA is
sampled so that the I&Q data at Baseband can be pre-
distorted before being sent to the Tx DAC to counteract
the distortion inherent in the downstream PA. The signal
coupled from the PA is adjusted via a digital step
attenuator to a lower level and then sub-sampled at an
IF frequency of ~200 MHz which necessitates the need
for a highly linear demodulator to downmix to
quadrature IF from the Transmit frequency. By
sampling IF_I and IF_Q independently and then digitally
combining these signals, an effective doubling of the
sample rate can be achieved. Any distortion in this path
will degrade the performance of the DPD algorithm. By
utilizing an ultra-linear demodulator w/integrated DSA
such as the IDTF1320, the ACLR and/or power
consumption of the full Tx system can be improved
significantly.
D
DP
PD
D
f
fu
ul
ll
l
p
pa
at
th
h
A
AC
CL
LR
R:
:
1
1
d
dB
B
I
Ic
cc
c:
:
D
DP
PD
D
f
fu
un
nc
ct
ti
io
on
n
P
Po
ow
we
er
r
C
Co
on
ns
su
um
mp
pt
ti
io
on
n
4
40
0%
%
Z
Ze
er
ro
o-
-D
Di
is
st
to
or
rt
ti
io
on
nT
TM
M
D
De
em
mo
od
d
e
el
li
im
mi
in
na
at
te
es
s
2
2
I
IF
F
a
am
mp
ps
s
I
In
nt
te
eg
gr
ra
at
te
es
s
2
2
B
BP
PF
Fs
s,
,
2
2
B
Ba
al
lu
un
ns
s,
,
2
2
S
SP
P2
2T
Ts
s
G
Gl
li
it
tc
ch
h-
-F
Fr
re
ee
eT
TM
M
g
ga
ai
in
n
c
co
on
nt
tr
ro
ol
l
PART# MATRIX
5
5,
,6
6,
,8
8,
,1
12
2,
,1
13
3,
,
1
14
4,
,1
17
7
H
Hi
ig
gh
h
S
Si
id
de
e
o
or
r
L
Lo
ow
w
S
Si
id
de
e
1
1,
,2
2,
,3
3,
,4
4,
,9
9,
,1
10
0
7
7,
,2
21
1,
,
2
24
4,
,
3
38
8
H
Hi
ig
gh
h
S
Si
id
de
e
o
or
r
L
Lo
ow
w
S
Si
id
de
e
FEATURES (I OR Q PATH)
Wide flat performance IF BW
Wide RF and LO BWs (~ 0.8 GHz)
Ideal for Multi-Carrier Systems
D
Dr
ri
iv
ve
es
s
A
AD
DC
C
d
di
ir
re
ec
ct
tl
ly
y
Ultra linear
Low Noise Figure
Excellent ACLR performance
200 Ω output impedance
Fully integrated DPD demodulator
6
6x
x6
6
3
36
6
p
pi
in
n
p
pa
ac
ck
ka
ag
ge
e
Standby Mode w/Fast Recovery
ICC:
DEVICE BLOCK DIAGRAM
ORDERING INFORMATION
IFI
RF VCO
IBIAS
Bias
Control
STBY
IFQ
90O
DEC
CLK
SPI
CSb SDI
RFSW
RFIN_X
RFIN_Y
.
SPLIT
LOSW
LOIN_A LOIN_B
ISET
2
Glitch-FreeTM
Glitch-FreeTM