IRF3704ZSPBF - INTERNATIONAL RECTIFIER

www.irf.com 1

6/29/04

IRF3704ZPbF

IRF3704ZSPbF

IRF3704ZLPbF

HEXFET® Power MOSFET

Notes  through  are on page 12

Applications

Benefits

lLow RDS(on) at 4.5V VGS

lUltra-Low Gate Impedance

lFully Characterized Avalanche Voltage

and Current

lHigh Frequency Synchronous Buck

Converters for Computer Processor Power

lLead-Free

PD - 95463

D2Pak

IRF3704ZS

TO-220AB

IRF3704Z

TO-262

IRF3704ZL

VDSS RDS(on) max Qg

20V 7.9m:8.7nC

Absolute Maximum Ratings

Parameter Units

VDS Drain-to-Source Voltage V

VGS Gate-to-Source Voltage

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V

IDM Pulsed Drain

urrent

PD @TC = 25°C Maximum Power Dissipation W

PD @TC = 100°C Maximum Power Dissipation

Linear Derating Factor W/°C

TJ Operating Junction and °C

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds

Mountin

Torque, 6-32 or M3 screw

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case

––– 2.65 °C/W

RθCS Case-to-Sink, Flat Greased Surface

0.50 –––

RθJA Junction-to-Ambient

fi

––– 62

RθJA Junction-to-Ambient (PCB Mount)

––– 40

10 lbf

in (1.1N

300 (1.6mm from case)

-55 to + 175

0.38

Max.

260

± 20

IRF3704Z/S/LPbF

2www.irf.com

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– V

∆ΒVDSS

∆TJ Breakdown Voltage Temp. Coefficient ––– 0.014 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 6.5 7.9 mΩ

––– 9.1 11.1

VGS(th) Gate Threshold Voltage 1.65 2.1 2.55 V

∆VGS(th)

∆TJ Gate Threshold Voltage Coefficient ––– -5.6 ––– mV/°C

IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

gfs Forward Transconductance 48 ––– ––– S

QgTotal Gate Charge ––– 8.7 13

Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.9 –––

Qgs2 Post-Vth Gate-to-Source Charge ––– 1.1 ––– nC

Qgd Gate-to-Drain Charge ––– 2.3 –––

Qgodr Gate Charge Overdrive ––– 2.4 ––– See Fig. 16

Qsw Switch Charge (Qgs2 + Qgd)––– 3.4 –––

Qoss Output Charge ––– 5.6 ––– nC

td(on) Turn-On Delay Time ––– 8.9 –––

trRise Time ––– 38 –––

td(off) Turn-Off Delay Time ––– 11 ––– ns

tfFall Time ––– 4.2 –––

Ciss Input Capacitance ––– 1220 –––

Coss Output Capacitance ––– 390 ––– pF

Crss Reverse Transfer Capacitance ––– 190 –––

Avalanche Characteristics

Parameter Units

EAS

anc

nergy

IAR

anc

urrent



EAR

epet

anc

nergy

Diode Characteristics

Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– –––

(Body Diode) A

ISM Pulsed Source Current ––– ––– 260

(Bod

Diode)

c

VSD Diode Forward Voltage ––– ––– 1.0 V

trr Reverse Recovery Time ––– 11 17 ns

Qrr Reverse Recovery Charge ––– 2.3 3.5 nC

MOSFET symbol

VGS = 4.5V, ID = 17A

–––

VGS = 4.5V

Typ.

–––

ID = 17A

VGS = 0V

VDS = 10V

TJ = 25°C, IF = 17A, VDD = 10V

di/dt = 100A/µs

TJ = 25°C, IS = 17A, VGS = 0V

showing the

integral reverse

p-n junction diode.

VDS = VGS, ID = 250µA

VDS = 16V, VGS = 0V

VDS = 16V, VGS = 0V, TJ = 125°C

Clamped Inductive Load

VDS = 10V, ID = 17A

VDS = 10V, VGS = 0V

VDD = 10V, VGS = 4.5V

ID = 17A

VDS = 10V

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 21A

VGS = 20V

VGS = -20V

Conditions

5.7

Max.

ƒ = 1.0MHz

IRF3704Z/S/LPbF

www.irf.com 3

Fig 4. Normalized On-Resistance

vs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.1 110

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

60µs PULSE WIDTH

Tj = 25°C

3.0V

VGS

TOP 10V

9.0V

7.0V

5.0V

4.5V

4.0V

3.5V

BOTTOM 3.0V

0.1 110

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

60µs PULSE WIDTH

Tj = 175°C

3.0V

VGS

TOP 10V

9.0V

7.0V

5.0V

4.5V

4.0V

3.5V

BOTTOM 3.0V

3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

10.0

100.0

1000.0

ID, Drain-to-Source Current (Α)

VDS = 10V

60µs PULSE WIDTH

TJ = 25°C

TJ = 175°C

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 42A

VGS = 10V

IRF3704Z/S/LPbF

4www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

C, Capacitance (pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = C gs + Cgd, C ds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0 5 10 15 20 25

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 16V

VDS= 10V

ID= 17A

0.0 0.5 1.0 1.5 2.0

VSD, Source-toDrain Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

0 1 10 100

VDS , Drain-toSource Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY RDS(on)

100µsec

IRF3704Z/S/LPbF

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.

Case Temperature

Fig 10. Threshold Voltage vs. Temperature

25 50 75 100 125 150 175

TC , Case Temperature (°C)

ID , Drain Current (A)

LIMITED BY PACKAGE

-75 -50 -25 025 50 75 100 125 150 175 200

TJ , Temperature ( °C )

0.6

1.0

1.4

1.8

2.2

2.6

VGS(th) Gate threshold Voltage (V)

ID = 250µA

1E-006 1E-005 0.0001 0.001 0.01

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

Thermal Response ( Z thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)

0.920 0.000139

0.194 0.000602

0.538 0.001567

τJ

τ1

τ1τ2

τ2τ3

τ3

R1R2

R2R3

τC

Ci= τi/Ri

IRF3704Z/S/LPbF

6www.irf.com

D.U.T. V

3mA

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

Fig 13. Gate Charge Test Circuit

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

Fig 14a. Switching Time Test Circuit

Fig 14b. Switching Time Waveforms

VGS

VDS

90%

10%

td(on) td(off)

trtf

VGS

Pulse Width < 1µs

Duty Factor < 0.1%

VDD

VDS

D.U.T

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

100

120

140

EAS, Single Pulse Avalanche Energy (mJ)

TOP 5.6A

8.5A

BOTTOM 17A

IRF3704Z/S/LPbF

www.irf.com 7

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

=10V

Driver Gate Drive

D.U.T. I

Waveform

D.U.T. V

Waveform

Inductor Curent

D = P. W .

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



Fig 16. Gate Charge Waveform

Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

IRF3704Z/S/LPbF

8www.irf.com

Control FET

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the Rds(on) of the

MOSFET, but these conduction losses are only about

one half of the total losses.

Power losses in the control switch Q1 are given

by;

Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput

This can be expanded and approximated by;

loss =Irms

2×Rds(on )

()

+I×Qgd

×V

in ×f

⎛

⎝

⎜ ⎞

⎠

⎟ +I×Qgs2

×Vin ×f

⎛

⎝

⎜ ⎞

⎠

⎟

+Qg×Vg×f

()

+Qoss

2×Vin ×f

⎛

⎝ ⎞

⎠

This simplified loss equation includes the terms Qgs2

and Qoss which are new to Power MOSFET data sheets.

Qgs2 is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Qgs1 and Qgs2, can be seen from

Fig 16.

Qgs2 indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to Idmax at which time the drain voltage be-

gins to change. Minimizing Qgs2 is a critical factor in

reducing switching losses in Q1.

Qoss is the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Qoss is formed by the

parallel combination of the voltage dependant (non-

linear) capacitances Cds and Cdg when multiplied by

the power supply input buss voltage.

Synchronous FET

The power loss equation for Q2 is approximated

by;

loss =P

conduction +P

drive +P

output

loss =Irms

2×Rds(on)()

+Qg×Vg×f

()

+Qoss

2×Vin ×f

⎛

⎝

⎜ ⎞

⎠ +Qrr ×Vin ×f

(

)

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, Rds(on) is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Qoss and re-

verse recovery charge Qrr both generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and Vin. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Qgd/Qgs1 must be minimized to reduce the

potential for Cdv/dt turn on.

Power MOSFET Selection for Non-Isolated DC/DC Converters

Figure A: Qoss Characteristic

IRF3704Z/S/LPbF

www.irf.com 9

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

EXAMPLE:

IN THE ASSEMBLY LINE "C"

T HIS IS AN IRF1010

LOT CODE 1789

AS S E MB L E D ON WW 19, 1997 PART NUMBER

AS S E MB L Y

LOT CODE

DATE CODE

YEAR 7 = 1997

LINE C

WEEK 19

LOGO

RE CT IF IER

INTERNAT IONAL

Note: "P" in assembly line

position indicates "Lead-Free"

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

- B -

1.32 (.052)

1.22 (.048)

3X 0.55 (.022)

0.46 (.018)

2.92 (.115)

2.64 (.104)

4.69 (.185)

4.20 (.165)

3X 0.93 (.037)

0.69 (.027)

4.06 (.160)

3.55 (.140)

1.15 (.045)

MIN

6.47 (.255)

6.10 (.240)

3.78 (.149)

3.54 (.139)

- A -

10.54 (.415)

10.29 (.405)

2.87 (.113)

2.62 (.103)

15.24 (.600)

14.84 (.584)

14.09 (.555)

13.47 (.530)

3X 1.40 (.055)

1.15 (.045)

2.54 (.100)

0.36 (.014) M B A M

1 2 3

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.

2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

HEXFET

1- GATE

2- DRAIN

3- SOURCE

4- DRAIN

LEAD ASSIGNMENTS

IGBTs, CoPACK

1- GATE

2- COLLECTOR

3- EMITTER

4- COLLECTOR

IRF3704Z/S/LPbF

10 www.irf.com

Note: "P " in as s embly line

pos ition indicates "L ead-F ree"

F 530S

T H IS IS AN IR F 530S WIT H

LOT CODE 8024

AS S E MB L ED ON WW 02, 2000

IN T H E AS S E MB L Y L INE "L"

AS S E MB L Y

LOT CODE

INT E R NAT IONAL

R E CT IF IE R

LOGO

PART NUMBER

DATE CODE

YEAR 0 = 2000

WEEK 02

LINE L

F 530S

A = AS S E MB L Y S IT E CODE

WEEK 02

P = DE S IGN AT E S L E AD -F R E E

PRODUCT (OPTIONAL)

R E CT IF IE R

INT E R N AT IONAL

LOGO

LOT CODE

AS S E M B L Y

YEAR 0 = 2000

DATE CODE

PART NUMBE R

D2Pak Part Marking Information (Lead-Free)

D2Pak Package Outline

Dimensions are shown in millimeters (inches)

IRF3704Z/S/LPbF

www.irf.com 11

ASSEMBLY

LOT CODE

RECTIFIER

INTERNATIONAL

ASS EMBL ED ON WW 19, 1997

Note: "P" in as s embly line

position indicates "Lead-Free"

IN THE ASSEMBLY LINE "C" LOGO

THIS IS AN IRL3103L

LOT CODE 1789

E X AMP L E :

LINE C

DAT E CODE

WEEK 19

YE AR 7 = 1997

PART NUMBER

LOGO

LOT CODE

ASSEMBLY

INTERNATIONAL

RECTIFIER

PRODUCT (OPTIONAL)

P = DESIGNATES LEAD-FREE

A = ASSEMBLY SITE CODE

WEEK 19

YEAR 7 = 1997

DAT E CODE

TO-262 Part Marking Information

TO-262 Package Outline

IGBT

1- GATE

2- COLLECTOR

3- EMITTER

IRF3704Z/S/LPbF

12 www.irf.com

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 3/04

TO-220AB package is not recommended for Surface Mount Application.

TRR

FEED DIRECTION

1.85 (.073)

1.65 (.065)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

TRL

FEED DIRECTION

10.90 (.429)

10.70 (.421)

16.10 (.634)

15.90 (.626)

1.75 (.069)

1.25 (.049)

11.60 (.457)

11.40 (.449) 15.42 (.609)

15.22 (.601)

4.72 (.136)

4.52 (.178)

24.30 (.957)

23.90 (.941)

0.368 (.0145)

0.342 (.0135)

1.60 (.063)

1.50 (.059)

13.50 (.532)

12.80 (.504)

330.00

(14.173)

MAX.

27.40 (1.079)

23.90 (.941)

60.00 (2.362)

MIN.

30.40 (1.197)

MAX.

26.40 (1.039)

24.40 (.961)

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

D2Pak Tape & Reel Infomation

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting TJ = 25°C, L = 0.25mH, RG = 25Ω,

IAS = 17A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

 This is only applied to TO-220AB pakcage.

 This is applied to D2Pak, when mounted on 1" square PCB (FR-

4 or G-10 Material). For recommended footprint and soldering

techniques refer to application note #AN-994.

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 42A.

 Rθ is measured at TJ approximately 90°C

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/