8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface AD5424/AD5433/AD5445 Data Sheet FEATURES GENERAL DESCRIPTION 2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of 1 LSB for 12-bit DAC 10 MHz multiplying bandwidth 10 V reference input Extended temperature range: -40C to +125C 20-lead TSSOP and chip scale (4 mm x 4 mm) packages 8-, 10-, and 12-bit current output DACs Upgrades to AD7524/AD7533/AD7545 Pin-compatible 8-, 10-, and 12-bit DACs in chip scale Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Readback function 0.4 A typical power consumption The AD5424/AD5433/AD5445 1 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs utilize data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing with a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. While these devices are upgrades of the AD5424/AD5433/ AD5445 in multiplying bandwidth performance, they have a latched interface and cannot be used in transparent mode. APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming The AD5424 is available in small, 20-lead LFCSP and 16-lead TSSOP packages, while the AD5433/AD5445 DACs are available in small, 20-lead LFCSP and TSSOP packages. The EVAL-AD5445SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-333 evaluation board user guide. 1 U.S Patent No. 5,689,257. FUNCTIONAL BLOCK DIAGRAM VDD AD5424/ AD5433/ AD5445 POWER-ON RESET CS R/W VREF R RFB IOUT1 8-/10-/12-BIT R-2R DAC IOUT2 DAC REGISTER GND DB7/DB9/DB11 DB0 DATA INPUTS 03160-001 INPUT LATCH Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005-2011 Analog Devices, Inc. All rights reserved. AD5424/AD5433/AD5445 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 18 Applications....................................................................................... 1 Bipolar Operation....................................................................... 19 General Description ......................................................................... 1 Single-Supply Applications ....................................................... 20 Functional Block Diagram .............................................................. 1 Positive Output Voltage ............................................................. 20 Revision History ............................................................................... 2 Adding Gain................................................................................ 21 Specifications..................................................................................... 3 DACs Used as a Divider or Programmable Gain Element ... 21 Timing Characteristics..................................................................... 5 Reference Selection .................................................................... 22 Absolute Maximum Ratings............................................................ 6 Amplifier Selection .................................................................... 22 ESD Caution.................................................................................. 6 Parallel Interface......................................................................... 23 Pin Configurations and Function Descriptions ........................... 7 Microprocessor Interfacing....................................................... 23 Typical Performance Characteristics ........................................... 10 PCB Layout and Power Supply Decoupling................................ 24 Terminology ................................................................................ 17 Outline Dimensions ....................................................................... 25 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 26 REVISION HISTORY 12/12--Rev. B to Rev. C Changes to General Description Section ...................................... 1 Added Note 2 to Table 1 .................................................................. 4 Added EPAD Note to Table 4 and EPAD Note to Figure 4......... 7 Added EPAD Note to Table 5 and EPAD Note to Figure 6......... 8 Added EPAD Note to Table 6 and EPAD Note to Figure 8......... 9 Deleted the Evaluation Board for AD5424/AD5433/AD5445 Section and Power Supplies for Evaluation Board Section ....... 23 Deleted Figure 59; Renumbered Sequentially ............................ 24 Deleted Figure 60 and Figure 61................................................... 25 Changes to Ordering Guide .......................................................... 26 Deleted Figure 62 and Table 12; Renumbered Sequentially ..... 26 3/05--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Specifications.................................................................4 Changes to Figure 49...................................................................... 17 Changes to Figure 50...................................................................... 18 Changes to Figure 51, Figure 52, and Figure 54 ......................... 19 Added Microprocessor Interfacing Section ................................ 22 Added Figure 59 ............................................................................. 24 Added Figure 60 ............................................................................. 25 10/03--Initial Version: Revision 0 8/09--Rev. A to Rev. B Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 29 Rev. C | Page 2 of 28 Data Sheet AD5424/AD5433/AD5445 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: -40C to +125C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient 1 Output Leakage Current1 REFERENCE INPUT1 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code Zero Scale Code Full Scale DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Min Typ Max Unit Test Conditions 8 0.25 0.5 Bits LSB LSB Guaranteed monotonic 10 0.5 1 Bits LSB LSB Guaranteed monotonic 12 1 -1/+2 10 10 20 Bits LSB LSB mV ppm FSR/C nA nA 10 10 10 12 12 V k k 3 5 6 8 pF pF 5 8 8 1.7 0.6 VDD - 1 VDD - 0.5 Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Measured to 16 mV of full scale Measured to 4 mV of full scale Measured to 1 mV of full scale Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error 4 0.4 0.4 1 10 10 30 35 80 20 15 2 70 48 V V V V V V A pF MHz 60 70 120 40 30 ns ns ns ns ns nV-s dB dB Rev. C | Page 3 of 28 Guaranteed monotonic Data = 0x0000, TA = 25C, IOUT1 Data = 0x0000, T = -40C to +125C, IOUT1 Input resistance TC = -50 ppm/C Input resistance TC = -50 ppm/C VDD = 4.5 V to 5 V, ISOURCE = 200 A VDD = 2.5 V to 3.6 V, ISOURCE = 200 A VDD = 4.5 V to 5 V, ISINK = 200 A VDD = 2.5 V to 3.6 V, ISINK = 200 A VREF = 3.5 V; DAC loaded all 1s VREF = 3.5 V, RLOAD = 100 , DAC latch alternately loaded with 0s and 1s Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s, VREF = 3.5 V Reference = 1 MHz Reference = 10 MHz AD5424/AD5433/AD5445 Parameter Output Capacitance IOUT1 Data Sheet Min IOUT2 Digital Feedthrough Analog THD Digital THD 50 kHz fOUT Output Noise Spectral Density 2 SFDR Performance (Wide Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD Typ Max Unit Test Conditions 12 25 22 10 1 17 30 25 12 pF pF pF pF nV-s All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Clock = 10 MHz, VREF = 3.5 V 81 dB 65 25 dB nVHz 55 63 65 dB dB dB 50 60 62 dB dB dB AD5445, VREF = 3.5 V 73 80 82 dB dB dB 70 75 80 dB dB dB AD5445, VREF = 3.5 V 65 72 dB dB 51 65 dB dB 2.5 0.4 Power Supply Sensitivity 1 2 @ 1 kHz AD5445, VREF = 3.5 V 5.5 0.6 5 0.001 V A A %/% Guaranteed by design, not subject to production test. Specification measured with OP27. Rev. C | Page 4 of 28 TA = 25C, logic inputs = 0 V or VDD Logic inputs = 0 V or VDD, T= -40C to +125C VDD = 5% Data Sheet AD5424/AD5433/AD5445 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: -40C to +125C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 VDD = 4.5 V to 5.5 V 0 0 10 6 0 5 7 10 20 5 10 Unit ns min ns min ns min ns min ns min ns min ns min ns typ ns max ns typ ns max Test Conditions/Comments R/W to CS setup time R/W to CS hold time CS low time (write cycle) Data setup time Data hold time R/W high to CS low CS min high time Data access time Bus relinquish time Guaranteed by design, not subject to production test. R/W t2 t1 t2 t6 t7 CS t3 t4 DATA t5 DATA VALID t9 t8 DATA VALID Figure 2. Timing Diagram Rev. C | Page 5 of 28 03160-002 1 VDD = 2.5 V to 5.5 V 0 0 10 6 0 5 9 20 40 5 10 AD5424/AD5433/AD5445 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Inputs and Output 1 Operating Temperature Range Extended Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP JA Thermal Impedance 20-Lead TSSOP JA Thermal Impedance 20-Lead LFCSP JA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) 1 Rating -0.3 V to +7 V -12 V to +12 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +150C 150C 150C/W 143C/W 135C/W 300C 235C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Overvoltages at DBx, CS, and R/W, are clamped by internal diodes. Rev. C | Page 6 of 28 Data Sheet AD5424/AD5433/AD5445 IOUT2 IOUT1 RFB VREF VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IOUT1 1 16 RFB IOUT2 2 15 VREF 14 VDD 13 R/W 12 CS DB5 6 11 DB0 (LSB) DB4 7 10 DB1 DB3 8 9 DB2 (Not to Scale) GND DB7 DB6 DB5 DB4 1 2 3 4 5 PIN 1 INDICATOR AD5424 TOP VIEW 15 14 13 12 11 R/W CS NC NC NC 6 7 8 9 10 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 03160-005 DB6 5 AD5424 DB3 DB2 DB1 DB0 NC DB7 4 03160-004 GND 3 20 19 18 17 16 Figure 4. AD5424 Pin Configuration (LFCSP) Figure 3. AD5424 Pin Configuration (TSSOP) Table 4. AD5424 Pin Function Descriptions Pin No. TSSOP 1 2 3 4 to 11 12 LFCSP 19 20 1 2 to 9 10 to 13 14 Mnemonic IOUT1 IOUT2 GND DB7 to DB0 NC CS 13 15 R/W 14 15 16 16 17 18 VDD VREF RFB Not applicable EPAD Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground. Parallel Data Bits 7 to 0. No Internal Connection. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. The exposed pad should be connected to ground. Rev. C | Page 7 of 28 Data Sheet IOUT1 1 20 RFB IOUT2 IOUT1 RFB VREF VDD AD5424/AD5433/AD5445 IOUT2 2 19 VREF 20 19 18 17 16 GND 3 18 VDD DB9 4 17 R/W 16 CS 15 NC DB6 7 14 NC DB5 8 13 DB0 (LSB) DB4 9 12 DB1 DB3 10 11 DB2 PIN 1 INDICATOR AD5433 TOP VIEW 15 14 13 12 11 R/W CS NC NC DB0 6 7 8 9 10 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 5. AD5433 Pin Configuration (TSSOP) 03160-007 NC = NO CONNECT 1 2 3 4 5 DB5 DB4 DB3 DB2 DB1 DB7 6 AD5433 (Not to Scale) 03160-006 DB8 5 GND DB9 DB8 DB7 DB6 Figure 6. AD5433 Pin Configuration (LFCSP) Table 5. AD5433 Pin Function Descriptions Pin No. TSSOP 1 2 3 4 to 13 14, 15 16 LFCSP 19 20 1 2 to 11 12, 13 14 Mnemonic IOUT1 IOUT2 GND DB9 to DB0 NC 17 15 R/W 18 19 20 Not applicable 16 17 18 VDD VREF RFB EPAD CS Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground. Parallel Data Bits 9 to 0. Not Internally Connected. Chip Select Input. Active low. Use in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. The exposed pad should be connected to ground. Rev. C | Page 8 of 28 AD5424/AD5433/AD5445 IOUT1 1 20 RFB IOUT2 IOUT1 RFB VREF VDD Data Sheet IOUT2 2 19 VREF 20 19 18 17 16 GND 3 18 VDD DB11 4 17 R/W 16 CS 15 DB0 (LSB) DB8 7 14 DB1 DB7 8 13 DB2 DB6 9 12 DB3 DB5 10 11 DB4 PIN 1 INDICATOR AD5445 TOP VIEW 15 14 13 12 11 R/W CS DB0 DB1 DB2 6 7 8 9 10 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 7. AD5445 Pin Configuration (TSSOP) 03160-009 AD5445 (Not to Scale) 1 2 3 4 5 DB7 DB6 DB5 DB4 DB3 DB9 6 03160-008 DB10 5 GND DB11 DB10 DB9 DB8 Figure 8. AD5445 Pin Configuration (LFCSP) Table 6. AD5445 Pin Function Descriptions Pin No. TSSOP 1 2 3 4 to 15 16 LFCSP 19 20 1 2 to 13 14 Mnemonic IOUT1 IOUT2 GND DB11 to DB0 CS 17 15 R/W 18 19 20 16 17 18 VDD VREF RFB Not applicable EPAD Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Parallel Data Bits 11 to 0. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. The exposed pad should be connected to ground. Rev. C | Page 9 of 28 AD5424/AD5433/AD5445 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 TA = 25C VREF = 10V VDD = 5V 0.10 0.05 0.05 DNL (LSB) 0.10 0 -0.05 -0.05 -0.10 -0.10 -0.15 -0.15 -0.20 50 100 150 200 250 CODE -0.20 0 50 200 250 Figure 12. DNL vs. Code (8-Bit DAC) 0.5 TA = 25C VREF = 10V VDD = 5V 0.4 0.3 0.2 0.2 0.1 0.1 DNL (LSB) 0.3 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 200 400 600 800 1000 CODE -0.5 03160-011 -0.5 0 TA = 25C VREF = 10V VDD = 5V 0.4 0 200 400 600 800 1000 CODE 03160-014 0.5 Figure 13. DNL vs. Code (10-Bit DAC) Figure 10. INL vs. Code (10-Bit DAC) 1.0 1.0 TA = 25C VREF = 10V VDD = 5V 0.8 0.6 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 500 1000 1500 2000 2500 3000 3500 CODE 4000 03160-012 -0.4 0 TA = 25C VREF = 10V VDD = 5V 0.8 -1.0 0 500 1000 1500 2000 2500 3000 3500 CODE Figure 14. DNL vs. Code (12-Bit DAC) Figure 11. INL vs. Code (12-Bit DAC) Rev. C | Page 10 of 28 4000 03160-015 INL (LSB) 150 CODE Figure 9. INL vs. Code (8-Bit DAC) INL (LSB) 100 03160-013 0 0 TA = 25C VREF = 10V VDD = 5V 0.15 03160-010 INL (LSB) 0.15 Data Sheet AD5424/AD5433/AD5445 0.6 2.0 0.5 1.5 0.4 0.2 LSB MAX INL 0.3 INL (LSB) TA = 25C VREF = 0V VDD = 3V MAX INL 1.0 TA = 25C VDD = 5V 0.1 0.5 MAX DNL 0 -0.5 0 MIN INL -1.0 -0.1 MIN DNL MIN INL 2 3 4 5 6 7 8 9 10 REFERENCE VOLTAGE -2.0 0.5 03160-016 -0.3 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VBIAS (V) Figure 15. INL vs. Reference Voltage, AD5445 03160-019 -1.5 -0.2 Figure 18. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 4 -0.40 TA = 25C VDD = 5V -0.45 TA = 25C VREF = 2.5V VDD = 3V 3 MAX DNL 2 MAX INL 1 LSB DNL (LSB) -0.50 -0.55 0 -1 -2 -0.60 MIN DNL MIN DNL MIN INL -3 -0.65 2 3 4 5 6 7 8 9 10 REFERENCE VOLTAGE -5 03160-017 -0.70 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 5 0.5 4 0.4 0.3 VDD = 5V TA = 25C VREF = 0V VDD = 3V AND 5V GAIN ERROR 0.2 VOLTAGE (mV) 2 1 0 VDD = 2.5V -1 0.1 0 -0.1 OFFSET ERROR -0.2 -2 -0.3 -3 VREF = 10V -5 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 120 140 -0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VBIAS (V) Figure 20. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 Figure 17. Gain Error vs. Temperature Rev. C | Page 11 of 28 03160-021 -0.4 -4 03160-018 ERROR (mV) 0.4 VBIAS (V) Figure 16. DNL vs. Reference Voltage, AD5445 3 0.2 03160-020 -4 AD5424/AD5433/AD5445 Data Sheet 0.5 8 0.4 7 0.3 6 GAIN ERROR 0.1 CURRENT (mA) VOLTAGE (mV) 0.2 0 -0.1 OFFSET ERROR -0.2 5 VDD = 5V 4 3 2 TA = 25C VREF = 2.5V VDD = 3V AND 5V VDD = 2.5V -0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VDD = 3V 1 2.0 VBIAS (V) 0 03160-022 -0.4 Figure 21. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE (V) 03160-025 -0.3 Figure 24. Supply Current vs. Logic Input Voltage (Driving DB0 to DB11, All Other Digital Inputs qt Supplies) 3 1.6 TA = 25C VREF = 0V VDD = 5V 2 MAX INL 1.4 1.2 IOUT1 VDD 5V IOUT LEAKAGE (nA) LSB 1 MAX DNL 0 -1 1.0 IOUT1 VDD 3V 0.8 0.6 0.4 -2 0.2 MIN INL 1.5 2.0 2.5 VBIAS (V) 0 -40 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 22. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 Figure 25. IOUT1 Leakage Current vs. Temperature 4 0.50 TA = 25C VREF = 2.5V VDD = 5V 3 0.45 0.40 MAX DNL 2 VDD = 5V 0.35 CURRENT (A) 1 0 MAX INL -1 MIN DNL -2 ALL 0s 0.30 ALL 1s 0.25 0.20 VDD = 2.5V 0.15 -3 MIN INL ALL 1s ALL 0s 0.10 -4 1.0 1.5 2.0 VBIAS (V) 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 26. Supply Current vs. Temperature Figure 23. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 Rev. C | Page 12 of 28 140 03160-027 0.05 -5 0.5 03160-024 LSB -20 03160-026 1.0 03160-023 -3 0.5 MIN DNL Data Sheet AD5424/AD5433/AD5445 14 3 TA = 25C LOADING ZS TO FS TA = 25C VDD = 5V AD5445 12 VDD = 5V 0 GAIN (dB) 8 6 -3 VDD = 3V 2 1 10 100 1k 10k 100k 1M 10M -9 10k 03160-028 0 100M FREQUENCY (Hz) 0.045 ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 10 100 1k 10M 0x7FF TO 0x800 VDD = 5V OUTPUT VOLTAGE (V) 0.035 TA = 25C VDD = 5V VREF = 3.5V INPUT CCOMP = 1.8pF AD8038 AMPLIFIER AD5445 DAC 10k 100k 1M 10M 0.030 0.025 VDD = 3V 0.020 0.015 0x800 TO 0x7FF 0.010 VDD = 3V 0.005 0 -0.005 100M FREQUENCY (Hz) VDD = 5V -0.010 0 20 40 60 80 100 120 140 160 180 200 TIME (ns) Figure 31. Midscale Transition, VREF = 0 V Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code -1.68 0.2 TA = 25C VREF = 3.5V AD8038 AMPLIFIER CCOMP = 1.8pF 0x7FF TO 0x800 -1.69 VDD = 5V 0 OUTPUT VOLTAGE (V) -1.70 -0.2 -0.4 TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER AD5445 DAC -0.6 10 100 -1.72 VDD = 3V -1.73 VDD = 5V -1.74 VDD = 3V -1.76 0x800 TO 0x7FF -0.8 1 -1.71 -1.75 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 03160-030 GAIN (dB) 100M TA = 25C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF 0.040 ALL OFF 1 1M Figure 30. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor 03160-029 GAIN (dB) TA = 25C LOADING ZS TO FS 100k FREQUENCY (Hz) Figure 27. Supply Current vs. Update Rate 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 VREF = 2V, AD8038 CC 1.47pF VREF = 2V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1.47pF VREF = 3.51V, AD8038 CC 1.8pF 03160-031 -6 VDD = 2.5V 03160-032 4 -1.77 Figure 29. Reference Multiplying Bandwidth--All 1s Loaded 0 20 40 60 80 100 120 140 160 TIME (ns) Figure 32. Midscale Transition, VREF = 3.5 V Rev. C | Page 13 of 28 180 200 03160-033 IDD (mA) 10 AD5424/AD5433/AD5445 1.8 Data Sheet 100 TA = 25C MCLK = 1MHz 1.6 80 VIH 1.2 SFDR (dB) 1.0 VIL 0.8 MCLK = 200kHz 60 MCLK = 0.5MHz 40 0.6 TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5445 20 0.2 3.0 3.5 4.0 VOLTAGE (V) 4.5 5.0 5.5 0 03160-062 0 2.5 0 20 40 60 80 140 160 180 200 90 20 TA = 25C VDD = 3V AMP = AD8038 0 80 MCLK = 5MHz 70 -20 MCLK = 10MHz 60 SFDR (dB) -40 -60 50 MCLK = 25MHz 40 30 FULL SCALE -80 20 ZERO SCALE -100 TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5445 10 0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 0 03160-034 -120 100 200 300 400 500 600 700 800 900 1000 fOUT (kHz) 03160-037 PSRR (dB) 120 Figure 36. Wideband SFDR vs. fOUT Frequency Figure 33. Threshold Voltages vs. Supply Voltage Figure 37. Wideband SFDR vs. fOUT Frequency Figure 34. Power Supply Rejection vs. Frequency 0 -60 TA = 25C VDD = 3V VREF = 3.5V p-p -65 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES -10 -20 -30 SFDR (dB) -70 -75 -40 -50 -60 -80 -70 -85 -80 -90 -90 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 03160-035 THD + N (dB) 100 fOUT (kHz) 03160-036 0.4 0 2 4 6 8 10 12 FREQUENCY (MHz) Figure 38. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 35. THD and Noise vs. Frequency Rev. C | Page 14 of 28 03160-038 THRESHOLD VOLTAGE (V) 1.4 Data Sheet AD5424/AD5433/AD5445 0 20 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES -10 -20 0 -20 -30 -40 SFDR (dB) SFDR (dB) TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES -50 -60 -40 -60 -70 -80 -80 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) -120 50 03160-039 -100 80 90 100 110 120 130 140 150 Figure 42. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz 0 0 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES -10 -20 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES -10 -20 -30 -30 -40 -40 (dB) -50 -50 -60 -60 -70 -70 -80 -80 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) 03160-040 0 -100 200 300 350 400 450 500 550 600 650 700 FREQUENCY (kHz) Figure 40. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz Figure 43. Narrow-Band IMD, fOUT = 400 kHz, 500 kHz, Clock = 10 MHz 0 0 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES -10 -20 -20 -40 (dB) -30 -40 -50 -50 -60 -70 -70 -80 -80 -90 -90 350 400 450 500 550 FREQUENCY (kHz) 600 650 700 750 03160-041 -60 300 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES -10 -30 -100 250 250 03160-043 -90 -90 Figure 41. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz -100 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (kHz) Figure 44. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz Rev. C | Page 15 of 28 03160-044 SFDR (dB) 70 FREQUENCY (kHz) Figure 39. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz SFDR (dB) 60 03160-042 -90 AD5424/AD5433/AD5445 Data Sheet 0 0 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES -10 -20 -30 -30 -40 -40 (dB) -50 -50 -60 -60 MCLK 10MHz VDD 5V -70 -70 -80 -80 -90 -100 20 25 30 35 40 45 50 55 60 65 70 FREQUENCY (kHz) 03160-045 -90 -100 Figure 45. Narrow-Band IMD, fOUT = 40 kHz, 50 kHz, Clock = 10 MHz TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES -20 -30 -50 -60 -70 -80 -90 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 03160-046 (dB) -40 -100 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) Figure 47. Wideband IMD, fOUT = 60 kHz, 50 kHz, Clock = 10 MHz 0 -10 0 Figure 46. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz Rev. C | Page 16 of 28 03160-047 (dB) -20 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES -10 Data Sheet AD5424/AD5433/AD5445 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled through the device to show up as noise on the IOUT pins and subsequently in the following circuitry. This noise is called digital feedthrough. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB maximum over the operating temperature range ensures monotonicity. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1, or IOUT2, to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 resistor to ground. The settling time specification includes the digital delay from the CS rising edge to the full-scale output change. Digital-to-Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA seconds or nV seconds, depending upon whether the glitch is measured as a current or voltage signal. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. THD = 20 log (V2 2 + V3 2 +V4 2 + V5 2 ) V1 Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa - fb and 2fb - fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is measured by the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fS/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case, 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Rev. C | Page 17 of 28 AD5424/AD5433/AD5445 Data Sheet THEORY OF OPERATION The AD5424, AD5433, and AD5445 are 8-, 10-, and 12-bit current output DACs consisting of a standard inverting R-2R ladder configuration. A simplified diagram for the 8-bit AD5424 is shown in Figure 48. The matching feedback resistor RFB has a value of R. The value of R is typically 10 k (minimum 8 k and maximum 12 k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of resistance value R. The DAC output (IOUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node. R R 2R 2R 2R S1 S2 S3 S8 2R R RFBA IOUT1 These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal digital logic to drive the DAC switches' on and off states. These DACs are also designed to accommodate ac reference input signals in the range of -10 V to +10 V. Table 7 shows the relationship between digital code and expected output voltage for unipolar operation (AD5424, 8-bit device). 03160-048 IOUT2 DAC DATA LATCHES AND DRIVERS Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. With a fixed 10 V reference, the circuit shown in Figure 49 gives a unipolar 0 V to -10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. VREF 2R D = 0 to 255 (8-bit AD5424) = 0 to 1023 (10-bit AD5433) = 0 to 4095 (12-bit AD5445) Table 7. Unipolar Code Table Figure 48. Simplified Ladder Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, 4-quadrant multiplication in bipolar mode or in single-supply modes of operation. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity. Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 VDD R2 RFB VDD CIRCUIT OPERATION Unipolar Mode VREF VREF R1 Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 49. When an output amplifier is connected in unipolar mode, the output voltage is given by VOUT = -VREF x Analog Output (V) -VREF (255/256) -VREF (128/256) = -VREF/2 VREF (1/256) VREF (0/256) = 0 D 2n AD5424/ AD5433/ AD5445 R/W CS IOUT1 C1 A1 IOUT2 VOUT = 0 TO -VREF GND AGND DATA INPUTS NOTES: 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 49. Unipolar Operation Rev. C | Page 18 of 28 03160-049 R where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. Data Sheet AD5424/AD5433/AD5445 R3 20k R2 VDD VDD R1 VREF AD5424/ AD5433/ AD5445 R/W CS RFB C1 IOUT1 R4 10k A1 IOUT2 A2 VOUT = -VREF TO +VREF GND AGND DATA INPUTS NOTES: 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. 03160-050 VREF 10V R5 20k Figure 50. Bipolar Operation (4-Quadrant Multiplication) BIPOLAR OPERATION Stability In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors, as shown in Figure 50. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage, results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF). In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as closely as possible and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in closed-loop applications. VOUT = (V REF x D / 2 n -1 ) - V REF where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. An optional compensation capacitor, C1, can be added in parallel with RFB for stability, as shown in Figure 49 and Figure 50. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for compensation. D = 0 to 255 (8-bit AD5424) = 0 to 1023 (10-bit AD5433) = 0 to 4095 (12-bit AD5445) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 8 shows the relationship between digital code and the expected output voltage for bipolar operation (AD5424, 8-bit device). Table 8. Bipolar Code Table Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (127/128) 0 -VREF (127/128) -VREF (128/128) Rev. C | Page 19 of 28 AD5424/AD5433/AD5445 Data Sheet VDD SINGLE-SUPPLY APPLICATIONS R1 R2 Current Mode Operation RFB VIN IOUT1 Figure 52. Single-Supply Voltage-Switching Mode Operation VBIAS should be a low impedance source capable of sinking and sourcing all possible variations in current at the IOUT2 terminal. VDD DAC C1 IOUT1 A1 IOUT2 VOUT GND POSITIVE OUTPUT VOLTAGE 03160-051 VBIAS NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same sourcedrain drive voltage. As a result, there on resistance differs, which degrades the linearity of the DAC. See Figure 18 to Figure 23. Also, VIN must not go negative by more than 0.3 V; otherwise, an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost. Figure 51. Single-Supply Current Mode Operation It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same sourcedrain drive voltage. As a result, there on resistance differs and the linearity of the DAC degrades. Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5 V respectively, as shown in Figure 53. VDD = 5V ADR03 VOUT VIN GND +5V VDD -2.5V Voltage Switching Mode of Operation Figure 52 shows these DACs operating in the voltage-switching mode. The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. The output from the DAC is a voltage at a constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. Therefore, the voltage input should be driven from a low impedance source. C1 RFB IOUT1 VREF IOUT2 VOUT = 0V TO +2.5V GND -5V Rev. C | Page 20 of 28 NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY. 2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. Figure 53. Positive Voltage Output with Minimum of Components 03160-053 VREF VOUT NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. VOUT = VBIAS to VOUT = 2VBIAS - VIN VIN A1 VREF GND As D varies from 0 to 255 (AD5424), 0 to 1023 (AD5433), or 0 to 4095 (AD5445), the output voltage varies from RFB DAC IOUT2 VOUT = [D x (RFB/RDAC) x (VBIAS - VIN)] + VBIAS VDD VDD 03160-052 The current mode circuit in Figure 51 shows a typical circuit for operation with a single 2.5 V to 5 V supply. IOUT2 and therefore IOUT1 is biased positive by the amount applied to VBIAS. In this configuration, the output voltage is given by Data Sheet AD5424/AD5433/AD5445 ADDING GAIN In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier or it can be achieved in a single stage. It is important to consider the effect of the temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients and results in larger gain temperature coefficient errors. Instead, the circuit shown in Figure 54 is a recommended method of increasing the gain of the circuit. R1, R2, and R3 should have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains greater than 1 are required. As D is reduced, the output voltage increases. For small values of D, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. For example, in the circuit shown in Figure 55, an 8-bit DAC driven with the binary code 0x10 (00010000), that is, 16 decimal, should cause the output voltage to be 16 x VIN. However, if the DAC has a linearity specification of 0.5 LSB, then D can in fact have a weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage falls in the range 15.5 VIN to 16.5 VIN--an error of 3% even though the DAC itself has a maximum error of 0.2%. VDD VIN RFB VDD VDD IOUT1 VREF IOUT2 R1 VIN VREF 8-/10-/12-BIT DAC RFB GND C1 IOUT1 IOUT2 VOUT VOUT R3 GND NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. GAIN = R2 + R3 R2 R2R3 R1 = R2 + R3 NOTE: ADDITIONAL PINS OMITTED FOR CLARITY Figure 54. Increasing the Gain of the Current Output DAC DACS USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT Current steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor, as shown in Figure 55, then the output voltage is inversely proportional to the digital input fraction, D. For D = 1 - 2-n the output voltage is Figure 55. Current-Steering DAC Used as a Divider or Programmable Gain Element 03160-054 R2 03160-055 VDD DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Since only a fraction, D, of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows: Output Error Voltage due to DAC Leakage = (Leakage x R)/D where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k, and a gain (that is, 1/D) of 16, the error voltage is 1.6 mV. VOUT = -VIN/D = -VIN/(1 - 2-n) Rev. C | Page 21 of 28 AD5424/AD5433/AD5445 Data Sheet Table 9. Suitable ADI Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5 5 2.5 2.5 3 3 2.5 5 2.5 5 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.10 0.10 0.10 0.10 0.04 0.04 0.16 0.10 Temp Drift (ppm/C) 3 9 3 9 3 9 3 9 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.8 0.8 0.12 0.12 Output Noise (V p-p) 20 20 10 10 6 6 10 10 3.5 8 5 8 Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23 Table 10. Suitable ADI Precision Op Amps Part No. OP97 OP1177 AD8551 AD8603 AD8628 Supply Voltage (V) 2 to 20 2.5 to 15 2.7 to 5 1.8 to 6 2.7 to 6 VOS (Max) (V) 25 60 5 50 5 IB (Max) (nA) 0.1 2 0.05 0.001 0.1 0.1 Hz to 10 Hz Noise (V p-p) 0.5 0.4 1 2.3 0.5 Supply Current (A) 600 500 975 50 850 Package SOIC-8 MSOP, SOIC-8 MSOP, SOIC-8 TSOT TSOT, SOIC-8 Table 11. Suitable ADI High Speed Op Amps Part No. AD8065 AD8021 AD8038 AD9631 Supply Voltage (V) 5 to 24 2.5 to 12 3 to 12 3 to 6 BW at ACL (MHz) 145 490 350 320 Slew Rate (V/s) 180 120 425 1300 VOS (Max) (V) 1500 1000 3000 10000 IB (Max) (nA) 6000 10500 750 7000 Package SOIC-8, SOT-23, MSOP SOIC-8, MSOP SOIC-8, SC70-5 SOIC-8 REFERENCE SELECTION AMPLIFIER SELECTION When selecting a reference for use with the AD5424/AD5433/ AD5445 family of current output DACs, pay attention to the reference's output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0C to 50C dictates that the maximum system drift with temperature should be less than 78 ppm/C. The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of the DAC) of the circuit. A change in the noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the DAC to be nonmonotonic. In general, the input offset voltage should be <1/4 LSB to ensure monotonic behavior when stepping through codes. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/C. By choosing a precision reference with low output temperature coefficient this error source can be minimized. Table 9 suggests some references available from Analog Devices that are suitable for use with this range of current output DACs. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing into the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent significant errors in 12-bit applications. Common-mode rejection of the op amp is important in voltageswitching circuits, since it produces a code dependent error at the voltage output of the circuit. Most op amps have adequate common mode rejection for use at 8-, 10-, and 12-bit resolution. Rev. C | Page 22 of 28 Data Sheet AD5424/AD5433/AD5445 Provided the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low inputs capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. There is a large range of single-supply amplifiers available from Analog Devices. 8xC51-to-AD5424/AD5433/AD5445 Interface Figure 57 shows the interface between the AD5424/AD5433/ AD5445 and the 8xC51 family of DSPs. To facilitate external data memory access, the address latch enable (ALE) mode is enabled. The low byte of the address is latched with this output pulse during access to external memory. AD0 to AD7 are the multiplexed low order addresses and data bus and require strong internal pull-ups when emitting 1s. During access to external memory, A8 to A15 are the high order address bytes. Since these ports are open drained, they also require strong internal pull-ups when emitting 1s. A8 TO A15 ADDRESS BUS PARALLEL INTERFACE A read event takes place when R/W is held high and CS is brought low. New data is loaded from the DAC register back to the input register and out onto the data line where it can be read back to the controller for verification or diagnostic purposes. MICROPROCESSOR INTERFACING ADSP-21xx-to-AD5424/AD5433/AD5445 Interface Figure 56 shows the AD5424/AD5433/AD5445 interfaced to the ADSP-21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD5424/ AD5433/AD5445 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family user's manual for details). ALE R/W DB0 TO DB11 8-BIT LATCH AD0 TO AD7 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 57. 8xC51-to-AD5424/AD5433/AD5445 Interface ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface Figure 58 shows a typical interface between the AD5424/ AD5433/AD5445 and the ADSP-BF5xx family of DSPs. The asynchronous memory write cycle of the processor drives the digital inputs of the DAC. The AMSx line is actually four memory select lines. Internal ADDR lines are decoded into AMS3-0, these lines are then inserted as chip selects. The rest of the interface is a standard handshaking operation. ADDR1 TO ADRR19 ADDRESS BUS AD5424/ AD5433/ AD5445* ADSP-BF5xx AMSx AD5424/ AD5433/ AD5445* ADDRESS DECODER CS WR ADDRESS BUS ADSP-21xx* DMS ADDRESS DECODER ADDRESS DECODER CS AWE R/W DB0 TO DB11 CS WR R/W DATA 0 TO DATA 23 DATA BUS DB0 TO DB11 *ADDITIONAL PINS OMITTED FOR CLARITY DATA 0 TO DATA 23 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY 03160-056 Figure 58. ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface Figure 56. ADSP21xx-to-AD5424/AD5433/AD5445 Interface Rev. C | Page 23 of 28 03160-057 ADDR0 TO ADRR13 AD5424/ AD5433/ AD5445* 8051* 03160-063 Data is loaded to the AD5424/AD5433/AD5445 in the format of an 8-, 10-, or 12-bit parallel word. Control lines CS and R/W allow data to be written to or read from the DAC register. A write event takes place when CS and R/W are brought low, data available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data-word to the DAC register. The DAC latches are not transparent, thus a write sequence must consist of a falling and rising edge on CS to ensure that data is loaded to the DAC register and its analog equivalent is reflected on the DAC output. AD5424/AD5433/AD5445 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5424/AD5433/AD5445 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply, located as close to the package as possible and ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible. Table 12. Overview of AD54xx and AD55xx Devices Part No. AD5424 AD5426 AD5428 AD5429 AD5450 AD5432 AD5433 AD5439 AD5440 AD5451 AD5443 AD5444 AD5415 AD5405 AD5445 AD5447 AD5449 AD5452 AD5446 AD5453 AD5553 AD5556 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 Resolution 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 No. DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2 INL(LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.25 1 0.5 1 1 1 1 1 0.5 1 2 1 1 1 1 2 2 2 2 Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Package RU-16, CP-20 RM-10 RU-20 RU-10 RJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 RJ-8 RM-10 RM-8 RU-24 CP-40 RU-20, CP-20 RU-24 RU-16 RJ-8, RM-8 RM-8 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38 Rev. C | Page 24 of 28 Features 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 50 MHz serial interface 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width Data Sheet AD5424/AD5433/AD5445 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 59. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 60. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. C | Page 25 of 28 0.75 0.60 0.45 AD5424/AD5433/AD5445 Data Sheet 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BCS SQ 0.50 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD (BOTTOM VIEW) 5 10 1.00 0.85 0.80 12 MAX SEATING PLANE 0.75 0.60 0.50 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 012508-B TOP VIEW 6 11 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 61. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5424YRU AD5424YRU-REEL AD5424YRU-REEL7 AD5424YRUZ AD5424YRUZ-REEL AD5424YRUZ-REEL7 AD5424YCPZ AD5424YCPZ-REEL7 AD5433YRU AD5433YRU-REEL AD5433YRU-REEL7 AD5433YRUZ AD5433YRUZ-REEL AD5433YRUZ-REEL7 AD5433YCPZ AD5445YRU AD5445YRU-REEL AD5445YRU-REEL7 AD5445YRUZ AD5445YRUZ-REEL AD5445YRUZ-REEL7 AD5445YCPZ EVAL-AD5445EBZ 1 Resolution (Bits) 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 12 12 12 12 12 12 12 INL (LSB) 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1 1 1 1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Z = RoHS Compliant Part. Rev. C | Page 26 of 28 Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead LFCSP_VQ Evaluation Board Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20-1 CP-20-1 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 CP-20-1 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 CP-20-1 Data Sheet AD5424/AD5433/AD5445 NOTES Rev. C | Page 27 of 28 AD5424/AD5433/AD5445 Data Sheet NOTES (c)2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03160-0-12/11(C) Rev. C | Page 28 of 28