MM74HCT373WM_NL - Fairchild Semiconductor

Februa ry 198 4

Revised May 2005

MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop

MM74HCT373 • MM74HCT374

3-STATE Oct al D-Type Latch •

3-STATE Octal D-Type Flip-Flop

General Descript ion

The MM74HCT373 octal D-type latches and

MM74HCT374 Octal D-type flip flops advanced silicon-gate

CMOS techno logy, whi ch provides the inher ent benefits of

low power co nsumpti on and wide po wer supp ly range, but

are LS- TTL input and output char acteristic & p in-out com -

patible. The 3-STATE outputs are capable of driving 15 LS-

TTL loads. All inputs are protected from damage due to

static discharge by internal diodes to VCC and ground.

When the MM74HCT373 LATCH ENABLE input is HIGH,

the Q outputs will follow the D inputs. When the LATCH

ENABLE goes LOW, data at the D inputs will be retained at

the outputs until LATCH ENABLE returns HIGH again.

When a high logic level is applied to the OUTPUT CON-

TROL input, all outputs go to a high impedance state,

regardless of what signals are present at the other inputs

and the state of the storage elements.

The MM74HCT374 are positive edge triggered flip-flops.

Data at the D inputs, meeting the setup and hold time

requirements, are transferred to the Q outputs on po sitive

going transitions of the CLOCK (CK) input. When a high

logic level is applied to the OUTPUT CONTROL (OC)

input, a ll outputs go to a high impeda nce state, reg ardless

of what signals are present at the other inputs and the state

of the storage elements.

MM74HCT devices ar e intended to interfa ce betwe en TTL

and NMOS components and standard CMOS devices.

These parts are also plug in replacements for LS-TTL

devices and can be used to red uce power consump tion in

existing designs.

Features

■TTL input characteristic compatible

■Typical propagation delay: 20 ns

■Low input current: 1

A maximum

■Low quiescent current: 80

A maximum

■Compatible with bus-oriented systems

■Output drive capability: 15 LS-TTL loads

Ordering Code:

Devices also available in Tape and R eel. Specify by ap pending th e s uffix let t er “X” to the or dering code.

Order Number Package Number Package Descriptions

MM74HCT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HCT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HCT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HCT373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

MM74HCT374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HCT374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HCT374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HCT374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

MM74HCT373 • MM74HCT374

Connection Diagrams

Top View

MM74HCT373 Top View

MM74HCT374

Truth Tables

MM74HCT373

HIGH Level

LOW Level

Level of output before steady-state input conditions were established.

High Impeda nc e

MM74HCT374

HIG H Level

LOW Le vel

Don’t Care

Transition from LOW-to-HIGH

High Impedance State

The level of the output before steady state input conditions were

established.

Output LE Data 373

Control Output

LHHH

LHLL

LLXQ

HXXZ

Output Clock Data Output

Control (374)

LLXQ

HXXZ

3 www.fairchildsemi.com

MM74HCT373 • MM74HCT374

Logic Diagrams

MM74HCT373

MM74HCT374

www.fairchildsemi.com 4

MM74HCT373 • MM74HCT374

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-

age to the device may occur.

Note 2: Unless ot herwise spec ified all vo ltag es are referenc ed to ground.

Note 3: Power Dis sipation temp erature de rating — plastic “N” package:



12 mW/

C from 65

C to 85

DC Electrical Characteristics

VCC

10% (unless otherwise specified)

Note 4: Measured per pin. All othe rs tie d t o VCC or ground.

Supply Voltag e (VCC)



0.5 to



7.0V

DC Input Voltage (VIN)



1.5 to VCC



1.5V

DC Output Voltage (VOUT)



0.5 to VCC



0.5V

Clamp Diode Current (IIK, IOK)

20 mA

DC Output Current, per pin (IOUT)

35 mA

DC VCC or GND Current, per pin (ICC)

70 mA

Storage Temperature Range (TSTG)



C to



150

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 260

Min Max Units

Supply Voltage (VCC)4.55.5V

DC Input or Output Voltage 0 VCC V

(VIN, VOUT)

Operating Temperature Range (TA)





Input Rise or Fall Times

(tr, tf) 500 ns

Symbol Parameter Conditions TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0 2.0 2.0 V

Input Voltage

VIL Maximum LOW Level 0.8 0.8 0.8 V

Input Voltage

VOH Minimum HIGH Level VIN

VIH or VIL

Output Voltage |IOUT|

CC VCC



0.1 VCC



0.1 VCC



0.1 V

|IOUT|

6.0 mA, VCC

4.5V 4.2 3.98 3.84 3.7 V

|IOUT|

7.2 mA, VCC

5.5V 5.7 4.98 4.84 4.7 V

VOL Maximum LOW Level VIN

VIH or VIL

Voltage |IOUT|

A 0 0.1 0.1 0.1 V

|IOUT|

6.0 mA, VCC

4.5V 0.2 0.26 0.33 0.4 V

|IOUT|

7.2 mA, VCC

5.5V 0.2 0.26 0.33 0.4 V

IIN Maximum Input VIN

VCC or GND,

0.1

1.0

Current VIH or VIL

IOZ Maximum 3-STATE VOUT

VCC or GND

Output Leakage Enable

VIH or VIL

0.5

5.0

Current

ICC Maximum Quiescent VIN

VCC or GND 8.0 80 160

Supply Current IOUT

VIN

2.4V or 0.5V (Note 4) 1.0 1.3 1.5 mA

5 www.fairchildsemi.com

MM74HCT373 • MM74HCT374

AC Electrical Characteristics

MM74HCT373: VCC

5.0V, tr

6 ns TA

C (unless otherwise specified)

AC Electrical Characteristics

MM74HCT373: VCC

5.0V

10%, tr

6 ns (unless otherwise specified)

Note 5: CPD determines the no load dynamic power consumption, PD

CPD VCC2 f



ICC VCC, and the no load dynam ic c urrent con sumpti on,

CPD VCC f



ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

tPHL, tPLH Maximum Propagation Delay CL

45 pF 18 25 ns

Data to Output

tPHL, tPLH Maximum Propagation Delay CL

45 pF 21 30 ns

Latch Enable to Output

tPZH, tPZL Maximum Enable Propagation Delay CL

45 pF 20 28 ns

Control to Output RL

1 k

tPHZ, tPLZ Maximum Disable Propagation Delay CL

5 pF 18 25 ns

Control to Output RL

1 k

tWMinimum Clock Pulse Width 16 ns

tSMinimum Setup Time Data to Clock 5 ns

tHMinimum Hold Time Clock to Data 10 ns

Symbol Parameter Conditions TA



40 to 85



55 to 125

CUnits

Typ Guar ant eed Lim i ts

tPHL, tPLH Maximum Propagation CL

50 pF 22 30 37 45 ns

Delay Data to Output CL

150 pF 30 40 50 60 ns

tPHL, tPLH Maximum Propagation Delay CL

50 pF 25 35 44 53 ns

Latch Enable to Output CL

150 pF 32 45 56 68 ns

tPZH, tPZL Maximum Enable Propagation CL

50 pF 21 30 37 45 ns

Delay Control to Output CL

150 pF 30 40 50 60 ns

1 k

tPHZ, tPLZ Maximum Disable Propagation CL

50 pF 21 30 37 45 ns

Delay Control to Output RL

1 k

tTHL, tTLH Maximum Output Rise CL

50 pF 8 12 15 18 ns

and Fall Time

tWMinimum Clock Pulse Width 16 2 0 24 ns

tSMini mum Setup Time D ata to Clock 5 6 8 ns

tHMinimum Hold Time Clock to Data 10 13 20 ns

CIN Maximum Input Capacitance 10 10 10 pF

COUT Maximum Output Capacitance 20 20 20 pF

CPD Power Dissipation Capacitance OC

VCC 5pF

(Note 5) OC

GND 52 pF

www.fairchildsemi.com 6

MM74HCT373 • MM74HCT374

AC Electrical Characteristics

MM74HCT374: VCC

5.0V, tr

6 ns TA

C (unless otherwise specified)

AC Electrical Characteristics

MM74HCT374: VCC

5.0V

10%, tr

6 ns (unless otherwise specified)

Note 6: CPD determines t he no load p ow er consumptio n, PD

CPD VCC2 f



ICC VCC, and the no load dynam ic c urrent con sumpti on, IS

CPD VCC f



ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

fMAX Maximum Clock Frequency 50 30 MHz

tPHL, tPLH Maximum Propagation Delay C L

45 pF 20 32 ns

to Output

tPZH, tPZL Maximum Enable Propagation Delay CL

45 pF 19 28 ns

Control to Output RL

1 k

tPHZ, tPLZ Maximum Disable Propagation Delay CL

5 pF 17 25 ns

Control to Output RL

1 k

tWMinimum Clock Pulse Width 20 ns

tSMinimum Setup Time Data to Clock 5 ns

tHMinimum Hold Time Clock to Data 16 ns

Symbol Parameter Conditions TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

fMAX Maximum Clock Frequency 30 24 20 MHz

tPHL, tPLH Maximum Propagation Delay CL

50 pF 22 36 45 48 ns

to Output CL

150 pF 30 46 57 69 ns

tPZH, tPZL Maximum Enable Propagation CL

50 pF 21 30 37 45 ns

Delay Control to Output CL

150 pF 30 40 50 60 ns

1 k

tPHZ, tPLZ Maximum Disable Propagation CL

50 pF 21 30 37 45 ns

Delay Control to Output RL

1 k

tTHL, tTLH Maximum Output Rise CL

50 pF 8 12 15 18 ns

and Fall Time

tWMinimum Clock Pulse Width 16 20 24 ns

tSMinimum Setup Time Data to Clock 20 25 30 ns

tHMinimum Hold Time Clock to Data 5 5 5 ns

CIN Maximum Input Capacitance 10 10 10 pF

COUT Maximum Output Capacitance 20 20 20 pF

CPD Power Dissipation Capacitance OC

VCC 5pF

(Note 6) OC

GND 58 pF

7 www.fairchildsemi.com

MM74HCT373 • MM74HCT374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

www.fairchildsemi.com 8

MM74HCT373 • MM74HCT374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Pack age (SOP), EIAJ TYPE II, 5 .3mm Wide

Package Number M20D

9 www.fairchildsemi.com

MM74HCT373 • MM74HCT374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

www.fairchildsemi.com 10

MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.