REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
OP249
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
Dual, Precision
JFET High-Speed Operational Amplifier
PIN CONNECTIONS
FEATURES
Fast Slew Rate: 22 V/␮s Typ
Settling Time (0.01%): 1.2 ␮s Max
Offset Voltage: 300 ␮V Max
High Open-Loop Gain: 1000 V/mV Min
Low Total Harmonic Distortion: 0.002% Typ
Improved Replacement for AD712, LT1057, OP215,
TL072 and MC34082
Available in Die Form
APPLICATIONS
Output Amplifier for Fast D/As
Signal Processing
Instrumentation Amplifiers
Fast Sample/Holds
Active Filters
Low Distortion Audio Amplifiers
Input Buffer for A/D Converters
Servo Controllers
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, simi-
lar to the popular single op amp, the OP42. The OP249 outper-
forms available dual amplifiers by providing superior speed with
excellent dc performance. Ultrahigh open-loop gain (1 kV/mV
minimum), low offset voltage and superb gain linearity, makes
the OP249 the industry’s first true precision, dual high speed
amplifier.
With a slew rate of 22 V/µs typical, and a fast settling time of
less than 1.2 µs maximum to 0.01%, the OP249 is an ideal
choice for high speed bipolar D/A and A/D converter applica-
tions. The excellent dc performance of the OP249 allows the
full accuracy of high resolution CMOS D/As to be realized.
Symmetrical slew rate, even when driving large load, such as
600 Ω or 200 pF of capacitance, and ultralow distortion, make
the OP249 ideal for professional audio applications, active
filters, high speed integrators, servo systems and buffer amplifiers.
The OP249 provides significant performance upgrades to the
TL072, AD712, OP215, MC34082 and the LT1057.
8-Lead Cerdip (Z Suffix),
8-Lead Plastic Mini-DIP
(P Suffix)
1
2
3
4
8
7
6
5
A
B
++–
+IN A
V– +IN B
–IN B
–IN A
OUT A V+
OUT B
–
TO-99 (J Suffix)
OUTA 1
–IN A 2
+IN A 3
4
V–
5 +IN B
6 –IN B
7 OUT B
V+
8
B
+–
A
+–
8-Lead SO
(S Suffix)
1
2
3
4
8
7
6
5
A
B
+
–
+
–
+IN A
V–
+IN B
–IN B
–IN A
OUT A
V+
OUT B
10
0%
100
90
500ns
10mV
870ns
Figure 1. Fast Settling (0.01%)
0.010
0.001
20 10k
100 1k 20k
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 10k⍀
A
V
= 1
Figure 2. Low Distortion A
V
= 1,
R
L
= 10 k
Ω
20-Terminal LCC (RC Suffix)
123
4
8
7
6
5
NC
NC
NC
V–
OUT B
OUT A
NC
–IN A
+IN A
NC
NC
NC
NC
+IN B
NC
V+
19
20
18
17
16
15
14
131211
10
NC
NC
9
–IN B
NC
NC = NO CONNECT
10
0%
100
90
1µs5V
Figure 3. Excellent Output Drive,
R
L
= 600
Ω
–2– REV. D
OP249–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
OP249A OP249E OP249F
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Offset Voltage V
OS
0.2 0.5 0.1 0.3 0.2 0.7 mV
Long Term Offset Voltage V
OS
(Note 1) 0.8 0.6 1.0 mV
Offset Stability 1.5 1.5 1.5 µV/Month
Input Bias Current I
B
V
CM
= 0 V, T
J
= 25°C 3075 2050 3075pA
Input Offset Current I
OS
V
CM
= 0 V, T
J
= 25°C 6 25 4 15 6 25 pA
Input Voltage Range IVR (Note 2) 12.5 12.5 12.5 V
±11 ±11 ±11 V
–12.5 –12.5 –12.5 V
Common-Mode Rejection CMR V
CM
= ±11 V 8090 8695 80 90 dB
Power-Supply Rejection Ratio PSRR V
S
= ±4.5 V to ±18 V 12 31.6 9 31.6 12 50 µV/V
Large-Signal Voltage Gain A
VO
V
O
= ±10 V, R
L
= 2 kΩ1000 1400 1000 1400 500 1200 V/mV
Output Voltage Swing V
O
R
L
= 2 kΩ12.5 12.5 12.5 V
±12.0 ±12.0 ±12.0 V
–12.5 –12.5 –12.5 V
Short-Circuit Current Limit I
SC
Output Shorted to 36 36 36 mA
Ground ±20 ±50 ±20 ±50 ±20 ±50 mA
–33 –33 –33 mA
Supply Current I
SY
No Load, V
O
= 0 V 5.6 7.0 5.6 7.0 5.6 7.0 mA
Slew Rate SR R
L
= 2 kΩ, C
L
= 50 pF 18 22 18 22 18 22 V/µs
Gain-Bandwidth Product GBW (Note 3) 3.5 4.7 3.5 4.7 3.5 4.7 MHz
Settling Time t
S
10 V Step 0.01%
4
0.9 1.2 0.9 1.2 0.9 1.2 µs
Phase Margin θ
0
0 dB Gain 55 55 55 Degrees
Differential Input Impedance Z
IN
10
12
610
12
610
12
6ΩpF
Open-Loop Output Resistance R
O
35 35 35 Ω
Voltage Noise e
n
p-p 0.1 Hz to 10 Hz 2 2 2 µV p-p
Voltage Noise Density e
n
f
O
= 10 Hz 75 75 75 nV/√Hz
f
O
= 100 Hz 26 26 26 nV/√Hz
f
O
= 1 kHz 17 17 17 nV/√Hz
f
O
= 10 kHz 16 16 16 nV/√Hz
Current Noise Density i
n
f
O
= 1 kHz 0.003 0.003 0.003 pA/√Hz
Voltage Supply Range V
S
±4.5 ±15 ±18 ±4.5 ±15 ±18 ±4.5 ±15 ±18 V
NOTES
1
Long-term offset voltage is guaranteed by a 1000 HR life test performed on three independent wafer lots at 125 °C with LTPD of three.
2
Guaranteed by CMR test.
3
Guaranteed by design.
4
Settling time is sample tested.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
OP249G
Parameter Symbol Conditions Min Typ Max Unit
Offset Voltage V
OS
0.4 2.0 mV
Input Bias Current I
B
V
CM
= 0 V, T
J
= 25°C4075pA
Input Offset Current I
OS
V
CM
= 0 V, T
J
= 25°C1025pA
Input Voltage Range IVR (Note 1) 12.5 V
±11 V
–12.0 V
Common-Mode Rejection CMR V
CM
= ±11 V 76 90 dB
Power Supply Rejection Ratio PSRR V
S
= ±4.5 V to ±18 V 12 50 µV/V
Large Signal Voltage Gain A
VO
V
O
= ±10 V; R
L
= 2 kΩ500 1100 V/mV
Output Voltage Swing V
O
R
L
= 2 kΩ12.5 V
±12.0 V
–12.5 V
Short-Circuit Current Limit I
SC
Output Shorted to Ground 36 mA
±20 ±50 mA
–33 mA
Supply Current I
SY
No Load; V
O
= 0 V 5.6 7.0 mA
Slew Rate SR R
L
= 2 kΩ, C
L
= 50 pF 18 22 V/µs
Gain Bandwidth Product GBW (Note 2) 4.7 MHz
Settling Time t
S
10 V Step 0.01% 0.9 1.2 µs
Phase Margin θ
0
0 dB Gain 55 Degree
Differential Input Impedance Z
IN
10
12
6ΩpF
(@ VS = ⴞ15 V, TA = 25ⴗC, unless otherwise noted)
(@ VS = ⴞ15 V, TA = 25ⴗC, unless otherwise noted)
–3–REV. D
OP249
OP249G
Parameter Symbol Conditions Min Typ Max Unit
Open Loop Output Resistance R
O
35 Ω
Voltage Noise e
n
p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density e
n
f
O
= 10 Hz 75 nV/√Hz
f
O
= 100 Hz 26 nV/√Hz
f
O
= 1 kHz 17 nV/√Hz
f
O
= 10 kHz 16 nV/√Hz
Current Noise Density i
n
f
O
= 1 kHz 0.003 pA/√Hz
Voltage Supply Range V
S
±4.5 ±15 ±18 V
NOTES
1
Guaranteed by CMR test.
2
Guaranteed by design.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
OP249A OP249E OP249F
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Offset Voltage V
OS
0.12 1.0 0.1 0.5 0.5 1.1 mV
Offset Voltage Temperature
Coefficient TCV
OS
15 13 2.26µV/°C
Input Bias Current I
B
(Note 1) 4 20 0.25 3.0 0.3 4.0 nA
Input Offset Current I
OS
(Note 1) 0.04 4 0.01 0.7 0.02 1.2 nA
Input Voltage Range IVR (Note 2) 12.5 12.5 12.5 V
±11 ±11 ±11 V
–12.5 –12.5 –12.5 V
Common-Mode Rejection CMR V
CM
= ±11 V 76 110 86 100 80 90 dB
Power-Supply Rejection Ratio PSRR V
S
= ±4.5 V to ±18 V 5 50 5 50 7 100 µV/V
Large-Signal Voltage Gain A
VO
R
L
= 2 kΩ; V
O
= ±10 V 500 1400 750 1400 250 1200 V/mV
Output Voltage Swing V
O
R
L
= 2 kΩ12.5 12.5 12.5 V
±12.0 ±12.0 ±12.0 V
–12.5 –12.5 –12.5 V
Short-Circuit Current Limit I
SC
Output Shorted to
Ground ±10 ±60 ±18 ±60 ±18 ±60 mA
Supply Current I
SY
No Load, V
O
= 0 V 5.6 7.0 5.6 7.0 5.6 7.0 mA
NOTES
1
T
J
= 85°C for E/F Grades; T
J
= 125°C for A Grade.
2
Guaranteed by CMR test.
Specifications subject to change without notice.
(@ VS = ⴞ15 V, –40ⴗC ≤ TA ≤ +85ⴗC for E/F grades, and –55ⴗC ≤ TA ≤ +125ⴗC for
A grade unless otherwise noted)
ELECTRICAL CHARACTERISTICS
OP249G
Parameter Symbol Conditions Min Typ Max Unit
Offset Voltage V
OS
1.0 3.6 mV
Offset Voltage Temperature
Coefficient TCV
OS
625 µV/°C
Input Bias Current I
B
(Note 1) 0.5 4.5 nA
Input Offset Current I
OS
(Note 1) 0.04 1.5 nA
Input Voltage Range IVR (Note 2) 12.5 V
±11 V
–12.5 V
Common-Mode Rejection CMR V
CM
= ±11 V 76 95 dB
Power-Supply Rejection Ratio PSRR V
S
= ±4.5 V to ±18 V 10 100 µV/V
Large-Signal Voltage Gain A
VO
R
L
= 2 kΩ; V
O
= ±10 V 250 1200 V/mV
Output Voltage Swing V
O
R
L
= 2 kΩ12.5 V
±12.0 V
–12.5 V
Short-Circuit Current Limit I
SC
Output Shorted to Ground ±18 ±60 mA
Supply Current I
SY
No Load, V
O
= 0 V 5.6 7.0 mA
NOTES
1
T
J
= 85°C.
2
Guaranteed by CMR test.
Specifications subject to change without notice.
(@ VS = ⴞ15 V, –40ⴗC ≤ TA ≤ +85ⴗC for unless otherwise noted)
OP249
–4– REV. D
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65°C to +175°C
Operating Temperature Range
OP249A (J, Z, RC) . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP249E, F (J, Z) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
OP249G (P, S) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature
OP249 (J, Z, RC) . . . . . . . . . . . . . . . . . . . –65°C to +175°C
OP249 (P, S) . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300°C
ORDERING GUIDE
1
Model Temperature Range Package Descriptions
2
Package Options
OP249AZ
2
–55°C to +125°C 8-Lead Cerdip Q-8
OP249ARC/883 –55°C to +125°C 20-Terminal LCC E-20A
OP249EJ –40°C to +85°C TO-99 H-08A
OP249FZ –40°C to +85°C 8-Lead Cerdip Q-8
OP249GP –40°C to +85°C 8-Lead Plastic DIP N-8
OP249GS
3
–40°C to +85°C 8-Lead SO SO-8
OP249GS-REEL –40°C to +85°C 8-Lead SO SO-8
OP249GS-REEL7 –40°C to +85°C 8-Lead SO SO-8
NOTES
1
Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet.
3
For availability and burn-in information on SO and PLCC packages, contact your local sales office.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP249 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Package Type ␪
JA3
␪
JC
Unit
TO-99 (J) 145 16 °C/W
8-Lead Hermetic DIP (Z) 134 12 °C/W
8-Lead Plastic DIP (P) 96 37 °C/W
20-Terminal LCC (RC) 88 33 °C/W
8-Lead SO (S) 150 41 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ±18 V, the absolute maximum input voltage is equal
to the supply voltage.
3
θ
JA
is specified for worst case mounting conditions, i.e., θ
JA
is specified for device
in socket for TO, cerdip, P-DIP, and LCC packages; θ
JA
is specified for device
soldered to printed circuit board for SO package.
OP249
–5–REV. D
DICE CHARACTERISTICS
OUT (A)
–IN (A)
+IN (A)
V–
+IN (B)
–IN (B)
OUT (B)
V+
DIE SIZE 0.072 in ⴛ 0.112 in, 8,064 sq. mils
(
1.83 mmⴛ 2.84 mm
,
5.2 s
q
. mm
)
WAFER TEST LIMITS
OP249GBC
Parameter Symbol Conditions Limits Unit
Offset Voltage V
OS
0.5 mV max
Offset Voltage Temperature Coefficient TCV
OS
–40°C ≤ T
J
≤ +85°C 6.0 µV/°C max
Input Bias Current I
B
V
CM
= 0 V 225 pA max
Input Offset Current I
OS
V
CM
= 0 V 75 pA max
Input Voltage Range IVR (Note 1) ±11 V min
Common-Mode Rejection CMR V
CM
= ±11 V 76 dB min
Power Supply Rejection Ratio PSRR V
S
= ±4.5 V to ±18 V 100 µV/V max
Large-Signal Voltage Gain A
VO
R
L
= 2 kΩ250 V/mV min
Output Voltage Swing V
O
R
L
= 2 kΩ±12.0 V min
Short-Circuit Current Limit I
SC
Output Shorted to Ground ±20/±60 mA min/max
Supply Current I
SY
No Load; V
O
= 0 V 7.0 mA max
Slew Rate SR R
L
= 2 kΩ, C
L
= 50 pF 16.5 V/µs min
NOTES
1
Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
(@ VS = ⴞ15 V, TJ = 25ⴗC unless otherwise noted)
OP249
–6– REV. D
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
120
1k
100
80
60
40
20
0
–20
10k 100k 1M 10M 100M
0
45
90
135
180
225
TA = 25ⴗC
VS = ⴞ15V
RL = 2k⍀
⍜m = 55
GAIN
PHASE
PHASE – ⴗC
Figure 4. Open-Loop Gain, Phase vs.
Frequency
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
1k
120
100
80
60
40
20
0
10k 100k 1M
T
A
= 25ⴗC
V
S
= ⴞ15V
100
10
–PSRR
+PSRR
Figure 7. Power Supply Rejection vs.
Frequency
CAPACITIVE LOAD – pF
SLEW RATE – V/␮s
35
30
0
25
T
A
= 25ⴗC
V
S
= ⴞ15V
20
15
10
5100 200 300 400 500
NEGATIVE
POSITIVE
Figure 10. Slew Rate vs. Capacitive
Load
TEMPERATURE – ⴗC
PHASE MARGIN – ⴗC
65
60
45
–75
55
50
–50 –25 0 25 50 75 100 125
GAIN BANDWIDTH PRODUCT – MHz
10
8
2
6
4
V
S
= ⴞ15V
GBW
⍜m
Figure 5. Gain Bandwidth Product,
Phase Margin vs. Temperature
TEMPERATURE – ⴗC
SLEW RATE – V/␮s
28
26
–75
24
–50 –25 0 25 50 75 100 125
V
S
= ⴞ15V
R
L
= 2k⍀
C
L
= 50pF
+SR
–SR
22
20
18
16
Figure 8. Slew Rate vs. Temperature
0.1%
SETTLING TIME – ns
OUTPUT STEP SIZE – Volts
0
T
A
= 25ⴗC
V
S
= ⴞ15V
A
VCL
= 1
–10 200 400 600 800 1000
0.01%
–8
–6
–4
–2
0
2
4
6
8
10
0.1%
0.01%
Figure 11. Settling Time vs. Step
Size
FREQUENCY – Hz
COMMON-MODE REJECTION – dB
140
1k
120
100
80
60
40
20
0
10k 100k 1M 10M
T
A
= 25ⴗC
V
S
= ⴞ15V
100
Figure 6. Common-Mode Rejection
vs. Frequency
DIFFERENTIAL INPUT VOLTAGE – Volts
SLEW RATE – V/␮s
28
26
0
24
T
A
= 25ⴗC
V
S
= ⴞ15V
R
L
= 2k⍀
22
20
18
16 0.2 0.4 0.6 0.8 1.0
Figure 9. Slew Rate vs. Differential
Input Voltage
FREQUENCY – Hz
100
0100
80
60
40
20
0
TA = 25ⴗC
VS = ⴞ15V
1k 10k
VOLTAGE NOISE DENSITY – nV Hz
Figure 12. Voltage Noise Density vs.
Frequency
–Typical Performance Characteristics
OP249
–7–REV. D
0.010
20 100
0.001
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 10k⍀
A
V
= 1
1k 10k 20k
Figure 13. Distortion vs. Frequency
0.10
20 100
0.010
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 10k⍀
A
V
= 1
1k 10k 20k
Figure 16. Distortion vs. Frequency
+1␮V
–1␮V
BANDWIDTH (0.1Hz TO 10Hz)
TA = 25ⴗCV
S = ⴞ15V
500mV 1s
Figure 19. Low Frequency Noise
0.010
20 100
0.001
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 2k⍀
A
V
= 1
1k 10k 20k
Figure 14. Distortion vs. Frequency
0.10
20 100
0.010
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 2k⍀
A
V
= 10
1k 10k 20k
Figure 17. Distortion vs. Frequency
FREQUENCY – Hz
CLOSED-LOOP GAIN – dB
1k
10
0
–10
10k 100k 1M 10M
T
A
= 25ⴗC
V
S
= ⴞ15V
60
50
40
30
20
–20
100M
A
VCL
= 100
A
VCL
= 5
A
VCL
= 1
A
VCL
= 10
Figure 20. Closed-Loop Gain vs.
Frequency
0.010
20 100
0.001
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 600⍀
A
V
= 1
1k 10k 20k
Figure 15. Distortion vs. Frequency
0.10
20 100
0.010
T
A
= 25ⴗC
V
S
= ⴞ15V
V
O
= 10V p-p
R
L
= 600⍀
A
V
= 10
1k 10k 20k
Figure 18. Distortion vs. Frequency
FREQUENCY – Hz
IMPEDANCE – ⍀
1k
10
0
10k 100k 1M 10M
T
A
= 25ⴗC
V
S
= ⴞ15V
50
40
30
20 A
VCL
= 100
A
VCL
= 1
A
VCL
= 10
100
Figure 21. Closed-Loop Output
Impedance vs. Frequency
OP249
–8– REV. D
FREQUENCY – Hz
MAXIMUM OUTPUT SWING – Volts
25
20
15
10
0
TA = 25ⴗC
VS = ⴞ15V
AVCL = 1
RL = 10k⍀
1k 10k
30
5
100k 1M 10M
Figure 22. Maximum Output Swing
vs. Frequency
SUPPLY VOLTAGE – Volts
OUTPUT VOLTAGE SWING – Volts
0
T
A
= 25ⴗC
R
L
= 2k⍀
–20
ⴞ5ⴞ10 ⴞ15 ⴞ20
–15
–10
–5
0
5
10
15
20
Figure 25. Output Voltage Swing vs.
Supply Voltage
VOS – ␮V
UNITS
–600
TA = 25ⴗC
VS = ⴞ15V
350 ⴛ OP249
(700 OP AMPS)
–1k
320
360
280
240
200
160
120
80
40
0
–800 –200
–400 200
0600
400 800 1k
Figure 28. V
OS
Distribution
(J Package)
LOAD CAPACITANCE – pF
OVERSHOOT – %
60
50
40
100
V
S
= ⴞ15V
R
L
= 2k⍀
V
IN
= 100mV p-p
30
20
10
0
A
VCL
= 1
NEGATIVE EDGE
A
VCL
= 1
POSITIVE EDGE
A
VCL
= 5
0 200 300 400 500
70
80
90
Figure 23. Small Overshoot vs. Load
Capacitance
TEMPERATURE – ⴗC
SUPPLY CURRENT – mA
V
S
= ⴞ15V
NO LOAD
5.2
–75
5.4
5.6
5.8
6.0
–50 –25 0 25 50 75 100 125
Figure 26. Supply Current vs.
Temperature
V
OS
– ␮V
UNITS
–600
T
A
= 25ⴗC
V
S
= ⴞ15V
415 ⴛ OP249
(830 OP AMPS)
–1k
160
180
140
120
100
80
60
40
20
0
–800 –200
–400 200
0600
400 800 1k
Figure 29. V
OS
Distribution
(P Package)
LOAD RESISTANCE – ⍀
MAXIMUM OUTPUT SWING – Volts
TA = 25ⴗC
VS = ⴞ15V
14
12
10
8
0
100 10k
16
6
1k
+VOHM = |–VOHM |
4
2
Figure 24. Maximum Output Voltage
vs. Load Resistance
SUPPLY VOLTAGE – Volts
SUPPLY CURRENT – mA
T
A
= 25ⴗC
5.0
5.2
5.4
5.6
5.8
6.0
0 5 10 15 20
T
A
= 125ⴗC
T
A
= –55ⴗC
Figure 27. Supply Current vs. Supply
Voltage
␮
V/ⴗC
UNITS
0.5
V
S
= ⴞ15V
–40ⴗC TO +85ⴗC
(700 OP AMPS)
0
240
270
210
180
150
120
90
60
30
01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Figure 30. TCV
OS
Distribution
(J Package)
OP249
–9–REV. D
␮
V/ⴗC
UNITS
2
V
S
= ⴞ15V
–40ⴗC TO +85ⴗC
(830 OP AMPS)
0
240
300
210
180
150
120
90
60
30
0
270
4 6 8 10 12 14 16 18 20 22 24
Figure 31. TCV
OS
Distribution
(P Package)
–15
10
0
–10 –5051015
BIAS CURRENT – pA
COMMON-MODE VOLTAGE – Volts
T
A
= 25ⴗC
V
S
= ⴞ15V
10
1
10
2
10
3
10
4
Figure 34. Bias Current vs.
Common-Mode Voltage
TEMPERATURE – ⴗC
OPEN-LOOP GAIN – V/mV
–75
80
20
0
40
V
S
= ⴞ15V
60
–50 –25 0 25 50 75 100 125
R
L
= 2k⍀
R
L
= 10k⍀
Figure 37. Open-Loop Gain vs.
Temperature
TIME AFTER POWER APPLIED – Minutes
OFFSET VOLTAGE – ␮V
1
V
S
= ⴞ15V
0
50
20
30
024
40
10
35
Figure 32. Offset Voltage Warm-Up
Drift
TIME AFTER POWER APPLIED – Minutes
INPUT BIAS CURRENT – pA
20
50
20
30
048
40
10
610
T
A
= 25ⴗC
V
S
= ⴞ15V
Figure 35. Bias Current Warm-Up
Drift
TEMPERATURE – ⴗC
SHORT-CIRCUIT OUTPUT CURRENT – mA
–75
80
20
0
40
VS = ⴞ15V
60
–50 –25 0 25 50 75 100 125
SINK
SOURCE
Figure 38. Short-Circuit Output
Current vs. Junction Temperature
–75
100
1k
10k
10
1
–50 –25 0 25 50 75 100 125
INPUT BIAS CURRENT – pA
TEMPERATURE – ⴗC
V
S
= ⴞ15V
V
CM
= 0V
Figure 33. Input Bias Current vs.
Temperature
TEMPERATURE – ⴗC
INPUT OFFSET CURRENT – pA
–75
80
20
0
40
TA = 25ⴗC
VCM = 0V
60
–50 –25 0 25 50 75 100 125
Figure 36. Input Offset Current vs.
Temperature
OP249
–10– REV. D
+IN
–IN
V+
V
OUT
V–
Figure 39. Simplified Schematic (1/2 OP249)
1/2
OP249
3V 5k⍀
+18V
–18V
3V 5k⍀
1/2
OP249
Figure 40. Burn-In Circuit
APPLICATIONS INFORMATION
The OP249 represents a reliable JFET amplifier design, featur-
ing an excellent combination of dc precision and high speed. A
rugged output stage provides the ability to drive a 600 Ω load
and still maintain a clean ac response. The OP249 features a large
signal response that is more linear and symmetric than previ-
ously available JFET input amplifiers—compare the OP249’s
large-signal response, as illustrated in Figure 41, to other
industry standard dual JFET amplifiers.
Typically, JFET amplifier’s stewing performance is simply specified
as just a number of volts/µs. There is no discussion on the quality,
i.e., linearity, symmetry, etc., of the stewing response.
A) OP249
B) LT1057
C) AD712
Figure 41. Large-Signal Transient Response, A
V
= 1,
V
IN
= 20 V p-p, Z
L
= 2 k
Ω
//200 pF, V
S
=
±
15 V
OP249
–11–REV. D
The OP249 was carefully designed to provide symmetrically
matched slew characteristics in both the negative and positive
directions, even when driving a large output load.
An amplifier’s slewing limitation determines the maximum
frequency at which a sinusoidal output can be obtained without
significant distortion. It is, however, important to note that the
nonsymmetric stewing typical of previously available JFET
amplifiers adds a higher series of harmonic energy content to
the resulting response—and an additional dc output component.
Examples of potential problems of nonsymmetric slewing
behavior could be in audio amplifier applications, where a natural
low distortion sound quality is desired, and in servo or signal
processing systems where a net dc offset cannot be tolerated.
The linear and symmetric stewing feature of the OP249 makes
it an ideal choice for applications that will exceed the full-power
bandwidth range of the amplifier.
Figure 42. Small-Signal Transient Response, A
V
= 1,
Z
L
= 2 k
Ω
100 pF, No Compensation, V
S
=
±
15 V
As with most JFET-input amplifiers, the output of the OP249
may undergo phase inversion if either input exceeds the speci-
fied input voltage range. Phase inversion will not damage the
amplifier, nor will it cause an internal latch-up condition.
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier. A 0.1 µF
and a 10 µF capacitor should be placed between each supply
pin and ground.
OPEN-LOOP GAIN LINEARITY
The OP249 has both an extremely high open-loop gain of
1 kV/mV minimum and constant gain linearity. This feature of
the OP249 enhances its dc precision, and provides superb accu-
racy in high closed-loop gain applications. Figure 43 illustrates
the typical open-loop gain linearity—high gain accuracy is assured,
even when driving a 600 Ω load.
OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP249 will make offset
adjustments unnecessary in most applications. However, where
a lower offset error is required, balancing can be performed with
simple external circuitry, as illustrated in Figures 44 and 45.
VERTICAL 50␮V/DIV
INPUT VARIATION
HORIZONTAL 5V/DIV
OUTPUT CHARGE
Figure 43. Open-Loop Gain Linearity. Variation in Open-
Loop Gain Results in Errors in High Closed-Loop Gain
Circuits. R
L
= 600
Ω
, V
S
=
±
15 V
1/2
OP249
–V
+V
V
IN
R3
R1
200k⍀
R5
50k⍀
R2
31⍀
V
OUT
R4
V
OS
ADJUST RANGE = ⴞVR2
R1
Figure 44. Offset Adjust for Inverting Amplifier
Configuration
1/2
OP249
–V
+V
V
IN
R1
200k⍀
R3
50k⍀
R2
33⍀
V
OUT
R5
V
OS
ADJUST RANGE = ⴞVR2
R1
1 + R5
R4 IF R2 << R4
V
OUT
V
IN
GAIN = = 1 + R5
R4 + R2
R4
Figure 45. Offset Adjust for Noninverting Amplifier
Configuration
In Figure 44, the offset adjustment is made by supplying a small
voltage at the noninverting input of the amplifier. Resistors R1
and R2 attenuates the pot voltage, providing a ±2.5 mV (with
V
S
= ±15 V) adjustment range, referred to the input. Figure 45
illustrates offset adjust for the noninverting amplifier configura-
tion, also providing a ±2.5 mV adjustment range. As indicated
in the equations in Figure 45, if R4 is not much greater than R2,
there will be a resulting closed-loop gain error that must be
accounted for.
OP249
–12– REV. D
SETTLING TIME
Settling time is the time between when the input signal begins
to change and when the output permanently enters a prescribed
error band. The error bands on the output are 5 mV and 0.5 mV,
respectively, for 0.1% and 0.01% accuracy.
Figure 46 illustrates the OP249’s typical settling time of 870 ns.
Moreover, problems in settling response, such as thermal tails
and long-term ringing are nonexistent.
10
0%
100
90
500ns
10mV
870ns
Figure 46. Settling Characteristics of the OP249 to 0.01%
REFERENCE
OR V
IN
V
OUT
+15V
–15V
PM7545
DB
11
– DB
0
12
500⍀
C
33pF
75⍀
V
DD
0.1␮F
0.1␮F
OUT
1
AGND
V
REF
1/2
OP249
0.1␮F
DGND
R
FB
V
DD
DATA INPUT
a. Unipolar Operation
REFERENCE
OR VIN
VOUT
1/2
OP249
+15V
PM7545
500⍀
C
33pF
75⍀
OUT1
AGND
VREF
RFB
–15V
0.1␮F
R4
20k⍀
1%
R5
10k⍀
1%
R3
10k⍀
1%
0.1␮F
1/2
OP249
DGND
DB11 – DB0
12
DATA INPUT
VDD
0.1␮F
VDD
b. Bipolar Operation
Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance
DAC OUTPUT AMPLIFIER
Unity-gain stability, a low offset voltage of 300 µV typical, and a
fast settling time of 870 ns to 0.01%, makes the OP249 an ideal
amplifier for fast digital-to-analog converters.
For CMOS DAC applications, the low offset voltage of the
OP249 results in excellent linearity performance. CMOS DACs,
such as the PM-7545, will typically have a code-dependent
output resistance variation between 11 kΩ and 33 kΩ. The
change in output resistance, in conjunction with the 11 kΩ
feedback resistor, will result in a noise gain change. This causes
variations in the offset error, increasing linearity errors. The
OP249 features low offset voltage error, minimizing this effect
and maintaining 12-bit linearity performance over the full-scale
range of the converter.
Since the DAC’s output capacitance appears at the operational
amplifiers inputs, it is essential that the amplifier is adequately
compensated. Compensation will increase the phase margin,
and ensure an optimal overall settling response. The required
lead compensation is achieved with Capacitor C in Figure 47.
OP249
–13–REV. D
Figure 48 illustrates the effect of altering the compensation on
the output response of the circuit in Figure 48a. Compensation
is required to address the combined effect of the DAC’s output
capacitance, the op amp’s input capacitance and any stray capaci-
tance. Slight adjustments to the compensation capacitor may be
required to optimize settling response for any given application.
The settling time of the combination of the current output DAC
and the op amp can be approximated by:
tSTOTAL =(tSDAC )2+(tSAMP )2
The actual overall settling time is affected by the noise gain of
the amplifier, the applied compensation, and the equivalent
input capacitance at the amplifier’s input.
DISCUSSION ON DRIVING A/D CONVERTERS
Settling characteristics of operational amplifiers also include an
amplifier’s ability to recover, i.e., settle, from a transient current
output load condition. An example of this includes an op amp
driving the input from a SAR type A/D converter. Although the
comparison point of the converter is usually diode clamped, the
input swing of plus-and-minus a diode drop still gives rise to a
significant modulation of input current. If the closed-loop output
impedance is low enough and bandwidth of the amplifier is
sufficiently large, the output will settle before the converter
makes a comparison decision which will prevent linearity errors
or missing codes.
Figure 49 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1 mA. As seen in Figure 50, the OP249 has extremely
fast recovery of 274 ns (to 0.01%), for a 1 mA load transient.
The performance makes it an ideal amplifier for data acquisition
systems.
BA
C = 5pF
RESPONSE IS GROSSLY UNDERDAMPED,
AND EXHIBITS RINGING
C = 15pF
FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE
OF SLIGHT PEAKING IN RESPONSE
Figure 48. Effect of Altering Compensation from Circuit in Figure 47a—PM7545 CMOS DAC with 1/2 OP249, Unipolar
Operation. Critically Damped Response Will Be Obtained with C
33 pF
|V
REF
|
1k⍀
⌬I
OUT
=
1/2
OP249
+15V
–15V
0.1␮F
0.1␮F
+15V
1.5k⍀
1N4148
0.1␮F
220⍀
1.8k⍀
1k⍀
2N3904
1k⍀
10␮F
V
REF
0.47␮F
0.01␮F
*
*
*NOTE: DECOUPLE CLOSE TOGETHER
ON GROUND PLANE WITH
SHORT LEAD LENGTHS
TTL INPUT
+15V
2N2907
7A13 PLUG-IN
7A13 PLUG-IN
300pF
Figure 49. Transient Output Impedance Test Fixture
The combination of high speed and excellent dc performance of
the OP249 makes it an ideal amplifier for 12-bit data acquisition
systems. Examining the circuit in Figure 51, one amplifier in the
OP249 provides a stable –5 V reference voltage for the V
REF
input
of the ADC912. The other amplifier in the OP249 performs
high speed buffering of the A/D’s input.
Examining the worst case transient voltage error (Figure 52) at
the Analog In node of the A/D converter: the OP249 recovers in
less than 100 ns. The fast recovery is due to both the OP249’s
wide bandwidth and low dc output impedance.
OP249
–14– REV. D
Figure 50. OP249’s Transient Recovery Time from a 1 mA
Load Transient to 0.01%
1/2
OP249
+15V
–15V
0.1␮F
0.1␮F
AGND
V
REF
IN
ANALOG
INPUT
ANALOG IN
DGND HBEN CS
BUSY
CLK IN
ADC912
RD
10␮F||0.1␮F10␮F||0.1␮F
+5V –15V
1/2
OP249
+15V
–5V
0.1␮F
0.1␮F
10⍀
10␮F||0.1␮F
REF02
GND
IN
OUT
Figure 51. OP249 Dual Amplifiers Provide Both Stable –5 V
Reference Input, and Buffers Input to ADC912
Figure 52. Worst-Case Transient Voltage, at Analog In,
Occurs at the Half-Scale Point of the A/D. OP249 Buffers
the A/D Input from Figure 51, and Recovers in Less than
100 ns.
OP249
–15–REV. D
99
I1
V2
4
7
I
OS
C
IN
3
J1 J2
E
OS
R3 R4
C2
56
50
2
IN–
IN+
R1
R2
V3
10
D2
D1
8
9
R5 C3
C4
R6
G3
G4 R8
R7
13
C6
C5
12
R9
R10
G6
G5
R11
R12
R13
R14 L2
L1
G1
G2
1
14
15
16
G7
99
17
G8
C9
R15
R16 C10
C11
R17
R18 C12
G11
18 19 20
L3
G12
C13
C14
G13
G14
R22
R21
R20
R19
G9
G10
21
22
L4
50
50
99
G15
G16
R23
R24
C15
C16 R26
R25
24
23
25
26
D3
D4
D7 D8
G17 G18
R27
R28
L5 30
29
D5 D6
V
OUT
G19
G20
27 28
+–
+–
V4
V5
Figure 53. OP249 Macro-Model
OP249 SPICE MACRO-MODEL
Figures 53 and Table I show the node and net list for a SPICE
macromodel of the OP249 The model is a simplified version of
the actual device and simulates important dc parameters such as
V
OS
, I
OS
, I
B
, A
VO
, CMR, V
O
and I
SY
. AC parameters such as slew
rate, gain and phase response and CMR change with frequency
are also simulated by the model.
The model uses typical parameters for the OP249. The poles
and zeros in the model were determined from the actual open
and closed-loop gain and phase response of the OP249. In this
way the model presents an accurate ac representation of the actual
device. The model assumes an ambient temperature of 25°C.
OP249
–16– REV. D
OP249 MACRO-MODEL
• subckt OP249 1 2 30 99 50
*
INPUT STAGE & POLE AT 100MHz
*
r1 2 3 5E11
r2 1 3 5E11
r3 5 50 652.3
r4 6 50 652.3
cin 1 2 5E-12
c2 5 6 1.22E-12
i1 99 4 1E-3
ios 1 2 3.1E-12
eos 7 1 poly(1) 20 24 150E-6 1
j1 5 2 4 jx
j2 6 7 4 jx
*
* SECOND STAGE & POLE AT 12.2Hz
*
r5 9 99 326.1E6
r6 9 50 326.1E6
c3 9 99 40E-12
c4 9 50 40E-12
g1 99 9 poly(1) 5 6 4.25E-3 1.533E-3
g2 9 50 poly(1) 6 5 4.25E-3 1.533E-3
v2 99 8 2.9
v3 10 50 2.9
d1 9 8 dx
d2 10 9 dx
*
* POLE-ZERO PAIR AT 2MHz/4.0MHz
*
r7 11 99 1E6
r8 11 50 1E6
r9 11 12 1E6
r10 11 13 1E6
c5 12 99 37.79E-15
c6 13 50 37.79E-15
g3 99 11 9 24 1E-6
g4 11 50 24 9 1E-6
*
* ZERO-POLE PAIR AT 4MHz/8MHz
*
r11 99 15 IE6
r12 14 15 1E6
r13 14 16 1E6
r14 50 16 1E6
I1 99 15 19.89E-3
I2 50 16 19.89E-3
g5 99 14 11 24 1E-6
g6 14 50 24 11 1E-6
*
* POLE AT 20MHz
*
r15 17 99 1E6
r16 17 50 1E6
c9 17 99 7.96E-15
c10 17 50 7.96E-15
g7 99 17 14 24 1E-6
g8 17 50 24 14 1E-6
*
* POLE AT 50MHz
*
r17 18 99 1E6
r18 18 50 1E6
c11 18 99 3.18E-15
c12 18 50 3.18E-15
g9 99 18 17 24 1E-6
g10 18 50 24 17 1E-6
Table I. SPICE Net List
*
* POLE AT 50MHz
*
r19 19 99 1E6
r20 19 50 1E6
c13 19 99 3.18E-15
c14 19 50 3.18E-15
g11 99 19 18 24 1E-6
g12 19 50 24 18 1E-6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 60kHZ
*
r21 20 21 1E6
r22 20 22 1E6
I3 21 99 2.65
I4 22 50 2.65
g13 99 20 3 24 1.78E-11
g14 20 50 24 3 1.78E-11
*
* POLE AT 50MHZ
*
r23 23 99 1E6
r24 23 50 1E6
c15 23 99 3.18E-15
c16 23 50 3.18E-15
g15 99 23 19 24 1E-6
g16 23 50 24 19 1E-6
*
* OUTPUT STAGE
*
r25 24 99 135E3
r26 24 50 135E3
r27 29 99 70
r28 29 50 70
I5 29 30 4E-7
g17 27 50 23 29 14.3E-3
g18 28 50 29 23 14.3E-3
g19 29 99 99 23 14.3E-3
g20 50 29 23 50 14.3E-3
v4 25 29 .4
v5 29 26 .4
d3 23 25 dx
d4 26 23 dx
d5 99 27 dx
d6 99 28 dx
d7 50 27 dy
d8 50 28 dy
*
MODELS USED
*
• model jx PJF(BETA=1.175E-3 VTO=–2.000 IS=21E-12)
• model dx D(IS=1E-15)
• model dy D(IS=1E-15 BV=50)
• ends OP249
*
*
PSpice is a registered trademark of MicroSim Corporation.
**
HSPICE is a tradename of Meta-Software, Inc.
OP249
–17–REV. D
8-Lead Cerdip
(Q-8)
8
14
5
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.4)
MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX 0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.405 (10.29)
MAX
15ⴗ
0ⴗ
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Terminal Leadless Chip Carrier
(E-20A)
TOP
VIEW
0.358 (9.09)
0.342 (8.69)
SQ
1
20 4
9
8
13
19
BOTTOM
VIEW
14
3
18 0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) BSC
0.200 (5.08)
BSC
0.150 (3.81)
BSC
0.075
(1.91)
REF
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
8-Lead Metal Can (TO-99)
(H-08A)
0.250 (6.35) MIN
0.750 (19.05)
0.500 (12.70)
0.185 (4.70)
0.165 (4.19)
REFERENCE PLANE
0.050 (1.27) MAX
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
0.045 (1.14)
0.010 (0.25)
0.040 (1.02) MAX
BASE & SEATING PLANE
0.335 (8.51)
0.305 (7.75)
0.370 (9.40)
0.335 (8.51)
0.034 (0.86)
0.027 (0.69)
0.045 (1.14)
0.027 (0.69)
0.160 (4.06)
0.110 (2.79)
0.100 (2.54) BSC
6
28
7
5
4
3
1
0.200
(5.08)
BSC
0.100
(2.54)
BSC
45ⴗ BSC
8-Lead Plastic DIP
(N-8)
8
14
5
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
8-Lead Narrow Body (SOIC)
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
85
41
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8°
0°
0.0196 (0.50)
0.0099 (0.25)x 45°
C00296a–0–9/00 (rev. D)
PRINTED IN U.S.A.