HARRIS SEMICOND SECTOR a ) SEMICONDUCTOR bLE D MM@ 4302271 0047057 211 MBHAS CA555, LM555 Timers for Timing Delays and Oscillator Applications March 1993 in Commercial, Industrial and Military Equipment Features Description : pennies eee from Microsecoms through Hours The CA555 and CASS5C are highly stable timers for use in . Adjustable D rcvele je Operation precision timing and oscillator applications. As timers, these * Output Ca able of Sourcin or Sinking up to 200mA monolithic integrated circuits are capable of producing accu- -O out c able of Drivin hel Devices P rate time delays for periods ranging from microseconds . Nornalt ON and OFF Ow, uts through hours. These devices are also useful for astable * High Tempe rature Stablity, 0.005%C oscillator operation and can maintain an accurately con- * cicectly Interchangeable with SE5S5, NESS . trolled free running frequency and duty cycle with only two Directly Interchangeable with SE555, NE555, MC 1555, external resistors and one capacitor. A p plications The circuits of the CA555 and CA555C may be triggered by the falling edge of the waveform signal, and the output of these circuits can source or sink up to a 200mA current or drive TTL circuits. Precision Timing Sequential Timing * Time Delay Generation Pulse Generation Pulse Detector Pulse Width and Position Modulation These types are direct replacements for industry types in packages with similar terminal arrangements e.g. SE555 Ordering Information and NE555, MC1555 and MC1455, respectively. The CA555 type circuits are intended for applications requiring premium PART NO. TEMP. RANGE PACKAGE electrical performance. The CAS555C type circuits are CA0555E -55C to +125C | 8 Lead Plastic DIP intended for applications requiring less stringent electrical CA0555M -55C to +125C =| 8 Lead SOIC characteristics. CAQSSSM96 55C to +128C 8 Lead SOIC Technical data on LM branded types is identical to the corre- CAO555T -55C to +125C [8 Pin TO-5 Matal Can sponding CA branded types. CA0555CE 0C to +70C 8 Lead Plastic DIP CA0555CM 0C to +70C 8 Lead SOIC CA0555CM96 0C to +70C 8 Lead SOIC* CA0555CT 0C to +70C 8 Pin TO-5 Metal Can LM555N OC to +70C _ | 8 Lead Plastic DIP ~~ LM555CN 0C to +70C 8 Lead Plastic DIP * Denotes Tape and Reel 8 an Pinouts Functional Diagram 25 CAS555, CA555C, LMS555C (PDIP, SOIC) a f TOP VIEW Ye conrmon <mmusser oe 7 @) CONTROL & o GND Gd ral v+ y vorrace @ a triaaer [2] 17] DISCHARGE + output FBI 6] THRESHOLD T RESET [4] 5] CONTROL a , TRIGGER :-G) E VOLTAGE : O THRESHOLD 7 COMPAR TO-5 Style Package with Formed Leads | compas I y CAS55, CAS55C, LMS55C (METAL CAN) > L$ TOP VIEW = 1 3 dr 4 FLIP-FLOP Ww GND RESET CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. FileNumber 834.2 Copyright Harris Corporation 1993 7-3HARRIS SEMICOND SECTOR bLE D MM 4302271 0047058 158 MBHAS Specifications CA555, CA555C, LM555 Absolute Maximum Ratings Operating Conditions DC Supply Voltage 0.2.2... cece c cece cree ceseuece 18V Operating Temperature Range Power Dissipation CASES ook ec cece cece eceecenseus -65C to +125C Upto Ty= 455 oo cece e eee c ees 600mWw CASSSC.. occ cece cece cena sce e nes 0C to +70C Above Ty = +55C. 0... Derate Linearly SmWPC Storage Temperature Range.............6.00. -B5C to +150C Junction Temperature... cee c cee c ee eees +175C Junction Temperature (Plastic Packages)...........000. +150C Lead Temperature (Soldering 10 Sec.)...........00000. +300C CAUTION: Stresses above those listed in Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this Specification Is not implied. Electrical Specifications _T, = +25C, V+. = 5V to 15V Unless Otherwise Specified LIMITS CASSS CAS55C PARAMETER SYMBOL TEST CONDITIONS MIN | TYP |] MAX | MIN | TYP | MAX | UNITS DC Supply Voltage V+ 45 : 18 45 : 16 v OC Supply Current (Low State), 1+ V+ = 5V, Ry = oe - 3 - 3 6 mA Note 1 V+ = 15V, Al = 00 - | wo] 2]. 10 | 15 [ ma Threshold Voltage Vm - [vel - - [Ave] - Vv Trigger Voltage V+ =5V 1.45 | 1.67 1.9 - 1.67 : Vv V+ = 15V 48 5 5.2 : 5 - v Trigger Current - 0.5 - - 0.5 - pA Threshold Current, Note 2 Ity . 0.1 0.25 . 01 0.25 pA Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 v Reset Current : 0.1 - - 0.1 - mA Control Voitage Level V+ =5V 2.9 3.33 3.8 2.6 3.33 4 v V+ = 15V 9.6 10 10.4 9 10 1 v Output Voltage Vo V+ = 5Y, Ising = SMA - - . - 0.25 | 0.35 v Low State Igink = 8MA - 0.1 | 0.25 - - - v V+ = 15V, ln = 10mA - O1 O15] - 0.1 | 0.25 v lank = SOMA - | 04 | Os : 04 | 075 f Vv Isiuk = 100mA - 20 | 22 - 20 | 0.5 Vv tginxk = 200MA - 2.5 - - 25 - Vv Quiput Voltage Vou | V+=5V, Isournce = 100mA] 3.0 3.3 : 2.75 | 3.3 : v High State V+ = 15V, Isource = 13.0 / 133, - J1275}1a3] - v 100mA lsource = 200mA . 12.5 - 12.5 . Vv Timing Error (Monostable) Ry, Ro = 1k to 100kQ, - 0.5 2 - 1 - % Frequency Drift with Temperature sv, v Hf ve tod at V+ = - 30 100 - 50 - ppm Drift with Supply Voltage - 0.05 | 0.2 - 0.41 - HIN Output Rise Time tp . 100 - . 100 - ns Output Fall Time tr - 100 - - 100 - ns NOTES: 1. When the output is in a high state, the DC supply current is typically 1mA less than the low state value. 2. RY Re 20M purrent will determine the sum of the values of R, and R, to be used in Figure 14 (astable operation); the maximum total 7-4HARRIS SEMICOND SECTOR bLE D MM 4302271 0047059 O94 MMHAS CA555, CA555C, LM555 Schematic Diagram CA555 AND CASSSC THRESHOLD TRIGGER COMPARATOR COMPARATOR 4.7K $30 4.7K 1K 01 DISCHARGE 100 RESISTANCE VALUES ARE IN 2 i 8 Typical Performance Curves z E Z@ o0 a 150 z _ a F - = 100 a 8 & > > a 9 = 3 2 so & z > = C7 0 0.1 0.2 0.3 0.4 MINIMUM TRIGGER (PULSE) VOLTAGE (x V+)* o 385 5 euppuy VOLTAGE ws 8 *Where x is the decimal multiplier of the supply voltage ) FIGURE 1. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER FIGURE 2. SUPPLY CURRENT vs SUPPLY VOLTAGE VOLTAGE 75HARRIS SEMICOND SECTOR bE D MM 4302271 DO47060 806 MMHAS CA555, CA555C, LM555 Typical Performance Curves w ea = a is 2 a 2 > BV< Vis 15V SUPPLY VOLTAGE - OUTPUT VOLTAGE (V) 10 100 SOURCE CURRENT (mA) -_ FIGURE 3. OUTPUT VOLTAGE DROP (HIGH STATE) vs SOURCE CURRENT 10.0 V+ 2 10V = a +4125C 425C e = OUTPUT VOLTAGE - LOW STATE (V) 2 = 10 SINK CURRENT (mA) FIGURE 5. OUTPUT VOLTAGE LOW STATE vs SINK CURRENT AT V+ = 10V 1.400 , Ty = 425C i = E x x 5 1.000 ~ Qa Qo Ww Z 2 0.990 S z 6.980 o 625 5 758 10 125 18 175 SUPPLY VOLTAGE (V) FIGURE 7. DELAY TIME vs SUPPLY VOLTAGE = 2 2 = z 1.0 7 g _ 0.41 0.01 1 10 100 SINK CURRENT (mA) FIGURE 4. OUTPUT VOLTAGE LOW STATE vs SINK CURRENT AT V+ = 5V 10.0 = B & z 1.0 - g Boas e E 0.014 10 100 SINK CURRENT (mA) FIGURE 6. OUTPUT VOLTAGE LOW STATE vs SINK CURRENT AT V+ = 15V mw = E > a Q 1,005 a 5 = & 0.995 z 0985 30 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (C) FIGURE 8. DELAY TIME vs TEMPERATURE 7-6HARRIS SEMICOND SECTOR BLE D MM 4302271] OO47061 742 BBHAS CA555, CA555C, LM555 Typical Performance Curves wz wo 2 F 250 % 200 & & 150 E q 400 oc 3 425C = 50 +70C. 125C 0 0.1 0.2 0.3 04 MINIMUM TRIGGER (PULSE) VOLTAGE (x V+}* *Where x is the decimal multiplier of the supply voltage FIGURE 9. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE Typical Applications Figure 11 shows the typical waveforms generated during this mode of operation, and Figure 12 gives the family of time Reset Timer (Monostable Operation) delay curves with variations in R, and Cy. Figure 10 shows the CA555 connected as a reset timer. In this mode of operation capacitor Cr is initially held discharged by SWITCH $1 OPEN a transistor on the integrated circuit. Upon closing the start av . nae . INPUT switch, or applying a negative trigger pulse to terminal 2, the VOLTAGE (TERMINAL 2) integral timer flip-flop is set and releases the short circut SWITCH $1 CLOSED across Cy which drives the output voltage high (relay ener- . gized). The action allows the voltage across the capacitor to BBV cnenesneeceecesenesstnscnnsnsnaennnrenneeeey increase exponentially with the constant t = R,C;. When the CAPACITOR voltage across the capacitor equals 2/3 V+, iC comparator VOLTAGE eile 8.7) resets the flip-flop which in turn discharges the capacitor rap- tp idly and drives the output to its low state. ALL RESISTANCE VALUES ARE IN 0 = FIGURE 10. RESET TIMER (MONOSTABLE OPERATION) RESET wv os L OUTPUT SR 2 680 VOLTAGE g (TERMINAL 3) 3 op < 9 ZE <3 t FIGURE 11. TYPICAL WAVEFORMS FOR RESET TIMER a HN4001 oo < ui S 10K & RELAY | = 100 T 7mCy S eso Get Ty = 425C y y 5 0.01pF> V+ = 5V we 4 yf FP 1 Ry = 1k VA L L) Z 10k2 yo N IN N ALK, CAPACITANCE (uF) Since the charge rate and threshold level of the comparator o "4 7 v 7 somo are both directly proportional to V+, the timing interval is rel- 1) A J) 1 atively independent of supply voltage variations. Typically, 0.01 the timing varies only 0.05% for a 1V change in V+. 7 7 7 Applying a negative pulse simultaneously to the reset termi- / / / nal (4) and the trigger terminal (2) during the timing cycle one 404 10 102 107 1 40 discharges C,; and causes the timing cycle to restart. TIME DELAY(a) Momentarily closing only the reset switch during the timing interval discharges Cy, but the timing cycle does not restart. FIGURE 12. TIME DELAY vs RESISTANCE AND CAPACITANCE SSHARRIS SEMICOND SECTOR BLE D M@ 4302271 OO470be 644 MMHAS CA555, CA555C, LM555 Repeat Cycle Timer (Astable Operation) Figure 13 shows the CA555 connected as a repeat cycle timer. In this mode of operation, the total period is a function of both Ry and Ro. 2 7F 0.01F FIGURE 13. REPEAT CYCLE TIMER (ASTABLE OPERATION) T = 0.693 (Ry + 2Ra) Cr =t, + ty where t, = 0.693 (R; + Re) Cy and tz = 0.693 (Ra) Cy the duty cycle is: ty RY HR, tytt, Ry +2Ry Typical waveforms generated during this mode of operation are shown in Figure 14. Figure 15 gives the family of curves of free running frequency with variations in the value of (Ry + 2Ro) and Cr. sv 3.3V 1.7V Top Trace: Output voltage (2V/div. and 0.5ms/div.) Bottom Trace: Capacitor voltage (1V/div. and 0.5ms/div.) FIGURE 14. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER t T N\ IN \ Ty = 425C, V+ = 5V X X Ne 100 LA CAPACITANCE (uF) y 7 VA) MW So cJ = NAN 10? 103 104 105 FREQUENCY (Hz) FIGURE 15. FREE RUNNING FREQUENCY OF REPEAT CYCLE TIMER WITH VARIATION IN CAPACITANCE AND RESISTANCE VA 0.001 to7 1 10