LTC4261/LTC4261-2
1
42612fd
For more information www.linear.com/LTC4261
Negative Voltage
Hot Swap Controllers with
ADC and I2C Monitoring
The LT C
®
4261/LTC4261-2 negative voltage Hot Swap
TM
controllers allow a board to be safely inserted and removed
from a live backplane. Using an external N-channel pass
transistor, the board supply voltage can be ramped at an
adjustable rate. The devices feature independently adjust-
able inrush current and overcurrent limits to minimize
stresses on the pass transistor during start-up, input
step and output short conditions. The L
TC4261 defaults
to latch-off while the L
TC4261-2 defaults to auto-retry on
overcurrent faults.
An I2C interface and onboard 10-bit ADC allow monitoring
of board current, voltage and fault status. A single-wire
broadcast mode is available to simplify the interface by
eliminating two optoisolators.
The controllers have additional features to interrupt the
host when a fault has occurred, notify when output power
is good, detect insertion of a board and turn off the pass
transistor if an external supply monitor fails to indicate
power good within a timeout period.
n AdvancedTCA Systems
n Telecom Infrastructure
n –48V Distributed Power Systems
n Power Monitors
n Allows Safe Insertion into Live –48V Backplanes
n 10-Bit ADC Monitors Current and Voltages
n I2C/SMBus Interface or Single-Wire Broadcast Mode
n Floating Topology Allows Very High Voltage
Operation
n Independently Adjustable Inrush and Overcurrent
Limits
n Controlled Soft-Start Inrush
n Adjustable UV/OV Thresholds and Hysteresis
n Sequenced Power Good Outputs with Delays
n Adjustable Power Good Input Timeout
n Programmable Latchoff or Auto-Retry After Faults
n Alerts Host After Faults
n Available in 28-Lead Narrow SSOP and 24-Lead
(4mm × 5mm) QFN Packages
–48V/200W Hot Swap Controller with I2C and ADC
+
PGI
ALERT
SDAO
SDAI
SCL
ADIN
PGIO
PG
UVL
UVH
ADIN2
OV
INTVCC
ON
RAMPDRAINGATE
LTC4261CGN
VIN
VEE
ENTMRSS SENSE
1M
4 × 1k IN SERIES
1/4W EACH
453k
1%
–48V RTN
–48V INPUT
UV = 38.5V
UV RELEASE
AT 43V
OV RELEASE
AT 71V
OV = 72.3V
16.9k
1%
11.8k
1%
10nF
100V
5%
47nF0.1µF
1µF 220nF 47nF
0.008Ω
1%
10Ω
VOUT
Q1
IRF1310NS
1k
330µF
100V
LOAD
ON
42612 TA01
VIN+
VIN–
Start-Up Behavior
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
–48V INPUT
50V/DIV
VOUT
50V/DIV
SENSE
0.5A/DIV
PG
50V/DIV
10ms/DIV 42612 TA01b
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners. Protected by U.S. Patents, including 7382167, 8194379, 8230151.
LTC4261/LTC4261-2
2
42612fd
For more information www.linear.com/LTC4261
VIN (Note 3) .......................................... –0.3V to 10.65V
Drain (Note 4) .......................................... –0.3V to 3.5V
PGI, ON, ALERT, SDAO, SDAI, SCL, ADIN, ADIN2,
OV, SENSE, ADR1, ADR0, FLTI N , TMR,
SS, RAMP Voltages ...................–0.3V to INTVCC + 0.3V
UVL, UVH, EN ............................................ –0.3V to 10V
GATE Voltage .................................. –0.3V to VIN + 0.3V
PG, PGIO Voltages .................................... –0.3V to 80V
Supply Voltage (INTVCC) .......................... –0.3V to 5.5V
(Notes 1, 2)
Operating Ambient Temperature Range
LTC4261C ................................................ 0°C to 70°C
LTC4261I .............................................–40°C to 85°C
Storage Temperature Range
SSOP ................................................. –65°C to 150°C
QFN .................................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
SSOP Only ........................................................ 300°C
ABSOLUTE MAXIMUM RATINGS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
GN PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGI
ON
ALERT
SDAO
SDAI
SCL
INTV
CC
UVL
UVH
ADIN2
OV
NC
VEE
SENSE
PGIO
PG
EN
ADR1
ADR0
ADIN
FLTIN
VIN
TMR
SS
RAMP
NC
DRAIN
GATE
TJMAX = 125°C, θJA = 85°C/W
8 9
TOP VIEW
25
UFD PACKAGE
24-LEAD (4mm
×
5mm) PLASTIC QFN
10 11 12
24 23 22 21 20
6
5
4
3
2
1
SDAO
SDAI
SCL
INTV
CC
UVL
UVH
OV
EN
ADR1
ADR0
ADIN
VIN
TMR
SS
ALERT
ON
PGI
PGIO
PG
VEE
SENSE
GATE
DRAIN
RAMP
7
14
15
16
17
18
19
13
TJMAX = 125°C, θJA = 45°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4261CGN#PBF LTC4261CGN#TRPBF LTC4261CGN 28-Lead Plastic SSOP 0°C to 70°C
LTC4261IGN#PBF LTC4261IGN#TRPBF LTC4261IGN 28-Lead Plastic SSOP –40°C to 85°C
LTC4261CGN-2#PBF LTC4261CGN-2#TRPBF LTC4261IGN-2 28-Lead Plastic SSOP 0°C to 70°C
LTC4261IGN-2#PBF LTC4261IGN-2#TRPBF LTC4261IGN-2 28-Lead Plastic SSOP –40°C to 85°C
LTC4261CUFD#PBF LTC4261CUFD#TRPBF 4261 24-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C
LTC4261IUFD#PBF LTC4261IUFD#TRPBF 4261 24-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
LTC4261CUFD-2#PBF LTC4261CUFD-2#TRPBF 42612 24-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C
LTC4261IUFD-2#PBF LTC4261IUFD-2#TRPBF 42612 24-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC4261/LTC4261-2
3
42612fd
For more information www.linear.com/LTC4261
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at IIN = 5mA, TA = 25°C. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
General
VZShunt Regulator Voltage at VIN IIN = 5mA l10.65 11.2 11.8 V
DVZShunt Regulator Load Regulation IIN = 5mA to 25mA l370 600 mV
IIN VIN Supply Current VIN = VZ – 0.3V l2 5 mA
VIN(UVLO) VIN Undervoltage Lockout Threshold VIN Rising l8.5 9 9.5 V
DVIN(UVLO) VIN Undervoltage Lockout Hysteresis l0.3 0.7 1 V
INTVCC Internal Regulator Voltage ILOAD = 1mA to 20mA, IIN = 25mA l4.75 5 5.25 V
Gate Drive
VGATEH GATE Pin Output High Voltage VIN = 10.65V l10 10.25 10.5 V
IGATE(UP) GATE Pin Pull-Up Current VGATE = 4V l–7.5 –11.5 –15.5 µA
IGATE(OFF) GATE Turn-Off Current VSENSE = 400mV, VGATE = 4V l45 90 120 mA
Gate Off, VGATE = 4V l60 110 140 mA
tPHL(SENSE) SENSE High to Current Limit VSENSE = 100mV, GATE Open l0.5 1.5 µs
Propagation Delay VSENSE = 300mV, GATE Open l0.2 0.5 µs
tPHL(GATE) GATE Off Propagation Delay Input High (OV, EN, PGI), Input Low (ON, UVL),
GATE Open
l0.2 0.5 µs
tPHLCB Circuit Breaker Gate Off Delay VGATE < 2V, GATE Open l440 530 620 µs
IRAMP RAMP Pin Current VSS = 2.56V l–18 –20 –22 µA
VSS SS Pin Clamp Voltage l2.43 2.56 2.69 V
ISS(UP) SS Pin Pull-Up Current VSS = 0V l–7 –10 –13 µA
ISS(DN) SS Pin Pull-Down Current VSS = 2.56V l6 12 20 mA
Input Pins
VUVH(TH) UVH Threshold Voltage VUVH Rising LTC4261C
LTC4261I
l
l
2.534
2.522
2.56
2.56
2.586
2.598
V
VUVL(TH) UVL Threshold Voltage VUVL Falling LTC4261C
LTC4261I
l
l
2.263
2.254
2.291
2.291
2.319
2.328
V
DVUV(HYST) Built-In UV Hysteresis UVH and UVL Tied Together l256 269 282 mV
dVUV UVH, UVL Minimum Hysteresis 15 mV
VUVLR(TH) UVL Reset Threshold Voltage VUVL Falling l1.12 1.21 1.30 V
DVUVLR(HYST) UVL Reset Hysteresis 60 mV
VOV(TH) OV Pin Threshold Voltage VOV Rising LTC4261C
LTC4261I
l
l
1.744
1.735
1.770
1.770
1.796
1.805
V
DVOV(HYST) OV Pin Hysteresis l18 37.5 62 mV
DVSENSE Current Limit Sense Voltage Threshold VSENSE – VEE l45 50 55 mV
VINPUT(TH) ON, EN, PGI, FLTIN Threshold Voltage ON, EN, PGI, FLTIN Falling or Rising l0.8 1.4 2 V
DVINPUT(HYST) ON, EN, PGI, FLTIN Hysteresis 170 mV
VPGIO(TH) PGIO Pin Input Threshold Voltage VPGIO Rising l1.10 1.25 1.40 V
DVPGIO(HYST) PGIO Pin Input Hysteresis 100 mV
IINPUT ON, EN, UVH, UVL, OV, SENSE, PGI,
FLTIN Input Current
ON, EN, UVH, UVL, OV, SENSE, PGI, FLTIN = 3V l0 ±2 µA
ELECTRICAL CHARACTERISTICS
LTC4261/LTC4261-2
4
42612fd
For more information www.linear.com/LTC4261
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Timer
VTMR(H) TMR Pin High Threshold VTMR Rising l2.43 2.56 2.69 V
VTMR(L) TMR Pin Low Threshold VTMR Falling l40 75 110 mV
ITMR(UP) TMR Pin Pull-Up Current Turn-On and Auto-Retry (Except OC) Delays,
VTMR = 0.2V
l–7 –10 –13 µA
Power Good, PGI Check and OC Auto-Retry
Delays, VTMR = 0.2V
l–3.5 –5 –6.5 µA
ITMR(DN) TMR Pin Pull-Down Current Delays Except PGI Check or OC Auto-Retry,
VTMR = 2.56V
l6 12 20 mA
PGI Check and OC Auto-Retry Delays,
VTRM = 2.56V
l3 5 7 µA
Output Pins
VPWRGD PG, PGIO Pins Output Low IPG, IPGIO = 3mA
IPG, IPGIO = 500µA
l
l
0.8
0.15
1.6
0.4
V
V
IPWRGD PG, PGIO Pins Leakage Current PG, PGIO = 80V l0 ±10 µA
ADC
Resolution (No Missing Codes) (Note 5) l10 Bits
INL Integral Nonlinearity SENSE l±0.5 ±2.5 LSB
ADIN2/OV, ADIN l±0.25 ±1.25 LSB
VOS Offset Error SENSE l±1.75 LSB
ADIN2/OV, ADIN l±1.25 LSB
Full-Scale Voltage SENSE l62.8 64 65.2 mV
ADIN2/OV, ADIN l2.514 2.560 2.606 V
Total Unadjused Error SENSE l±1.8 %
ADIN2/OV, ADIN l±1.6 %
Conversion Rate l5.5 7.3 9 Hz
RADIN ADIN, ADIN2 Pins Input Resistance ADIN, ADIN2 = 1.28V l2 10 MW
IADIN ADIN, ADIN2 Pins Input Current ADIN, ADIN2 = 2.56V l0 ±2 µA
I2C Interface
VADR(H) ADR0, ADR1 Input High Threshold lINTVCC
– 0.8
INTVCC
– 0.5
INTVCC
– 0.3
V
VADR(L) ADR0, ADR1 Input Low Threshold l0.3 0.5 0.8 V
IADR(IN) ADR0, ADR1 Input Current ADR0, ADR1 = 0V, 5V l±80 µA
ADR0, ADR1 = 0.8V, (INTVCC – 0.8V) l±10 µA
VALERT(OL) ALERT Pin Output Low Voltage IALERT = 4mA l0.2 0.4 V
VSDAO(OL) SDAO Pin Output Low Voltage ISDAO = 4mA l0.2 0.4 V
ISDAO,ALERT(IN) SDAO, ALERT Input Current SDAO, ALERT = 5V l0 ±5 µA
VSDAI,SCL(TH) SDAI, SCL Input Threshold l1.6 1.8 2 V
ISDAI,SCL(IN) SDAI, SCL Input Current SDAI, SCL = 5V l0 ±2 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at IIN = 5mA, TA = 25°C. (Note 2)
ELECTRICAL CHARACTERISTICS
LTC4261/LTC4261-2
5
42612fd
For more information www.linear.com/LTC4261
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I2C Interface Timing (Note 5)
fSCL(MAX) Maximum SCL Clock Frequency 400 kHz
tLOW Minimum SCL Low Period 0.65 1.3 µs
tHIGH Minimum SCL High Period 50 600 ns
tBUF(MIN) Minimum Bus Free Time Between Stop/
Start Condition
0.12 1.3 µs
tHD,STA(MIN) Minimum Hold Time After (Repeated)
Start Condition
140 600 ns
tSU,STA(MIN) Minimum Repeated Start Condition
Set-Up Time
30 600 ns
tSU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns
tHD,DATI(MIN) Minimum Data Hold Time Input –100 0 ns
tHD,DATO(MIN) Minimum Data Hold Time Output 300 600 900 ns
tSU,DAT(MIN) Minimum Data Set-Up Time Input 30 100 ns
tSP(MAX) Maximum Suppressed Spike Pulse
Width
50 110 250 ns
tRST Stuck-Bus Reset Time SCL or SDAI Held Low 25 66 ms
CX SCL,SDA Input Capacitance SDAI Tied to SDAO 5 10 pF
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at IIN = 5mA, TA = 25°C. (Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
device GND (VEE) unless otherwise specified.
Note 3: An internal shunt regulator limits the VIN pin to a minimum of
10.65V. Driving this pin to voltages beyond 10.65V may damage the part.
The pin can be safely tied to higher voltages through a resistor that limits
the current below 50mA.
Note 4: An internal clamp limits the DRAIN pin to a minimum of 3.5V.
Driving this pin to voltages beyond the clamp may damage the part. The
pin can be safely tied to higher voltages through a resistor that limits the
current below 2mA.
Note 5: Guaranteed by design and not subject to test.
ELECTRICAL CHARACTERISTICS
LTC4261/LTC4261-2
6
42612fd
For more information www.linear.com/LTC4261
Shunt Regulator Voltage
vs Input Current
Shunt Regulator Voltage
vs Temperature INTVCC vs Load Current
GATE Output High Voltage
vs Temperature
GATE Pull-Up Current
vs GATE Voltage
RAMP Pin Current vs Temperature UVH Threshold vs Temperature UVL Threshold vs Temperature
IIN = 5mA, TA = 25°C, unless otherwise noted
SHUNT REGULATOR VOLTAGE AT VIN (V)
10.8
0
V
IN
PIN INPUT CURRENT (mA)
5
10
15
20
25
30
11 11.2 11.4 11.6
42612 G01
11.8
TEMPERATURE (°C)
–50
11.10
SHUNT REGULATOR VOLTAGE AT V
IN
(V)
11.15
11.20
11.25
11.30
11.35
–25 0 25 50
42612 G02
75
100
IIN = 5mA
LOAD CURRENT (mA)
0
INTV
CC
VOLTAGE (V)
5.00
5.02
20
42612 G03
4.98
4.96 510 15
5.06
5.04
IIN = 25mA
TEMPERATURE (°C)
–50
10.0
GATE OUTPUT HIGH VOLTAGE (V)
10.1
10.2
10.3
10.4
–25 0 25 50
42612 G04
75
100
10.5
VIN = 10.65V
GATE Turn-Off Current
vs SENSE Voltage
TEMPERATURE (°C)
–50
2.545
UVH THRESHOLD VOLTAGE (V)
2.550
2.555
2.560
2.565
2.575
–25 0 25 50
42612 G08
75
100
2.570
TEMPERATURE (°C)
–50
2.275
UVH THRESHOLD VOLTAGE (V)
2.280
2.285
2.290
2.295
2.305
–25 0 25 50
42612 G09
75
100
2.300
GATE VOLTAGE (V)
0
–12
GATE PULL-UP CURRENT (µA)
–2
–4
–6
–8
0
24 6 8
42612 G05
10 12
–10
TEMPERATURE (°C)
–50
–19.0
RAMP PIN CURRENT (µA)
–19.5
–20.0
–20.5
–21.0
–22.0
–25 0 25 50
42612 G07
75
100
–21.5
TYPICAL PERFORMANCE CHARACTERISTICS
VSENSE (mV)
I
GATE(OFF)
(mA)
100
42612 G06
1
10
100 500400300200
0
VGATE = 4V
LTC4261/LTC4261-2
7
42612fd
For more information www.linear.com/LTC4261
OV Threshold vs Temperature OV Hysteresis vs Temperature
Current Limit Voltage
vs Temperature
Current Limit Propagation Delay
(tPHL(SENSE)) vs VSENSE
PG, PGIO Output Low
vs Load Current
ADC Total Unadjusted Error
vs Code (ADIN Pin)
ADC Full-Scale Error vs
Temperature (ADIN Pin) ADC INL vs Code (ADIN Pin) ADC DNL vs Code (ADIN Pin)
IIN = 5mA, TA = 25°C, unless otherwise noted
TEMPERATURE (°C)
–50
1.755
OV THRESHOLD VOLTAGE (V)
1.760
1.765
1.770
1.775
1.785
–25 0 25 50
42612 G10
75
100
1.780
TEMPERATURE (°C)
–50
25
OV HYSTERESIS (mV)
30
35
40
45
50
–25 0 25 50
42612 G11
75 100
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–50
49.0
CURRENT LIMIT SENSE VOLTAGE (mV)
49.5
50.0
50.5
51.0
52.0
–25 0 25 50
42612 G12
75
100
51.5
VSENSE (mV)
0
t
PHL(SENSE)
(ns)
400
42612 G13
100 100 200 300
500
1000
CGATE = 1pF
LOAD CURRENT (mA)
0
0
PG OUTPUT LOW VOLTAGE (V)
1
2
3
4
5
6
2 4 6 8
42612 G14
10
TA = 85°C
TA = 25°C
TA = –40°C
CODE
0
ADC TOTAL UNADJUSTED ERROR (LSB)
0
0.5
1024
42612 G15
–0.5
–1.0 256 512 768
1.0
TEMPERATURE (°C)
–50
–3
ADC FULL-SCALE ERROR (LSB)
–2
–1
0
1
3
–25 0 25 50
42612 G16
75
100
2
CODE
0
ADC INL (LSB)
0
0.5
1024
42612 G17
–0.5
–1.0 256 512 768
1.0
CODE
0
ADC DNL (LSB)
0
0.5
1024
42612 G18
–0.5
–1.0 256 512 768
1.0
LTC4261/LTC4261-2
8
42612fd
For more information www.linear.com/LTC4261
ADIN (Pin 23/Pin 16): ADC Input. A voltage between 0V
and 2.56V applied to this pin is measured by the on-chip
ADC. Tie to VEE if unused.
ADIN2 (Pin 10/NA): Second ADC Input. Not available on
QFN package.
ADR0, ADR1 (Pins 24, 25/Pins 17, 18): Serial Bus Ad-
dress Inputs. Tying these pins to VEE, OPEN or INTVCC
configures one of nine possible addresses. See Table 1
in Applications Information.
ALERT (Pin 3/Pin 24): Fault Alert Output. Open-drain logic
output that pulls to VEE when a fault occurs to alert the host
controller. A fault alert is enabled by the ALERT register.
See Applications Information. Connect to VEE if unused.
DRAIN (Pin 16/Pin 11): Drain Sense Input. Connect an
external 1M resistor between this pin and the drain terminal
(VOUT) of the N-channel FET. When the DRAIN pin volt-
age is less than 1.77V and the GATE pin voltage is above
VZ
– 1.2V the power good outputs are asserted after a
delay. The voltage at this pin is internally clamped to 4V.
EN (Pin 26/Pin 19): Device Enable Input. Pull low to enable
the N-channel FET to turn-on after a start-up debounce
delay set by the TMR pin. When this pin is pulled high, the
FET is off. Transitions on this pin will be recorded in the
FAULT register. A high-to-low transition activates the logic
to read the state of the ON pin and clear faults. Requires
external pull-up. Debouncing with an external capacitor
is recommended when used to monitor board present.
Connect to VEE if unused.
Exposed Pad (Pin 25, QFN Only): Exposed Pad may be
left open or connected to device ground (VEE).
FLTIN (Pin 22/NA): General Purpose Fault Input. If this
pin pulls low, the FAULT register bit B7 is latched to “1.”
This pin is used to sense an external fault condition and
its status does not affect the FET control functions of the
LTC4261. Not available on the QFN package. Connect to
INTVCC if unused.
GATE (Pin 15/Pin 10): N-Channel FET Gate Drive Output.
This pin is pulled up by an internal current source IGATE
(11.5µA when the SS pin reaches its clamping voltage).
GATE stays low until VIN and INTVCC cross the UVLO
thresholds, UV and OV conditions are satisified and an
adjustable timer delay expires. During turn-off, caused by
faults or undervoltage lockout (VIN or INTVCC), a 110mA
pull-down current between GATE and VEE is activated.
INTVCC (Pin 7/Pin 4): Low Voltage (5V) Supply Output.
This is the output of the internal linear regulator with an
internal UVLO threshold of 4.25V. This voltage powers up
the data converter and logic control circuitry. Bypass this
pin with a 0.1µF capacitor to VEE.
ON (Pin 2/Pin 23): On Control Input. A rising edge turns
on the external N-channel FET while a falling edge turns it
off. This pin is also used to configure the state of the FET
ON register bit D3 in the CONTROL register (and hence
the external FET) at power-up. For example if the ON pin
is tied high, then the register bit D3 goes high one timer
cycle after power-up. Likewise, if the ON pin is tied low, then
the device remains off after power-up until the register bit
D3 is set high using the I2C bus. A high-to-low transition
on this pin clears faults.
OV (Pin 11/Pin 7): Overvoltage Detection Input. Connect
this pin to an external resistive divider from VEE. If the
voltage at the pin rises above 1.77V, the N-channel FET is
turned off. The overvoltage condition does not affect the
status of the power good outputs. On the QFN package,
this pin is also measured by the on-chip ADC. Connect
to VEE if unused.
PG (Pin 27/Pin 20): Power Good Status Output. This open-
drain pin pulls low and stays latched a timer delay after
the FET is on (when GATE reaches VZ – 1.2V and DRAIN
is within 1.77V of VEE). The power good output is reset
in all GATE pull-down events except an overvoltage fault.
Connect to VEE if unused.
PIN FUNCTIONS
(SSOP/QFN)
LTC4261/LTC4261-2
9
42612fd
For more information www.linear.com/LTC4261
PGI (Pin 1/Pin 22): Power Good Input. This pin along with
the PGI check timer serves as a watchdog to monitor the
power-up of the DC/DC converter. The PGI pin must be low
before the PGI check timer expires, otherwise the GATE
pin pulls down and stays latched and a power bad fault
is logged into the FAULT register. The PGI timer is started
after the second power good is latched and its delay is
equal to four times the start-up debounce delay. Connect
to VEE if unused.
PGIO (Pin 28/Pin 21): General Purpose Input/Output.
Open-drain logic output and logic input. Defaults to pull
low a timer delay after the PG pin goes low to indicate a
second power good output. Configure according to Table 6.
RAMP (Pin 18/Pin 12): Inrush Current Ramp Control
Pin. The inrush current is set by placing a capacitor (CR)
between the RAMP pin and the drain terminal of the FET.
At start-up, the GATE pin is pulled up by IGATE(UP) until the
pass transistor begins to turn on. A current, IRAMP, then
flows through CR to ramp down the output voltage VOUT.
The value of IRAMP is controlled by the SS pin voltage.
When the SS pin reaches its clamp voltage (2.56V), IRAMP
= 20µA. The ramp rate of VOUT and the load capacitor CL
set the inrush current: IINRUSH = (CL/CR) • IRAMP.
SCL (Pin 6/Pin 3): Serial Bus Clock Input. Data at the
SDAI pin is shifted in and data at the SDAO pin is shifted
out on rising edges of SCL. This is a high impedance pin
that is generally connected to the output of the incoming
optoisolator driven by the SCL port of the master controller.
An external pull-up resistor or current source is required.
Pull up to INTVCC if unused.
SDAI (Pin 5/Pin 2): Serial Bus Data Input. This is a high
impedance input pin used for shifting in command bits,
data bits and SDAO acknowledge bits. An external pull-up
resistor or current source is required. Normally connected
to the output of the incoming optoisolator that is driven
by the SDA port of the master controller. If the master
controller separates SDAI and SDAO, data read at SDAO
needs to be echoed back to SDAI for proper I2C commu-
nication. Pull up to INTVCC if unused.
SDAO (Pin 4/Pin 1): Serial Bus Data Output. Open-drain
output used for sending data back to the master controller
or acknowledging a write operation. An external pull-up
resistor or current source is required. Normally connected
to the input of the outgoing optoisolator that outputs to
the SDA port of the master controller. In the single-wire
broadcast mode, the SDAO pin sends out selected data
that is encoded with an internal clock.
SENSE (Pin 14/Pin 9): Current Limit Sense Input. Load
current through the external sense resistor (RS) is moni-
tored and controlled by an active current limit amplifier
to 50mV/RS. Once VSENSE reaches 50mV, a circuit breaker
timer starts and turns off the pass transistor after 530µs. In
the event of a catastrophic short circuit, if VSENSE crosses
250mV, a fast response comparator immediately pulls the
GATE pin down to control the current of the N-channel FET.
SS (Pin 19/Pin 13): Soft-Start Input. Connect a capaci-
tor to this pin to control the rate of rise of inrush current
(dI/dt) during start-up. An internal 10µA current source
charging the external soft-start capacitor (CSS) creates
a voltage ramp. This voltage is converted to a current to
charge the GATE pin up and to ramp the output voltage
down. The SS pin is internally clamped to 2.56V limiting
IGATE(UP) to 11.5µA and IRAMP to 20µA. If the SS capacitor
is absent, the SS pin ramps from 0V to 2.56V in 220µs.
TMR (Pin 20/Pin 14): Delay Timer Input. Connect a capaci-
tor (CTMR) to this pin to create timing delays at start-up,
when power good outputs pull down, during PGI check
and when auto-retrying after faults (except overvoltage
fault). Internal pull-up currents of 10µA and 5µA and
pull-down currents of 5µA and 12mA configure the delay
periods as multiples of a nominal delay of 256ms • CTMR/
µF. Delays for start-up and auto-retry following undervolt-
age or power bad fault are the same as the nominal delay.
Delays for sequenced power good outputs are twice of the
nominal delay. Delays for PGI check and auto-retry fol-
lowing overcurrent fault are four times the nominal delay.
(SSOP/QFN)
PIN FUNCTIONS
LTC4261/LTC4261-2
10
42612fd
For more information www.linear.com/LTC4261
VEE (Pin 13/Pin 8): Negative Supply Voltage Input and
Device Ground. Connect this pin to the negative side of
the power supply.
VIN (Pin 21/Pin 15): Positive Supply Input. Connect this
pin to the positive supply through a dropping resistor. An
internal shunt regulator clamps VIN at 11.2V. An internal
undervoltage lockout (UVLO) circuit holds the GATE low
until VIN is above 9V. Bypass this pin with a 1µF capacitor
to VEE.
UVH (Pin 9/Pin 6): Undervoltage High Level Input. Con-
nect this pin to an external resistive divider from VEE. If
the voltage at the UVH pin rises above 2.56V the pass
transistor is allowed to turn on. A small capacitor at this
pin prevents transients and switching noise from affecting
the UVH threshold. Connect to INTVCC if unused.
UVL (Pin 8/Pin 5): Undervoltage Low Level Input. Con-
nect this pin to an external resistive divider from VEE. If
the voltage at the UVL pin drops below 2.291V, the pass
transistor is turned off and the power good outputs go
high impedance. Pulling this pin below 1.21V resets faults
and allows the pass transistor to turn back on. Connect
to INTVCC if unused.
PIN FUNCTIONS
(SSOP/QFN)
LTC4261/LTC4261-2
11
42612fd
For more information www.linear.com/LTC4261
BLOCK DIAGRAM
+
–
UVLO:
VIN = 9V
INTVCC = 4.25V
VEE
VEE
VEE
VSENSE
50mV
VEE
VEE
VIN
VIN
VCC
SSA
SSC
ACL
UVL
UVH
OV
20µA
INTVCC
GATE
RAMP
SENSE
2.56V
2.291V
10µA 50nA
3pF
5V
11.2V
+
–
+
–
+
–
+
–
+
–
+
–
+
–
2.56V
1.77V
+
–
2.56V
5µA 5µA
TMR
TMR
ADR0
VEE
ADR1
I2C DEVICE ADDRESS
SINGLE-WIRE ENABLE
OV
UVH
UVL
SS
12mA 5µA
8
+
–
LOGIC
ADIN
ADIN2/OV
A0
VSENSE
MUX REGISTER
I2C
INTERFACE
•
•
A7
A8
10 10
VREF = 2.56V
10-BIT ADC
42612 BD
VEE
VEE
VEE
+–
40¥
PG
PGIO
FLTIN
PGI
EN
ON
1.77V
DC
GC
4V
VZ – 1.2V
GATE
DRAIN
SCL
SDAI
SDAO
ALERT
DECODER
LTC4261/LTC4261-2
12
42612fd
For more information www.linear.com/LTC4261
The LTC4261/LTC4261-2 are designed to turn a board’s
supply voltage on and off in a controlled manner, allowing
the board to be safely inserted or removed from a live – 48V
backplane. The devices also feature an onboard 10-bit ADC
and I2C interface that allows monitoring board current,
voltages and faults. The main functional circuits of the
LTC4261/LTC4261-2 are illustrated in the Block Diagram.
In normal operation after a start-up debounce delay, the
GATE pin turns on the external N-channel FET passing
power to the load. The GATE pin is powered by a shunt
regulated 11.2V supply on the VIN pin that is derived
from –48V RTN through a dropping resistor. The turn-on
sequence starts by pulling the SS pin up. The voltage at
the SS pin is converted to a current, IGATE(UP), pulling the
GATE up. When the pass FET starts to turn on and charge
the load capacitor, the inrush current flowing through the
FET is a function of the capacitor at RAMP (CR), the load
capacitor (CL) and the ramp current (IRAMP) that flows
from the RAMP pin to CR:
IINRUSH =IRAMP •CL
C
R
IRAMP and IGATE(UP) are approximately proportional to
the SS pin voltage and are limited to 20µA and 11.5µA,
respectively when SS reaches its clamping voltage (2.56V).
The ACL amplifier is used for overcurrent and short-circuit
protection. It monitors the load current through the SENSE
pin voltage and a sense resistor RS. In an overcurrent
condition, the ACL amplifier limits the current to 50mV/
RS by pulling down GATE in an active servo loop. After a
530µs timeout, the ACL amplifier turns off the pass FET.
In the event of a catastrophic short circuit, when VSENSE
crosses 250mV, a fast response comparator immediately
pulls the GATE pin down.
The DRAIN and the GATE voltages are monitored to de-
termine if power is available for the load. Two power good
signals are sequenced on the PG pin (first power good
signal) and the PGIO pin (second power good signal), each
with a debounce delay that is twice the start-up delay. The
PGIO pin can also be used as a general purpose input or
output. The PGI pin serves as a watchdog to monitor the
output of the DC/DC module. If the module output fails to
come up, the LTC4261/LTC4261-2 shut down.
The TMR pin generates delays for initial start-up, auto-
retry following a fault, power good outputs and PGI check.
The logic circuits a re powered by an internally generated
5V supply (available on the INTVCC pin). Prior to turning
on the pass FET, both VIN and INTVCC voltages must ex-
ceed their undervoltage lockout thresholds. In addition,
the control inputs UVH, UVL, OV, EN, ON and PGI are
monitored by comparators. The FET is held off until all
start-up conditions are met.
A 10-bit analog-to-digital converter (ADC) is included in the
LTC4261/LTC4261-2. The ADC measures SENSE resistor
voltage as well as voltage at the ADIN2/OV (SSOP/QFN)
and ADIN pins. The results are stored in on-board registers.
An I2C interface is provided to read the ADC data registers.
It also allows the host to poll the device and determine if a
fault has occurred. If the ALERT line is used as an interrupt,
the host can respond to a fault in real time. The SDA line
is divided into SDAI (input) and SDAO (output) to facili-
tate opto coupling with the system host. Two three-state
pins, ADR0 and ADR1, are used to decode eight device
addresses. The interface can also be configured through
the ADR0 and ADR1 pins for a single-wire broadcast
mode, sending ADC data and faults status through the
SDAO pin to the host without clocking the SCL line. This
single-wire, one-way communication simplifies system
design by eliminating two optocouplers on SCL and SDAI
that are required by an I2C interface.
OPERATION
LTC4261/LTC4261-2
13
42612fd
For more information www.linear.com/LTC4261
The LTC4261/LTC4261-2 are ideally suited for –48V
distributed power systems and AdvancedTCA systems.
A basic 200W application circuit using the LTC4261 is
shown in Figure 1. A more complete application circuit
with AdvancedTCA connections is shown in Figure 2.
Input Power Supply
Power for the LTC4261/LTC4261-2 is derived from the
–48V RTN through an external current limiting resistor
(RIN) to the VIN pin. An internal shunt regulator clamps
+
FLTIN
PGI
SCL
SDAI
SDAO
ALERT
PG
ADIN
8
9
10
11
19
20
26
2
25
24
22
1
6
5
4
3
27 PWRGD1
23
UVL
UVH
ADIN2
OV
SS
TMR
EN
ON
ADR1
ADRO
RAMPDRAINGATE
LTC4261CGN
VIN
INTVCC
VEE SENSE
RD
1M
RIN
4 × 1k IN SERIES
1/4W EACH
R3
453k
1%
–48V RTN
–48V INPUT
UV = 38.5V
UV RELEASE
AT 43V
OV RELEASE
AT 71V
OV = 72.3V
R2
16.9k
1%
R1
11.8k
1% CR
10nF
100V
5%
CF
33nF
CTMR
47nF
CSS
220nF
CVCC
0.1µF
CIN
1µF
CUV
100nF CG 47nF
RS
0.008Ω
1%
RG
10Ω
Q1
IRF1310NS
R11
402k 1%
R10
10k 1%
RF
1k
13 14 15 16 18
CL
330µF
100V
217
MODULE2
ON
42612 F01
VIN+
VIN–MODULE1
ON
VIN+
VIN–
VOUT
PGIO 28 PWRGD2
Figure 1. –48V/200W Hot Swap Controller Using LTC4261 with Current,
Input Voltage and VDS Monitoring (5.6A Current Limit, 0.66A Inrush)
Figure 2a. 200W AdvancedTCA Hot Swap Controller with Input/Output Monitoring
and Power Good Watchdog Using LTC4261 in I2C Mode (Part One)
8
9
10
11
19
20
26
2
25
24
RD
1M
RH
604Ω
1%
R3
412k
1%
UV TURN OFF = 34.2V
UV RELEASE = 37.5V
OV TURN OFF = 74.8V
OV RELEASE = 73.2V
R2
19.1k
1%
R14
100k
R11
100k
R10
100k
RTN A
RTN B
ENABLE A
ENABLE B
–48V A
–48V B
R13
10k
R12
10k
MBRM5100
10A
10A
R15
100k
Q10
2N5401
R1
10.5k
1%
R16
100k
CR
10nF
100V
5%
CF
33nF
CTMR
330nF
CSS
330nF
CUV
100nF
1N4148
×2
CG 47nF
RS
0.008Ω
5%
RG
10Ω
Q1
IRF1310NS
RF
1k
13 14 15 16 18
42612 F02a
CEN
1µF
HZS5C1
MBRM5100
Q9
2N5401
7A LTC4354
PLUG-IN
CARD
7A
BACKPLANE
A
B
UVL
UVH
ADIN2
OV
SS
TMR
EN
ON
ADR1
ADR0
RAMPDRAINGATE
LTC4261CGN
VEE
VEE
SENSE
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
14
42612fd
For more information www.linear.com/LTC4261
22
1
6
5
28
27
4
3
VEE
R6
100k
RIN
8 × 240Ω IN SERIES
1/4W EACH
CVCC
0.1µF
VEE
CIN
1µF
MOC207
217 23 R8
7.5k
R7A
10k
R7B
10k
R9
5.1k
R7
100k
R24
5.1k
R23
1k
R22
1k
R17
100k
1%
Q11
2N5401
OUTPUT
SENSE
Q12
2N5401
R19
2.49k
1%
VEE
VEE
VOUT
VOUT
VOUT
R20
2.49k
1%
R18
100k
1%
R4
20k
R21
1k
5V
LUCENT
FLTR100V10
VIN+
–48V RTN OUTPUT
VIN–CASE
VOUT+
VOUT–
MICRO-
CONTROLLER
VDD
GND
SCL
SDA
ALERT
MBRM5100
CL
4000µF
100V
0V TRANSIENT
RESEVOIR
CAPACITOR
RST
LUCENT
JW050A1-E
VIN+
VIN–
VEE
Q5
MOC207
ON/OFF
CASE
LTC2900
SUPPLY
MONITOR
VDD
RST
GND
VOUT+
VOUT–
RL
343Ω
7 × 2.4k, 0805
EACH 28.7W
+
Q8
A
B
ANODE
VCC
Q3
HCPL-0300
GND
CATHODE
RL
VOUT
ANODE
VCC
Q4
Q6 Q7
42612 F02b
5V
PS9113 PS9113
6N139
CATHODE
VO
VO
VCC
GND
ANODE
CATHODE
VO
VCC
ANODE
CATHODE
GND
GND
FLTIN
PGI
SCL
SDAI
PGIO
PG
SDAO
ALERT
LTC4261CGN
VIN
INTVCC ADIN
Figure 2b. 200W AdvancedTCA Hot Swap Controller with Input/Output Monitoring
and Power Good Watchdog Using LTC4261 in I2C Mode (Part Two)
the voltage at VIN to 11.2V (VZ) and provides power to the
GATE driver. The data converter and logic control circuits
are powered by an internal linear regulator that derives
5V from the 11.2V supply. The 5V output is available at
the INTVCC pin for driving external circuits (up to 20mA
load current).
Bypass capacitors of 1µF and 0.1µF are recommended
at VIN and INTVCC, respectively. RIN should be chosen to
accommodate the maximum supply current requirement
of the LTC4261/LTC4261-2 (5mA) plus the supply current
required by any external devices driven by the VIN and
INTVCC pins at the minimum intended operation voltage.
RIN ≤
V
48V(MIN)
– V
Z(MAX)
IIN(MAX) +IEXTERNAL
The maximum power dissipation in the resistor is:
P
MAX =V48V(MAX) – VZ(MIN)
( )
2
R
IN
If the power dissipation is too high for a single resistor,
use multiple resistors in series or supply external loads
from a separate NPN buffer as illustrated in Figure 3.
Initial Start-Up and Inrush Control
Several conditions must be satisfied before the FET turn-on
sequence is started. First the voltage at VIN must exceed
its 9V undervoltage lockout level. Next the internal supply
INTVCC must cross its 4.25V undervoltage lockout level.
This generates a 100µs to 160µs power-on-reset pulse
during which the FAULT register bits are cleared and the
CONTROL register bits are set or cleared as described in
the register section. After the power-on-reset pulse, the
voltages at the UVH, UVL and OV pins must satisfy UVH
> 2.56V, UVL > 2.291V and OV < 1.77V to indicate that
the input power is within the acceptable range and the EN
pin must be pulled low. All the above conditions must be
satisfied throughout the duration of the start-up debounce
delay that is set by an external capacitor (CTMR) connected
to the TMR pin. CTMR is charged with a pull-up current of
APPLICATIONS INFORMATION
RTN
100Ω
BCP56
V
IN OR
INTV
CC
10.5V OR 4.3V
42612 F03
Figure 3. NPN Buffer Relieves RIN of Excessive Dissipation
when Supplying External Loads
LTC4261/LTC4261-2
15
42612fd
For more information www.linear.com/LTC4261
10µA until the voltage at TMR reaches 2.56V. CTMR is then
quickly discharged with a 12mA current. The initial delay
expires when TMR is brought below 75mV. The duration
of the start-up delay is given by:
tD=256ms • CTMR
1µF
If any of the above conditions is violated before the start-up
delay expires, CTMR is quickly discharged and the turn-on
sequence is restarted. After all the conditions are validated
throughout the start-up delay, the ON pin is then checked.
If it is high, the FET will be turned on. Otherwise, the FET
will be turned on when the ON pin is raised high or the FET
ON bit D3 in the CONTROL register is set to “1” through
the I2C interface.
The FET turn-on sequence follows by charging an external
capacitor at the SS pin (CSS) with a 10µA pull-up current
and the voltage at SS (VSS) is converted to a current
(IGATE(UP)) of 11.5µA· VSS/2.56V for GATE pull-up. When
the GATE reaches the FET threshold voltage, the inrush
current starts to flow through the FET and a current (IRAMP)
of 20µA· VSS/2.56V flows out of the RAMP pin and through
an external capacitor (CR) connected between RAMP and
VOUT. The SS voltage is clamped to 2.56V, which cor-
responds to IGATE(UP) = 11.5µA and IRAMP = 20µA. The
RAMP pin voltage is regulated at 1.1V and the ramp rate
of VOUT determines the inrush current:
IINRUSH =20µA • CL
C
R
The ramp rate of VSS determines dI/dt of the inrush current:
dI
INRUSH
dt =20µA •
C
L
C
R
•
1µF
256ms • C
SS
If CSS is absent, an internal circuit pulls the SS pin from
0V to 2.56V in about 220µs.
When VOUT is ramped down to VEE, IGATE returns to
the GATE pin and pulls the GATE up to VGATEH. Figure 4
illustrates the start-up sequence of the LTC4261/
LTC4261-2.
During board insertion and input power step, an internal
clamp turns on to hold the RAMP pin low. Capacitor CF
and resistor RF suppress the noise at the RAMP pin. For
proper operation, RF • CR should not exceed 50µs. The
recommended value of CF is 3 • CR.
Power Good Monitors
When VDS of the pass transistor falls below 1.77V and
GATE pulls above VZ – 1.2V, an internal power good signal
is latched and a series of three delay cycles are started
as shown in Figure 4. When the first delay cycle with a
duration of 2tD expires, the PG pin pulls low as a power
good signal to turn on the first module. When the second
delay cycle (2tD) expires, the PGIO pin pulls low as a power
good signal to turn on the second module. The third delay
cycle with a duration of 4tD is for PGI check. Before the
third delay cycle expires, the PGI pin must be pulled low
by an external supply monitor (such as the LTC2900 in
Figure 2) to keep the FET on. Otherwise, the FET is turned
off and the power bad fault (PBAD) is logged in the FAULT
register. The 2tD timer delay is obtained by charging CTMR
with a 5µA current and discharging CTMR with a 12mA
current when TMR reaches 2.56V. For the 4tD timer delay,
the charging and discharging currents of CTMR are both
5µA. The power good signals at PG and PGIO are reset in
all FET turn-off conditions except the overvoltage fault.
Turn-Off Sequence and Auto-Retry
In any of the following conditions, the FET is turned off
by pulling down GATE with a 110mA current, and CSS
and CTMR are discharged with 12mA currents.
1. The ON pin is low or the ON bit in the CONTROL reg-
ister is set to 0.
2. The EN pin is high.
3. The voltage at UVL is lower than 2.291V and the volt-
age at UVH is lower than 2.56V (undervoltage fault).
4. The voltage at OV is higher than 1.77V (overvoltage
fault).
5. The voltage at VIN is lower than 9V (VIN undervoltage
lockout).
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
16
42612fd
For more information www.linear.com/LTC4261
6. The voltage at INTVCC is lower than 4.25V (INTVCC
undervoltage lockout).
7. VSENSE > 50mV and the condition lasts longer than
530µs (overcurrent fault).
8. The PGI pin is high when the PGI check timer expires
(power bad fault).
For conditions 1, 2, 5, 6, after the condition is cleared,
the LTC4261/LTC4261-2 will automatically enter the FET
turn-on sequence as previously described.
For any of the fault conditions 3, 4, 7, 8, the FET off
mode is programmable by the corresponding auto-retry
bit in the CONTROL register. If the auto-retry bit is set
to 0, the FET is latched off upon the fault condition. If
the auto-retry bit is set to 1, after the fault condition is
cleared, a delay timer is started. After the timer expires,
the FET enters the auto-retry mode and GATE is pulled
up. The auto-retry delay following the undervoltage fault
or the power bad fault has a duration of tD. The auto-
retry delay following the overcurrent fault has a duration
of 4tD for extra cooling time. The auto-retry following the
overvoltage fault does not have a delay. The auto-retry
control bits and their defaults at power up are listed in
Table 6. Note that the LTC4261 defaults to latch-off while
the LTC4261-2 defaults to auto-retry following the over-
current fault.
Figure 4. LTC4261 Turn-On Sequence
APPLICATIONS INFORMATION
RTN_VEE
TMR
UVH
1x
START-UP DELAY
SS
GATE
VOUT
SENSE
PG
PGIO
PGI
INTERNAL
PWRGD
2x
VZ – 1.2V
1.77V
PWRGD1
DELAY
2x
PWRGD2
DELAY
4x
PGI CHECK
DELAY
50mV
INRUSH
LOAD 1
LATCHED
PWRGD1
READY
LOAD 1 + LOAD 2
PWRGD2
READY
NORMAL PGI
POWER BAD
42612 F04
LTC4261/LTC4261-2
17
42612fd
For more information www.linear.com/LTC4261
EN and ON
Figure 5 shows a logic diagram for EN and ON as they
relate to GATE, ALERT and internal registers A4, A7, B4,
C4 and D3. Also affecting GATE is the status of UV, OV
and several other fault conditions. The EN and ON pins
have 0.8V to 2V logic thresholds relative to VEE with a
maximum input leakage current of ±2µA.
Register bit A4 indicates the present state of EN, and B4
is set high whenever EN changes state. Rising and falling
edges at the ON pin set and clear FET-on control bit, D3.
Another path allows a falling edge at EN to latch a high
state at the ON pin (such as when ON is permanently
pulled high) into D3 after a time delay. Both B4 and D3
can be set or cleared directly by I2C, and both are cleared
low whenever INTVCC drops below its UVLO threshold.
The condition of the GATE pin output is controlled by
register bit A7, which is the AND of A4, D3 and the ab-
sence of UV, OV and other faults.
Overcurrent Protection and Overcurrent Fault
The LTC4261/LTC4261-2 feature two levels of protec-
tion from short-circuit and overcurrent conditions. Load
current is monitored by the SENSE pin and resistor
RS. There are two distinct thresholds for the voltage at
SENSE: 50mV for engaging the active current limit loop
and starting a 530µs circuit breaker timer and 250mV for
a fast GATE pull-down to limit peak current in the event
of a catastrophic short circuit or an input step.
In an overcurrent condition, when the voltage drop across
RS exceeds 50mV, the current limit loop is engaged and
an internal 530µs circuit breaker timer is started. The
current limit loop servos the GATE to maintain a constant
output current of 50mV/RS. When the circuit breaker
timer expires, the FET is turned off by pulling GATE down
with a 110mA current, the capacitors at SS and TMR are
discharged and the power good signals are reset. At this
time, the overcurrent present bit A2 and the overcurrent
fault bit B2 are set, and the circuit breaker timer is reset.
After the FET is turned off, the overcurrent present bit
A2 is cleared. If the overcurrent auto-retry bit D2 has
been set, the FET will turn on again automatically after
a cooling time of 4tD. Otherwise, the FET will remain off
until the overcurrent fault bit B2 is reset. When the over-
current fault bit is reset (see Resetting Faults), the FET
is allowed to turn on again after a delay of 4tD. The 4tD
cooling time associated with the overcurrent fault will not
be interrupted by any other fault condition. See Figure 6
for operation of LTC4261/LTC4261-2 under overcurrent
condition followed by auto-retry.
Figure 5. Logic Block Diagram of EN and ON Pins
APPLICATIONS INFORMATION
R/W
I2C
CLR
Q
S
R
R/W
CLR
INTVCC UVLO
INTV
CC
UVLO
ABSENCE OF UV/OV AND OTHER FAULTS
Q
S
CLR
Q
S
1 tD
TIMER
DELAY
EDGE
DETECTOR
STATE-CHANGE
DETECTOR
EN
ON
B4
C4
ALERT*
GATE ON
ALERT
42612 F05
READ ANY REGISTER
*B4 •C4 IS ONE OF SEVEN CONDITIONS
THAT CAN GENERATE AN ALERT OUTPUT.
SEE TABLE 5
I2C ALERT RESPONSE
A4 A7
D3
LTC4261/LTC4261-2
18
42612fd
For more information www.linear.com/LTC4261
Figure 6. Overcurrent Fault and Auto-Retry
In the case of a low impedance short circuit on the load
side or an input step during battery replacement, current
overshoot is inevitable. A fast SENSE comparator with a
threshold of 250mV detects the overshoot and immedi-
ately pulls GATE low. Once the SENSE voltage drops to
50mV, the current limit loop takes over and servos the
current as previously described. If the short-circuit con-
dition lasts longer than 530µs, the FET is shut down and
the overcurrent fault is registered.
In the case of an input step, after an internal clamp pulls the
RAMP pin down to 1.1V, the inrush control circuit takes
over and the current limit loop is disengaged before the
circuit breaker timer expires. From this point on, the device
works as in the initial start-up: VOUT is ramped down at the
rate set by IRAMP and CR followed by GATE pull-up. The
power good signals on the PG and PGIO pins, the TMR
pin, and the SS pin are not interrupted through the input
step sequence. The waveform in Figure 7 shows how the
LTC4261/LTC4261-2 responds to an input step.
Note that the current limit threshold should be set
sufficiently high to accommodate the sum of the load
current and the inrush current to avoid engagement of
the current limit loop in the event of an input step. The
maximum value of the inrush current is given by:
IINRUSH ≤0.8 •
45mV
R
S
– ILOAD
where the 0.8 factor is used as a worst case margin com-
bined with the minumum threshold (45mV).
The active current limit circuit is compensated using the
capacitor CG with a series resistor RG (10W) connected
between GATE and VEE, as shown in Figure 1. The sug-
gested value for CG is 50nF. This value should work for
most pass transistors (Q1).
Overvoltage Fault
An overvoltage fault occurs when the OV pin rises above
its 1.77V threshold. This shuts off the pass transistor
immediately, sets the overvoltage present bit A0 and
the overvoltage fault bit B0, and pulls the SS pin down.
Note that the power good signals are not affected by the
overvoltage fault. If the OV pin subsequently falls back
below the threshold, the pass transistor will be allowed
to turn on again immediately (without delay) unless the
APPLICATIONS INFORMATION
TMR
SS
GATE
VOUT
SENSE
PG
PGIO
OC COOLING DELAY
PWRGD1
DELAY
4x 2x
VZ – 1.2V
1.77V
INRUSH
PWRGD2
DELAY
2x
50mV
530µs
42612 F06
LTC4261/LTC4261-2
19
42612fd
For more information www.linear.com/LTC4261
overvoltage auto-retry has been disabled by clearing reg-
ister bit D0.
Undervoltage Comparator and Undervoltage Fault
The LTC4261/LTC4261-2 provide two undervoltage pins,
UVH and UVL, for adjustable UV threshold and hyster-
esis. The UVH and UVL pins have the following accurate
thresholds:
For UVH rising, VUVH(TH) = 2.56V, turn on
For UVL falling, VUVL(TH) = 2.291V, turn off
Both UVH and UVL pins have a minimum hysteresis of
dVUV (15mV typical). In either a rising or a falling input
supply, the undervoltage comparator works in such a way
that both the UVH and the UVL pins have to cross their
thresholds for the comparator output to change state.
The UVH, UVL, and OV threshold ratio is designed to
match the standard telecom operating range of 43V to
71V and UV hysteresis of 4.5V when UVH and UVL are
tied together as in Figure 1, where the built-in UV hyster-
esis referred to the UVL pin is:
DVUV(HYST) = VUVH(TH) – VUVL(TH) = 0.269V
Using R1 = 11.8k, R2 = 16.9k and R3 = 453k as in Figure 1
gives a typical operating range of 43.0V to 70.7V, with
an undervoltage shutdown threshold of 38.5V and an
overvoltage shutdown threshold of 72.3V.
The UV hysteresis can be adjusted by separating the
UVH and the UVL pins with a resistor RH (Figure 8). To
increase the UV hysteresis, the UVL tap should be placed
above the UVH tap as in Figure 8a. To reduce the UV hys-
teresis, place the UVL tap under the UVH tap as in Figure
8b. UV hysteresis referred to the UVL pin is given by:
for V
UVL
≥V
UVH
,
DV
UVL(HYST) = DV
UV(HYST) +2.56V • RH
R1+R2
or for V
UVL <V
UVH,
DV
UVL(HYST) = DV
UV(HYST) – 2.56V • RH
R1+R2 +R
H
For VUVL < VUVH, the minimum UV hysteresis allowed is
the minimum hysteresis at UVH and UVL: dVUV = 15mV
when RH(MAX) = 0.11 • (R1 + R2)
The design of the LTC4261/LTC4261-2 protects the UV
comparator from chattering even when RH is larger than
RH(MAX).
An undervoltage fault occurs when the UVL pin falls
below 2.291V and the UVH pin falls below 2.56V – dVUV.
This activates the FET turn-off and sets the undervoltage
Figure 7. –36V to –72V Step Response
APPLICATIONS INFORMATION
RTN – V
EE
TMR
SS
GATE
VOUT
SENSE
PG
PGIO
36V
0V
2.56V
VGATEH
LOAD LOAD
0V
0V
42612 F07
50mV LOAD + INRUSH
FET VTH
72V
LTC4261/LTC4261-2
20
42612fd
For more information www.linear.com/LTC4261
Figure 8. Adjustment of Undervoltage Thresholds
for Larger (8a) or Smaller (8b) Hysteresis
present bit A1 and the undervoltage fault bit B1. The
power good signals at PG and PGIO are also reset.
The undervoltage present bit A1 is cleared when the
UVH pin rises above 2.56V and the UVL pin rises above
2.291V + dVUV. After a delay of tD, the FET will turn on
again unless the undervoltage auto-retry has been dis-
abled by clearing bit D1.
When power is applied to the device, if UVL is below
the 2.291V threshold and UVH is below 2.56V – dVUV
after INTVCC crosses its undervoltage lock out threshold
(4.25V), an undervoltage fault will be logged in the fault
register.
Because of the compromises of selecting from a table of
discrete resistor values (1% resistors in 2% increments,
0.1% resistors in 1% increments), best possible OV and
UV accuracy is achieved using separate dividers for each
pin. This increases the total number of resistors from
three or four to as many as six, but maximizes accuracy,
greatly simplifies calculations and facilitates running
changes to accommodate multiple standards or custom-
ization without any board changes.
To improve noise immunity, put the resistive divider to
the UV and OV pins close to the chip and keep traces to
RTN and VEE short. A 0.1µF capacitor from the UVH or
UVL pin (and OV pin through resistor R2) to VEE helps
reject supply noise.
FET Short Fault
A FET short fault will be reported if the data converter mea-
sures a current sense voltage greater than or equal to 2mV
while the FET is turned off. This condition sets the FET
short present bit A5 and the FET short fault bit B5.
Power Bad Fault
After the FET is turned on and the power good outputs
pull PG and PGIO low, a delay timer with duration of 4tD is
started and the level of the PGI pin is checked (Figure 3).
If the PGI pin is pulled below its 1.4V threshold before
the PGI check timer expires, the FET will remain on.
Otherwise, the FET is immediately turned off, the power
good signals are reset and the power bad present bit A3
and the power bad fault bit B3 are set. After the FET is
turned off, the power bad present bit A3 will be cleared.
If the PGI pin is subsequently pulled low, the FET will
remain off unless the power bad auto-retry has been en-
abled by setting bit D4 or the power bad fault bit B3 is
cleared. In either of those two conditions, the FET will
turn on again following a delay of tD and the PGI pin is
checked again as described above.
External Fault Monitors
The FLTIN pin (SSOP only) and the PGIO pin, when con-
figured as general purpose input, allow monitoring of ex-
ternal fault conditions such as broken fuses. If FLTIN is
pulled below its 1.4V threshold, bit B7 in the FAULT reg-
ister is set. An associated alert bit, C7, is also available
in the ALERT register. When the PGIO pin is configured
as general purpose input, if the voltage at PGIO is above
1.25V, both bit A6 in the STATUS register and bit B6 in
the FAULT register are set, though there is no alert bit as-
sociated with this fault. The external fault conditions do
not directly affect the GATE control functions.
Fault Alerts
When any of the fault bits in FAULT register B is set, an
optional bus alert can be generated by setting the appropri-
ate bit in the ALERT register C. This allows only selected
faults to generate alerts. At power-up the default state is not
to alert on faults. If an alert is enabled, the corresponding
APPLICATIONS INFORMATION
R3
453k
1%
UVL
TURN-ON = 46V
TURN-OFF = 38.5V
HYSTERESIS = 7.5V
–48V RTN
(8a)
VEE VEE
RH
1.91k
1%
UVH
R2
15k
1%
R1
11.8k
1%
0V
R3
453k
1%
UVH
TURN-ON = 43V
TURN-OFF = 41.2V
HYSTERESIS = 1.8V
–48V RTN
(8b)
RH
1.91k
1%
UVL
R2
15k
1%
R1
11.8k
1%
0V
42612 F08
LTC4261/LTC4261-2
21
42612fd
For more information www.linear.com/LTC4261
fault will cause the ALERT pin to pull low. After the bus
master controller broadcasts the alert response address,
the LTC4261/LTC4261-2 will respond with its address on
the SDA line and release ALERT as shown in Figure 14.
If there is a collision between two LTC4261’s responding
with their addresses simultaneously, then the device with
the lower address wins arbitration and responds first. The
ALERT line will also be released if the device is addressed
by the bus master.
Once the ALERT signal has been released for one fault,
it will not be pulled low again until the FAULT register
indicates a different fault has occurred, or the original
fault is cleared and it occurs again. Note that this means
repeated or continuing faults will not generate alerts until
the associated FAULT register bit has been cleared.
Resetting Faults
Faults are reset with any of the following conditions.
First, writing zeros to the FAULT register B will clear the
associated fault bits. Second, the entire FAULT register
is cleared when either the ON pin or bit D3 goes from
high to low, or if INTVCC falls below its 4.25V undervolt-
age lockout. Pulling the UVL pin below its 1.21V reset
threshold also clears the entire FAULT register. When the
UVL pin is brought back above 1.21V but below 2.291V,
the undervoltage fault bit B1 is set if the UVH pin is below
2.56V. This can be avoided by holding the UVH pin above
2.56V while toggling the UVL pin to reset faults. Finally,
when EN is brought from high to low, all fault bits except
bit B4 are cleared. The bit B4 that indicates an EN change
of state will be set.
Fault bits with associated conditions that are still pres-
ent (as indicated in the STATUS Register A) cannot be
cleared. The FAULT register will not be cleared when
auto-retrying. When auto-retry is disabled, the existence
of B0 (overvoltage), B1 (undervoltage), B2 (overcurrent)
or B3 (power bad) fault keeps the FET off. After the fault
bit is cleared and a delay of tD (for B0, B1 and B3) or 4tD
(for B4) expires, the FET will turn on again. Note that if
the overvoltage fault bit B0 is cleared by writing a zero
through I2C, the FET is allowed to turn on without a de-
lay. If auto-retry is enabled, then a high value in A0, A1,
A2 or A3 will hold the FET off and the FAULT register is
ignored. Subsequently, when the A0, A1, A2 and A3 bits
are cleared, the FET is allowed to turn on again.
Turning the LTC4261/LTC4261-2 On and Off
Many methods of on/off control are possible using the
ON, EN, UV/OV, FLTIN or PGIO pins along with the I2C
port. The EN pin works well with logic inputs or float-
ing switch contacts; I2C control is intended for systems
where the board operates only under command of a cen-
tral control processor and the ON pin is useful with sig-
nals referenced to RTN, as are the UV (UVH, UVL) and
OV pins. PGIO and FLTIN control nothing directly, but are
useful for I2C monitoring of connection sense or other
important signals.
On/off control is possible with or without I2C interven-
tion. Further, the LTC4261/LTC4261-2 may reside on
either the removable board or on the backplane. Even
when operating autonomously, the I2C port can still ex-
ercise control over the GATE output, although depending
on how they are connected, EN and ON could subse-
quently override conditions set by I2C. UV, OV and other
fault conditions seize control as needed to turn off the
GATE output, regardless of the state of EN, ON or the I2C
port. Figure 9 shows five configurations of on/off control
of the LTC4261/LTC4261-2.
Determining factors in selecting a pin configuration for
autonomous operation are the polarity and voltage of the
controlling signal.
Optical Isolation. Figure 9a shows an opto-isolator driv-
ing the ON pin. Rising and falling edges at the ON pin
turn the GATE output on and off. If ON is already high
when power is applied, GATE is delayed one tD period.
The status of ON can be examined or overridden through
the I2C port at register bit D3. This circuit works in both
backplane and board resident applications.
Logic Control. Figure 9b shows an application using log-
ic signal control. Again, the ON pin is used as an input;
all remarks made concerning opto-isolator control apply
here as well.
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
22
42612fd
For more information www.linear.com/LTC4261
Ejector Switch or Loop-Through Connection Sense.
Floating switch contacts or a connection sense loop also
work well with the ON pin, replacing the phototransistor
in Figure 9a. If an insertion debounce delay is desired,
use the EN pin as shown in Figure 9c. Like Figures 9a
and 9b, this circuit works on either side of the backplane
connector.
Short Pin to RTN. Figure 9d uses the UV divider string to
detect board insertion. This method works equally well in
both backplane and board resident applications.
AdvancedTCA Style Control. Figure 2 shows an ATCA
application using EN as the interface to the LTC4261.
Register bit A4 allows the I2C port to monitor the status
of EN and by setting C4 high, bit B4 can generate an alert
to instantly report any changes in the state of EN.
I2C Only Control. To lock out EN and ON, use the con-
figuration shown in Figure 9e and control the GATE pin
with register bit D3. The circuit defaults off at power up.
To default on, connect the ON pin to INTVCC. Either FLTIN
or PGIO can be used as an input to monitor a connection
sense or other control signal. PGIO is configured as an
input by setting register bits D6 and D7 high; its input
state is stored at location B6. FLTIN is always an input
whose state is available from register bit B7. FLTIN gen-
erates an alert if C7 is set high.
Data Converter
The LTC4261/LTC4261-2 incorporates a 10-bit DΣ ana-
log-to-digital converter (ADC) that continuously moni-
tors three different voltages at (in the sequence of)
SENSE, ADIN2/OV (SSOP/QFN) and ADIN. The DΣ ar-
chitecture inherently averages signal noise during the
measurement period. The voltage between the SENSE
pin and VEE is monitored with a 64mV full scale and
62.5µV resolution, and the data is stored in registers E
and F. The ADIN and the ADIN2/OV pins are monitored
with a 2.56V full scale and 2.5mV resolution. The data
for the ADIN2/OV pin is stored in registers G and H. The
data for the ADIN pin is stored in registers I and J.
The results in registers E, F, G, H, I and J are updated at
a frequency of 7.3Hz. Setting CONTROL register bit D5
invokes a test mode that halts updating of these registers
so that they can be written to and read from for software
testing. By invoking the test mode right before reading
the ADC data registers, the 10-bit data separated in two
registers are synchronized.
The ADIN and ADIN2 pins can be used to monitor input
and output voltages of the Hot Swap controller as shown
in Figures 1 and 2.
Figure 9. On/Off Control of the LTC4261
APPLICATIONS INFORMATION
INTVCC
LTC4261
(9a) Opto-Isolator Control
5V
ON
47k
1k
EN
–48V
VEE
INTVCC
LTC4261
(9c) Contact Debounce Delay Upon
Insertion for Use with an Ejector
Switch or Loop-Through Style
Connection Sense
EN
100k
LOOP OR
SWITCH
10nF
1M
ON
–48V
VEE
INTVCC
LTC4261
(9b) Logic Control
ON EN
–48V
VEE
INTVCC
I2C
42612 F09
LTC4261
(9e) I
2
C-Only Control
ON
EN
SDAO
SDAI
SCL
DEFAULT
ON
DEFAULT
OFF
–48V
VEE
INTVCC
LTC4261
(9d) Short Pin Connection Sense to RTN
ON
EN
UVL
UVH
28.7k
–48V
INPUT
–48V
RTN
VEE
453k
LTC4261/LTC4261-2
23
42612fd
For more information www.linear.com/LTC4261
Configuring the PGIO Pin
Table 6 describes the possible states of the PGIO pin us-
ing the CONTROL register bits D6 and D7. At power-up
the default state is for the PGIO pin to pull low when
the second power good signal is ready. Other uses for
the PGIO pin are to go high impedence when the sec-
ond power good is ready, a general purpose output and a
general purpose input. When the PGIO pin is configured
as a general purpose output, the status of bit C6 is sent
out to the pin. When it is configured as a general pur-
pose input, if the input voltage at PGIO is higher than
1.25V, both bit A6 in the STATUS register and bit B6 in
the FAULT register are set. If the input voltage at PGIO
subsequently drops below 1.25V, bit A6 is cleared. Bit
B6 can be cleared by resetting the FAULT register as de-
scribed previously.
Design Example
As a design example, consider the 200W application with
CL = 330µF as shown in Figure 1. The operating voltage
range is from 43V to 71V with a UV turn-off threshold of
38.5V.
The design flow starts with calculating the maximum in-
put current:
IMAX =200W
36V
=5.6A
where 36V is the minimum input voltage.
The selection of the sense resistor, RS, is determined by
the minimum current limit threshold and maximum input
current:
RS=
DV
SENSE(MIN)
I
MAX
=45mV
5.6A =8mW
The inrush current is set to 0.66A using CR:
CR=CL•
I
RAMP
I
INRUSH
=330µF •
20µA
0.66A =10nF
The value of RF and CF are chosen to 1k and 33nF as
discussed previously.
The FET is selected to handle the maximum power dissi-
pation during start-up or an input step. The latter usually
results in a larger power due to summation of the inrush
current charging CL and the load current. For a 36V input
step, the total P2t in the FET is approximated by:
P2t=36V •IMAX
( )
2•t
3
where t is the time it takes to charge up CL:
t=CL• 36V
I
INRUSH
=330µF • 36V
0.66A =18m
s
which gives a P2t value of 244W2s.
Now the P2t given by the SOA (safe operating area)
curves of candidate FETs must be higher than 244W2s.
The SOA curves of the IRF1310NS provide for 5A at 50V
(250W) for 10ms, which gives a P2t value of 625W2s and
satisfies the requirement.
Sizing R1, R2 and R3 for the required UV and OV thresh-
old voltages:
VUV(RISING) = 43V, VUV(FALLING) = 38.5V, (using
VUVH(TH) = 2.56V and VUVH(TH) = 2.291V)
VOV(RISING) = 72.3V, VOV(FALLING) = 70.7V (using
VOV(TH) = 1.77V rising and 1.7325V falling)
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended (Figure 10). The minimum trace width
for 1oz copper foil is 0.02" per amp to make sure the
trace stays at a reasonable temperature. Using 0.03" per
amp or wider is recommended. Note that 1oz copper ex-
hibits a sheet resistance of about 530µW/square. Small
resistances add up quickly in high current applications.
The VEE pin of the LTC4261 should be connected to a
separate plane that is different from the main –48V in-
put plane. To improve noise immunity, as shown in
Figure10, the VEE connections of all capacitors, resistive
dividers, opto-isolators and I2C common must be made
directly to the local VEE plane, not the –48V input plane.
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
24
42612fd
For more information www.linear.com/LTC4261
I2C Interface
The LTC4261/LTC4261-2 feature an I2C interface to pro-
vide access to the ADC data registers and four other regis-
ters for monitoring and control of the pass FET. Figure 11
shows a general data transfer format using the I2C. The
LTC4261/LTC4261-2 are read-write slave devices and
support SMBus bus Read Byte, Write Byte, Read Word and
Write Word commands. The second word in a Read Word
command will be identical to the first word. The second
word in a Write Word command is ignored. The data for-
mats for these commands are shown in Figures 12 to 15.
Using Opto-Isolators with SDA
The LTC4261/LTC4261-2 split the SDA line into SDAI (in-
put) and SDAO (output) for convenience of opto-coupling
with the host. If opto-isolators are not used then tie SDAI
and SDAO together to form a normal SDA line. When us-
ing opto-isolators, connect the SDAI pin to the output of
the incoming opto-isolator and connect the SDAO pin to
the input of the outgoing opto-isolator (see Figure 2). If
the SDAI and SDAO on the master controller are not tied
together, the ACK bit of SDAO must be returned back to
SDAI. If the ALERT line is used as an interrupt for the
host to respond to a fault in real time, connect the ALERT
pin to an opto-isolator in a way similar to that for the
SDAO pin as shown in Figure 2.
Figure 11. Data Transfer over I2C or SMBus
Figure 12. LTC4261 Serial Bus SDA Write Byte Protocol
Figure 13. LTC4261 Serial Bus SDA Write Word Protocol
Figure 14. LTC4261 Serial Bus SDA Read Byte Protocol
Figure 15. LTC4261 Serial Bus SDA Read Word Protocol
APPLICATIONS INFORMATION
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/WACK DATA ACK DATA ACK
1 - 7 8 9
42612 F11
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
S ADDRESS
0 0 1 a3:a0
42612 F12
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A
: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
COMMAND DATA
X X X X b3:b00
W
0 0 0b7:b0
A A A P S ADDRESS
0 0 1 a3:a0
COMMAND DATA DATA
X X X X b3:b00
W
0 0 0 0
42612 F13
X X X X X X X Xb7:b0
AA A A P
S ADDRESS
0 0 1 a3:a0 0 0 1 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X b3:b00
W
0 0
42612 F14
A A AP
S ADDRESS
0 0 1 a3:a0 0 0 1 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X b3:b00
W
0 0
42612 F15
A
0
A
b7:b0
DATA
AAP
MOSFET
TO SENSE PIN
–48V INPUT PLANE
VEE PLANE
LTC4261 VEE PIN
ALL CAPACITORS
ALL RESISTIVE DIVIDERS
ALL OPTO-ISOLATORS
I2C COMMON
D
G
S
RS
VIAS
42612 F10
•
•
•
•
Figure 10. Layout Example of VEE Plane, –48V Input Plane and
Sense Resistor Connection
LTC4261/LTC4261-2
25
42612fd
For more information www.linear.com/LTC4261
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transiting SDA from high to low
while SCL is high. When the master has finished com-
municating with the slave, it issues a STOP condition by
transiting SDA from low to high while SCL is high. The
bus is then free for another transmission.
Stuck-Bus Reset
The LTC4261/LTC4261-2 I2C interface features a stuck-
bus reset timer. The low conditions of the SCL and the
SDAI pins are ORed to start the timer. The timer is reset
when both SCL and SDAI are pulled high. If the SCL pin
or the SDAI pin is held low for over 66ms, the stuck-bus
timer will expire and the internal I2C state machine will
be reset to allow normal communication after the stuck-
low condition is cleared. When the SCL pin and the SDAI
pin are held low alternatively, if the ORed low period of
SCL and SDAI exceeds 66ms before the timer reset con-
dition (both SCL and SDAI are high) occurs, the stuck-
bus timer will expire and the I2C state machine is reset.
I2C Device Addressing
Any of eight distinct I2C bus addresses are selectable us-
ing the three-state pins ADR0 and ADR1, as shown in
Table 1. Note that the configuration of ADR0 = L and ADR1
= H is used to enable the single-wire broadcasting mode.
For the eight I2C bus addresses, address bits B6, B5 and
B4 are configured to (001) and the least significant bit B0
is the R/W bit. In addition, the LTC4261/LTC4261-2 will
respond to two special addresses. Address (0011 111)
is a mass write used to write to all LTC4261/LTC4261-2s,
regardless of their individual address settings. Address
(0001 100) is the SMBus Alert Response Address. If the
LTC4261/LTC4261-2 are pulling low on the ALERT pin,
it will acknowledge this address using the SMBus Alert
Response Protocol.
Acknowledge
The acknowledge signal is used for handshaking be-
tween the transmitter and the receiver to indicate that the
last byte of data was received. The transmitter always re-
leases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it must pull down the SDA
line so that it remains LOW during this pulse to acknowl-
edge receipt of the data. If the slave fails to acknowl-
edge by leaving SDA HIGH, then the master can abort
the transmission by generating a STOP condition. When
the master is receiving data from the slave, the master
must pull down the SDA line during the clock pulse to
indicate receipt of the data. After the last byte has been
received the master will leave the SDA line HIGH (not
acknowledge) and issue a STOP condition to terminate
the transmission.
Write Protocol
The master begins communication with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero. The addressed LTC4261/LTC4261-2
acknowledge this and then the master sends a command
byte which indicates which internal register the master
wishes to write. The LTC4261/LTC4261-2 acknowledge
this and then latch the lower four bits of the command
byte into its internal Register Address pointer. The master
then delivers the data byte and the LTC4261/LTC4261-2
acknowledge once more and latch the data into its inter-
nal register. The transmission is ended when the master
sends a STOP condition. If the master continues sending
a second data byte, as in a Write Word command, the
second data byte will be acknowledged by the LTC4261/
LTC4261-2 but ignored.
Read Protocol
The master begins a read operation with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero. The addressed LTC4261/LTC4261-2
acknowledge this and then the master sends a command
byte that indicates which internal register the master
wishes to read. The LTC4261/LTC4261-2 acknowledge
this and then latch the lower four bits of the command
byte into its internal Register Address pointer. The mas-
ter then sends a repeated START condition followed by
the same seven bit address with the R/W bit now set to
one. The LTC4261/LTC4261-2 acknowledge and send the
contents of the requested register. The transmission is
ended when the master sends a STOP condition. If the
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
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master acknowledges the transmitted data byte, as in a
Read Word command, the LTC4261/LTC4261-2 will re-
peat the requested register as the second data byte. Note
that the Register Address pointer is not cleared at the
end of the transaction. Thus the Receive Byte protocol
can be used to repeatedly read a specific register.
Alert Response Protocol
The LTC4261/LTC4261-2 implement the SMBus Alert
Response Protocol as shown in Figure 16. If enabled
to do so through the ALERT register C, the LTC4261/
LTC4261-2 will respond to faults by pulling the ALERT
pin low. Multiple LTC4261/LTC4261-2s can share a com-
mon ALERT line and the protocol allows a master to de-
termine which LTC4261/LTC4261-2s are pulling the line
low. The master begins by sending a START bit followed
by the special Alert Response Address (0001 100)b with
the R/W bit set to one. Any LTC4261/LTC4261-2 that is
pulling its ALERT pin low will acknowledge and begin
sending back its individual slave address.
Figure 16. LTC4261 Serial Bus SDA Alert Response Protocol
APPLICATIONS INFORMATION
this means repeated or continuing faults will not gener-
ate alerts until the associated FAULT register bit has been
cleared.
Single-Wire Broadcast Mode
The L
TC4261/LTC4261-2 provides a single-wire broadcast
mode in which selected register data are sent out to the
SDAO pin without clocking the SCL line (Figure 17). The
single-wire broadcast mode is enabled by setting the
ADR1 pin high and the ADR0 pin low (the I2C interface is
disabled). At the end of each conversion of the three ADC
channels, a stream of eighteen bits are broadcasted to
SDAO with a serial data rate of 15.3kHz ±20% in a format
as illustrated in Figure 18. The data bits are encoded with
an internal clock in a way similar to Manchester encoding
that can be easily decoded by a microcontroller or FPGA.
Each data bit consists of a noninverting phase and an
inverting phase. During the conversion of each ADC chan-
nel, SDAO is idle at high. At the end of the conversion, the
SDAO pulls low. The START bit indicates the beginning of
data broadcasting and is used along with the dummy bit
(DMY) to measure the internal clock cycle (i.e., the serial
data rate). Following the DMY bit are two channel code
bits CH1 and CH0 labeling the ADC channel (see Table
10). Ten data bits of the ADC channel (ADC9-0) and three
FAULT register bits (B2, B1 and B0) are then sent out. A
parity bit (PRTY) ends each data stream. After that the
SDAO line enters the idle mode with SDAO pulled high.
The following data reception procedure is recommended:
0. Wait for INTVCC rising edge.
1. Wait for SDAO falling edge.
2. The first falling edge could be a glitch, so check again
after a delay of 10µs. If back to high, wait again. If still
low, it is the START bit.
3. Use the following low-to-high and high-to-low transis-
tions to measure 1/2 of the internal clock cycle.
S
ALERT
RESPONSE
ADDRESS
0 0 0 1 1 0 0
DEVICE
ADDRESS
0 0 1 a3:a0 0 11
R
0
42612 F16
AAP
An arbitration scheme ensures that the LTC4261/
LTC4261-2 with the lowest address will have priority;
all others will abort their response. The successful re-
sponder will then release its ALERT pin while any others
will continue to hold their ALERT pins low. Polling may
also be used to search for any LTC4261/LTC4261-2 that
have detected faults. Any LTC4261/LTC4261-2 pulling its
ALERT pin low will also release it if it is individually ad-
dressed during a read or write transaction.
The ALERT signal will not be pulled low again until the
FAULT register indicates a different fault has occurred or
the original fault is cleared and it occurs again. Note that
LTC4261/LTC4261-2
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Figure 17. Single-Wire Broadcast Mode
Figure 18. Single-Wire Broadcast Data Format
4. Wait for the second low-to-high transistion (middle of
DMY bit).
5. Wait 3/4 of a clock cycle.
6. Sample bit CH1, wait for transistion.
7. Wait 3/4 of a clock cycle.
8. Sample bit CH0, wait for transistion.
9. Wait 3/4 of a clock cycle.
10. Sample ADC9, wait for transistion.
11. Continue until all bits are read.
APPLICATIONS INFORMATION
The above procedure can be ported to a microcontroller
or used to design a state machine in FPGA. Code should
have timeouts in case an edge is missed. Abort the read
if it takes more than double the typical time (1.2ms) for
all 18 bits to be clocked out.
A typical application circuit with the LTC4261/LTC4261-2
in the broadcast mode is illustrated in Figure 19, where
input voltage, VDS of the FET and VSENSE are monitored.
Register Addresses and Contents
The register addresses and contents are summerized in
Table 1 and Table 2. The function of each register bit is
detailed in Tables 3 to 9.
SDAI
SCL
SDAO
ADR1
ADR0 LTC4261
VIN
INTVCC
VEE
6 × 0.51k IN SERIES
1/4W EACH
–48V RTN
–48V INPUT
0.1µF
1µF
7.5k
42612 F17
VDD
5V
DIN
VCC
GND
ANODE
CATHODE
RL
HCPL-0300
VOUT MICRO-
CONTROLLER
INTERNAL
CLK
DATA
SDAO
START
START DMY CH1 CH0 OC OV PRTY
4261 F18
UVADC9 .. .. .. ADC0
CH1
CH1
CH0
CH0
0C
0C
UV
UV
OV
OV
ADC9
ADC0
ADC9
ADC0
PRTY
PRTY
LTC4261/LTC4261-2
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Table 1. LTC4261 Device Addressing
DESCRIPTION
HEX DEVICE
ADDRESS BINARY DEVICE ADDRESS
LTC4261
ADDRESS PINS
h 6543210R/WADR1 ADR0
Mass Write 3E 0 0 1 1 1 1 1 0 X X
Alert Response 19 0 0 0 1 1 0 0 1 X X
0 20 0 0 1 0 0 0 0 X L L
1 22 0 0 1 0 0 0 1 X L NC
2 24 0 0 1 0 0 1 0 X H NC
3 26 0 0 1 0 0 1 1 X L H
4 28 0 0 1 0 1 0 0 X NC L
5 2A 0 0 1 0 1 0 1 X NC NC
6 2C 0 0 1 0 1 1 0 X H H
7 2E 0 0 1 0 1 1 1 X NC H
8 Single-Wire Broadcast Mode H L
H = Tie to INVCC; L = Tie to VEE; NC = No connect, open; X = Don’t care
Table 2. LTC4261 Register Address and Contents
REGISTER
ADDRESS*
REGISTER
NAME READ/WRITE DESCRIPTION
00h STATUS (A) R System Status Information
01h FAULT (B) R/W Fault Log and PGIO Input
02h ALERT (C) R/W Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register
03h CONTROL (D) R/W Controls Whether the Part Retries After Faults, Set the On/Off Switch State
04h SENSE (E) R/W** ADC Current Sense Voltage Data (8 MSBs)
05h SENSE (F) R/W** ADC Current Sense Voltage Data (2 LSBs)
06h ADIN2/OV (G) R/W** ADC ADIN2/OV (SSOP/QFN) Voltage Data (8 MSBs)
07h ADIN2/OV (H) R/W** ADC ADIN2/OV (SSOP/QFN) Voltage Data (2 LSBs)
08h ADIN (I) R/W** ADC ADIN Voltage Data (8 MSBs)
09h ADIN (J) R/W** ADC ADIN Voltage Data (2 LSBs)
*Register address MSBs b7-b4 are ignored. **Writable if bit D5 set.
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
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Table 3. STATUS Register A (00h)—Read Only
BIT NAME OPERATION
A7 FET On Indicates State of FET; 1 = FET On, 0 = FET Off
A6 PGIO Input Indicates State of the PGIO Pin when Configured to General Purpose Input: 1 = PGIO High, 0 = PGIO Low
A5 FET Short Indicates Potential FET Short if Current Sense Voltage Exceeds 2mV While FET is Off; 1 = FET is Shorted, 0 = FET is Not Shorted
A4 EN Indicates State of the EN Pin; 1 = EN Pin High, 0 = EN Pin Low
A3 Power Bad Indicates Power is Bad when PGI is High at the End of the PGI Check Timer; 1 = PGI High, 0 = PGI Low
A2 Overcurrent Indicates Overcurrent Condition; 1 = Overcurrent, 0 = Not Overcurrent
A1 Undervoltage Indicates Input Undervoltage when Both UVH and UVL are Low; 1 = UVH and UVL Low, 0 = UVH or UVL High
A0 Overvoltage Indicates Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low
Table 4. FAULT Register B (01h)—Read/Write
BIT NAME OPERATION
B7 External Fault
Occurred
Latched to 1 if FLTIN Goes Low; 1 = FLTIN Low State Detected, 0 = FLTIN has Not Been Low
B6 PGIO Input
High Occurred
Latched to 1 if the PGIO Pin Goes High when Configured to General Purpose Input; 1 = PGIO High Detected,
0 = PGIO has Been Low
B5 FET Short Fault
Occurred
Indicates Potential FET Short was Detected When Measured Current Sense Voltage Exceeded 2mV While FET was Off;
1 = FET Short Fault Occurred, 0 = No FET Short Fault
B4 EN Changed
State
Indicates That a Board was Inserted or Extracted when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged
B3 Power Bad
Fault Occurred
Indicates Power was Bad when PGI was High at the End of the PGI Check Timer; 1 = Power Bad Fault Occurred,
0 = No Power Bad Fault
B2 Overcurrent
Fault Occurred
Indicates Overcurrent Fault Occurred; 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Fault
B1 Undervoltage
Fault Occurred
Indicates Input Undervoltage Fault Occurred when Both UVH and UVL went Low; 1 = Undervoltage Fault Occurred,
0 = No Undervoltage Fault
B0 Overvoltage
Fault Occurred
Indicates Input Overvoltage Fault Occurred when OV was High; 1 = Overvoltage Fault Occurred, 0 = No Overvoltage Fault
Table 5. ALERT Register C (02h)—Read/Write
BIT NAME OPERATION
C7 External Fault
Alert
Enables Alert for External Fault When FLTIN was Low; 1 = Enable Alert, 0 = Disable Alert (Default)
C6 PGIO Output Output Data Bit to PGIO Pin when Configured as Output. Defaults to 0
C5 FET Short Alert Enables Alert for FET Short Fault; 1 = Enable Alert, 0 = Disable Alert (Default)
C4 EN State
Change Alert
Enables Alert when EN Changed State; 1 = Enable Alert, 0 Disable Alert (Default)
C3 Power Bad
Alert
Enables Alert for Power Bad Fault; 1 = Enable Alert, 0 Disable Alert (Default)
C2 Overcurrent
Alert
Enables Alert for Overcurrent Fault; 1 = Enable Alert, 0 Disable Alert (Default)
C1 Undervoltage
Alert
Enables Alert for Undervoltage Fault; 1 = Enable Alert, 0 Disable Alert (Default)
C0 Overvoltage
Alert
Enables Alert for Overvoltage Fault; 1 = Enable Alert, 0 Disable Alert (Default)
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
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Table 6. CONTROL Register D (03h)—Read/Write
BIT NAME OPERATION
D7:6 PGIO Configure Configures Behavior of PGIO Pin
FUNCTION D6 D7 PGIO PIN
Power Good (Default) 0 0 Open Drain
Power Good 0 1 Open Drain
General Purpose Output 1 0 PGIO = C6
General Purpose Input 1 1 PGIO = Hi-Z
D5 Test Mode Enable Test Mode Halts ADC Operation and Enables Writes to ADC Registers; 1 = Enable Test Mode, 0 = Disable Test Mode (Default)
D4 Power Bad
Auto-Retry
Enables Auto-Retry After a Power Bad Fault; 1 = Retry Enabled, 0 = Retry Disabled (Default)
D3 FET On Control Turns FET On and Off; 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Start-Up Debounce Delay
D2 Overcurrent
Auto-Retry
Enables Auto-Retry After an Overcurrent Fault; 1 = Retry Enabled (Default, LTC4261-2),
0 = Retry Disabled (Default, LTC4261)
D1 Undervoltage
Auto-Retry
Enables Auto-Retry After an Undervoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled
D0 Overvoltage
Auto-Retry
Enables Auto-Retry After an Overvoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled
Table 7. SENSE Registers E (04h) and F (O5h)—Read/Write
BIT NAME OPERATION
E7:0, F7:6 SENSE Voltage Data 10-Bit Data of Current Sense Voltage with 62.5µV LSB and 64mV Full Scale
F5:0 Reserved Always Returns 0, Not Writable
Table 8. ADIN2/OV Registers G (06h) and H (O7h)—Read/Write
BIT NAME OPERATION
G7:0, H7:6 ADIN2/OV Voltage Data 10-Bit Data of ADIN2/OV (SSOP/QFN) Voltage with 2.5mV LSB and 2.56V Full Scale
H5:0 Reserved Always Returns 0, Not Writable
Table 9. ADIN Registers I (08h) and J (O9h)—Read/Write
BIT NAME OPERATION
I7:0, J7:6 ADIN Voltage Data 10-Bit Data of ADIN Voltage with 2.5mV LSB and 2.56V Full Scale
J5:0 Reserved Always Returns 0, Not Writable
Table 10. ADC Channel Labeling for Single-Wire Broadcast Mode
CH1 CH0 ADC CHANNEL
0 0 SENSE Voltage
0 1 ADIN2/OV (SSOP/QFN) Voltage
1 0 ADIN Voltage
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
31
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For more information www.linear.com/LTC4261
TYPICAL APPLICATION
PACKAGE DESCRIPTION
Using the LTC4261 and a Thermistor to Monitor Temperature
VIN
LTC4261CGN
SDAO
SDAI
SCL
ADIN
100k AT 25°C
1%
VISHAY
NTCS0402E3104*HT
30.1k
1%
10k
1%
T (°C) = 38.05 • (V
ADIN
(V) – 0.1458), 20°C < T < 60°C
1µF
42612 TA02
–48V RTN
–48V INPUT
I2C
6 ×
0.51k IN SERIES
1/4W EACH
VEE
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.386 – .393*
(9.804 – 9.982)
GN28 REV B 0212
1 2 345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
202122232425262728 19 18 17
13 14
1615
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
LTC4261/LTC4261-2
32
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PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
23 24
1
2
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05 R = 0.115
TYP
R = 0.05 TYP PIN 1 NOTCH
R = 0.20 OR C = 0.35
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD24) QFN 0506 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.65 ±0.05
2.00 REF
3.00 REF
4.10 ±0.05
5.50 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
2.00 REF
3.00 REF
3.65 ±0.10
3.65 ±0.05
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1696 Rev A)
LTC4261/LTC4261-2
33
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For more information www.linear.com/LTC4261
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 9/11 Change to Electrical Characteristics Gate Turn-Off Current
Update to Typical Performance Characteristics graph G06
Update to Pin Functions SDAI (Pin 5/Pin 2) description
Update to Block Diagram
Text changes to Operations section
Added Figure 3
Update to Figure 4
Text changes to Applications Information
Update to Typical Applications Figure 17
3
6
9
11
12
14
16
14, 17, 18, 22, 24
34
D 6/14 Separated VEE connection of LTC4261 and related components from –48V input plane in circuit figures
Added patent numbers
Changed delay conditions to GATE Open from CGATE = 1pF
Layout Considerations section: Added paragraph and Figure 10 on separating local VEE plane from -48V
input plane
1, 13, 20, 22, 27, 31, 34
1
3
23, 24
(Revision history begins at Rev C)
LTC4261/LTC4261-2
34
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For more information www.linear.com/LTC4261
LINEAR TECHNOLOGY CORPORATION 2005
LT 0614 REV D • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4261
PART NUMBER DESCRIPTION COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to –80V
LTC1921 Dual –48V Supply and Fuse Monitor UV/OV Monitor, –10V to –80V Operation, MSOP Package
LT4250L/LT4250H –48V Hot Swap Controllers in SO-8 Active Current Limiting, Supplies from –18V to –80V
LTC4251/LTC4251-1 –48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
–48V Hot Swap Controllers in MS8 Fast Active Current Limiting, Supplies from –15V
,
±1% UV/OV (LTC4252A)
LTC4253 –48V Hot Swap Controller with Sequencer Fast Current Limiting with Three Sequenced Power Good Outputs,
Supplies from –15V
LTC4260 Positive High Voltage Hot Swap Controller With I2C and ADC, Supplies from 8.5V to 80V
LTC4354 Negative Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, 80V Operation
Figure 19. Application Circuit of the LTC4261 in Single-Wire Broadcast Mode
TYPICAL APPLICATIONS
RELATED PARTS
SDAI
SCL
SDAO
ADIN
UVL
UVH
ADIN2
OV
ADR1
ADR0
GATE DRAIN RAMP
LTC4261CGN
VIN
INTVCC
ON
VEE
TMRSS EN SENSE
RIN
6 × 0.51k IN SERIES
1/4W EACH
R3
432k
1%
–48V RTN
–48V INPUT
R2
15.8k
1%
R1
11.5k
1%
CVCC
0.1µF
CTMR
47nF
CSS
220nF CG
47nF
CF
33nF
CR
10nF
100V
5%
RG
10Ω
RD
1M
CIN
1µF
RS
0.02Ω
1% VOUT
Q1
IRF1310NS
R6
10k 1%
R7
402k 1%
CL
330µF
100V
4261 F19
VDD
5V
DIN
MICRO-
CONTROLLER
GND
VCC
ANODE
R4
7.5k
CATHODE
RL
HCPL-0300
VOUT
RF
1k
