HT36B4
Music Synthesizer 8-Bit MCU
Block Diagram
Rev. 1.00 1 October 18, 2006
Features
·Operating voltage: 2.4V~5.0V
·Operating frequency: 3.58MHz~12MHz
(typ. 11.059MHz)
·28 bidirectional I/O lines
·Two 16-bit programmable timer/event counters with
overflow interrupts
·Watchdog Timer
·Built-in 8-bit MCU with 208´8 bits RAM
·Built-in 64K´16-bit ROM for program/data shared
·Digital output pins for external DAC
·Single data format with 16 bits digital stereo audio
output
·Two High D/A converter resolution: 16 bits
·Polyphonic up to 16 notes
·Independent pan and volume mix can be assigned to
each sound component
·Sampling rate of 44.1kHz as 11.059MHz for system
frequency
·Eight-level subroutine nesting
·HALT function and wake-up feature to reduce power
consumption
·Bit manipulation instructions
·16-bit table read instructions
·63 powerful instructions
·All instructions in 1 or 2 machine cycles
·48-pin SSOP package
General Description
The HT36B4 is an 8-bit high performance RISC-like
microcontroller specifically designed for music applica-
tions. It provides an 8-bit MCU and a 16 channel
wavetable synthesizer. The program ROM is composed
of both program control codes and wavetable voice
codes, and can be easily programmed.
The HT36B4 has a built-in 8-bit microprocessor which
programs the synthesizer to generate the melody by
setting the special register from 20H~2AH. A HALT fea-
ture is provided to reduce power consumption.
8 - B i t
M C U
64K
´
1 6 - b i t
R O M
208
´
8
R A M
M u l t i p l i e r / P h a s e
G e n e r a l
1 6 - B i t
D A C
P A 0 ~ P A 7
P B 0 ~ P B 7
P C 0 ~ P C 7
P D 0 ~ P D 3
O S C 1
O S C 2
R E S
1 6 - B i t
D A C
V D D
V S S
V D D A
RCH
L C H
P D 3 / D C K
P D 2 / L O A D
P D 1 / D O U T
P F 0 ~ 2
V S S A
Technical Document
·Tools Information
·FAQs
·Application Note
Pin Assignment
Pad Assignment
Chip size: 2690 ´3095 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT36B4
Rev. 1.00 2 October 18, 2006
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
N C
O S C 1
V S S
V S S
V D D
N C
N C
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
P B 1
N C
P B 2
P B 3
P B 4
P B 5
P B 6
N C
N C
O S C 2
V D D A
L C H
RCH
V S S A
N C
R E S
P D 3
P D 2
P D 1
P D 0
P C 7
P C 6
P C 5
P C 4
N C
N C
P C 3
P C 2
P C 1
P C 0
P B 7
N C
H T 3 6 B 4
4 8 S S O P - A
( 0 , 0 )
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
P D 3
P D 2
P D 1
P D 0
R E S
RCH
L C H
O S C 2
O S C 1
V S S
V S S
V D D
V D D A
V S S A
1
2
3
4
5
6
7
8
9
1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
2 4
2 3
2 2
2 1
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
P A 7
P B 0
P B 1
Pad Coordinates Unit: mm
Pad No. X Y Pad No. X Y
1-1194.900 1108.540 20 1198.360 -1396.900
2-1194.900 1013.540 21 1194.200 -1191.950
3-1194.900 910.540 22 1194.200 -1096.950
4-1194.900 815.540 23 1194.200 -993.950
5-1194.900 712.540 24 1194.200 -898.950
6-1194.900 617.540 25 1194.200 36.550
7-1194.900 514.540 26 1194.200 131.550
8-1194.900 -1203.060 27 1194.200 234.550
9-1194.900 -1306.060 28 1194.200 329.550
10 -1194.900 -1401.060 29 1194.200 432.550
11 -989.950 -1396.900 30 1138.475 1393.120
12 -894.950 -1396.900 31 1038.450 1393.120
13 -791.950 -1396.900 32 925.450 1393.120
14 -696.950 -1396.900 33 819.765 1393.120
15 -593.950 -1396.900 34 -154.540 1392.655
16 802.360 -1396.900 35 -249.540 1392.655
17 905.360 -1396.900 36 -376.070 1390.100
18 1000.360 -1396.900 37 -487.200 1390.600
19 1103.360 -1396.900 38 -601.535 1390.100
Pad Description
Pad No. Pad Name I/O Internal
Connection Function
1~8 PA0~PA7 I/O Pull-High
or None Bidirectional 8-bit Input/Output port, wake-up by mask option
9~16,
17~24,
25
PB0~PB7,
PC0~PC7,
PD0
I/O Pull-High
or None Bidirectional 8-bit Input/Output port
26 PD1/DOUT I/O Pull-High
or None Bidirectional 8-bit Input/Output port DAC data out
27 PD2/LOAD I/O Pull-High
or None Bidirectional 8-bit Input/Output port DAC word clock
28 PD3/DCK I/O Pull-High
or None Bidirectional 8-bit Input/Output port DAC bit clock
29 RES I¾Reset input, active low
30 VSSA ¾¾
Negative power supply of DAC, ground
31 RCH O CMOS R channel audio output
32 LCH O CMOS L channel audio output
33 VDDA ¾¾
DAC power supply
35
34
OSC1
OSC2
I
O¾
OSC1 and OSC2 are connected to an RC network or a crystal (by
mask option) for the internal system clock. In the case of RC opera-
tion, OSC2 is the output terminal for 1/4 system clock
(fOSC2=fOSC/8). The system clock may come from the crystal, the
two pins cannot be floating.
36, 37 VSS ¾¾
Negative power supply, ground
38 VDD ¾¾
Positive power supply
HT36B4
Rev. 1.00 3 October 18, 2006
Absolute Maximum Ratings
Supply Voltage .............................VSS-0.3V to VSS+6V Storage Temperature ...........................-50°Cto125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-40°Cto85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾¾ 2.4 3 5 V
IDD Operating Current 5V No load,
fOSC=11.0592MHz ¾816mA
ISTB Standby Current (WDT Disabled) 5V No load, System HALT ¾0¾mA
IOL I/O Ports Sink Current 5V VOL=0.5V 9.7 16.2 ¾mA
IOH I/O Ports Source Current 5V VOH=4.5V -5.2 -8.7 ¾mA
RPH Pull-High Resistance of I/O Ports 5V VIL=0V 11 22 44 kW
VIH1 Input High Voltage for I/O Ports 5V ¾3.5 ¾5V
VIL1 Input Low Voltage for I/O Ports 5V ¾0¾1.5 V
VIH2 Input High Voltage (RES)5V ¾¾
4¾V
VIL2 Input Low Voltage (RES)5V ¾¾
2.5 ¾V
A.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
MCU interface
fOSC System Frequency 5V 12MHz crystal ¾12 ¾MHz
fSYS System Clock 5V ¾4¾16 MHz
tWDT Watchdog Time-Out Period (RC) ¾Without WDT prescaler 9 17 35 ms
tRES External Reset Low Pulse Width ¾¾ 1¾¾ms
Symbol Parameter Figure Min. Typ. Max. Unit
DAC interface
fBC DCK Bit Clock Frequency Fig 1 ¾fSYS/16 ¾MHz
tCH DCK Bit Clock H Level Time Fig 1 600 ¾¾ns
tDOS Data Output Setup Time Fig 1 200 ¾¾ns
tDOH Data Output Hold Time Fig 1 200 ¾¾ns
tLCS Load Clock Setup Time Fig 1 200 ¾¾ns
tLCH Load Clock Hold Time Fig 1 200 ¾¾ns
HT36B4
Rev. 1.00 4 October 18, 2006
Characteristics Curves
V vs F Characteristics Curve
R vs F Characteristics curve
HT36B4
Rev. 1.00 5 October 18, 2006
V o l t a g e ( V )
H T 3 6 B 4 V v s F C h a r t
8
9
1 0
1 1
1 2
1 3
1 4
2 2 . 5 33 . 5 4 4 . 5 5 5 . 5 6
F r e q u e n c y ( M H z )
1 1 M H z / 1 0 0 k W
F r e q u e n c y ( M H z )
H T 3 6 B 4 R v s F C h a r t
4
6
8
1 0
1 2
1 4
1 6
1 8
2 0
5 6 7 5 1 0 0 2 0 0
5 . 0 V
4 . 5 V
R ( k
W )
HT36B4
Rev. 1.00 6 October 18, 2006
Function Description
Execution Flow
The system clock for the HT36B4 is derived from either
a crystal or an RC oscillator. The oscillator frequency di-
vided by 2 is the system clock for the MCU
(fOSC=fSYS´2) and it is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
Program Counter -PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 8192 ad-
dresses for each bank.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Other-
wise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Once a control transfer takes place, an additional
dummy cycle is required.
Program ROM
HT36B4 provides 16 address lines WA15~0 to read the
Program ROM which is up to 1M bits, and is commonly
used for the wavetable voice codes and the program
memory. It provides two address types, one type is for
program ROM, which is addressed by a bank pointer
PF2~0 and a 13-bit program counter 12~0; and the
other type is for wavetable code, which is addressed by
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C P C + 1 P C + 2
S y s t e m C l o c k o f M C U
( f S Y S = f O S C / 2 )
P C
Execution Flow
Mode Program Counter
*15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0000000000000000
Timer/Event Counter 0 Overflow 0000000000001000
Timer/Event Counter 1 Overflow 0000000000001100
Skip Program Counter + 2
Loading PCL PF2 PF1 PF0 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch PF2 PF1 PF0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return From Subroutine PF2 PF1 PF0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: *12~*0: Bits of Program Counter @7~@0: Bits of PCL
#12~#0: Bits of Instruction Code S12~S0: Bits of Stack Register
@7~@0: Bits of PCL PF2~PF0: Bits of Bank Register
HT36B4
Rev. 1.00 7 October 18, 2006
the start address ST11~0. On the program type,
WA15~0= PF2~0 ´213+ PC12~0. On the wave table
ROM type, WA16~0=ST11~0 ´25.
Program Memory -ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.
Certain locations in the program memory of each bank
are reserved for special usage:
·Location 000H on bank0
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H on bank0.
·Location 008H
This area is reserved for the Timer/Event Counter 0 in-
terrupt service program on each bank. If timer interrupt
results from a timer/event counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program
begins execution at location 008H corresponding to its
bank.
·Location 00CH
This area is reserved for the Timer/Event Counter 1
interrupt service program on each bank. If a timer in-
terrupt results from a Timer/Event Counter 1 overflow,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH corre-
sponding to its bank.
·Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table lo-
cation. Before accessing the table, the location must
be placed in TBLP. The TBLH is read only and cannot
be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruc-
tion, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the ta-
ble read instruction in the main routine and the ISR si-
multaneously should be avoided. However, if the table
read instruction has to be applied in both the main rou-
tine and the ISR, the interrupt should be disabled prior
to the table read instruction. It will not be enabled until
the TBLH has been backed up. All table related in-
structions need 2 cycles to complete the operation.
These areas may function as normal program mem-
ory depending upon user requirements.
·Bank pointer
The program memory is organized into 8 banks and
each bank into 8192´16 of bits program ROM. PF2~0
is used as the bank pointer. After an instruction has
been executed to write data to the PF register to se-
lect a different bank, note that the new bank will not be
selected immediately. After an instruction cycle is exe-
cuted, the new bank is only selected. When the PF
register is used to select the bank, the PF register is
write only. It is not until the following instruction has
completed execution that the bank will be actually se-
lected. It should be note that the PF register has to be
cleared before setting to output mode.
0000H
0008H
T i m e r / e v e n t C o u n t e r 0 i n t e r r u p t s u b r o u t i n e
P r o g r a m
R O M
1 6 b i t s
Look-up table (256 w ords)
n00H
Look-up table (256 w ords)
1 F F F H
N o t e : n r a n g e s f r o m 0 0 t o 1 F .
n F F H
T i m e r / e v e n t C o u n t e r 1 i n t e r r u p t s u b r o u t i n e
000C H
D e v i c e i n i t i a l i z a t i o n p r o g r a m
Program Memory for Each Bank
Instruction(s) Table Location
*15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P15 P14 P13 P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] P15 P14 P13 11111@7@6@5@4@3@2@1@0
Table Location
Note: *12~*0: Bits of table location @7~@0: Bits of table pointer
P12~P8: Bits of current Program Counter P15~P13: Bits of bank PF2~PF0
HT36B4
Rev. 1.00 8 October 18, 2006
Wavetable ROM
The ST11~0 is used to defined the start address of each
sample on the wavetable and read the waveform data
from the location. HT36B4 provides 21 output address
lines from WA16~0, the ST11~0 is used to locate the
major 16 bits i.e. WA16~5 and the undefined data from
WA4~0 is always set to 00000b. So the start address of
each sample have to be located at a multiple of 32. Oth-
erwise, the sample will not be read out correctly be-
cause it has a wrong starting code.
Stack Register -Stack
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subse-
quently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return ad-
dress are stored).
Data Memory -RAM
The data memory is designed with 256´8 bits. The data
memory is divided into three functional groups: special
function registers, wavetable function register, and gen-
eral purpose data memory (208´8). Most of them are
read/write, but some are read only.
The unused space before 30H is reserved for future ex-
panded usage and reading these locations will return
the result 00H. The general purpose data memory, ad-
dressed from 30H to FFH, is used for data and control
information under instruction command.
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through Memory pointer registers
(MP0;01H, MP1;03H).
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H directly will return the result 00H.
And writing directly results in no operation.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
20H
21H
22H
23H
24H
25H
26H
27H
29H
2 A H
2 B H
2 F H
G e n e r a l P u r p o s e
D a t a M e m o r y
( 2 0 8 B y t e s )
F F H
28H
30H
S p e c i a l P u r p o s e
D a t a M e m o r y
: U n u s e d .
R e a d a s " 0 0 "
W a v e t a b l e
F u n c t i o n
R e g i s t e r
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
M P 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
M P 1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
I N T C
T M R 0 H
T M R 0 L
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
P D
P D C
P F
D A C H i g h B y t e ( D A H )
D A C L o w B y t e ( D A L )
D A C C o n t r o l ( D A C )
C h a n n e l N u m b e r S e l e c t ( C H A N )
F r e q u e n c y N u m b e r H i g h B y t e ( F r e q N H )
F r e q u e n c y N u m b e r L o w B y t e ( F r e q N L )
S t a r t A d d r e s s H i g h B y t e ( A d d r H )
S t a r t A d d r e s s L o w B y t e ( A d d r L )
R e p e a t N u m b e r H i g h B y t e ( R e H )
R e p e a t N u m b e r L o w B y t e ( R e L )
C o n t r o l R e g i s t e r ( E N V )
L e f t V o l u m e C o n t r o l ( L V C )
R i g h t V o l u m e C o n t r o l ( R V C )
RAM Mapping
HT36B4
Rev. 1.00 9 October 18, 2006
The function of data movement between two indirect ad-
dressing registers, is not supported. The memory
pointer registers, MP0 and MP1, are 8-bit register which
can be used to access the data memory by combining
corresponding indirect addressing registers.
Accumulator
The accumulator closely relates to ALU operations. It is
mapped to location 05H of the data memory and it can
operate with immediate data. The data movement be-
tween two data memory locations must pass through
the accumulator.
Arithmetic and Logic Unit -ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
·Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·Logic operations (AND, OR, XOR, CPL)
·Rotation (RL, RR, RLC, RRC)
·Increment & Decrement (INC, DEC)
·Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
can also change the status register.
Status Register -STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag
(TO). It also records the status information and controls the
operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PDF flags. In addition it should
be noted that operations related to the status register
may give different results from those intended. The TO
and PDF flags can only be changed by system power
up, Watchdog Timer overflow, executing the HALT in-
struction and clearing the Watchdog Timer.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
status are important and the subroutine can corrupt the
status register, the programmer must take precautions
to save it properly.
Interrupt
The HT36B4 provides two internal timer/event counter
interrupts on each bank. The Interrupt Control register
(INTC;0BH) contains the interrupt control bits that sets
the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt needs servicing within the service routine, the pro-
grammer may set the EMI bit and the corresponding bit
of the INTC to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full.
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified locations in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which may corrupt the desired control se-
quence, then the programmer must save the contents
first.
Bit No. Label Function
0C
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate
through carry instruction.
1AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-
est-order bit, or vice versa; otherwise OV is cleared.
4 PDF PDF is cleared by either a system power-up or executing the CLR WDT instruction.
PDF is set by executing the HALT instruction.
5TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by
a WDT time-out.
6~7 ¾Unused bit, read as ²0²
STATUS (0AH) Register
HT36B4
Rev. 1.00 10 October 18, 2006
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC), caused by a Timer/Event
Counter 0 overflow. When the interrupt is enabled, and
the stack is not full and the T0F bit is set, a subroutine
call to location 08H will occur. The related interrupt re-
quest flag (T0F) will be reset and the EMI bit cleared to
disable further interrupts.
The Timer/Event Counter 1 interrupt is operated in the
same manner as Timer/Event Counter 0. The related in-
terrupt control bits ET1I and T1F of the Timer/Event
Counter 1 are bit 3 and bit 6 of the INTC respectively.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the RET or RETI in-
struction may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source Priority Vector
Timer/event Counter 0 overflow 1 08H
Timer/event Counter 1 overflow 2 0CH
Once the interrupt request flags (T0F, T1F) are set, they
will remain in the INTC register until the interrupts are
serviced or cleared by a software instruction. It is
recommended that a program does not use the ²CALL
subroutine²within the interrupt subroutine. Because in-
terrupts often occur in an unpredictable manner or need
to be serviced immediately in some applications, if only
one stack is left and enabling the interrupt is not well
controlled, once the ²CALL subroutine²operates in the in-
terrupt subroutine, it may damage the original control
sequence.
Oscillator Configuration
The HT36B4 provides two types of oscillator circuit for
the system clock, i.e., RC oscillator and crystal oscilla-
tor. No matter what type of oscillator, the signal divided
by 2 is used for the system clock. The HALT mode stops
the system oscillator and ignores external signal to con-
serve power. If the RC oscillator is used, an external re-
sistor between OSC1 and VSS is required, and the
range of the resistance should be from 56kWto 680kW.
The system clock, divided by 4, is available on OSC2
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscilla-
tion may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore, not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.
Bit No. Label Function
0 EMI Controls the Master (Global) interrupt (1=enabled; 0=disabled)
1¾Unused bit, read as ²0²
2 ET0I Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3 ET1I Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4¾Unused bit, read as ²0²
5 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7¾Unused bit, read as ²0²
INTC (OBH) Register
C r y s t a l O s c i l l a t o r R C O s c i l l a t o r
O S C 1
O S C 2
O S C 2
f
O S C
/ 8
O S C 1 VD D
System Oscillator
HT36B4
Rev. 1.00 11 October 18, 2006
Watchdog Timer -WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown loca-
tion with unpredictable results. The Watchdog Timer can
be disabled by mask option. If the Watchdog Timer is
disabled, all the executions related to the WDT result in
no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of ap-
proximately 20ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.
WS2 WS1 WS0 Division Ratio
000 1:1
001 1:2
010 1:4
011 1:8
1 0 0 1:16
1 0 1 1:32
1 1 0 1:64
1 1 1 1:128
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a²chip reset²and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
only the program counter and SP are reset to zero. To
clear the WDT contents (including the WDT prescaler ),
3 methods are implemented; external reset (a low level
to RES), software instructions, or a HALT instruction.
The software instructions include CLR WDT and the
other set -CLR WDT1 and CLR WDT2. Of these two
types of instructions, only one can be active depending
on the mask option -²CLR WDT times selection op-
tion².Ifthe²CLR WDT²is selected (i.e. CLRWDT times
equal one), any execution of the CLR WDT instruction
will clear the WDT. In case ²CLR WDT1²and ²CLR
WDT2²are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip because
of time-out.
Power Down Operation -HALT
The HALT mode is initialized by a HALT instruction and
results in the following...
·The system oscillator will turn off but the WDT oscilla-
tor keeps running (If the WDT oscillator is selected).
Watchdog Timer -WDT
·The contents of the on-chip RAM and registers remain
unchanged
·The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).
·All I/O ports maintain their original status.
·The PDF flag is set and the TO flag is cleared.
·The HALT pin will output a high level signal to disable
the external ROM.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the CLR WDT instruction and it is set when a
HALT instruction is executed. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and stack pointer, the others remain
in their original status.
fO S C / 8
8 - b i t C o u n t e r
W D T P r e s c a l e r
7 - b i t C o u n t e r
8 - t o - 1 M U X
W D T T i m e - o u t
W S 0 ~ W S 2
M a s k
O p t i o n
S e l e c t
W D T
O S C
Watchdog Timer
HT36B4
Rev. 1.00 12 October 18, 2006
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the in-
terrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re-
sponse takes place.
Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will execute immediately after
a dummy period has finished. If an interrupt request flag
is set to ²1²before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are 3 ways in which a reset can occur:
·RES reset during normal operation
·RES reset during HALT
·WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set²that just resets the program counter and SP, leaving
the other circuits to maintain their state. Some registers
remain unchanged during any other reset conditions.
Most registers are reset to the ²initial condition²when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
TO PDF RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u²stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The functional units chip reset status are shown below.
Program Counter 000H
Interrupt Disable
Prescaler Clear
WDT Clear. After master reset,
WDT begins counting
Timer/Event Counter (0/1) Off
Input/output ports Input mode
Stack Pointer Points to the top of stack
tS S T
R E S
V D D
S S T T i m e - o u t
C h i p R e s e t
Reset Timing Chart
R E S
V
D D
Reset Circuit
W D T
H A L T
W D T
T i m e - o u t
R e s e t
R E S
C o l d
R e s e t
W a r m R e s e t
P o w e r - o n D e t e c t i n g
SST
1 0 - s t a g e
R i p p l e C o u n t e r
O S C I
Reset Configuration
HT36B4
Rev. 1.00 13 October 18, 2006
The registers status is summarized in the following table:
Register Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Program Counter 0000H 0000H 0000H 0000H 0000H
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC -00- 00-0 -00- 00-0 -00- 00-0 -00- 00-0 -uu- uu-u
TMR0H xx-x x--- xx-x x--- xx-x x--- xx-x x--- uu-u u---
TMR0L xx-x x--- xx-x x--- xx-x x--- xx-x x--- uu-u u---
TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu
TMR1H xx-x x--- xx-x x--- xx-x x--- xx-x x--- uu-u u---
TMR1L xx-x x--- xx-x x--- xx-x x--- xx-x x--- uu-u u---
TMR1C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PD ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu
PDC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu
PF ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu
DAH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
DAL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
DAC ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu
CHAN 00-- 0000 uu-- uuuu uu-- uuuu uu-- uuuu uu-- uuuu
FreqNH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
FreqNL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
AddrH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
AddrL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ReH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ReL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ENV x-xx xxxx u-uu uuuu u-uu uuuu u-uu uuuu u-uu uuuu
LVC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
RVC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note: ²*²stands for warm reset
²u²stands for unchanged
²x²stands for unknown
HT36B4
Rev. 1.00 14 October 18, 2006
Timer/Event Counter
Two timer/event counters are implemented in the
HT36B4. The Timer/Event Counter 0 and Timer/Event
Counter 1 contain 16-bit programmable count-up coun-
ters and the clock comes from the system clock divided
by 4.
There are three registers related to Timer/Event Coun-
ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH).
Writing TMR0L only writes the data into a low byte
buffer, and writing TMR0H will write the data and the
contents of the low byte buffer into the Timer/Event
Counter 0 Preload register (16-bit) simultaneously. The
Timer/Event Counter 0 Preload register is changed by
writing TMR0H operations and writing TMR0L will keep
the Timer/Event Counter 0 Preload register unchanged.
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid a false timing problem. Reading
TMR0L returns the contents of the low byte buffer. In
other words, the low byte of the Timer/Event Counter 0
cannot be read directly. It must read the TMR0H first to
make the low byte contents of the Timer/Event Counter
0 latched into the buffer.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same man-
ner as Timer/Event Counter 0.
The TMR0C is the Timer/Event Counter 0 control regis-
ter, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options with
Timer/Event Counter 0 and is defined by TMR1C.
The Timer/event Counter control registers define the op-
erating mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode. The
Event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The Timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR). The counting is based on the instruction clock.
In the Event count or Timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter Preload register and simulta-
neously generates the corresponding interrupt request
flag (T0F/T1F; bit 5/6 of INTC).
In pulse width measurement mode with the TON and TE
bits equal to one, once the TMR has received a transient
from low to high (or high to low; if the TE bit is 0) it will
start counting until the TMR returns to the original level
and resets the TON. The measured result will remain in
the even if the activated transient occurs again. In other
words, only one cycle measurements can be done. Until
setting the TON, the cycle measurement will function
again as long as it receives further transient pulse. Note
that, in this operating mode, the timer/event counter
starts counting not according to the logic level but ac-
cording to the transient edges. In the case of counter
overflows, the counter is reloaded from the timer/event
counter preload register and issues the interrupt request
just like the other two modes.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the
pulse width measurement mode, the TON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the TON can only
be reset by instruction. The overflow of the timer/event
counter is one of the wake-up sources. No matter what
the operation mode is, writinga0toET0I/ET1I can dis-
able the corresponding interrupt service.
In the case of timer/event counter OFF condition, writing
data to the Timer/event Counter Preload register will
also reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter will only be kept in the timer/event
counter preload register. The timer/event counter will
still operate until overflow occurs.
Bit No. Label Function
0~2 ¾Unused bit, read as ²0²
3TE
Define the TMR active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
4 TON Enable/disable timer counting
(0=disable; 1=enable)
5¾Unused bit, read as ²0²
6
7
TM0
TM1
Defines the operating mode
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C(0EH) / TMR1C(11H) Register
HT36B4
Rev. 1.00 15 October 18, 2006
When the timer/event counter (reading TMR0H/
TMR1H) is read, the clock will be blocked to avoid er-
rors. As this may results in a counting error, this must be
taken into consideration by the programmer.
The two timer counters of HT36B4 are internal clock
mode only, so only Timer mode can be selected. There-
fore the (TM1, TM0) bits can only be set to (TM1,TM0) =
(1,0), and the other clock modes are invalid.
Input/Output Ports
There are 28 bidirectional input/output lines labeled
from PA to PD, which are mapped to the data memory of
[12H], [14H], [16H], [18H] respectively. All these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H, 16H or 18H). For output oper-
ation, all data is latched and remains unchanged until
the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt Trig-
ger input with or without pull-high resistor (mask option)
structures can be reconfigured dynamically under soft-
ware control. To function as an input, the corresponding
latch of the control register must write a ²1². The
pull-high resistance will exhibit automatically if the
pull-high option is selected. The input source also de-
pends on the control register. If the control register bit is
²1², input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write²instruc-
tion. For output function, CMOS is the only configura-
tion. These control registers are mapped to locations
13H, 15H, 17H and 19H).
After a chip reset, these input/output lines remain at high
levels or floating (mask option). Each bit of these in-
put/output latches can be set or cleared by the SET [m].i
or CLR [m].i (m=12H, 14H, 16H or 18H) instruction.
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability to wake-up the
device.
fO S C / 8
T M 1
T M 0
T E
T M 1
T M 0
T O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
T i m e r / e v e n t C o u n t e r 0
P r e l o a d R e g i s t e r
T i m e r / e v e n t
C o u n t e r 0
D a t a B u s
R e l o a d
O v e r f l o w
T o I n t e r r u p t
L o w B y t e
B u f f e r
G N D
Timer/Event Counter 0/1
Q
D
C K S
Q
Q
D
C K S
Q
MUX
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e I / O
R e a d I / O
S y s t e m W a k e - U p ( P A o n l y )
W e a k
P u l l - u p
P A 0 ~ P A 7
P B 0 ~ P B 7
M a s k O p t i o n
M a s k O p t i o n
P C 0 ~ P C 7
P D 0 ~ P D 3
VD D
VD D
Input/Output Ports
HT36B4
Rev. 1.00 16 October 18, 2006
16 Channel Wavetable Synthesizer
Wavetable Function Memory Mapping
Special Register for Wavetable Synthesizer
RAM B7 B6 B5 B4 B3 B2 B1 B0
20H VM FR ¾¾
CH3 CH2 CH1 CH0
21H BL3 BL2 BL1 BL0 FR11 FR10 FR9 FR8
22H FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0
23H ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8
24H ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
25H WBS RE14 RE13 RE12 RE11 RE10 RE9 RE8
26H RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
27H A_R ¾VL9 VL8 ENV1 ENV0 VR9 VR8
29H VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
2AH VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0
Wavetable Function Register Table
Register Name Register Function B7 B6 B5 B4 B3 B2 B1 B0
20H Channel Number Selection CH3 CH2 CH1 CH0
20H Change Parameter Selection VM FR
21H Block Number Selection BL3 BL2 BL1 BL0
21H
Frequency Number Selection
FR11 FR10 FR9 FR8
22H FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0
23H
Start Address Selection
ST11 ST10 ST9 ST8
24H ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
25H Waveform Format Selection WBS
25H
Repeat Number Selection
RE14 RE13 RE12 RE11 RE10 RE9 RE8
26H RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
27H Envelope Type Selection ENV1 ENV0
27H Attach and Release Selection A_R
27H
Left Volume Controller
VL9 VL8
29H VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
27H
Right Volume Controller
VR9 VR8
2AH VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0
HT36B4
Rev. 1.00 17 October 18, 2006
·CH3~0 channel number selection
The HT36B4 has a built-in 16 output channels and
CH3~0 is used to define which channel is selected.
When this register is written to, the wavetable synthe-
sizer will automatically output the dedicated PCM
code. So this register is also used as a start playing
key and it has to be written to after all the other
wavetable function registers are already defined.
·Change parameter selection
These two bits, VM and FR, are used to define which
register will be updated on this selected channel.
There are two modes that can be selected to reduce
the process of setting the register. Please refer to the
statements of the following table:
VM FR Function
0 0 Update all the parameter
0 1 Only update the frequency number
1 0 Only update the volume
·Output frequency definition
The data on BL3~0 and FR11~0 are used to define
the output speed of the PCM file, i.e. it can be used to
generate the tone scale. When the FR11~0 is 800H
and BL3~0 is 6H, each sample data of the PCM code
will be sent out sequentially.
When the fOSC is 12.8MHz, the formula of a tone fre-
quency is:
fOUT=f
RECORD ´50kHz
SR ´FR11~ 0
2(17 BL3~0)-
where fOUT is the output signal frequency, fRECORD and
SR is the frequency and sampling rate on the sample
code, respectively.
So if a voice code of C3 has been recorded which has
the fRECORD of 261Hz and the SR of 11025Hz, the tone
frequency (fOUT) of G3: fOUT=196Hz.
Can be obtained by using the fomula:
196Hz= 261Hz ´50kHz
11025Hz ´FR11~ 0
2(17 BL3~0)-
A pair of the values FR11~0 and BL3~0 can be deter-
mined when the fOSC is 12.8MHz.
·Start address definition
The HT36B4 provides two address types for extended
use, one is the program ROM address which is pro-
gram counter corresponding with PF value, the other
is the start address of the PCM code.
The ST11~0 is used to define the start address of
each PCM code and reads the waveform data from
this location. The HT36B4 provides 16 input data lines
from WA16~0, the ST11~0 is used to locate the major
16 bits i.e. WA16~5 and the undefined data from
WA4~0 is always set as 00000b. In other words, the
WA16~0=ST11~0´25´8 bit. So each PCM code has to
be located at a multiple of 32. Otherwise, the PCM
code will not be read out correctly because it has a
wrong start code.
·Waveform format definition
The HT36B4 accepts two waveform formats to ensure
a more economical data space. WBS is used to define
the sample format of each PCM code.
¨WBS=0 means the sample format is 8-bit
¨WBS=1 means the sample format is 12-bit
The 12-bit sample format allocates location to each
sample data. Please refer to the waveform format
statement as shown below.
·Repeat number definition
The repeat number is used to define the address
which is the repeat point of the sample. When the re-
peat number is defined, it will be output from the start
code to the end code once and always output the
range between the repeat address to the end code
(80H) until the volume become close.
The RE14~0 is used to calculate the repeat address
of the PCM code. The process for setting the RE14~0
is to write the 2¢s complement of the repeat length to
RE14~0, with the highest carry ignored. The HT36B4
will get the repeat address by adding the RE14~0 to
the address of the end code, then jump to the address
to repeat this range.
·Left and Right volume control
The HT36B4 provides the left and right volume control
independently. The left and right volume are con-
trolled by VL9~0 and VR9~0 respectively. The chip
provides 1024 levels of controllable volume, the 000H
is the maximum and 3FFH is the minimum output vol-
ume.
·Envelope type definition
The HT36B4 provides a function to easily program the
envelope by setting the data of ENV1~0 and A_R. It
forms a vibrato effect by a change of the volume to at-
tach and release alternately.
The A_R signal is used to define the volume change in
attach mode or release mode and ENV1~0 is used to
define which volume control bit will be changeable.
On the attach mode, the control bits will be sequen-
tially signaled down to 0. On the release mode, the
control bits will be sequentially signaled up to 1. The
relationship is shown in the following table.
·The PCM code definition
The HT36B4 can only solve the voice format of the
signed 8-bit raw PCM. And the MCU will take the
voice code 80H as the end code.
So each PCM code section must be ended with the
end code 80H.
1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B
1 H 1 M 1 L 2 L 2 H 2 M 3 H 3 M
A s a m p l i n g d a t a c o d e ; B m e a n s o n e d a t a b y t e .
8 - B i t
1 2 - B i t 3 L
N o t e : " 1 H " H i g h N i b b l e
" 1 M " M i d d l e N i b b l e
" 1 L " L o w N i b b l e
A s a m p l i n g d a t a c o d e
Waveform Format
HT36B4
Rev. 1.00 18 October 18, 2006
D/A Converter Interface
HT36B4 provides the IIS serial data format to support the
multiple D/A converters, one bit clock output and a word
clock signal for left/right stereo serial data transmission.
Clock Signal
The bit clock output signals DCK are used to synchronize
the IIS serial data.
The word clock signal LOAD divides the serial data into
left channel and right channel data for two-way audio out-
put.
·LOAD
The word clock signal LOAD is used for IIS serial data.
The stereo serial data consists of 16-channel sound
generator.
·DOUT
On IIS format, a ²H²state on LOAD is used for the right
channel, and a ²L²state is used for the left channel.
·DCK
DCK bit clock is the clock source for the signal.
Stereo Serial Data Format
The audio output data is in serial mode with 16 bit digi-
tal signal and LSB first output. There is a high sam-
pling rate of 50kHz when the system clock is 12.8MHz
and with two channel outputs for Right/Left channel.
HT36B4 provides only one serial data format as IIS
mode. The user could directly connect a D/A converter
which can accept the IIS serial data format, like
HT82V731.
Mask Option
No. Mask Option Function
1 WDT source On-chip RC/Instruction clock/
disable WDT
2CLRWDT
times
One time, two times
(CLR WDT1/WDT2)
3 Wake-up PA only
4 Pull-High PA, PB, PC, PD input
5 OSC mode Crystal or Resistor type
6 I/O DAC pin PD1~3 DAC pin selection
D O U T
DCK
L O A D L S B M S B
S a m p l e O u t
R i g h t L e f t
D/A Converter Timing
A_R ENV1 ENV0 Volume Control Bit Control Bit Final Value Mode
0 0 0 VL2~0, VR2~0 111b
Release mode0 0 1 VL1~0, VR1~0 11b
0 1 0 VL0, VR0 1b
x 1 1 No Bit unchanged No change mode
1 0 0 VL2~0, VR2~0 000b
Attach mode1 0 1 VL1~0, VR1~0 00b
1 1 0 VL0, VR0 0b
Envelope Type Definition
Application Circuit
HT36B4
Rev. 1.00 19 October 18, 2006
R E S
H T 3 6 B 4
P C 0 ~ P C 7
P A 0 ~ P A 7
P B 0 ~ P B 7
P D 0 ~ P D 3
RCH
VD D
O S C I
O S C O
V
D D
4 7
m
F
0 . 1
m
F
V r e f
1 0
m
F
I N V D D
H T 8 2 V 7 3 3
V S S
C E
O U T N
O U T P
S P K
8
W
20k
W
L C H
R E S
H T 3 6 B 4
P C 0 ~ P C 7
P A 0 ~ P A 7
P B 0 ~ P B 7
P D 0
O P
VD D
O S C I
O S C O
1 2 M H z
D A C
P D 1 / D O U T
P D 3 / D C K
P D 2 / L O A D
H T 8 2 V 7 3 1
100k
W
0 . 1
m
F
1
2
3
5
7
4
8
100k
W
0 . 1
m
F
V
D D
V D D V D D A
1 0
W
4 7
m
F0 . 1
m
F
V S S A
V S S
V
D D
V D D V D D A
1 0
W
4 7
m
F0 . 1
m
F
V S S A
V S S
Instruction Set Summary
Mnemonic Description Instruction
Cycle
Flag
Affected
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
HT36B4
Rev. 1.00 20 October 18, 2006
Mnemonic Description Instruction
Cycle
Flag
Affected
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Table Read
TABRDC [m]
TABRDL [m]
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3):(1) and (2)
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
HT36B4
Rev. 1.00 21 October 18, 2006
Instruction Definition
ADC A,[m] Add data memory and carry to the accumulator
Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation ACC ¬ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
ADCM A,[m] Add the accumulator and carry to data memory
Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation [m] ¬ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
ADD A,[m] Add data memory to the accumulator
Description The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation ACC ¬ACC+[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
ADD A,x Add immediate data to the accumulator
Description The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation ACC ¬ACC+x
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
ADDM A,[m] Add the accumulator to the data memory
Description The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation [m] ¬ACC+[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
HT36B4
Rev. 1.00 22 October 18, 2006
AND A,[m] Logical AND accumulator with data memory
Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation ACC ¬ACC ²AND²[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
AND A,x Logical AND immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation ACC ¬ACC ²AND²x
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
ANDM A,[m] Logical AND data memory with the accumulator
Description Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation [m] ¬ACC ²AND²[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
CALL addr Subroutine call
Description The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation Stack ¬Program Counter+1
Program Counter ¬addr
Affected flag(s)
TO PDF OV Z AC C
¾ ¾¾¾¾¾
CLR [m] Clear data memory
Description The contents of the specified data memory are cleared to 0.
Operation [m] ¬00H
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 23 October 18, 2006
CLR [m].i Clear bit of data memory
Description The bit i of the specified data memory is cleared to 0.
Operation [m].i ¬0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
CLR WDT Clear Watchdog Timer
Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation WDT ¬00H
PDF and TO ¬0
Affected flag(s)
TO PDF OV Z AC C
00
¾¾¾¾
CLR WDT1 Preclear Watchdog Timer
Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation WDT ¬00H*
PDF and TO ¬0*
Affected flag(s)
TO PDF OV Z AC C
0* 0* ¾¾¾¾
CLR WDT2 Preclear Watchdog Timer
Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation WDT ¬00H*
PDF and TO ¬0*
Affected flag(s)
TO PDF OV Z AC C
0* 0* ¾¾¾¾
CPL [m] Complement data memory
Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation [m] ¬[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
HT36B4
Rev. 1.00 24 October 18, 2006
CPLA [m] Complement data memory and place result in the accumulator
Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation ACC ¬[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
DAA [m] Decimal-Adjust accumulator for addition
Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬(ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬(ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾ Ö
DEC [m] Decrement data memory
Description Data in the specified data memory is decremented by 1.
Operation [m] ¬[m]-1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
DECA [m] Decrement data memory and place result in the accumulator
Description Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬[m]-1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
HT36B4
Rev. 1.00 25 October 18, 2006
HALT Enter power down mode
Description This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation Program Counter ¬Program Counter+1
PDF ¬1
TO ¬0
Affected flag(s)
TO PDF OV Z AC C
01
¾¾¾¾
INC [m] Increment data memory
Description Data in the specified data memory is incremented by 1
Operation [m] ¬[m]+1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
INCA [m] Increment data memory and place result in the accumulator
Description Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬[m]+1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
JMP addr Directly jump
Description The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation Program Counter ¬addr
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
MOV A,[m] Move data memory to the accumulator
Description The contents of the specified data memory are copied to the accumulator.
Operation ACC ¬[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 26 October 18, 2006
MOV A,x Move immediate data to the accumulator
Description The 8-bit data specified by the code is loaded into the accumulator.
Operation ACC ¬x
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
MOV [m],A Move the accumulator to data memory
Description The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation [m] ¬ACC
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation Program Counter ¬Program Counter+1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
OR A,[m] Logical OR accumulator with data memory
Description Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation ACC ¬ACC ²OR²[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
OR A,x Logical OR immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation ACC ¬ACC ²OR²x
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
ORM A,[m] Logical OR data memory with the accumulator
Description Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation [m] ¬ACC ²OR²[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
HT36B4
Rev. 1.00 27 October 18, 2006
RET Return from subroutine
Description The program counter is restored from the stack. This is a 2-cycle instruction.
Operation Program Counter ¬Stack
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
RET A,x Return and place immediate data in the accumulator
Description The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation Program Counter ¬Stack
ACC ¬x
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
RETI Return from interrupt
Description The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation Program Counter ¬Stack
EMI ¬1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
RL [m] Rotate data memory left
Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation [m].(i+1) ¬[m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬[m].7
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
RLA [m] Rotate data memory left and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬[m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬[m].7
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 28 October 18, 2006
RLC [m] Rotate data memory left through carry
Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation [m].(i+1) ¬[m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬C
C¬[m].7
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾ Ö
RLCA [m] Rotate left through carry and place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬[m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬C
C¬[m].7
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾ Ö
RR [m] Rotate data memory right
Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation [m].i ¬[m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬[m].0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
RRA [m] Rotate right and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i) ¬[m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬[m].0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
RRC [m] Rotate data memory right through carry
Description The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation [m].i ¬[m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬C
C¬[m].0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾ Ö
HT36B4
Rev. 1.00 29 October 18, 2006
RRCA [m] Rotate right through carry and place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.i ¬[m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬C
C¬[m].0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾ Ö
SBC A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation ACC ¬ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation [m] ¬ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
SDZ [m] Skip if decrement data memory is 0
Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, [m] ¬([m]-1)
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SDZA [m] Decrement data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, ACC ¬([m]-1)
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 30 October 18, 2006
SET [m] Set data memory
Description Each bit of the specified data memory is set to 1.
Operation [m] ¬FFH
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SET [m]. i Set bit of data memory
Description Bit i of the specified data memory is set to 1.
Operation [m].i ¬1
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SIZ [m] Skip if increment data memory is 0
Description The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, [m] ¬([m]+1)
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SIZA [m] Increment data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ¬([m]+1)
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SNZ [m].i Skip if bit i of the data memory is not 0
Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation Skip if [m].i¹0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 31 October 18, 2006
SUB A,[m] Subtract data memory from the accumulator
Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation ACC ¬ACC+[m]+1
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
SUBM A,[m] Subtract data memory from the accumulator
Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation [m] ¬ACC+[m]+1
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
SUB A,x Subtract immediate data from the accumulator
Description The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation ACC ¬ACC+x+1
Affected flag(s)
TO PDF OV Z AC C
¾¾ÖÖÖÖ
SWAP [m] Swap nibbles within the data memory
Description The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation [m].3~[m].0 «[m].7~[m].4
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SWAPA [m] Swap data memory and place result in the accumulator
Description The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation ACC.3~ACC.0 ¬[m].7~[m].4
ACC.7~ACC.4 ¬[m].3~[m].0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 32 October 18, 2006
SZ [m] Skip if data memory is 0
Description If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SZA [m] Move data memory to ACC, skip if 0
Description The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
SZ [m].i Skip if bit i of the data memory is 0
Description If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m].i=0
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
TABRDC [m] Move the ROM code (current page) to TBLH and data memory
Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ROM code (low byte)
TBLH ¬ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
TABRDL [m] Move the ROM code (last page) to TBLH and data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ROM code (low byte)
TBLH ¬ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C
¾¾¾¾¾¾
HT36B4
Rev. 1.00 33 October 18, 2006
XOR A,[m] Logical XOR accumulator with data memory
Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation ACC ¬ACC ²XOR²[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
XORM A,[m] Logical XOR data memory with the accumulator
Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation [m] ¬ACC ²XOR²[m]
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
XOR A,x Logical XOR immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation ACC ¬ACC ²XOR²x
Affected flag(s)
TO PDF OV Z AC C
¾¾¾Ö¾¾
HT36B4
Rev. 1.00 34 October 18, 2006
Package Information
48-pin SSOP (300mil) Outline Dimensions
Symbol Dimensions in mil
Min. Nom. Max.
A 395 ¾420
B 291 ¾299
C8
¾12
C¢613 ¾637
D85
¾99
E¾25 ¾
F4
¾10
G25¾35
H4
¾12
a0°¾8°
HT36B4
Rev. 1.00 35 October 18, 2006
4 8
1
2 5
2 4
AB
C
D
F
C ' G
H
a
E
Product Tape and Reel Specifications
Reel Dimensions
SSOP 48W
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 100±0.1
C Spindle Hole Diameter 13.0+0.5
-0.2
D Key Slit Width 2.0±0.5
T1 Space Between Flange 32.2+0.3
-0.2
T2 Reel Thickness 38.2±0.2
HT36B4
Rev. 1.00 36 October 18, 2006
AC
B
T 1
T 2 D
Carrier Tape Dimensions
SSOP 48W
Symbol Description Dimensions in mm
W Carrier Tape Width 32.0±0.3
P Cavity Pitch 16.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 14.2±0.1
D Perforation Diameter 2.0 Min.
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 12.0±0.1
B0 Cavity Width 16.20±0.1
K1 Cavity Depth 2.4±0.1
K2 Cavity Depth 3.2±0.1
t Carrier Tape Thickness 0.35±0.05
C Cover Tape Width 25.5
HT36B4
Rev. 1.00 37 October 18, 2006
PD 1
P 1P 0
D
E
F
t
K 2
B 0
A 0
W
K 1
C
HT36B4
Rev. 1.00 38 October 18, 2006
Copyright Ó2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
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4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
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7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
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Fax: 021-6485-0313
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5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
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Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
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Tel: 028-6653-6590
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Fax: 510-252-9885
http://www.holmate.com
