EPCS1SI8 - INTEL - Datasheet.Directory

April 2014 Altera Corporation

C51014-5.1 Datasheet

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Serial Configuration (EPCS) Devices

Datasheet

This datasheet describes serial configuration (EPCS) devices.

Supported Devices

Ta ble 1 lists the supported Altera EPCS devices.

Table 1. Altera EPCS Devices

Device Memory Size

(bits)

On-Chip

Decompression

Support

ISP Support Cascading

Support Reprogrammable

Recommended

Operating

Voltage (V)

EPCS1 1,048,576 No Yes No Yes 3.3

EPCS4 4,194,304 No Yes No Yes 3.3

EPCS16 16,777,216 No Yes No Yes 3.3

EPCS64 67,108,864 No Yes No Yes 3.3

EPCS128 134,217,728 No Yes No Yes 3.3

fFor more information about programming EPCS devices using the Altera

Programming Unit (APU) or Master Programming Unit (MPU), refer to the Altera

Programming Hardware Datasheet.

fThe EPCS device can be re-programmed in system with ByteBlaster II download

cable or an external microprocessor using SRunner. For more information, refer to

AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming.

Features

EPCS devices offer the following features:

■Supports active serial (AS) x1 configuration scheme

■Easy-to-use four-pin interface

■Low cost, low pin count, and non-volatile memory

■Low current during configuration and near-zero standby mode current

■2.7-V to 3.6-V operation

■EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated

circuit (SOIC) package

■EPCS64 and EPCS128 devices available in 16-pin SOIC package

Page 2 Functional Description

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

■Enables the Nios processor to access unused flash memory through AS memory

interface

■Reprogrammable memory with more than 100,000 erase or program cycles

■Write protection support for memory sectors using status register bits

■In-system programming (ISP) support with SRunner software driver

■ISP support with USB-Blaster, EthernetBlaster, or ByteBlaster II download cables

■Additional programming support with the APU and programming hardware

from BP Microsystems, System General, and other vendors

■By default, the memory array is erased and the bits are set to

Functional Description

To configure a system using an SRAM-based device, each time you power on the

device, you must load the configuration data. The EPCS device is a flash memory

device that can store configuration data that you use for FPGA configuration purpose

after power on. You can use the EPCS device on all FPGA that support AS x1

configuration scheme.

For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the

EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from

the EPCS64 device to the EPCS128 device.

With the new data decompression feature supported, you can determine using which

EPCS device to store the configuration data for configuring your FPGA.

Example 1 shows how you can calculate the compression ratio to determine which

EPCS device is suitable for the FPGA.

Example 1. Compression Ratio Calculation

EP4SGX530 = 189,000,000 bits

EPCS128 = 134,217,728 bits

Preliminary data indicates that compression typically reduces the

configuration bitstream size by 35% to 55%. Assume worst case that is 35%

decompression.

189,000,000 bits x 0.65 = 122,850,000 bits

The EPCS128 device is suitable.

fFor more information about the FPGA decompression feature, refer to the

configuration chapter in the appropriate device handbook.

Active Serial FPGA Configuration Page 3

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

Figure 1 shows the EPCS device block diagram.

Figure 1. EPCS Device Block Diagram

Control

Logic

I/O Shift

Memory

Array

Status RegisterAddress Counter

Decode Logic

Data Buffer

nCS

DCLK

DATA

ASDI

EPCS Device

Accessing Memory in EPCS Devices

You can access the unused memory locations of the EPCS device to store or retrieve

data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for

creating bus-based (especially microprocessor-based) systems in Altera devices.

SOPC Builder assembles library components such as processors and memories into

custom microprocessor systems.

SOPC Builder includes the EPCS device controller core, which is an interface core

designed specifically to work with the EPCS device. With this core, you can create a

system with a Nios embedded processor that allows software access to any memory

location within the EPCS device.

Active Serial FPGA Configuration

The following Altera FPGAs support the AS configuration scheme with EPCS devices:

■Arria series

■Cyclone series

■All device families in the Stratix series except the Stratix device family

There are four signals on the EPCS device that interface directly with the FPGA’s

control signals. The EPCS device signals are

DATA

DCLK

ASDI

, and

nCS

interface with

the

DATA0

DCLK

ASDO

, and

nCSO

control signals on the FPGA, respectively.

1For more information about the EPCS device pin description, refer to Table 23 on

page 36.

Page 4 Active Serial FPGA Configuration

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

Figure 2 shows the configuration of an FPGA device in the AS configuration scheme

with an EPCS device using a download cable.

Figure 2. Altera FPGA Configuration in AS Mode Using a Download Cable (1), (4)

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[]

nCEO

CONF_DONE

ASDO

VCC (1) VCC (1) VCC (1)

VCC (1)

10 kΩ10 kΩ10 kΩ

10 kΩ

(3)

Altera FPGA

EPCS Device (2)

Pin 1

N.C.

Notes to Figure 2:

(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

Active Serial FPGA Configuration Page 5

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

Figure 3 shows the configuration of an FPGA device in the AS configuration scheme

with an EPCS device using the APU or a third-party programmer.

Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer (1), (4)

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[]

nCEO

CONF_DONE

ASDO

(1) V

(1)

10 kΩ10 kΩ10 kΩ

(3)

Altera FPGA

EPCS Device (2)

N.C.

Notes to Figure 3:

(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

In an AS configuration, the FPGA acts as the configuration master in the

configuration flow and provides the clock to the EPCS device. The FPGA enables the

EPCS device by pulling the

nCS

signal low using the

nCSO

signal as shown in Figure 2

and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device

using the

ASDO

signal. The EPCS device responds to the instructions by sending the

configuration data to the FPGA’s

DATA0

pin on the falling edge of

DCLK

. The data is

latched into the FPGA on the next

DCLK

signal’s falling edge.

1Before the FPGA enters configuration mode, ensure that VCC of the EPCS device is

ready. If VCC is not ready, you must hold

nCONFIG

low until all power rails of EPCS

device are ready.

The FPGA controls the

nSTATUS

and

CONF_DONE

pins during configuration in the AS

mode. If the

CONF_DONE

signal does not go high at the end of configuration, or if the

signal goes high too early, the FPGA pulses its

nSTATUS

pin low to start a

reconfiguration. If the configuration is successful, the FPGA releases the

CONF_DONE

pin, allowing the external 10-k resistor to pull the

CONF_DONE

signal high. The FPGA

initialization begins after the

CONF_DONE

pin goes high. After the initialization, the

FPGA enters user mode.

fFor more information about configuring the FPGAs in AS configuration mode or

other configuration modes, refer to the configuration chapter in the appropriate

device handbook.

Page 6 Active Serial FPGA Configuration

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

You can configure multiple devices with a single EPCS device. However, you cannot

cascade EPCS devices. To ensure that the programming file size of the cascaded

FPGAs does not exceed the capacity of an EPCS device, refer to Table 1 on page 1.

Figure 4 shows the AS configuration scheme with multiple FPGAs in the chain. The

first FPGA is the configuration master and its

MSEL[]

pins are set to AS mode. The

following FPGAs are configuration slave devices and their

MSEL[]

pins are set to PS

mode.

Figure 4. Multiple Devices in AS Mode (1), (5)

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[ ]

nCEO

CONF_DONE

ASDO

VCC (1)

10 kΩ

VCC (1)

10 kΩ

VCC (1)

10 kΩ

(3)

Altera FPGA (Master)

DATA0

DCLK

nCE

nCONFIG

nSTATUS

MSEL[ ]

nCEO

CONF_DONE

(4)

Altera FPGA (Slave)

EPCS Device (2)

N.C.

Notes to Figure 4:

(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) Connect the

MSEL[]

input pins to select the PS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(5) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

EPCS Device Memory Access Page 7

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

EPCS Device Memory Access

This section describes the memory array organization and operation codes of the

EPCS device. For the timing specifications, refer to “Timing Information” on page 29.

Memory Array Organization

Ta ble 2 lists the memory array organization details in EPCS128, EPCS64, EPCS16,

EPCS4, and EPCS1 devices.

Table 2. Memory Array Organization in EPCS Devices

Details EPCS128 EPCS64 EPCS16 EPCS4 EPCS1

Bytes 16,777,216 bytes

(128 Mb)

8,388,608 bytes

(64 Mb)

2,097,152 bytes

(16 Mb)

524,288 bytes

(4 Mb)

131,072 bytes

(1 Mb)

Number of sectors 64 128 32 8 4

Bytes per sector 262,144 bytes

(2 Mb)

65,536 bytes

(512 Kb)

65,536 bytes

(512 Kb)

65,536 bytes

(512 Kb)

32,768 bytes

(256 Kb)

Pages per sector 1,024 256 256 256 128

Total number of

pages65,536 32,768 8,192 2,048 512

Bytes per page 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes

Ta ble 3 through Table 7 on page 12 list the address range for each sector in EPCS1,

EPCS4, EPCS16, EPCS64, and EPCS128 devices.

Table 3. Address Range for Sectors in EPCS1 Devices

Sector

Address Range (byte Addresses in HEX)

Start End

H’18000 H’1FFFF

H’10000 H’17FFF

H’08000 H’0FFFF

H’00000 H’07FFF

Table 4. Address Range for Sectors in EPCS4 Devices

Sector

Address Range (Byte Addresses in HEX)

Start End

H'70000 H'7FFFF

H'60000 H'6FFFF

H'50000 H'5FFFF

H'40000 H'4FFFF

H'30000 H'3FFFF

H'20000 H'2FFFF

H'10000 H'1FFFF

H'00000 H'0FFFF

Table 5. Address Range for Sectors in EPCS16 Devices

Sector

Address Range (Byte Addresses in HEX)

Start End

H'1F0000 H'1FFFFF

H'1E0000 H'1EFFFF

H'1D0000 H'1DFFFF

H'1C0000 H'1CFFFF

H'1B0000 H'1BFFFF

H'1A0000 H'1AFFFF

H'190000 H'19FFFF

H'180000 H'18FFFF

H'170000 H'17FFFF

H'160000 H'16FFFF

H'150000 H'15FFFF

H'140000 H'14FFFF

H'130000 H'13FFFF

H'120000 H'12FFFF

H'110000 H'11FFFF

H'100000 H'10FFFF

H'0F0000 H'0FFFFF

H'0E0000 H'0EFFFF

H'0D0000 H'0DFFFF

H'0C0000 H'0CFFFF

H'0B0000 H'0BFFFF

H'0A0000 H'0AFFFF

H'090000 H'09FFFF

H'080000 H'08FFFF

H'070000 H'07FFFF

H'060000 H'06FFFF

H'050000 H'05FFFF

H'040000 H'04FFFF

H'030000 H'03FFFF

H'020000 H'02FFFF

H'010000 H'01FFFF

H'000000 H'00FFFF

Page 8 EPCS Device Memory Access

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

EPCS Device Memory Access Page 9

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

Table 6. Address Range for Sectors in EPCS64 Devices (Part 1 of 4)

Sector

Address Range (Byte Addresses in HEX)

Start End

127

H'7F0000 H'7FFFFF

126

H'7E0000 H'7EFFFF

125

H'7D0000 H'7DFFFF

124

H'7C0000 H'7CFFFF

123

H'7B0000 H'7BFFFF

122

H'7A0000 H'7AFFFF

121

H'790000 H'79FFFF

120

H'780000 H'78FFFF

119

H'770000 H'77FFFF

118

H'760000 H'76FFFF

117

H'750000 H'75FFFF

116

H'740000 H'74FFFF

115

H'730000 H'73FFFF

114

H'720000 H'72FFFF

113

H'710000 H'71FFFF

112

H'700000 H'70FFFF

111

H'6F0000 H'6FFFFF

110

H'6E0000 H'6EFFFF

109

H'6D0000 H'6DFFFF

108

H'6C0000 H'6CFFFF

107

H'6B0000 H'6BFFFF

106

H'6A0000 H'6AFFFF

105

H'690000 H'69FFFF

104

H'680000 H'68FFFF

103

H'670000 H'67FFFF

102

H'660000 H'66FFFF

101

H'650000 H'65FFFF

100

H'640000 H'64FFFF

H'630000 H'63FFFF

H'620000 H'62FFFF

H'610000 H'61FFFF

H'600000 H'60FFFF

H'5F0000 H'5FFFFF

H'5E0000 H'5EFFFF

H'5D0000 H'5DFFFF

H'5C0000 H'5CFFFF

H'5B0000 H'5BFFFF

H'5A0000 H'5AFFFF

Page 10 EPCS Device Memory Access

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

H'590000 H'59FFFF

H'580000 H'58FFFF

H'570000 H'57FFFF

H'560000 H'56FFFF

H'550000 H'55FFFF

H'540000 H'54FFFF

H'530000 H'53FFFF

H'520000 H'52FFFF

H'510000 H'51FFFF

H'500000 H'50FFFF

H'4F0000 H'4FFFFF

H'4E0000 H'4EFFFF

H'4D0000 H'4DFFFF

H'4C0000 H'4CFFFF

H'4B0000 H'4BFFFF

H'4A0000 H'4AFFFF

H'490000 H'49FFFF

H'480000 H'48FFFF

H'470000 H'47FFFF

H'460000 H'46FFFF

H'450000 H'45FFFF

H'440000 H'44FFFF

H'430000 H'43FFFF

H'420000 H'42FFFF

H'410000 H'41FFFF

H'400000 H'40FFFF

H'3F0000 H'3FFFFF

H'3E0000 H'3EFFFF

H'3D0000 H'3DFFFF

H'3C0000 H'3CFFFF

H'3B0000 H'3BFFFF

H'3A0000 H'3AFFFF

H'390000 H'39FFFF

H'380000 H'38FFFF

H'370000 H'37FFFF

H'360000 H'36FFFF

H'350000 H'35FFFF

H'340000 H'34FFFF

Table 6. Address Range for Sectors in EPCS64 Devices (Part 2 of 4)

Sector

Address Range (Byte Addresses in HEX)

Start End

EPCS Device Memory Access Page 11

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

H'330000 H'33FFFF

H'320000 H'32FFFF

H'310000 H'31FFFF

H'300000 H'30FFFF

H'2F0000 H'2FFFFF

H'2E0000 H'2EFFFF

H'2D0000 H'2DFFFF

H'2C0000 H'2CFFFF

H'2B0000 H'2BFFFF

H'2A0000 H'2AFFFF

H'290000 H'29FFFF

H'280000 H'28FFFF

H'270000 H'27FFFF

H'260000 H'26FFFF

H'250000 H'25FFFF

H'240000 H'24FFFF

H'230000 H'23FFFF

H'220000 H'22FFFF

H'210000 H'21FFFF

H'200000 H'20FFFF

H'1F0000 H'1FFFFF

H'1E0000 H'1EFFFF

H'1D0000 H'1DFFFF

H'1C0000 H'1CFFFF

H'1B0000 H'1BFFFF

H'1A0000 H'1AFFFF

H'190000 H'19FFFF

H'180000 H'18FFFF

H'170000 H'17FFFF

H'160000 H'16FFFF

H'150000 H'15FFFF

H'140000 H'14FFFF

H'130000 H'13FFFF

H'120000 H'12FFFF

H'110000 H'11FFFF

H'100000 H'10FFFF

H'0F0000 H'0FFFFF

H'0E0000 H'0EFFFF

Table 6. Address Range for Sectors in EPCS64 Devices (Part 3 of 4)

Sector

Address Range (Byte Addresses in HEX)

Start End

Page 12 EPCS Device Memory Access

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

H'0D0000 H'0DFFFF

H'0C0000 H'0CFFFF

H'0B0000 H'0BFFFF

H'0A0000 H'0AFFFF

H'090000 H'09FFFF

H'080000 H'08FFFF

H'070000 H'07FFFF

H'060000 H'06FFFF

H'050000 H'05FFFF

H'040000 H'04FFFF

H'030000 H'03FFFF

H'020000 H'02FFFF

H'010000 H'01FFFF

H'000000 H'00FFFF

Table 7. Address Range for Sectors in EPCS128 Devices (Part 1 of 3)

Sector

Address Range (Byte Addresses in HEX)

Start End

H'FC0000 H'FFFFFF

H'F80000 H'FBFFFF

H'F40000 H'F7FFFF

H'F00000 H'F3FFFF

H'EC0000 H'EFFFFF

H'E80000 H'EBFFFF

H'E40000 H'E7FFFF

H'E00000 H'E3FFFF

H'DC0000 H'DFFFFF

H'D80000 H'DBFFFF

H'D40000 H'D7FFFF

H'D00000 H'D3FFFF

H'CC0000 H'CFFFFF

H'C80000 H'CBFFFF

H'C40000 H'C7FFFF

H'C00000 H'C3FFFF

H'BC0000 H'BFFFFF

H'B80000 H'BBFFFF

H'B40000 H'B7FFFF

H'B00000 H'B3FFFF

Table 6. Address Range for Sectors in EPCS64 Devices (Part 4 of 4)

Sector

Address Range (Byte Addresses in HEX)

Start End

EPCS Device Memory Access Page 13

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

H'AC0000 H'AFFFFF

H'A80000 H'ABFFFF

H'A40000 H'A7FFFF

H'A00000 H'A3FFFF

H'9C0000 H'9FFFFF

H'980000 H'9BFFFF

H'940000 H'97FFFF

H'900000 H'93FFFF

H'8C0000 H'8FFFFF

H'880000 H'8BFFFF

H'840000 H'87FFFF

H'800000 H'83FFFF

H'7C0000 H'7FFFFF

H'780000 H'7BFFFF

H'740000 H'77FFFF

H'700000 H'73FFFF

H'6C0000 H'6FFFFF

H'680000 H'6BFFFF

H'640000 H'67FFFF

H'600000 H'63FFFF

H'5C0000 H'5FFFFF

H'580000 H'5BFFFF

H'540000 H'57FFFF

H'500000 H'53FFFF

H'4C0000 H'4FFFFF

H'480000 H'4BFFFF

H'440000 H'47FFFF

H'400000 H'43FFFF

H'3C0000 H'3FFFFF

H'380000 H'3BFFFF

H'340000 H'37FFFF

H'300000 H'33FFFF

H'2C0000 H'2FFFFF

H'280000 H'2BFFFF

H'240000 H'27FFFF

H'200000 H'23FFFF

H'1C0000 H'1FFFFF

H'180000 H'1BFFFF

Table 7. Address Range for Sectors in EPCS128 Devices (Part 2 of 3)

Sector

Address Range (Byte Addresses in HEX)

Start End

Page 14 EPCS Device Memory Access

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

Operation Codes

This section describes the operations that you can use to access the memory in EPCS

devices. Use the

DATA

DCLK

ASDI

, and

nCS

signals to access the memory in EPCS

devices. When performing the operation, addresses and data are shifted in and out of

the device serially, with MSB first.

The device samples the AS data input on the first rising edge of the

DCLK

after the

active low chip select (

nCS

) input signal is driven low. Shift the operation code, with

MSB first, into the EPCS device serially through the AS data input (

ASDI

) pin. Each

operation code bit is latched into the EPCS device on the rising edge of the

DCLK

Different operations require a different sequence of inputs. While executing an

operation, you must shift in the desired operation code, followed by the address bytes

or data bytes, both address and data bytes, or none of them. The device must drive

nCS

pin high after the last bit of the operation sequence is shifted in. Ta bl e 8 lists the

operation sequence for every operation supported by the EPCS devices.

For read operations, the data read is shifted out on the

DATA

pin. You can drive the

nCS

pin high after any bit of the data-out sequence is shifted out.

For write and erase operations, drive the

nCS

pin high at a byte boundary that is in a

multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.

All attempts to access the memory contents while a write or erase cycle is in progress

are rejected, and the write or erase cycle will continue unaffected.

H'140000 H'17FFFF

H'100000 H'13FFFF

H'0C0000 H'0FFFFF

H'080000 H'0BFFFF

H'040000 H'07FFFF

H'000000 H'03FFFF

Table 7. Address Range for Sectors in EPCS128 Devices (Part 3 of 3)

Sector

Address Range (Byte Addresses in HEX)

Start End

Table 8. EPCS Devices Operation Codes

Operation Operation Code (1) Address Bytes Dummy Bytes Data Bytes DCLK fMAX

(MHz)

Write enable

0000 0110

0 0 0 25

Write disable

0000 0100

0 0 0 25

Read status

0000 0101

0 0 1 to infinite (2) 32

Read bytes

0000 0011

3 0 1 to infinite (2) 20

Read silicon ID (4)

1010 1011

0 3 1 to infinite (2) 32

Fast read

0000 1011

3 1 1 to infinite (2) 40

Write status

0000 0001

0 0 1 25

Write bytes

0000 0010

3 0 1 to 256 (3) 25

Erase bulk

1100 0111

0 0 0 25

EPCS Device Memory Access Page 15

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

Write Enable Operation

The write enable operation code is

b'0000 0110

, and it lists the MSB first. The write

enable operation sets the write enable latch bit, which is bit

in the status register.

Always set the write enable latch bit before write bytes, write status, erase bulk, and

erase sector operations. Figure 5 shows the instruction sequence of the write enable

operation.

Figure 5. Write Enable Operation Timing Diagram

nCS

DCLK

ASDI

DATA

01234567

Operation Code

High Impedance

Write Disable Operation

The write disable operation code is

b'0000 0100

and it lists the MSB first. The write

disable operation resets the write enable latch bit, which is bit

in the status register.

To prevent the memory from being written unintentionally, the write enable latch bit

is automatically reset when implementing the write disable operation, and under the

following conditions:

■Power up

■Write bytes operation completion

■Write status operation completion

■Erase bulk operation completion

■Erase sector operation completion

Erase sector

1101 1000

3 0 0 25

Read device

identification (5) 1001 1111 0 2 1 to infinite (2) 25

Notes to Table 8:

(1) List MSB first and LSB last.

(2) The status register, data, or silicon ID is read out at least once on the

DATA

pin and is continuously read out until the

nCS

pin is driven high.

(3) A write bytes operation requires at least one data byte on the

DATA

pin. If more than 256 bytes are sent to the device, only the last 256 bytes

are written to the memory.

(4) The read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64 devices.

(5) The read device identification operation is available only for EPCS128 devices.

Table 8. EPCS Devices Operation Codes

Operation Operation Code (1) Address Bytes Dummy Bytes Data Bytes DCLK fMAX

(MHz)

Page 16 EPCS Device Memory Access

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

Figure 6 shows the instruction sequence of the write disable operation.

Figure 6. Write Disable Operation Timing Diagram

nCS

DCLK

ASDI

DATA

01234567

Operation Code

High Impedance

Read Status Operation

The read status operation code is

b'0000 0101

and it lists the MSB first. You can use

the read status operation to read the status register. Figure 7 and Figure 8 show the

status bits in the status register of the EPCS devices.

Figure 7. EPCS128, EPCS64, EPCS16, and EPCS4 Status Register Status Bits

Bit 7 Bit 0

Block Protect Bits [2..0] Write In

Progress Bit

Write Enable

Latch Bit

BP2 BP1 BP0 WEL WIP

Figure 8. EPCS1 Status Register Status Bits

Bit 7 Bit 0

Block Protect

Bits [1..0]

Write In

Progress Bit

Write Enable

Latch Bit

BP1 BP0 WEL WIP

Setting the write in progress bit to

indicates that the EPCS device is busy with a

write or erase cycle. Resetting the write in progress bit to

indicates no write or erase

cycle is in progress.

EPCS Device Memory Access Page 17

Serial Configuration (EPCS) Devices DatasheetApril 2014 Altera Corporation

Resetting the write enable latch bit to

indicates that no write or erase cycle is

accepted. Set the write enable latch bit to

before every write bytes, write status, erase

bulk, and erase sector operations.

The non-volatile block protect bits determine the area of the memory protected from

being written or erased unintentionally. Ta bl e 9 through Table 13 on page 19 list the

protected area in the EPCS devices with reference to the block protect bits. The erase

bulk operation is only available when all the block protect bits are set to

. When any

of the block protect bits are set to

, the relevant area is protected from being written

by a write bytes operation or erased by an erase sector operation.

Table 9. Block Protection Bits in the EPCS1 Device

Status Register Content Memory Content

BP1 Bit BP0 Bit Protected Area Unprotected Area

0 0

None All four sectors—0 to 3

0 1

Sector 3 Three sectors—0 to 2

1 0

Two sectors—2 and 3 Two sectors—0 and 1

1 1

All sectors None

Table 10. Block Protection Bits in the EPCS4 Device

Status Register Content Memory Content

BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

000

None All eight sectors—0 to 7

001

Sector 7 Seven sectors—0 to 6

010

Sectors 6 and 7 Six sectors—0 to 5

011

Four sectors—4 to 7 Four sectors—0 to 3

100

All sectors None

101

All sectors None

110

All sectors None

111

All sectors None

Page 18 EPCS Device Memory Access

Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation

Table 11. Block Protection Bits in the EPCS16 Device

Status Register

Content Memory Content

BP2

Bit

BP1

Bit

BP0

Bit Protected Area Unprotected Area

0 0 0

None All sectors (32 sectors 0 to 31)

0 0 1

Upper 32nd (Sector 31) Lower 31/32nds (31 sectors—0 to 30)

0 1 0

Upper sixteenth (two sectors—30 and 31) Lower 15/16ths (30 sectors—0 to 29)

0 1 1

Upper eighth (four sectors—28 to 31) Lower seven-eighths (28 sectors—0 to 27)

1 0 0

Upper quarter (eight sectors—24 to 31) Lower three-quarters (24 sectors—0 to 23)

1 0 1

Upper half (sixteen sectors—16 to 31) Lower half (16 sectors—0 to 15)

1 1 0

All sectors (32 sectors—0 to 31) None

1 1 1

All sectors (32 sectors—0 to 31) None

Table 12. Block Protection Bits in the EPCS64 Devices

Status Register

Content Memory Content

BP2