ee FAIRCHILD ee SEMICONDUCTOR 100352 General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). AQ out put follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is -2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when sev- eral loads share the bus. The 100352 outputs are designed to drive a doubly termi- nated 50Q transmission line (25Q load impedance). All in- puts have 50 kQ pull-down resistors. March 1998 Low Power 8-Bit Buffer with Cut-Off Drivers Features = Cut-off drivers @ Drives 250 load w Low power operation @ 2000V ESD protection w Voltage compensated operating range = -4.2V to -5.7V @ Available to industrial grade temperature range @ Available to MIL-STD-883 Ordering Code: Logic Symbol Dp Dy Dz Dz Dy Ds Dg Dy Qy 01 Q, 05 Oy O5 Qs Oy DS010248-1 Connection Diagrams 24-Pin DIP LA Dy! 24,-D; Ds42 23D, De-3 22;-D, by44 21F-Dp EN 5 20;-NC Veo 6 19; -NC Voca ]7 18--Vee Voca 18 '7F-Veoa a3 16a, Qg-4 10 15-9, git 14-9, Q4-412 13-03 DS610248-2 Pin Names Description Do-Dz Data Inputs OEN Output Enable Input Q,-Qz Data Outputs NC No Connect 28-Pin PCC Q1 Qs Q3 Vers Q4 O5 I 4 =) & Q Veca VEE Vees NC NC Do bal Dy Dy D3 Vezs Dy Ds Dg Ds010248-4 1998 Fairchild Semiconductor Corporation DS010248 www fairchildsemi.com SIDA HO-IND YUM J9jjNgG W-8 4aMOd MO] ZSEONLConnection Diagrams (Continued) 24-Pin Quad Cerpak Dy NC NC Vee Vecg Qp |_ jj jj) 24 23 22 21 20 19 yo! 18a, Dy 2 17 O, Dy43 16F Q5 D444 15> Q, Ds 5 14-05 Dg76 13-0, 7 8 9 10 11:12 rr ritd Dz OEN Yee Yeca Yoca Q7 DS010248-3 Logic Diagram Dg D, Dy Ds, D4 Ds Dg Dy Q Q Q Q Q Q Q Q 0 1 2 3 4 5 6 7 EN DS010248-5 Truth Table Inputs Outputs Dn Qn L L H H x H = HIGH Voltage Level L = LOW Voltage Level Cutoff = Lower-than-LOW State X = Don't Care www fairchildsemi.com 2Absolute Maximum Ratings (note 1) Above which the useful life may be impaired Storage Temperature (Tera) -65C to +150C Maximum Junction Temperature (Tj) Ceramic H175C Plastic +150C Vee Pin Potential to Ground Pin -7.0V to +0.5V Input Voltage (DC) Vee to +0.5V Output Current (DC Output HIGH) -100 mA ESD (Note 2) 22000V Commercial Version DC Electrical Characteristics Recommended Operating Conditions Case Temperature (Tg) Commercial 0C to +85C Industrial -40C to +85C Military -55C to +125C Supply Voltage (Vee) -5.7V to -4.2V Note 1: Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Vee = 4.2V to -5.7V, Voo = Voca = GND, To = 0C to +85C (Note 3) Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 -955 -870 mV Vin =Vin (Max Loading with Vor Output LOW Voltage -1830 | -1705 | -1620 or Vit (min) 25Q to -2.0V Voue Output HIGH Voltage -1035 mV Vin = Vin ein) Loading with Vote Output LOW Voltage -1610 or Vit (Max) 25Q to -2.0V Voiz Cut-Off LOW Voltage -1950 mV Vin = Vin amin) OF OEN = HIGH Vit (max) Vin Input HIGH Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 HA Vin = Vit (min) lia Input HIGH Current 240 HA Vin = Vin (max) lee Power Supply Current Inputs Open -138 -70 mA Vee = -4.2V to -4.8V -143 -70 Vee = -4.2V to -5.7V Note 3: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. DIP AC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = 0'C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.70 2.00 0.70 2.00 0.70 2.20 ns Figures 1, 2 tpHL Dn to Output (Note 4) tezH Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20 ns Figures 1, 2 tpuz OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 4) toy Transition Time 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 2 tH 20% to 80%, 80% to 20% Note 4: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. www fairchildsemi.comPCC and Cerpak AC Electrical Characteristics Vee = 4.2V to -5.7V, Veo = Vooa = GND Symbol Parameter To = OC To = +25C To = +85C Units Conditions Min Max Min Max Min Max TeLH Propagation Delay 0.70 1.80 0.70 1.80 0.70 2.00 ns Figures 1, 2 TeHL Dn to Output (Note 6) tpzH Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00 ns Figures 1, 2 tpuz OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 6) tty Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 2 tra 20% to 80%, 80% to 20% tosHL Maximum Skew Common Edge PCC only Output-to-Output Variation 230 230 230 ps (Note 5) Data to Output Path tosLH Maximum Skew Common Edge PCC only Output-to-Output Variation 240 240 240 ps (Note 5) Data to Output Path tost Maximum Skew Opposite Edge PCC only Output-to-Output Variation 350 350 350 ps (Note 5) Data to Output Path tps Maximum Skew PCC only Pin (Signal) Transition Variation 350 350 350 ps (Note 5) Data to Output Path Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tggy1), or LOW to HIGH (tog_y), or in opposite directions both HL and LH (tost). Parameters togt and tpg guaranteed by design. Note 6: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Industrial Version PCC DC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Voca = GND, To = -40C to +85C (Note 7) Symbol Parameter To = -40C To = OC to +85C Units Conditions Min Max Min Max Vou Output HIGH Voltage -1085 -870 -1025 -870 mV Vin = Vinmax) Loading with Vor Output LOW Voltage -1830 -1575 | -1830 -1620 or Vit(miny 252 to -2.0V Vouc Output HIGH Voltage -1095 -1035 mV Vin = Vinqminy Loading with Vote Output LOW Voltage -1565 -1610 or Viimax) 25Q to -2.0V Voiz Cut-Off LOW Voltage -1950 -1950 mV Vin = Vinqminy OF OEN =HIGH Vit (Max) Vin Input HIGH Voltage -1170 -870 -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1480 -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 0.50 HA Vin = Vicqminy lie Input HIGH Current 340 240 HA Vin = Vinmax) lee Power Supply Current Inputs Open -138 -60 -138 -70 mA Vee = -4.2V to -4.8V -143 -60 -143 -70 Vee = -4.2V to -5.7V Note 7: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. www fairchildsemi.comPCC AC Electrical Characteristics Vee = 4.2V to -5.7V, Veo = Vooa = GND Symbol Parameter To = -40C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.60 1.80 0.70 1.80 0.70 2.00 ns Figures 1, 2 TeHL Dn to Output (Note 8) tezH Propagation Delay 1.40 4.40 1.60 4.00 1.60 4.00 ns Figures 1, 2 tpuz OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 8) tty Transition Time 0.40 2.50 0.45 1.90 0.45 1.90 ns Figures 1, 2 tra 20% to 80%, 80% to 20% Note 8: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Military Version DC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND, To = -55C to +125C Symbol Parameter Min Max | Units Te Conditions Notes Vou Output HIGH Voltage |-1025 | -870 mV 0C to +125C | Vin = Vinimaxy Loading | (Notes 9, -1085 | -870 | mV -55C or Vitiminy with 10, 11) Vo. | Output LOW Voltage |-1830 |-1620] mv | 0C to +125C 252 to -1830 |-1555| mV -55C 2.00 Voue Output HIGH Voltage |-1035 mV O'S to +125C | Vin = Vincminy Loading | (Notes 9, 1085 mV 55C or Vit(max) with 10, 11) Voc | Output LOW Voltage te10| mv | 0Cto +125C 252 to -1555 | mV -55C 2.00 Voiz Cut-Off LOW Voltage -1950 | mV 0C to +125C | Vin = Vincminy,OF OEN (Notes 9, 1850 -55C Vit(max) =HIGH 10, 11) Vin Input HIGH Voltage -1165 | -870 mV | -55C to +125C | Guaranteed HIGH signal 1.2.3.4 for All inputs Vit Input LOW Voltage ~1830 }-1475 | mv | -88C to +125C | Guaranteed LOW signal (Notes 9, for All inputs o). lit Input LOW Current 0.50 HA 55C to +125C | Veg = 4.2V (Notes 9, Vin = Vit(min) 10, 11) lie Input HIGH Current 240 HA OC to+125C | Veg = -5.7V (Notes 9, 340 UA -55C Vin = Vinwmax) 10, 11) lee Power Supply Current 55C to +125C | Inputs Open (Notes 9, -145 | -55 mA Vee = -4.2V to -4.8V 10, 11) -150 Vee = -4.2V to -5.7V Note 9: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 10: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8. Note 11: Sample tested (Method 5005, Table |) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8. Note 12: Guaranteed by applying specified input condition and testing VoH/VoL. AC Electrical Characteristics Vee = 4.2V to -5.7V, Voo = Veca = GND Symbol Parameter To = -55C To = +25C Te +125C | Units | Conditions Notes Min Max Min Max Min Max teLH Propagation Delay 0.30 2.60 0.50 2.40 0.50 2.70 ns Figures 1, 2 (Notes 13, teu Dn to Output 14, 16, 17) www fairchildsemi.comAC Electrical Characteristics (continuea) Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = -55C To = +25C To +125C Units Conditions Notes Min Max Min Max Min Max tpzH Propagation Delay 1.20 4.40 1.40 4.20 1.20 4.40 ns Figures 1,2 (Notes 13, teuz OEN to Output 0.70 3.00 | 0.70 280 | 0.70 3.20 14, 15, 17) tty Transition Time 0.40 2.50 0.40 2.40 0.40 2.70 ns Figures 1,2 (Note 16) trae 20% to 80%, 80% to 20% Note 13: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immedi- ately after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 14: Screen tested 100% on each device at +25C temperature only, Subgroup AQ. Note 15: Sample tested (Method 5005, Table |) on each manufactured lot at +25C, Subgroup AQ, and at +125C and -55C temperatures, Subgroups A10 and A11. Note 16: Not tested at +25C, +125C, and -55C temperature (design characterization data). Note 17: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Test Circuitry ul PULSE Cy O SCOPE GENERATOR vt wt CHAN A I Voc LL R T tT" = n oni = 2 PULSE ny D Q ; cu SCOPE GENERATOR vt vt CHAN B | 500 TF 500 Ry 0.1 pF ~ DS010248-6 Notes: Voc. Voca = +2V, Veg = -2.5V L1 and L2 = equal length 50Q impedance lines Ry = 50Q terminator internal to scope Decoupling 0.1 pF from GND to Voc and Vee All unused outputs are loaded with 250 to GND C, = Fixture and stray capacitance < 3 pF FIGURE 1. AC Test Circuit Switching Waveforms mm OX X KX 1 OUTPUT ' ENABLE fl 1 1 1 1 1 1 T T OUTPUT ' 50% x AX L ' if ' 1 ' 1 ' 1 ro Pp >, et he ete tpuz tbzy DS010248-7 Note: The output AC measurement point for cut-off propagation delay testing = the 50% voltage point between active Vo_ and Voy. FIGURE 2. Propagation Delay, Cut-Off and Transition Times www fairchildsemi.com 6Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100352 D GC QB Device Number (Basic) ne Le Special Variation QB = Military grade device with environmental and burn-in processing Package Code D = Ceramic DIP F = Quad Cerpak P = Plastic DIP Temperature Range Q = Plastic Leaded Chip Carrier (PCC) C = Commercial (0C to + 85C) | = Industrial ( 40C to + 85C) (PCC Only) M = Military (55C to + 125C) DS010248-8 Physical DimeNnSiONS inches (millimeters) unless otherwise noted 1.215 . (30.86) 0.025 MAX 0.030 0.055 (0.64) 24 3 (0.761.40) nF mm RAD TYP 0.390 (9.91) MAX \ J Lhd he be hn he hn he ene yp| ng 9.0820.082 (0.81 1.07) _ 0.005 GLASS 0.0500.060 0.4000.430 0.180 0.13) SEALANT (.a71s2) YP) PS | |o.0150.056./,, *(10.16= 10.92) (4.57) MIN TYP (0.38 1.40) YY MAX T | i 0.225 b | es f | H (5.72) a | Vmax Tefll ~ A way rT 4 \ 90 100 0.008 0.012 TYP f TYP i %0.200.30) 0.125 Tye 0.055 | 0,0900.110 _ E 0.0150.021 | Lea) 0.4350.535 (1.40) (2.29 2.79) (0.38 0.83) MIN (99.05 =13.59) MAX TYP Tye TYP BOTH ENDS sae ev 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) Package Number J24E www fairchildsemi.comPhysical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 1.194-1.214 [30.33-30.84] 0.202 2A [5.13] 13 ee ee ee ee eee 0.035-0.045 f [0.89-1.14] b) 0.337-0.347 [8.56-8.81] Q u CDICDICI CIO CU tI Uo | 1 12 PIN NO. 1 IDENT 9 125 [3.18] 0.125-0.135 4 0.060 0.039 - [3.18-3.43] TYP >| fe 4X | he 0.390-0.410 [1.52] [0.99] 0.065 [9.91-10.41] [1.65] -_ Jay 5 ; 0.145-0.200 | | } 0-100 [3.68-5.08] 869-949 _ 0.380 0.020 ji L_ 0.125-0.140 rp , 4 Il [9.65] MN [ost] [5.18-5.56] | | | [.0.047-0.087 +0.040 nee 0.4287 0.050 ry. >| Tr19-1.45] TP | -0.015 [1.27] [10.87 *1-92) 0.015-0.021 0.090-0.110 0.009-0.015 -0.38] [0.38-0.53] TYP [2.29-2.79] TYP [0.23-0.38] N24E (REV A) 24-Lead Plastic Dual-In-Line Package (P) Package Number N24E www fairchildsemi.com 8Physical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) +0.006 0.450 "hoo +0.15 ee IDENT 450 x 7 04e [1.14] 0.017#0.004 TYP 4 1 26 9.02940.003 ryp [0.43+0.10] a} [0.7440.08] | -| _ []25 a n f + H 0.4100.020 L [10.410.51] L] L] L]19 12 18 SEATING PLANE 1 0.050 typ | ne ja [1.27] | fa 9-020 in Typ 0.300 yyp [0.51] [7.62] 0.10540.015 ago y 0-045 [2.6740.38] [1.14] 0.165-0.180 TYP [4.19-4.57] a 0.490#0.005 [12.4540.13] TYP V2BA (REV K) 28-Lead Plastic Chip Carrier (Q) Package Number V28A www fairchildsemi.com100352 Low Power 8-Bit Buffer with Cut-Off Drivers Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 0.360 ~ 9.250 TYP > PIN ND. 1 N (MOLDED BODY) 0.370 MIN 0.360 TYP 9959 TYP {24 19 111 18 fz __ | 1 _ J 6 3> 7 12 0.018 | 0.075 MAX o.o1g TYP 8 PLCS 0.050 + 0.005 , TYP LIFE SUPPORT POLICY 0.400 MAX ___,,. | TYP GLASS 0.007 * I~ o.o04 TYP 0.050 Pl 01035 -~t 0.085 MAX W248 (REV Di 24-Lead Quad Cerpak (F) Package Number W24B FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, failure to perform when properly used with instructions for use provided in th and (c) whose in accordance e labeling, can be reasonably expected to result in a significant injury 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Fairchild Semiconductor Fairchild Corporation Europe Semiconductor Americas Fax: +49 (0) 1 80-530 85 86 Customer Response Center Tel: 1-888-522-5372 Deutsch English Italy www fairchildsemi.com Email: europe.support@nsc.com Tel: +49 (0) 8 141-35-0 Tel: +44 (0) 1 793-85-68-56 Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, & Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.