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© 2005 Fairchild Semiconductor Corporation DS500159 www.fairchildsemi.com
March 2000
Revised June 2005
74VCX164245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
74VCX164245
Low Voltage 16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Descript ion
The VCX164245 is a dual supply, 16-bit translating trans-
ceiver tha t is designe d for two way asyn chronous co mmu-
nication between busses at different supply voltages by
providing tr ue signal trans lation . T he sup pl y r ails co nsist of
VCCB, which is t he hi gh er pot ent i al ra i l op era ti ng at 2.3 V to
3.6V and VCCA, which is the lower potential rail operating at
1.65V to 2.7V. (VCCA must be less than or equal to VCCB
for proper device operation.) This dual supply design
all o ws f or tr an s lat i o n f ro m 1. 8 V t o 2. 5 V b us se s t o bu s s es a t
a higher pot ential, up to 3.3 V.
The Transmit/Rec eive (T/R) input deter mines the direct ion
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports. Receive (ac tive-LOW) enab les data from
B Ports to A Ports. The Output Enable (OE) input, when
HIGH, disables both A and B Ports by placing them in a
High-Z condition. The A Port interfaces with the lower volt-
age bus (1.8V
2.5V). The B Port interfaces with the
higher voltage bus (2.7V
3.3V). Also the VCX164245 is
designe d so that t he control pins (T/R n, OEn) are s upplied
by VCCB.
The 74VCX164245 is suitable for mixed voltage applica-
tions such as notebook compute rs using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
■Bidirectional interface between busses ranging from
1.65V to 3.6V
■Supports Live Insertion and Withdrawal (Note 1)
■Static Drive (IOH/IOL)
r
24 mA @ 3.0V VCC
r
18 mA @ 2.3V VCC
r
6 mA @ 1.65V VCC
■Functionally compatible with 74 series 16245
■Latchup performance exceeds 300 mA
■ESD performa nce :
Human Body Model
!
2000V
Machine model
!
200V
■Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high impedance state during power up or power
down, OE n should be tied to VCCB through a pull up resistor. The minimum
value of the resist or is de term ined b y the cu rre nt so urcin g capab ility o f t he
driver.
Ordering Code:
Note 2: Ordering Code “G” indicates Trays.
Note 3: Device also av ailable in Tape and Reel . Specify by appending su ffix letter “X” to the ordering co de.
Logic Diagram
Order Number Package Number Package Descrip tion
74VCX164245G
(Note 2)(Note 3) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX164245MTD
(Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
■Uses proprietary noise /E MI reduct ion c ircui tr y
www.fairchildsemi.com 2
74VCX164245
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FB GA
(Top Through View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
HIGH Volt age Level
L
LOW Voltage Le ve l
X
Immaterial (HIG H or LOW, inputs may not float)
Z
High Impedance
Translator Power Up Sequence Recomm endations
To guard against power up problems, some simple guide-
lines need to be a dhered to. T he VCX16 4245 is designe d
so t hat the control pi ns (T/Rn, OEn) ar e supplied by VCCB.
Therefore the first recommendation is to begin by powering
up the control side of the device, VCCB. The OEn control
pins should be ramped with or ahead of VCCB, this will
guard against bus contentions and oscillations as all A Port
and B Port outputs will be disabled. To ensure the high
impedance state during power up or power down, OEn
shou ld be ti ed to VCCB throug h a pu ll up re sisto r. The mini-
mum value of the resistor is determined by the current
sourcing capability of the driver. Second, the T/Rn control
pins should be placed at logic low (0V) level, this will
ensure th at the B-s ide bus pins a re con fi gu red as inp uts to
help guard against bus contention and oscillations. B-side
Data Inputs should be driven to a valid logic level (0V or
VCCB), this will p revent exce ssive c urrent draw a nd oscilla-
tions. VCCA can then be powered up after VCCB, but should
never exceed the VCCB voltage level. Upon completion of
these steps the device can then be configured for the users
desired operation. Following these steps will help to pre-
vent possible damage to the translator device as well as
other system components.
Pin Names Descr ipt io n
OEnOutput Enable Input (Active LOW)
T/RnTransmit/Receive Inp ut
A0–A15 Side A Inputs or 3-STATE Outputs
B0–B15 Side B Inputs or 3-STATE Outputs
NC No Connect
123456
AB0NC T/R1OE1NC A0
BB2B1NC NC A1A2
CB4B3VCCB VCCA A3A4
DB6B5GND GND A5A6
EB8B7GND GND A7A8
FB10 B9GND GND A9A10
GB12 B11 VCCB VCCA A11 A12
HB14 B13 NC NC A13 A14
JB15 NC T/R2OE2NC A15
Inputs Outputs
OE1T/R1
L L Bus B0–B7 Data to Bus A0–A7
L H Bus A0–A7 Data to Bus B0–B7
H X HIGH Z State on A0–A7, B0–B7
Inputs Outputs
OE2T/R2
L L Bus B8–B15 Data to Bus A8–A15
L H Bus A8–A15 Data to Bus B8–B15
H X HIGH-Z State on A8–A15, B8–B15
3 www.fairchildsemi.com
74VCX164245
Logic Diagrams
Please not e t hat these dia grams are provided only for the und ers ta nding of logi c o perations and should not be used to estim ate propag at ion delays.
www.fairchildsemi.com 4
74VCX164245
Absolute Maximum Ratings(No t e 4) Recommended Operating
Conditions (Note 6)
Note 4: The “Absolute Maxim um Ratings” are those values be yond which
the saf ety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “R ecomm ended Ope rating Condition s” tabl e will d efine th e cond itions
for actu al device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Unused inputs or I/O pins must be held HIGH or LOW. They may
not float.
Note 7: Operat ion requires: VCCA
d
VCCB
DC Electrical Characteristics (1.65V VCCA d 1.95V, 2.3V VCCB d 2.7V)
Supply Voltage
VCCA
0.5V to VCCB
VCCB
0.5V to 4.6V
DC Input Voltage (VI)
0.5V to
4.6V
DC O utput Voltage (VI/O)
Outputs 3-STAT E
0.5V to
4.6V
Outputs Active (Note 5)
An
0.5V to VCCA
0.5V
Bn
0.5V to VCCB
0.5V
DC Input Diode Current (IIK)
VI
0V
50 mA
DC Output Diode Current (IOK)
V
O
0V
50 mA
V
O
!
VCC
50 mA
DC Output Source/Sink Current
r
50 mA
(IOH/IOL)
DC VCC or Ground Current
r
100 mA
Supply Pin (ICC or Ground)
Storage Temperature (TSTG)
65
q
C to
150
q
C
Power Supply (Note 7)
VCCA 1.65V to 2.7V
VCCB 2.3V to 3.6V
Input Voltage (VI) @ OE, T/R 0V to VCCB
Input/Output Voltage (VI/O)
An0V to VCCA
Bn0V to VCCB
Output Current in IOH/IOL
VCCA
2.3V to 2.7V
r
18 mA
VCCA
1.65V to 1.95V
r
6 mA
VCCB
3.0V to 3.6V
r
24 mA
VCCB
2.3V to 2.7V
r
18 mA
Free Air Operating Temperature (TA)
40
q
C to
85
q
C
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, VCC
3.0V 10 ns/V
Symbol Parameter Conditions VCCA VCCB Min Max Units
(V) (V)
VIHA HIGH Level Input V olt age An1.65
1.95 2.3
2.7 0.65 x VCC V
VIHB Bn, T/R, OE 1.65
1.95 2.3
2.7 1.6 V
VILA LOW Level Input Voltage An1.6
1.95 2.3
2.7 0.35 x VCC V
VILB Bn, T/R, OE 1.65
1.95 2.3
2.7 0.7 V
VOHA HIGH Level Output Voltage IOH
100
P
A1.65
1.95 2.3
2.7 VCCA
0.2 V
IOH
6 mA 1.65 2.3
2.7 1.25
VOHB HIGH Level Output Voltage IOH
100
P
A1.65
1.95 2.3
2.7 VCCB
0.2 V
IOH
18 mA 1.65
1.95 2.3 1.7
VOLA LOW Level Output Voltage IOL
100
P
A1.65
1.95 2.3
2.7 0.2 V
IOL
6 mA 1.65 2.3
2.7 0.3
VOLB LOW Level Output Voltage IOL
100
P
A1.65
1.95 2.3
2.7 0.2 V
IOL
18 mA 1.65
1.95 2.3 0.6
IIInput Leakage Current @ OE, T/R 0V
d
VI
d
3.6V 1.65
1.95 2.3
2.7
r
5.0
P
A
IOZ 3-STATE Output Leakage 0V
d
VO
d
3.6V 1.65
1.95 2.3
2.7
r
10
P
AOE
VCCB
VI
VIH or VIL
IOFF Power OFF Leakage Current 0
d
(VI, VO)
d
3.6V 0 0 10
P
A
ICCA/ICCB Quiescent Supply Current, An
VCCA or GND 1.65
1.95 2.3
2.7 20
P
A
per supply, VCCA / VCCB Bn, OE, & T/R
VCCB or GND
VCCA
d
An
d
3.6V 1.65
1.95 2.3
2.7
r
20
P
A
VCCB
d
Bn, OE, T/R
d
3.6V
'
ICC Increase in ICC per Input, Bn, T/R, OE VI
VCCB – 0.6V 1.65
1.95 2.3
2.7 750
P
A
Increase in ICC per Input, AnVI
VCCA – 0.6V 1.65
1.95 2.3
2.7 750
P
A
5 www.fairchildsemi.com
74VCX164245
DC Electrical Characteristics (1.65V VCCA d 1.95V, 3.0V VCCB d 3.6V)
DC Electrical Characteristics (2.3V VCCA d 2.7V, 3.0V d VCCB d 3.6V)
Symbol Parameter Conditions VCCA VCCB Min Max Units
(V) (V)
VIHA HIGH Level A n1.65–1.95 3.0–3.6 0.65 x VCC V
VIHB Input Voltage Bn, T/R, OE 1.65–1.95 3.0–3.6 2.0 V
VILA LOW Level An1.65–1.95 3.0–3.6 0.35 x VCC V
VILB Input Voltage Bn, T/R, OE 1.65–1.95 3.0–3.6 0.8 V
VOHA HIGH Level Output Voltage IOH
100
P
A1.65–1.95 3.0–3.6 VCCA–0.2 V
IOH
6 mA 1.65 3.0–3.6 1.25
VOHB HIGH Level Output Voltage IOH
100
P
A1.65–1.95 3.0–3.6 VCCA–0.2 V
IOH
24 mA 1.65–1.95 3.0 2.2
VOLA LOW Level Output Voltage IOL
100
P
A1.65–1.95 3.0–3.6 0.2 V
IOL
6 mA 1.65 3.0–3.6 0.3
VOLB LOW Level Output Voltage IOL
100
P
A1.65–1.95 3.0–3.6 0.2 V
IOL
24 mA 1.65–1.95 3.0 0.55
IIInput Leakage Current @ OE, T/R 0V
d
VI
d
3.6V 1.65–1.95 3.0–3.6
r
5.0
P
A
IOZ 3-STATE Output Leakage 0V
d
VO
d
3.6V 1.65–1.95 3.0–3.6
r
10
P
AOE*
VCCB
VI
VIH or VIL
IOFF Power Off Leakage Current 0
d
(VI, VO)
d
3.6V 0 0 10
P
A
ICCA/ICCB Quiescent Supply Current, An
VCCA or GND 1.65–1.95 3.0–3.6 20
P
A
per supply, VCCA/VCCB Bn, OE, & T /R
VCCB or GND
VCCA
d
An
d
3.6V 1.65–1.95 3.0–3.6
r
20
P
A
VCCB
d
Bn, OE, T/R
d
3.6V
'
ICC Increase in ICC per Input, Bn, T/R, OE VI
VCCB
0.6V 1.65 –1.95 3.0–3.6 750
P
A
Increase in ICC per Input, AnVI
VCCA
0.6V 1.65 –1.95 3.0–3.6 750
P
A
Symbol Parameter Conditions VCCA VCCB Min Max Units
(V) (V)
VIHA HIGH Level Input V olt age An2.3–2.7 3.0–3.6 1.6 V
VIHB Bn, T/R, OE 2.3–2.7 3.0–3.6 2.0 V
VILA LOW Level Input Voltage An2.3–2.7 3.0–3.6 0.7 V
VILB Bn, T/R, OE 2.3–2.7 3.0–3.6 0.8 V
VOHA HIGH Level Output Voltage IOH
100
P
A2.3–2.7 3.0–3.6 VCCA–0.2 V
IOH
18 mA 2.3 3.0–3.6 1.7
VOHB HIGH Level Output Voltage IOH
100
P
A2.3–2.7 3.0–3.6 VCCB–0.2 V
IOH
24 mA 2.3–2.7 3.0 2.2
VOLA LOW Level Output Voltage IOL
100
P
A2.3–2.7 3.0–3.6 0.2 V
IOL
18 mA 2.3 3.0–3.6 0.6
VOLB LOW Level Output Voltage IOL
100
P
A2.3–2.7 3.0–3.6 0.2 V
IOL
24 mA 2.3–2.7 3.0 0.55
IIInput Leakage Current @ OE, T/R 0V
d
VI
d
3.6V 2.3–2.7 3.0–3.6
r
5.0
P
A
IOZ 3-STATE Output Leakage @ An0V
d
VO
d
3.6V 2.3–2.7 3.0–3.6
r
10
P
AOE
VCCA
VI
VIH or VIL
IOFF Power OFF Leakage Current 0
d
(VI, VO)
d
3.6V 0 0 10
P
A
ICCA/ICCB Quiescent Supply Current, An
VCCA or GND 2.3–2.7 3.0–3.6 20
P
A
per supply, VCCA/VCCB Bn, OE, & T/R
VCCB or GND
VCCA
d
An
d
3.6V 2.3–2.7 3.0–3.6
r
20
P
A
VCCB
d
Bn, OE, T/R
d
3.6V
'
ICC Increase in ICC per Input, Bn, T/R, OE VI
VCCB
0.6V 2.3–2.7 3.0–3.6 750
P
A
Increase in ICC per Input, AnVI
VCCA
0.6V 2.3–2.7 3.0–3.6 750
P
A
www.fairchildsemi.com 6
74VCX164245
AC Electrical Characteristics
Note 8: Skew is defined as the absolute value o f t he difference between t he actual propagat ion delay fo r any two se parate outputs of the same device. The
specif ic ation appl ies t o any outputs switching in th e s ame direction, either HIGH-to-LOW (tosHL) or LOW-to-H IG H (t osLH).
Dynamic Switching Characteristics
Capacitance
Symbol Parameter
CL
30 pF, RL
500
:
, TA
40
q
C to
85
q
C,
Units
VCCA
1.65V to 1.95V VCCA
1.65V to 1.95V VCCA
2.3V to 2.7V
VCCB
2.3V to 2.7V VCCB
3.0V to 3.6V VCCB
3.0V to 3.6V
Min Max Min Max Min Max
tPHL, tPLH Propagation Delay, A to B 0.8 5.5 0.6 5.1 0.6 4.0 ns
tPHL, tPLH Propagation Delay, B to A 1.5 5.8 1.5 6.2 0.8 4.4 ns
tPZL, tPZH Output Enable Time, OE to B 0.8 5.3 0.6 5.1 0.6 4.0 ns
tPZL, tPZH Output Enable Time, OE to A 1.5 8.3 1.5 8.2 0.8 4.6 ns
tPLZ, tPHZ Output Disable Time, OE to B 0.8 5.2 0.8 5.6 0.8 4.8 ns
tPLZ, tPHZ Output Disable Time, OE to A 0.8 4.6 0.8 4.5 0.8 4.4 ns
tosHL Output to Output Skew 0.5 0.5 0.75 ns
tosLH (Note 8)
Symbol Parameter Conditions VCCA VCCB TA
25
q
CUnits
(V) (V) Typical
VOLP Quiet Output Dynamic Peak VOL,C
L
30 pF, VIH
VCC, VIL
0V 1.8 2.5 0.25 VB to A 1.8 3.3 0.25
2.5 3.3 0.6
Quiet Output Dynamic Peak VOL,C
L
30 pF, VIH
VCC, VIL
0V 1.8 2.5 0.6 VA to B 1.8 3.3 0.8
2.5 3.3 0.8
VOLV Quiet Output Dynamic Valley VOL, CL
30 pF, VIH
VCC, VIL
0V 1.8 2.5
0.25 VB to A 1.8 3.3
0.25
2.5 3.3
0.6
Quiet Output Dynamic Valley VOL, CL
30 pF, VIH
VCC, VIL
0V 1.8 2.5
0.6 VA to B 1.8 3.3
0.8
2.5 3.3
0.8
VOHV Quiet Output Dynamic Valley VOH,C
L
30 pF, VIH
VCC, VIL
0V 1.8 2.5 1.7 VA to B 1.8 3.3 2.0
2.5 3.3 2.0
Quiet Output Dynamic Valley VOH,C
L
30 pF, VIH
VCC, VIL
0V 1.8 2.5 1.3 VB to A 1.8 3.3 1.3
2.5 3.3 1.7
Symbol Parameter Conditions TA
25
q
CUnits
Typical
CIN Input Capacitance VCCA
2.5V, VCCB
3.3V, VI
0V or VCCA/B 5pF
CI/O Input/Output Capacitance VCCA
2.5V, VCCB
3.3V, VI
0V or VCCA/B 6pF
CPD Power Dissipation Capacitance VCCA
2.5V, VCCB
3.3V, VI
0V or VCCA/B 20 pF
f
10 MHz
7 www.fairchildsemi.com
74VCX164245
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-inverting Functions
tR
tF
d
2.0 ns, 10% to 90%
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
tR
tF
d
2.0 ns, 10% to 90%
FIGURE 4. 3-STATE Output Low Enable and Disable Time s for Low Voltage Logic
tR
tF
d
2.0 ns, 10% to 90%
TEST SWITCH
tPLH, tPHL OPEN
tPZL, tPLZ 6V at VCC
3.3
r
0.3V;
VCC x 2 at VCC
2.5
r
0.2V; 1.8V
r
0.15V
tPZH, tPHZ GND
Symbol VCC
3.3V
r
0.3V 2.5V
r
0.2V 1.8V
r
0.15V
Vmi 1.5V VCC/2 VCC/2
Vmo 1.5V VCC/2 VCC/2
VXVOL
0.3V VOL
0.15V VOL
0.15V
VYVOH
0.3V VOH
0.15V VOH
0.15V
8 www.fairchildsemi.com
74VCX164245
Physical Dim ensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
9 www.fairchildsemi.com
74VCX164245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
48-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP), JED EC MO-1 53, 6.1mm Wide
Package Number MTD48
Fairchild does not assum e any responsibility for use of any circuitry described, no circuit patent lice nses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the labe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A critic al com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause the fa i lure of the life supp or t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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