Ultralow Input Bias Current
Operational Amplifier
AD549
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Ultralow input bias current
60 fA maximum (AD549L)
250 fA maximum (AD549J)
Input bias current guaranteed over the common-mode
voltage range
Low offset voltage
0.25 mV maximum (AD549K)
1.00 mV maximum (AD549J)
Low offset drift
5 μV/°C maximum (AD549K)
20 μV/°C maximum (AD549J)
Low power
700 μA maximum supply current
Low input voltage noise
4 μV p-p over 0.1 Hz to 10 Hz
MIL-STD-883B parts available
APPLICATIONS
Electrometer amplifier
Photodiode preamp
pH electrode buffer
Vacuum ion gauge measurement
CONNECTION DIAGRAM
00511-001
AD549
OFFS ET NULL
OUTPUT
V–
OFFSET
NULL
NONINVERTING
INPUT
V+
GUARD PI N,
CONNECTED
TO CASE
INVERTING
INPUT
V
OS
TRIM –15V
10kΩ
6
1
5
4
7
3
2
8
15
4
Figure 1.
GENERAL DESCRIPTION
The AD549 is a monolithic electrometer operational amplifier
with very low input bias current. Input offset voltage and input
offset voltage drift are laser trimmed for precision performance.
The ultralow input current of the part is achieved with Topgate™
JFET technology, a process development exclusive to Analog
Devices, Inc. This technology allows fabrication of extremely
low input current JFETs compatible with a standard junction
isolated bipolar process. The 1015 Ω common-mode impedance,
which results from the bootstrapped input stage, ensures that
the input current is essentially independent of the common-
mode voltage.
The AD549 is suited for applications requiring very low input
current and low input offset voltage. It excels as a preamp for a
wide variety of current output transducers, such as photodiodes,
photomultiplier tubes, or oxygen sensors. The AD549 can also
be used as a precision integrator or low droop sample-and-hold.
The AD549 is pin compatible with standard FET and electrometer
op amps, allowing designers to upgrade the performance of
present systems at little additional cost.
The AD549 is available in a TO-99 hermetic package. The case
is connected to Pin 8, thus, the metal case can be independently
connected to a point at the same potential as the input terminals,
minimizing stray leakage to the case. The AD549 is available in
four performance grades. The J, K, and L versions are rated over
the commercial temperature range of 0°C to +70°C. The S grade
is specified over the military temperature range of −55°C to +125°C
and is available processed to MIL-STD-883B, Rev. C. Extended
reliability plus screening is also available. Plus screening includes
168 hour burn-in, as well as other environmental and physical
tests derived from MIL-STD-883B, Rev. C.
PRODUCT HIGHLIGHTS
1. The AD549 input currents are specified, 100% tested, and
guaranteed after the device is warmed up. They are guaran-
teed over the entire common-mode input voltage range.
2. The AD549 input offset voltage and drift are laser trimmed
to 0.25 mV and 5 μV/°C (AD549K), and to 1 mV and
20 μV/°C (AD549J).
3. A maximum quiescent supply current of 700 μA minimizes
heating effects on input current and offset voltage.
4. AC specifications include 1 MHz unity-gain bandwidth
and 3 V/μs slew rate. Settling time for a 10 V input step is
5 μs to 0.01%.
AD549
Rev. H | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description .................................................................. 10
Minimizing Input Current ........................................................ 10
Circuit Board Notes ................................................................... 10
Offset Nulling ............................................................................. 11
AC Response with High Value Source and Feedback
Resistance .................................................................................... 12
Common-Mode Input Voltage Overload ............................... 12
Differential Input Voltage Overload ........................................ 13
Input Protection ......................................................................... 13
Sample and Difference Circuit to Measure Electrometer
Leakage Currents ........................................................................ 13
Photodiode Interface ................................................................. 14
Log Ratio Amplifier ................................................................... 15
Temperature Compensated pH Probe Amplifier ................... 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/08—Rev. G to Rev. H
Changes to Features .......................................................................... 1
Changes to Figure 1 .......................................................................... 1
Deleted Package Option Parameter ............................................... 4
Inserted ESD Caution ...................................................................... 5
Changes to Figure 2, Figure 3, and Figure 7.................................. 6
Changes to Figure 11 ........................................................................ 7
Changes to Figure 17 ........................................................................ 8
Changes to Figure 41 ...................................................................... 14
7/07—Rev. F to Rev. G
Changes to Figure 45 ...................................................................... 16
Changes to Temperature Compensated pH Probe
Amplifier Section ............................................................................ 17
Changes to Figure 46 ...................................................................... 17
Changes to Ordering Guide .......................................................... 18
5/06—Rev. E to Rev. F
Removed ESD Caution ..................................................................... 5
8/05—Rev. D to Rev. E
Change to Figure 22 .......................................................................... 9
5/04—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features .......................................................................... 1
Updated Outline Dimensions ....................................................... 18
Added Ordering Guide .................................................................. 18
10/02—Rev. B to Rev. C
Deleted Product Highlights #5 ........................................................ 1
Edits to Specifications ....................................................................... 3
Deleted Metallization Photograph .................................................. 3
Updated Outline Dimensions ....................................................... 13
7/02—Rev. A to Rev. B
Edits to Specifications ....................................................................... 2
AD549
Rev. H | Page 3 of 20
SPECIFICATIONS
@ 25°C and VS = ±15 V dc, unless otherwise noted; all minimum and maximum specifications are guaranteed; specifications in boldface
are tested on all production units at final electrical test, and results from those tests are used to calculate outgoing quality levels.
Table 1.
AD549J AD549K AD549L AD549S
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
INPUT BIAS CURRENT1
Either Input, VCM = 0 V 150 250 75 100 40 60 75 100 fA
Either Input, VCM = ±10 V 150 250 75 100 40 60 75 100 fA
Either Input at TMAX,
VCM = 0 V
11 4.2 2.8 420 pA
Offset Current 50 30 20 30 fA
Offset Current at TMAX 2.2 1.3 0.85 125 pA
INPUT OFFSET VOLTAGE2
Initial Offset 0.5 1.0 0.15 0.25 0.3 0.5 0.3 0.5 mV
Offset at TMAX
1.9 0.4 0.9 2.0 mV
vs. Temperature 10 20 2 5 5 10 10 15 μV/°C
vs. Supply 32 100 10 32 10 32 10 32 μV/V
vs. Supply, TMIN to TMAX 32 100 10 32 10 32 32 50 μV/V
Long-Term Offset Stability 15 15 15 15 μV/month
INPUT VOLTAGE NOISE
f = 0.1 Hz to 10 Hz 4 4 6 4 4 μV p-p
f = 10 Hz 90 90 90 90 nV/√Hz
f = 100 Hz 60 60 60 60 nV/√Hz
f = 1 kHz 35 35 35 35 nV/√Hz
f = 10 kHz 35 35 35 35 nV/√Hz
INPUT CURRENT NOISE
f = 0.1 Hz to 10 Hz 0.7 0.5 0.36 0.5 fA rms
f = 1 kHz 0.22 0.16 0.11 0.16 fA/√Hz
INPUT IMPEDANCE
Differential
VDIFF = ±1 1013||1 1013||1 1013||1 1013||1 Ω||pF
Common Mode
VCM = ±10 V 1015||0.8 1015||0.8 1015||0.8 1015||0.8 Ω||pF
OPEN-LOOP GAIN
VOUT @ ±10 V, RL = 10 kΩ 300 1000 300 1000 300 1000 300 1000 V/mV
VOUT @ ±10 V, RL = 10 kΩ,
TMIN to TMAX
300 800 300 800 300 800 300 800 V/mV
VOUT = ±10 V, RL = 2 kΩ 100 250 100 250 100 250 100 250 V/mV
VOUT = ±10 V, RL = 2 kΩ,
TMIN to TMAX
80 200 80 200 80 200 25 150 V/mV
INPUT VOLTAGE RANGE
Differential3
±20 ±20 ±20 ±20 V
Common-Mode Voltage −10 +10 −10
+10 −10
+10 −10
+10 V
Common-Mode Rejection
Ratio
−10 V ≤ VCM ≤ +10 V 80 90
90 100 90 100 90 100 dB
TMIN to TMAX 76 80
80 90
80 90
80 90 dB
AD549
Rev. H | Page 4 of 20
AD549J AD549K AD549L AD549S
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
VOUT @ RL = 10 kΩ, TMIN to
TMAX
−12 +12 −12
+12 −12
+12 −12
+12 V
VOUT @ RL = 2 kΩ, TMIN to TMAX −10 +10 −10
+10 −10
+10 −10
+10 V
Short-Circuit Current 15 20 35 15
20 35 15
20 35 15
20 35 mA
TMIN to TMAX 9
9
9
6 mA
Load Capacitance Stability,
G = +1
4000 4000 4000 4000 pF
FREQUENCY RESPONSE
Unity Gain, Small Signal 0.7 1.0 0.7 1.0 0.7 1.0 0.7 1.0 MHz
Full Power Response 50 50 50 50 kHz
Slew Rate 2 3 2 3 2 3 2 3 V/μs
Settling Time, 0.1% 4.5 4.5 4.5 4.5 μs
Settling Time, 0.01% 5 5 5 5 μs
Overload Recovery, 50%
Overdrive, G = −1
2 2 2 2 μs
POWER SUPPLY
Rated Performance ±15 ±15 ±15 ±15 V
Operating ±5 ±18 ±5 ±18 ±5 ±18 ±5 ±18 V
Quiescent Current 0.60 0.70 0.60 0.70 0.60 0.70 0.60 0.70 mA
TEMPERATURE RANGE
Operating, Rated
Performance
0 70 0 70 0 70 −55 +125 °C
Storage −65 +150 −65 +150 −65 +150 −65 +150 °C
1 Bias current specifications are guaranteed after five minutes of operation at TA = 25°C. Bias current increases by a factor of 2.3 for every 10°C rise in temperature.
2 Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C.
3 Defined as maximum continuous voltage between the inputs, such that neither input exceeds ±10 V from ground.
AD549
Rev. H | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation 500 mW
Input Voltage1
±18 V
Output Short-Circuit Duration Indefinite
Differential Input Voltage +VS and −VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range
AD549J, AD549K, AD549L 0°C to +70°C
AD549S −55°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
1 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD549
Rev. H | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5
00 5 10 15 20
V
IN+
V
IN–
00511-002
SUPPLY VOLT AG E (±V)
INPUT VOLTAG E (V)
Figure 2. Input Voltage Range vs. Supply Voltage
20
15
10
5
00 5 10 15 20
+V
OUT
25°C
R
L
= 10kΩ
–V
OUT
00511-003
SUPPLY VOLT AG E (±V)
OUT P UT VO LTAGE SWING (V )
Figure 3. Output Voltage Swing vs. Supply Voltage
30
25
20
15
10
5
010 100 1k 10k 100k
00511-004
LO AD RE SISTANCE (Ω)
OUTPUT VOLTAGE SWING (V p-p)
V
S
= ±15V
Figure 4. Output Voltage Swing vs. Load Resistance
800
700
600
500
400 0 5 10 15 20
00511-005
SUPPLY VOLT AG E (±V)
AMPLIF IER QUIE SCENT CURRENT (µ A)
Figure 5. Quiescent Current vs. Supply Voltage
120
100
110
90
80
70
–20 –10 0 10 20
00511-006
INPUT COMMON-MODE VOLTAGE (V)
COMMON-MODE REJECTION RATIO (dB)
Figure 6. CMRR vs. Input Common-Mode Voltage
3000
1000
300
100 0 5 10 15 20
00511-007
SUPPLY VOLT AG E (±V)
OPEN-LOOP GAIN (V/mV)
Figure 7. Open-Loop Gain vs. Supply Voltage
AD549
Rev. H | Page 7 of 20
3000
1000
300
100
–55 –25 5 35 65 95 125
00511-008
TEM PE RAT URE ( ° C)
OPEN-LOOP GAIN (V/mV)
Figure 8. Open-Loop Gain vs. Temperature
30
25
20
15
10
5
001234567
00511-009
WARM-UP TIME (Minutes)
ΔIV
OS
I (µV)
Figure 9. Change in Offset Voltage vs. Warm-Up Time
50
45
40
35
30
25
20
–10 –5 0 5 10
00511-010
COMMON-MODE VOLTAGE (V)
INPUT CURRENT ( f A)
Figure 10. Input Bias Current vs. Common-Mode Voltage
50
45
40
35
30
25
20 0 5 10 15 20
00511-011
POWER SUPPLY VOLTAGE (±V)
INPUT CURRENT ( f A)
Figure 11. Input Bias Current vs. Power Supply Voltage
160
140
120
100
80
60
40
2010 100 1k 10k
00511-012
FREQUENCY (Hz )
NOI S E SPECT RAL DENSITY ( nV/ Hz )
Figure 12. Input Voltage Noise Spectral Density
100k
10k
1k
100
10
1
0.1
100k 1M 10M 100M 1G 10G 100G
00511-013
SOURCE RES I S T ANCE (Ω)
INPUT NO I S E V O LTAGE (µV p-p)
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPL IFIER NOISE , AMPLI FIE R NOIS E CAN BE
CONSIDERED NEGL IGIBLE FO R T HE APPL ICAT ION
RESISTOR
JOHNSON NOISE
10Hz BANDWIDT H
AMPL IFIER GENERAT E D NOIS E
1kHz BANDWI DT H
Figure 13. Noise vs. Source Resistance
AD549
Rev. H | Page 8 of 20
100
80
60
40
20
0
–20
–40
100
–40
–20
0
20
40
60
80
10 100 1k 10k 100k 1M 10M
00511-014
FREQUENCY ( Hz)
OEPN-LOOP GAIN (dB)
PHASE M A RGIN (Degrees)
Figure 14. Open-Loop Frequency Response
40
35
30
25
20
15
10
5
010 100 1k 10k 100k 1M
00511-015
FREQUENCY (Hz )
OUT P UT VO LTAGE SWING (V )
Figure 15. Large Signal Frequency Response
100
80
60
40
20
0
–2010 100 1k 10k 100k 10M1M
00511-016
FREQUENCY (Hz )
COMM ON-M ODE REJE CTION RATIO ( dB)
Figure 16. CMRR vs. Frequency
120
100
80
60
40
20
0
–2010 100 1k 10k 100k 10M1M
00511-017
FREQUENCY (Hz )
POWER SUP P LY REJECTI ON RATIO ( dB)
+PSSR
–PSSR
Figure 17. PSRR vs. Frequency Response
10
–10
–5
0
5
01 324
00511-018
SETTLING TIME (µs)
OUT P UT VO LTAGE SWING (V )
5
10mV
5mV
1mV
10mV
5mV
1mV
Figure 18. Output Voltage Swing and Error vs. Settling Time
AD549
Rev. H | Page 9 of 20
00511-019
2
3
5
7
4
AD549
R
L
10kΩ
C
L
100pF
0.1µF
0.1µF
V
IN
–V
S
+V
S
V
OUT
S
QUARE
W
AVE
INPUT
Figure 19. Unity-Gain Follower
0
0511-020
5V
5µs
Figure 20. Unity-Gain Follower Large Signal Pulse Response
0
0511-021
10mV
1µs
Figure 21. Unity-Gain Follower Small Signal Pulse Response
0
0511-022
2
3
5
7
4
AD549
R
L
10kΩ
C
L
100pF
0.1µF
0.1µF
V
IN
–V
S
+V
S
V
OUT
S
QUARE
W
AVE
INPUT
10kΩ
10kΩ
Figure 22. Unity-Gain Inverter
0
0511-023
5V
5µs
Figure 23. Unity-Gain Inverter Large Signal Pulse Response
0
0511-024
10mV
1µs
Figure 24. Unity-Gain Inverter Small Signal Pulse Response
AD549
Rev. H | Page 10 of 20
FUNCTIONAL DESCRIPTION
MINIMIZING INPUT CURRENT
The AD549 is optimized for low input current and offset
voltage. Careful attention to how the amplifier is used reduces
input currents in actual applications.
Keep the amplifier operating temperature as low as possible to
minimize input current. Like other JFET input amplifiers, the
AD549 input current is sensitive to chip temperature, rising by
a factor of 2.3 for every 10°C. Figure 25 is a plot of the AD549
input current vs. ambient temperature.
1n
A
100pA
10pA
1pA
100fA
10fA
1fA
–55 –25 5 35 65 12595
00511-025
TEM PE RAT URE ( ° C)
INPUT BIAS CURRE NT
Figure 25. Input Bias Current vs. Ambient Temperature
On-chip power dissipation raises the chip operating tempera-
ture, causing an increase in input bias current. Due to the low
quiescent supply current of the AD549, the chip temperature
is less than 3°C higher than its ambient temperature when the
(unloaded) amplifier is operating with 15 V supplies. The
difference in the input current is negligible.
However, heavy output loads can cause a significant increase in
chip temperature and a corresponding increase in the input
current. Maintaining a minimum load resistance of 10 Ω is
recommended. Input current vs. additional power dissipation
due to output drive current is plotted in Figure 26.
6
5
4
3
2
10 25 50 75 100 125 150 175 200
00511-026
ADDIT IONAL INTERNAL POWER DISSI P ATION (mW )
NORMAL I ZED I NPUT BI AS CURRENT
BASED O N
TYP I CAL I
B
= 40fA
Figure 26. Input Bias Current vs. Additional Power Dissipation
CIRCUIT BOARD NOTES
A number of physical phenomena generate spurious currents
that degrade the accuracy of low current measurements. Figure 27
is a schematic of a current to voltage (I-to-V) converter with
these parasitic currents modeled.
00511-027
2
3
6
8
AD549
+
V
OUT
–
f
S
C
F
R
F
V
S
R
P
C
P
I
I'
= +V +
C
P
V
R
P
dC
P
dT dV
dT
Figure 27. Sources of Parasitic Leakage Currents
Finite resistance from input lines to voltages on the board,
modeled by Resistor RP, results in parasitic leakage. Insulation
resistance of more than 1015 Ω must be maintained between
the amplifier signal and supply lines to capitalize on the low
input currents of the AD549. Standard PCB material does not
have high enough insulation resistance; therefore, connect the
input leads of the AD549 to standoffs made of insulating
material with adequate volume resistivity (that is, Teflon®). The
surface of the insulator must be kept clean to preserve surface
resistivity. For Teflon, an effective cleaning procedure consists
of swabbing the surface with high grade isopropyl alcohol,
rinsing with deionized water, and baking the board at 80°C for
10 minutes.
In addition to high volume and surface resistivity, other proper-
ties are desirable in the insulating material chosen. Resistance
to water absorption is important because surface water films
drastically reduce surface resistivity. The insulator chosen
should also exhibit minimal piezoelectric effects (charge
emission due to mechanical stress) and triboelectric effects
(charge generated by friction). Charge imbalances generated
by these mechanisms can appear as parasitic leakage currents.
These effects are modeled by Variable Capacitor CP in Figure 27.
Table 3 lists various insulators and their properties.1
Guarding the input lines by completely surrounding them with
a metal conductor biased near the potential of the input lines
has two major benefits. First, parasitic leakage from the signal
line is reduced because the voltage between the input line and
the guard is very low. Second, stray capacitance at the input
node is minimized. Input capacitance can substantially degrade
signal bandwidth and the stability of the I-to-V converter.
1 Electronic Measurements, pp. 15–17, Keithley Instruments, Inc., Cleveland,
Ohio, 1977.
AD549
Rev. H | Page 11 of 20
The case of the AD549 is connected to Pin 8 so that it can be
bootstrapped near the input potential. This minimizes pin
leakage and input common-mode capacitance due to the case.
Guard schemes for inverting and noninverting amplifier
topologies are illustrated in Figure 28 and Figure 29.
00511-028
2
3
6
8
AD549
+
VOUT
–
IN
CF
RF
GUARD
Figure 28. Inverting Amplifier with Guard
0
0511-029
3
2
6
8
AD549 +
V
OUT
–
V
S
+
–
GUARD
R
F
R
I
Figure 29. Noninverting Amplifier with Guard
Other guidelines include keeping the circuit layout as compact
as possible and keeping the input lines short. Keeping the assembly
rigid and minimizing sources of vibration reduces triboelectric
and piezoelectric effects. All precision, high impedance circuitry
requires shielding against interference noise. Use low noise coaxial
or triaxial cables for remote connections to the input signal lines.
OFFSET NULLING
The AD549 input offset voltage can be nulled by using balance
Pin 1 and Pin 5, as shown in Figure 30. Nulling the input offset
voltage in this fashion introduces an added input offset voltage
drift component of 2.4 μV/°C per mV of nulled offset (a maxi-
mum additional drift of 0.6 μV/°C for the AD549K, 1.2 μV/°C
for the AD549L, and 2.4 μV/°C for the AD549J).
00511-030
2
3
6
5
1
7
4
AD549
+
V
OUT
–
–V
S
+
V
S
10kΩ
Figure 30. Standard Offset Null Circuit
The approach in Figure 31 can be used when the amplifier is
used as an inverter. This method introduces a small voltage
referenced to the power supplies in series with the positive
input terminal of the amplifier. The amplifier input offset
voltage drift with temperature is not affected. However,
variation of the power supply voltages causes offset shifts.
00511-031
2
3
6
AD549
+
V
OUT
–
V
I
+
–
R
F
R
I
200Ω
100kΩ
499kΩ499kΩ
0.1µF –V
S
+V
S
Figure 31. Alternate Offset Null Circuit for Inverter
Table 3. Insulating Materials and Characteristics
Material
Volume Resistivity
(V to CM)
Minimal
Triboelectric Effect1
Minimal
Piezoelectric Effect1
Resistance to
Water Absorption1
Teflon 1017 to 1018 W W G
Kel-F® 1017 to 1018 W M G
Sapphire 1016 to 1018 M G G
Polyethylene 1014 to 1018 M G M
Polystyrene 1012 to 1018 W M M
Ceramic 1012 to 1014 W M W
Glass Epoxy 1010 to 1017 W M W
PVC 1010 to 1015 G M G
Phenolic 105 to 1012 W G W
1 G: good with regard to property; M: moderate with regard to property; W: weak with regard to property.
AD549
Rev. H | Page 12 of 20
AC RESPONSE WITH HIGH VALUE SOURCE AND
FEEDBACK RESISTANCE
Source and feedback resistances greater than 100 kΩ magnify
the effect of the input capacitances (stray and inherent to
the AD549) on the ac behavior of the circuit. The effects of
common-mode and differential input capacitances should be
taken into account because the circuit bandwidth and stability
can be adversely affected.
0
0511-032
10mV 5µs
Figure 32. Follower Pulse Response from 1 MΩ Source Resistance,
Case Not Bootstrapped
0
0511-033
10mV 5µs
Figure 33. Follower Pulse Response from 1 MΩ Source Resistance,
Case Bootstrapped
In a follower, the source resistance and input common-mode
capacitance form a pole that limits the bandwidth to ½πRSCS.
Bootstrapping the metal case by connecting Pin 8 to the output
minimizes capacitance due to the package. Figure 32 and Figure 33
show the follower pulse response from a 1 MΩ source resistance
with and without the package connected to the output. Typical
common-mode input capacitance for the AD549 is 0.8 pF.
In an inverting configuration, the differential input capacitance
forms a pole in the loop transmission of the circuit. This can
create peaking in the ac response and possible instability. A
feedback capacitance can be used to stabilize the circuit. The
inverter pulse response with RF and RS equal to 1 MΩ appears
in Figure 34. Figure 35 shows the response of the same circuit
with a 1 pF feedback capacitance. Typical differential input
capacitance for the AD549 is 1 pF.
0
0511-034
10mV 5µs
Figure 34. Inverter Pulse Response with 1 MΩ Source
and Feedback Resistance
0
0511-035
10mV 5µs
Figure 35. Inverter Pulse Response with 1 MΩ Source
and Feedback Resistance, 1 pF Feedback Capacitance
COMMON-MODE INPUT VOLTAGE OVERLOAD
The rated common-mode input voltage range of the AD549 is
from 3 V less than the positive supply voltage to 5 V greater than
the negative supply voltage. Exceeding this range degrades the
CMRR of the amplifier. Driving the common-mode voltage above
the positive supply causes the amplifier output to saturate at the
upper limit of the output voltage. Recovery time is typically 2 μs
after the input has been returned to within the normal operating
range. Driving the input common-mode voltage within 1 V of the
negative supply causes phase reversal of the output signal. In this
case, normal operation typically resumes within 0.5 μs of the
input voltage returning within range.
AD549
Rev. H | Page 13 of 20
00511-038
3
2
6
AD549
SOURCE
R
PROTECT
DIFFERENTIAL INPUT VOLTAGE OVERLOAD
A plot of the AD549 input currents vs. differential input
voltage (defined as VIN+ − VIN−) appears in Figure 36. The
input current at either terminal stays below a few hundred
femtoamps until one input terminal is forced higher than 1 V
to 1.5 V above the other terminal. Under these conditions, the
input current limits at 30 μA. Figure 38. Follower with Input Current Limit
Figure 39 is a schematic of the AD549 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Use low leakage diodes,
such as the FD333s, and shield them from light to prevent photo-
currents from being generated. Even with these precautions, the
diodes measurably increase input current and capacitance.
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
100f
10f–5 –4 –3 –2 –1 0 1 2 3 4 5
00511-036
DIFFERENTIAL INPUT VOLT AGE (V) (VIN+ – VIN–)
INPUT CURRENT ( A)
IIN–I
IN+
0
0511-039
2
3
6
AD549
SOURCE
R
F
PROTECT
DIODES
Figure 39. Input Voltage Clamp with Diodes
SAMPLE-AND-DIFFERENCE CIRCUIT TO MEASURE
ELECTROMETER LEAKAGE CURRENTS
Figure 36. Input Current vs. Differential Input Voltage
INPUT PROTECTION There are a number of methods used to test electrometer leakage
currents, including current integration and direct I-to-V con-
version. Regardless of the method used, board and interconnect
cleanliness, proper choice of insulating materials (such as Teflon
or Kel-F), correct guarding and shielding techniques, and care
in physical layout are essential to making accurate leakage
measurements.
The AD549 safely handles any input voltage within the supply
voltage range. Subjecting the input terminals to voltages beyond
the power supply can destroy the device or cause shifts in input
current or offset voltage if the amplifier is not protected.
A protection scheme for the amplifier as an inverter is shown
in Figure 37. RP is chosen to limit the current through the
inverting input to 1 mA for expected transient (less than 1 sec)
overvoltage conditions, or to 100 μA for a continuous overload.
Because RP is inside the feedback loop and is much lower in
value than the amplifier input resistance, it does not affect the
dc gain of the inverter. However, the Johnson noise of the
resistor adds root sum of squares to the amplifier input noise.
Figure 40 is a schematic of the sample-and-difference circuit. It
uses two AD549 electrometer amplifiers (A and B) as I-to-V
converters with high value (1010 Ω) sense resistors (RSa and
RSb). R1 and R2 provide for an overall circuit sensitivity of
10 fA/mV (10 pA full scale). CC and CF provide noise suppression
and loop compensation. CC should be a low leakage polystyrene
capacitor. An ultralow leakage Kel-F test socket is used for con-
tacting the device under test. Rigid Teflon coaxial cable is used
to make connections to all high impedance nodes. The use of
rigid coaxial cable affords immunity to error induced by mechan-
ical vibration and provides an outer conductor for shielding. The
entire circuit is enclosed in a grounded metal box.
00511-037
2
3
6
AD549
C
F
SOURCE
R
PROTECT
R
F
Figure 37. Inverter with Input Current Limit
In the corresponding version of this scheme for a follower,
shown in Figure 38, RP and the capacitance at the positive input
terminal produce a pole in the signal frequency response at a
f = ½πRC. Again, the Johnson noise, RP, adds to the input
voltage noise of the amplifier.
AD549
Rev. H | Page 14 of 20
The test apparatus is calibrated without a device under test
present. After power is turned on, a 5 minute stabilization
period is required. First, VERR1 and VERR2 are measured. These
voltages are the errors caused by the offset voltages and leakage
currents of the I-to-V converters.
VERR1 = 10 (VOSA – IBA × RSa)
VERR2 = 10 (VOSB – IBB × RSb)
00511-040
V
OS
+
–
2
3
6
8
A
AD549
R2
9.01kΩ
R1
1kΩ
RSa
10
10
Ω
+
V
ERR1
/V
A
V
ERR2
/V
B
V
OUT
–
CAL/TEST
C
C
20pF C
F
0.1µF
+
–
3
2
6
8
B
AD549
R2
9.01kΩ
R1
1kΩ
RSb
10
10
Ω
C
C
20pF C
F
0.1µF
C
F
0.1µF
R1
1kΩ
R2
9.01kΩ
DEVICE
UNDER
TEST
I (+)
I (–)
GUARD
Figure 40. Sample and Difference Circuit for Measuring
Electrometer Leakage Currents
Once measured, these errors are subtracted from the readings
taken with a device under test present. Amplifier B closes the
feedback loop to the device under testing in addition to pro-
viding the I-to-V conversion. The offset error of the device
under testing appears as a common-mode signal and does not
affect the test measurement. As a result, only the leakage
current of the device under testing is measured.
VA – VERR1 = 10[RSa × IB(+)]
VX – VERR2 = 10[RSb × IB(–)]
Although a series of devices can be tested after only one calibra-
tion measurement, calibration should be updated periodically
to compensate for any thermal drift of the I-to-V converters or
changes in the ambient environment. Laboratory results have
shown that repeatable measurements within 10 fA can be realized
when this apparatus is properly implemented. These results are
achieved in part by the design of the circuit, which eliminates
relays and other parasitic leakage paths in the high impedance
signal lines, and in part by the inherent cancellation of errors
through the calibration and measurement procedure.
PHOTODIODE INTERFACE
The low input current and low input offset voltage of the AD549
make it an excellent choice for very sensitive photodiode preamps
(see Figure 41). The photodiode develops a signal current, IS,
equal to
IS = R × P
where P is light power incident on the diode surface, in watts,
and R is the photodiode responsivity in amps/watt. RF converts
the signal current to an output voltage
VOUT = RF × IS
00511-041
2
3
6
5
1
4
AD549
–V
S
C
F
10pF
I
S
R
F
10
9
Ω
10kΩ
1µF V
OU
T
+
–
Figure 41. Photodiode Preamp
The dc error sources and an equivalent circuit for a small area
(0.2 mm square) photodiode are indicated in Figure 42.
00511-042
A
+
V
OUT
–
V
OS
+–
I
S
–I
S
R
S
10
9
Ω
C
S
20pF
R
F
10
9
Ω
C
F
10pF
Figure 42. Photodiode Preamp DC Error Sources
AD549
Rev. H | Page 15 of 20
gain that multiplies the op amp input voltage noise contribu-
tion. A single-pole filter at the output of the amplifier limits the
op amp output voltage noise bandwidth to 26 Hz, comparable
to the signal bandwidth. This greatly improves the signal-to-
noise ratio of the preamplifier (in this case, by a factor of 3).
Input current, IB, contributes an output voltage error, VE1,
proportional to the feedback resistance
VE1 = IB × RF
The input voltage offset of the op amp causes an error current
through the photodiode shunt resistance, RS
10µ
1µ
100n
10n 1 10 100 1k 10k 100k 1M
00511-044
FREQUENCY (Hz )
VOL TAG E NO I SE CO NTRIBUTIO NS
NOISE SPECTRAL DENSITY (nV/ Hz)
IF AND CS, NO F ILTERS
IF AND CS, WITH FILTERS
EN
CONTRIBUTION,
WITH FILTER
EN CONT RIBUTIO N,
NO FI LTER
AD549
OPEN-LOOP GAIN
I = VOS/RS
The error current results in an error voltage (VE2) at the
amplifier output equal to
VE2 = (1 + RF/RS)VOS
Given typical values of photodiode shunt resistance (on the order
of 109 Ω), RF/RS can easily be greater than 1, especially if a large
feedback resistance is used. Also, RF/RS increases with tempera-
ture because photodiode shunt resistance typically drops by a
factor of 2 for every 10°C rise in temperature. An op amp with
low offset voltage and low drift must be used to maintain accuracy.
The AD549K offers a guaranteed maximum 0.25 mV offset
voltage and 5 mV/°C drift for very sensitive applications.
Figure 44. Spectral Density of the Photodiode Preamp Noise
Sources vs. Frequency
Photodiode Preamp Noise
Noise limits the signal resolution obtainable with the preamp.
The output voltage noise divided by the feedback resistance is
the minimum current signal that can be detected. This mini-
mum detectable current divided by the responsivity of the
photodiode represents the lowest light power that is detectable
by the preamp.
LOG RATIO AMPLIFIER
Logarithmic ratio circuits are useful for processing signals with
wide dynamic range. The 60 fA maximum input current of the
AD549L makes it possible to build a log ratio amplifier with
1% log conformance for input currents ranging from 10 pA to
1 mA, a dynamic range of 160 dB.
Noise sources associated with the photodiode, amplifier, and
feedback resistance are shown in Figure 43; Figure 44 is the
spectral density vs. frequency plot of the contribution of each of
the noise sources to the output voltage noise (circuit parameters
in Figure 42 are assumed). The rms contribution of each noise
source to the total output voltage noise is obtained by
integrating the square of its spectral density function over
frequency. The rms value of the output voltage noise is the
square root of the sum of all contributions. Minimizing the total
area under these curves optimizes the resolution of the
preamplifier for a given bandwidth.
The log ratio amplifier in Figure 45 provides an output voltage
proportional to the log base 10 of the ratio of Input Current I1
and Input Current I2. Resistor R1 and Resistor R2 are provided
for voltage inputs. Because NPN devices are used in the feedback
loop of the front-end amplifiers that provide the log transfer
function, the output is valid only for positive input voltages and
input currents. The input currents set the Collector Current IC1
and Collector Current IC2 of a matched pair of log transistors,
Q1 and Q2, to develop Voltage VA and Voltage VB
VA, VB = –(kT/q)ln IC/IES
00511-043
A
I
S
R
S
C
S
C
F
R
F
IF
EN
IN
where IES is the saturation current of the transistor.
The difference of VA and VB is taken by the subtractor section to
obtain
VC = (kT/q)ln(IC2/IC1)
VC is scaled up by the ratio of (R9 + R10)/R8, which is equal to
approximately 16 at room temperature, resulting in the output
voltage
Figure 43. Photodiode Preamp Noise Sources
VOUT = 1 V × log(IC2/IC1)
The photodiode preamp in Figure 41 can detect a signal current
of 26 fA rms at a bandwidth of 16 Hz, which, assuming a
photodiode responsivity of 0.5 A/W, translates to a 52 fW rms
minimum detectable power. The photodiode used has a high
source resistance and low junction capacitance. CF sets the
signal bandwidth with RF and also limits the peak in the noise
R8 is a resistor with a positive 3500 ppm/°C temperature coeffi-
cient to provide the necessary temperature compensation. The
parallel combination of R15 and R7 is provided to keep the gain
of the subtractor section for positive and negative inputs matched
over temperature.
AD549
Rev. H | Page 16 of 20
Frequency compensation is provided by R11, R12, C1, and C2.
The bandwidth of the circuit is 300 kHz at input signals greater
than 50 μA; bandwidth decreases smoothly with decreasing
signal levels.
To trim the circuit, set the input currents to 10 μA and trim the
A3 offset using the trim potentiometer of the amplifier for the
output to equal 0. Next, set I1 to 1 μA and adjust the output to
equal 1 V by trimming R10. Additional offset trims on Ampli-
fier A1 and Amplifier A2 can be used to increase the voltage
input accuracy and dynamic range.
The very low input current of the AD549 makes this circuit
useful over a very wide range of signal currents. The total input
current (which determines the low level accuracy of the circuit)
is the sum of the amplifier input current, the leakage across the
compensating capacitor (negligible if a polystyrene or Teflon
capacitor is used), and the collector-to-collector and collector-
to-base leakages of one side of the dual log transistors. The
magnitudes of these last two leakages depend on the amplifier
input offset voltage and are typically less than 10 fA with 1 mV
offsets. The low level accuracy is limited primarily by the
amplifier input current, only 60 fA maximum when the
AD549L is used.
The effects of the emitter resistance of Q1 and Q2 can degrade
circuit accuracy at input currents above 100 μA. The networks
composed of R13, D1, R16, R14, D2, and R17 compensate for
these errors, so that this circuit has less than a 1% log confor-
mance error at 1 mA input currents. The correct value for R13
and R14 depends on the type of log transistors used. The 49.9 kΩ
resistors were chosen for use with LM394 transistors. Smaller
resistance values are needed for smaller log transistors.
TEMPERATURE COMPENSATED pH PROBE
AMPLIFIER
A pH probe can be modeled as an mV-level voltage source
with a series source resistance dependent on the electrode
composition and configuration. The glass bulb resistance of a
typical pH electrode pair falls between 106 Ω and 109 Ω. It is
therefore important to select an amplifier with low enough
input currents such that the voltage drop produced by the
amplifier input bias current and the electrode resistance does
not become an appreciable percentage of a pH unit.
The circuit in Figure 46 illustrates the use of the AD549 as a pH
probe amplifier. As with other electrometer applications, the use of
guarding, shielding, and Teflon standoffs is necessary to capitalize
on the AD549 low input current. If an AD549L (60 fA maximum
input current) is used, the error contributed by the input current is
held below 60 μV for pH electrode source impedances up to 109 Ω.
Input offset voltages (which can be trimmed) are below 0.5 mV.
00511-045
3
2
6
5
1
4
A3
AD549
R10
2kΩ
10kΩ
OUTPUT
OFFSET
SCALE
FACTOR
ADJ
V
OUT
R9
14.3kΩ
R8
1kΩ
*
*
R4
20kΩ
4.99kΩ
R6
20kΩ
R7
15kΩ
R15
1kΩ
R5
20kΩ
R3
20kΩ
0.1µF
0.1µF
+V
S
FOR EACH AMPLIFIE
R
PIN 7
PIN 4 –V
S
2
3
6
5
1
4
A2
AD549
V
2
OFFSET
10kΩ
D4
I
2
IN
V
2
IN C2
100pF
R2
10kΩQ2 B
D2
D1
I
1
IN
2
6
5
1
4
A1
AD549
V
1
OFFSET
10kΩ
D3
3
V
1
IN
R1
10kΩQ1 A
C1
100pF
R11
4.99kΩ
R14
49.9kΩ
R16
10Ω
R17
10ΩR13
49.9kΩ
Q1, Q2 = LM394
DUAL L O G T RANS IST ORS
D1, D4 1N4148 DIOD ES
R8, R15 1k Ω + 350 ppm/° C TC RESISTOR
*
TELLAB QB1 OR PRECISION RESISTOR PT146
ALL OTHE R RE S IST ORS ARE 1% M E TAL FI L M
V
OUT
= 1V × LOG
10
V
2
V
1
V
OUT
= 1V × LOG
10
I
2
I
1
Figure 45. Log Ratio Amplifier
AD549
Rev. H | Page 17 of 20
The pH probe output is ideally 0 V at a pH of 7, independent
of temperature. The slope of the transfer function of the probe,
though predictable, is temperature dependent (−54.2 mV/pH at
0°C and −74.04 mV/pH at 100°C). By using an AD590 tempera-
ture sensor and an AD534 analog divider, an accurate temperature
compensation network can be added to the basic pH probe ampli-
fier. Table 4 shows voltages at various points, thereby illustrating
the compensation. The AD549 is set for a noninverting gain of
13.51. The output of the AD590 circuitry (Point C) is equal to
10 V at 100°C and decreases by 26.8 mV/°C. The output of the
AD534 analog divider (Point D) is a temperature-compensated
output voltage centered at 0 V for a pH of 7 and has a transfer
function of –1.00 V/pH unit. The output range spans from
−7.00 V (pH = 14) to +7.00 V (pH = 0).
00511-046
8
14
10
Z
212
OUT
7
Y
2
6
Y
1
11
Z
1
1
X
1
2
X
2
AD534
0.1µF
+15
V
0.1µF
–15V
OUTPUT
(D)
(B)
(C)
26.6kΩ
+
–
AD590
IN STAINLESS
STEEL PROBE
OR AC2626
+15V
3
2
6
4
8
7
AD549
0.1µF
0.1µF
pH
PROBE
OUTPUT
(A)
1kΩ
12kΩ
1kΩ
SCALE FACTOR
ADJUST
Figure 46. Temperature Compensated pH Amplifier
Table 4. Illustration of Temperature Compensation
Point
Probe Temperature (°C) A (Probe Output) (mV) B (A × 13.51) (V) C (AD590 Output) (V) D (10 × (B ÷ C)) (V)
0 54.20 0.732 7.32 1.00
25 59.16 0.799 7.99 1.00
37 61.54 0.831 8.31 1.00
60 66.10 0.893 8.93 1.00
100 74.04 1.000 10.00 1.00
AD549
Rev. H | Page 18 of 20
OUTLINE DIMENSIONS
CONT ROLLING DI M E NSIONS ARE I N INCHES; M IL L IMETER DIMENS IONS
(IN PARENTHESE S) ARE ROUNDE D-OF F INCH E QUI VALENTS FOR
REFE RE NCE ONLY AND ARE NO T AP PROPRIAT E FO R US E IN DESIGN.
COMP LIANT TO JEDEC STANDARDS MO-002- AK
0.2500 (6.35) MIN
0.5000 ( 1 2.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFE RE NCE P LANE
0.0500 (1.27) MAX
0.0190 ( 0.48)
0.0160 ( 0.41)
0.0210 ( 0. 53 )
0.0160 ( 0. 41 )
0.0400 ( 1. 02 )
0.0100 ( 0. 25 )
0.0400 ( 1.02) M A X 0.0340 ( 0.86)
0.0280 ( 0.71)
0.0450 ( 1.14)
0.0270 ( 0.69)
0.1600 ( 4.06)
0.1400 ( 3.56)
0.1000 (2.54)
BSC
6
28
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
0.3700 ( 9. 40 )
0.3350 ( 8. 51 )
0.3350 (8.51)
0.3050 (7.75)
45° BSC
BASE & SEATING PLANE
022306-A
Figure 47. 8-Lead Metal Can [TO-99]
(H-08)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD549JH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549JHZ1
0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549KH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549KHZ1
0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549LH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549LHZ1
0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549SH/883B −55°C to +125°C 8-Lead Metal Can (TO-99) H-08
1 Z = RoHS Compliant Part.
AD549
Rev. H | Page 19 of 20
NOTES
AD549
Rev. H | Page 20 of 20
NOTES
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00511-0-3/08(H)
