HEF4541B MSs! PROGRAMMABLE TIMER The HEF4541B is a programmable timer which consists of a 16-stage binary counter, an integrated oscillator to be used with external timing components, an automatic power-on reset and output control logic. The frequency of the oscillator is determined by the external components Ry and C; within the frequency range 1 Hz to 100 kHz. This oscillator may be replaced by an external clock signal at input RS, the timer advances on the positive-going transition of RS. A LOW on the auto reset input (AR) and a LOW on the master reset input (MR) enables the internal power-on reset. A HIGH level at input MR resets the counter independent on all other inputs. Resetting disables the oscillator to provide no active power dissipation. A HIGH at input AR turns off the power-on reset to provide a low quiescent power dissipation of the timer. The 16-stage counter divides the oscillator frequency by 2, 2', 2'? or 2' depending on the state of the address inputs (Ag, A). The divided oscillator frequency is available at output O. The phase input (PH) features a complementary output signal. If the mode select input (MODE) is LOW or HIGH the timer can be used respectively as a single transition timer or 2 frequency divider. [3 \2 {1 12 {13 [10 RS [ere [rre Ag |A1 |MODE C control inputs 2a POWER-ON BINARY STAGE. oF Cp COUNTER 6]MR RESET 9] PH 7283068.2 14] fis] fiz} [11] fro} [9] [3] Vop Ay, Ag _ a.c. MODE PH O Fig. 1 Functional diagram. = HEF4541B HEF4541BP : 14-lead DIL; plastic (SOT-27). R c R c. AR MR V HEF4541BD: 14-lead DIL; ceramic (cerdip) (SOT-73). To Tc_ RS nec SS HEF4541BT : 14-lead mini-pack; plastic Li} L2} 13} 4) Ls} ie} 12 (SO-14; SOT-10BA). 7Z83067.1 Fig. 2 Pinning diagram. FAMILY DATA see Family Specifications Ipp LIMITS category MS! S Products approved to CECC 90 104-082. | (ey 1983 619620 HEF 4541B Msi pe" rs >o pe be CP 28 cOUNTER 28 RESET Ly 8 cp 2 COUNTER RESET 22 25 28 Po rty aS > POWER-ON AR Oo RESET PINNING Ag, Ay MODE AR MR PH RTC Ctc RS MUX MODE address inputs PH | >o | >o Jo > oO mode select input auto reset input 7283070.2 master reset input phase input Fig. 3 Logic diagram. external resistor connection (R;) external capacitor connection (C;) external resistor connection (Rg) or external clock input October 1900 ) 4Programmable timer HEF 4541B MsI FREQUENCY SELECTION TABLE number of f Ag | Aj | counter stages | _OS = an n fout L L 13 8 192 LIH 10 1024 HL 8 256 H | H 16 65 536 FUNCTION TABLE inputs = mode AR |MR]| PH MODE H L x Xx auto reset disabled L L x x auto reset enabled X H x 4 master reset active 4 L x H normal operation selected division to output xX TL x L single-cycle mode* X ITL L x output initially LOW, after reset xX 7L H x output initially HIGH, after reset H = HIGH state (the more positive voltage) L = LOW state (the !ess positive voltage) X = state is immaterial * The timer is initialized on a reset pulse and the output changes state after 2.-' counts and remains in that state (latched). Reset of this latch is obtained by master reset or by a LOW to HIGH transition on the MODE input. > (cctbe 1980 621HEF 4541B Mst RC oscillator reset clock to from logic counter a Rte Typical formula for oscillator frequency: c2 Rt 1 = ose 2,3 x Rt x Cy 7, 7283069.2 Fig. 4 External component connection for RC oscillator; Rg ~ 2R. Timing component limitations The oscillator frequency is mainly determined by RyC, provided Ry << Rg and RgC2 << R,yCy. The function of Rg is to minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance C2 should be kept as small as possible. In consideration of accuracy, C, must be larger than the inherent stray capacitance. Ry must be larger than the LOCMOS ON resistance in series with it, which typically is 500 Q at Vpp = 5 V, 300 2 at Vopp = 10 V and 200 Q at Vpp = 15 V. The recommended values for these components to maintain agreement with the typical oscillation formula are: C;, 2 100 pF, up to any typical value, 10 k2 < Rp <1 MQ. 622 October 10Programmable timer HEF 4541B MS! 7Z82715 105 osc (Hz) 104 103 102 10 103 104 , 105 oR, (2): 108 10-4 10-3 10-2 Cy (uF) 61071 Fig. 5 RC oscillator frequency as a function of Ry and C; at Vpp = 5 to 15 V; Tamp = 25 OC. Cy curve at Ry = 56 kQ; Rg = 120 kQ. Ry curve at Cy = 1 nF; Rg = 2Ry. | (ccs 1980 623HEF4541B MSI 10 7Z82714 At Vop= (%) ov 5 0 5 10 75 50 25 0 25 50 75 100 125 150 Tamb (C) Fig. 6 Frequency deviation (Af) as a function of ambient temperature; referenced at : fose at Tamb = 25 C and Vop = 10V. Ry = 96 k&Q2; Cy = 1 nF; Rg = 0. Ry = 56k; Cy = 1 nF; Rg = 120 kQ. 624 October 10 ) (Programmable timer HEF 4541B MSI D.C. CHARACTERISTICS Vss =OV Tamb (C) Vpp | Yot | YOu Vv Vv V [symbol] 40 +25 +85 min. max. min. typ. max. min. max. Supply current 5 - 800 20 80 230 pA power-on reset 10 Ip - 750 _ 250 600 700 pA enabled (note) 15 1600, 500 1300 1500 vA Supply voltage for automatic reset Vpp - - 85 5 - _ Vv initialization (note) Output current 5 4,6 0,5 - 0,4 = - 03 - mA HIGH; Crc, Rec] 10 9,5 |-lton | 1,4 _ 1,2 _ - 095 - mA 15 13,5 48 - 40 - - 3,2 - mA 5 2,5 !IlOH | 1,4 _ 1,2 _ - O95 - mA Output current 5 0,4 0,33 - 0,27 _ 0,20 - mA LOW; Crc, RTc | 10 0,5 lok 1,00 - 0,85 _ 0,68 - mA 15 1,5 3,20 - 2,70 - - 230 - mA Note All inputs at 0 V or Vpp, except input AR = input MR = 0 V (power-on reset active). A.C, CHARACTERISTICS Vss = 0 V; Tamb = 25 C; input transition times < 20 ns Yop typical formula for P (uW)* Dynamic power dissipation 5 1300 f + foCLVDD per package 10 5 300 f+ feCLVpp (P) 15 12000 f + foCLVpp? Total power dissipation 5 1300 foge + foCL VDD? + 2CtV pp fose + 19 Vop when using the 10 5 300 fogo + foCL VDD + 2CEV OD? fose + 100 Vop on-chip oscillator (P} 15 12 000 foge + fo $LVDD? + 2CeV DD fose + 400 Vop * where: f; = input frequency (MHz) fg = output frequency (MHz) Ci = load capacitance (pF) Vpp= supply voltage (V) C, = timing capacitance (pF) fose = oscillator frequency (MHz) ( October 1980 625HEF4541B MSI A.C. CHARACTERISTICS Vss = 9 V; Tamb = 25 C; C, = 50 pF; input transition times < 20 ns Vppb . typical extrapolation Y symbol | min. typ. max. formula Propagation delays RS 0 8 eee ow 5 375 750 ns. | 348 ns + (0,55 ns/pF) Cy Low t oHIGH 10 | TPHL: 150 300 ns__| 139 ns + (0,23 ns/pF) Cy 15 | tPLH 110. 220 ns_| 102 ns + (0,16 ns/pF) CL. RS 0 10 eee ow 5 425 850 ns_| 398 ns + (0,56 ns/pF) Cy Lowt HIGH 10. | PHL: 165 330 ns_ | 154 ns + (0,23 ns/pF) Cy. 15 | 'PLH 120. 240 ns__| 112 ns + (0,16 ns/pF) CL. RS 0 13 ce 2 Selected 5 510 1020 ns_ | 483 ns + (0,55 ns/pF) C HIGH to LOW tPHL: LOW to HIGH 10 190 380 ns__| 179 ns + (0,23 ns/pF) Cy. 15 | *PLH 135-270 ns__| 127 ns + (0,16 ns/pF) Cy. RS *0O 16 2 Hone Low 5 |i. 575 1150 ns | 548 ns + (0,55 ns/pF) C;. LOwt HIGH 10 Pht: 210 420 ns_-| 199 ns + (0,23 ns/pF) CL. 15 | *PLH 150 300 ns_ | 142 ns + (0,16 ns/pF) Cy Minimum clock 5 60 30 ns pulse width; LOW 10 |twrsc | 30 15 ns 15 24 12 ns Minimum reset 5 60 30 ns pulse width; HIGH 10 | twmrRH | 30 15 ns 15 24 12 ns Maximum clock 5 8 16 MHz pulse frequency 10 Tmax 15 30 MHz 15 18 36 MHz Oscillator frequency 5 90 kHz | Ry = 5kQ 10 | fose 90 kHz Cy = 1nF 15 90 kHz | | Rs = 10k Oscillator frequency 5 8 kHz | Ry 56 kQ 10 | fose 8 kHz Cy = 1nF 15 8 kHz | Rg = 120 kQ 626 October 20 (