DK-VIDEO-4SGX230N - Altera Corporation

101 Innovation Drive

San Jose, CA 95134

www.altera.com

UG-01066-2.0

Audio Video Development Kit, Stratix IV GX Edition

User Guide

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks

and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the

U.S. and other countries. All other product or service names are the property of their respective holders. Altera

products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and

copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance

with Altera's standard warranty, but reserves the right to make changes to any products and services at any time

without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

Contents

Chapter 1. About This Kit

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Chapter 2. Getting Started

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Inspect the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Chapter 3. Software Installation

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Altera Complete Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Audio Video Development Kit, Stratix IV GX Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Installing the USB-Blaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Chapter 4. Development Board Setup

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Factory Default Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Chapter 5. Board Update Portal

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Using the Board Update Portal to Update User Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Chapter 6. Board Test System

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Preparing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

The Config Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

MAX II Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

The SRAM&Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Number of Addresses to Write andRead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

The QDRII+ Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

The HSMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

The Video Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

The SDI HSMC - PRBS Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

AES in1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

AES in2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

SDI in1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

SDI in2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

The SDI HSMC - Video Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

Receiver Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22

The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23

Temperature Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

12V Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Graph Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25

The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25

Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

fXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

Disable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

Target Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

Reset Si570 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27

Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27

Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27

Appendix A. Programming the Flash Memory Device

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Preparing Design Files for Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Creating Flash Files Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Programming Flash Memory Using the Board Update Portal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Restoring the Flash Device to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

Restoring the MAX II CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

1. About This Kit

Introduction

The Altera® Audio Video Development Kit, Stratix® IV GX Edition is a complete

design environment that includes both the hardware and software you need to

develop Stratix IV GX FPGA designs. The PCI-SIG-compliant board, the serial digital

interface (SDI) high-speed mezzanine card (HSMC), and the one-year license for the

Quartus® II software provide everything you need to begin developing custom Stratix

IV GX FPGA designs. The following list describes what you can accomplish with the

development kit:

■Develop and test PCI Express 2.0 designs

■Develop and test memory subsystems consisting of DDR3 and QDR II+ memories

■Build designs capable of migrating to Altera’s low-cost HardCopy® IV ASICs

■Develop and test SDI and Audio Engineering Society (AES) designs using the SDI

HSMC in conjunction with the host development platform

■Take advantage of the modular and scalable design by using the second HSMC

connector to interface to over 20 different HSMCs provided by Altera partners,

supporting protocols such as Serial RapidIO®, 10 Gigabit Ethernet, SONET,

Common Public Radio Interface (CPRI), Open Base Station Architecture Initiative

(OBSAI) and others

Kit Features

This section briefly describes the Audio Video Development Kit, Stratix IV GX Edition

contents.

Hardware

■Stratix IV GX FPGA development board—A development platform that allows

you to develop and prototype hardware designs running on the Stratix IV GX

EP4SGX230 FPGA.

■For detailed information about the board components and interfaces, refer to the

Stratix IV GX FPGA Development Board Reference Manual.

■SDI HSMC - A daughtercard that features two SDI channels, two AES channels,

and clocking options to enable the development and testing of SDI and AES

designs.

fFor detailed information about the SDI HSMC components and interfaces,

refer to the SDI HSMC Reference Manual.

1–2 Chapter 1: About This Kit

Kit Features

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

■Power supply and cables—The development kit includes the following items:

■Power supply and AC adapters for North America/Japan, Europe, and the

United Kingdom

■USB cable

■Ethernet cable

■SMB cable

■BNC cable

Software

■Altera Complete Design Suite DVD—A DVD that includes the following items:

■Quartus II Software—The Quartus II software, including the SOPC Builder

system development tool, provides a comprehensive environment for

system-on-a-programmable-chip (SOPC) design. The Quartus II software

integrates into nearly any design environment and provides interfaces to

industry-standard EDA tools.

fThe kit includes a development kit edition (DKE) license for the Quartus II

software (Windows platform only). This license entitles you to all the

features of the subscription edition for a period of one year. After the year,

you must purchase a renewal subscription to continue using the software.

For more information, refer to the Altera website (www.altera.com).

■MegaCore® IP Library—A library that contains Altera IP MegaCore functions.

You can evaluate MegaCore functions by using the OpenCore Plus feature to

do the following:

■Simulate behavior of a MegaCore function within your system

■Verify functionality of your design, and quickly and easily evaluate its size

and speed

■Generate time-limited device programming files for designs that include

MegaCore functions

■Program a device and verify your design in hardware

1The OpenCore Plus hardware evaluation feature is an evaluation tool for

prototyping only. You must purchase a license to use a MegaCore function

in production.

fFor more information about OpenCore Plus, refer to AN 320: OpenCore

Plus Evaluation of Megafunctions.

■Nios® II Embedded Design Suite (EDS)—A full-featured set of tools that allow

you to develop embedded software for the Nios II processor which you can

include in your Altera FPGA designs.

■Audio Video Development Kit, Stratix IV GX Edition CD-ROM—A CD-ROM that

includes all the documentation and design examples for the kit.

Chapter 1: About This Kit 1–3

Kit Features

fUse the following links to check the Altera website to ensure you have the latest

software versions:

■For the Altera Complete Design Suite, refer to the Quartus II Subscription Edition

Download page.

■For the Audio Video Development Kit, Stratix IV GX Edition, refer to the Audio

Video Development Kit, Stratix IV GX Edition page.

1–4 Chapter 1: About This Kit

Kit Features

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

2. Getting Started

Introduction

This user guide leads you through the following Stratix IV GX FPGA development

board with SDI HSMC daughtercard setup steps:

■Inspecting the contents of the kit

■Installing the Altera Complete Design Suite DVD software

■Setting up, powering up, and verifying correct operation of the development

board

■Configuring the Stratix IV GX FPGA

■Running the Board Test System designs

fFor complete information about the development board, refer to the Stratix IV GX

FPGA Development Board Reference Manual.

Before You Begin

Before using the kit or installing the software, check the kit contents and inspect the

boards to verify that you received all of the items listed in this section. If any of the

items are missing, contact Altera before you proceed.

Inspect the Boards

To inspect each board, perform the following steps:

1. Place the board on an anti-static surface and inspect it to ensure that it has not been

damaged during shipment.

cWithout proper anti-static handling, you can damage the board.

2. Verify that all components are on the board and appear intact.

1In typical applications with the Stratix IV GX FPGA development board, a heat sink is

not necessary. However, under extreme conditions or for engineering sample silicon

the board might require additional cooling to stay within operating temperature

guidelines. You can perform power consumption and thermal modeling to determine

whether your application requires additional cooling.

fFor more information about power consumption and thermal modeling, refer to

AN 358: Thermal Management for FPGAs.

References

Use the following links to check the Altera website for the following other related

information:

2–2 Chapter 2: Getting Started

References

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

■For the latest board design files and reference designs, refer to the Audio Video

Development Kit, Stratix IV GX Edition page.

■For additional daughter cards available for purchase, refer to the Development

Board Daughtercards page.

■For the Stratix IV GX device documentation, refer to the Literature: Stratix IV

Devices page.

■To purchase devices from the eStore, refer to the Devices page.

■For Stratix IV GX OrCAD symbols, refer to the Capture CIS Symbols page.

■For Nios II 32-bit embedded processor solutions, refer to the Embedded

Processing page.

3. Software Installation

Introduction

This section explains how to install the following software:

■Altera Complete Design Suite

■Audio Video Development Kit, Stratix IV GX Edition

■USB-Blaster™ driver

Installing the Altera Complete Design Suite

The Altera Complete Design Suite provides the necessary tools used for developing

hardware and software for Altera FPGAs. Included on the Altera Complete Design

Suite DVD are the Quartus II software and the Nios II EDS. The Quartus II software

(including SOPC Builder) and the Nios II EDS are the primary FPGA development

tools used to create the reference designs in this development kit. To install the Altera

software tools, perform the following steps:

1. Insert the Altera Complete Design Suite DVD into your computer.

2. Follow the installer instructions to complete the installation process.

fIf you have difficulty installing the Quartus II software, refer to Quartus II Installation

& Licensing for Windows and Linux Workstations.

Licensing Considerations

Before using the Quartus II software, you must request a license file from the Altera

Licensing page of the Altera website and install it on your computer. When you

request a license file, Altera emails you a license.dat file that enables the software.

To license the Quartus II software, you need your computer’s network interface card

(NIC) ID, a number that uniquely identifies your computer. On the computer you use

to run the Quartus II software, type ipconfig /all at a command prompt to

determine the NIC ID. Your NIC ID is the 12-digit hexadecimal number on the

Physical Address line.

To obtain a license, perform the following steps.

1. Go to the Get My Altera License page of the Altera website.

2. Under Development Kit Licenses Request, click Licenses for RoHS-Compliant

Kits.

3. Follow the on-screen instructions to request your license. Altera sends you a

license file through email.

4. To install your license, refer to Specifying the License File in Quartus II Installation &

Licensing for Windows and Linux Workstations.

3–2 Chapter 3: Software Installation

Installing the Audio Video Development Kit, Stratix IV GX Edition

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

Installing the Audio Video Development Kit, Stratix IV GX Edition

To install the Audio Video Development Kit, Stratix IV GX Edition, perform the

following steps:

1. Insert the Audio Video Development Kit, Stratix IV GX Edition CD-ROM into

your computer.

1The CD-ROM should start an auto-install process. If it does not, browse to

the CD-ROM drive and double-click on the setup.exe file.

2. Follow the on-screen instructions to complete the installation process.

The installation program creates the directory structure for the Audio Video

Development Kit, Stratix IV GX Edition files shown in Figure 3–1.

Table 3–1 lists the file directory names and a description of their contents.

Installing the USB-Blaster Driver

The Stratix IV GX FPGA development board includes integrated USB-Blaster circuitry

for FPGA programming. However, for the host computer and board to communicate,

you must install the USB-Blaster driver on the host computer.

Figure 3–1. Audio Video Development Kit, Stratix IV GX Edition Installed Directory Structure (1)

Note to Figure 3–1:

(1) Early-release (engineering silicon) versions might have slightly different directory names.

documents

board_design_files

The default Windows installation directory is C:\altera\

examples

factory_recovery

demos

kits

stratixIVGX_4sgx230_av

Table 3–1. Installed Directory Contents

Directory Name Description of Contents

board_design_files Contains schematic, layout, assembly, and bill of material board design files. Use these files as a

starting point for a new prototype board design.

demos Contains demonstration applications.

documents Contains the development kit documentation.

examples Contains the sample design files for the Audio Video Development Kit, Stratix IV GX Edition.

factory_recovery Contains the original data programmed onto the board before shipment. Use this data to restore

the board with its original factory contents.

Chapter 3: Software Installation 3–3

Installing the USB-Blaster Driver

fInstallation instructions for the USB-Blaster driver for your operating system are

available on the Altera website. On the Altera Programming Cable Driver Information

page of the Altera website, locate the table entry for your configuration and click the

link to access the instructions.

3–4 Chapter 3: Software Installation

Installing the USB-Blaster Driver

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

4. Development Board Setup

Introduction

The instructions in this chapter explain how to set up the Stratix IV GX FPGA

development board.

Setting Up the Board

To set up and power up the board, perform the following steps:

1. The Stratix IV GX FPGA development board ships with its board switches

preconfigured to support the example designs in the development kit. If you

suspect your board might not be currently configured with the default settings,

follow the instructions in “Factory Default Switch Settings” on page 4–2 to return

the board to its factory settings before proceeding.

2. The development board ships with example designs stored in the flash memory

device. Verify the rotary switch (SW2) is set to the 0 position to load the design

stored in the factory portion of flash memory. Figure 4–1 shows the rotary switch

location on the Stratix IV GX FPGA development board.

3. Connect the SDI HSMC to the host board by performing the following steps:

a. Attach two standoffs at the corners of the SDI HSMC opposite the HSMC

connector. Place the standoffs under the board and hand-fasten screws from

the top through the holes adjacent to the AES audio BNC connectors J15 and J3.

b. Connect the J19 connector on the SDI HSMC to the J1 connector on the host

board. The host connector is labeled HSMC Port A and is the left connector on

the host board.

c. For added stability, optionally screw the two boards together using standoffs

and the mounting holes common to both boards.

d. Connect two SMA cables of equal length from J17 and J18 on the SDI HSMC to

J14 and J15 on the host board. This connection supplies the SDI HSMC

reference clock to the host board.

fFor information about the SDI HSMC, refer to the SDI HSMC Reference

Manual.

4. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J4) on the FPGA

board and plug the cord into a power outlet.

cUse only the supplied power supply. Power regulation circuitry on the

board can be damaged by power supplies with greater voltage.

5. Set the POWER switch (SW1) to the on position. When power is supplied to the

board, a blue LED (D24) illuminates indicating that the board has power.

4–2 Chapter 4: Development Board Setup

Factory Default Switch Settings

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

The MAX II device on the board contains a parallel flash loader (PFL) megafunction.

When the board powers up, the PFL reads one of two designs from flash memory and

configures the FPGA. The rotary switch (SW2) controls which design to load. When

the switch is in the 0 position, the PFL loads the design from the factory portion of

flash memory. When the switch is in the 1 position, the PFL loads the design from the

user portion of flash memory.

1The development kit includes the MAX II configuration design in the <install

dir>\kits\stratixIVGX_4sgx230_av\examples\max2 directory.

When configuration is complete, the CONF DONE LED (D5) illuminates, signaling

that the Stratix IV GX device configured successfully.

fFor more information about the PFL megafunction, refer to AN 386: Using the Parallel

Flash Loader with the Quartus II Software.

Factory Default Switch Settings

This section shows the factory switch settings for the Stratix IV GX FPGA

development board. Figure 4–1 shows the switch locations and the default position of

each switch on the top side of the board.

Figure 4–2 shows the switch locations and the default position of each switch on the

bottom side of the board.

Figure 4–1. Switch Locations and Default Settings on the Development Board Top

SW3

12345678

SW2

Rotary

Switch

ON = 0

OFF = 1

User DIP

Switch

Chapter 4: Development Board Setup 4–3

Factory Default Switch Settings

To restore the switches to their factory default settings, perform the following steps:

1. Set the rotary switch (SW2) to the 0 position, as shown in Figure 4–1.

2. Set DIP switch bank (SW3) to match Table 4–1 and Figure 4–1.

3. Set DIP switch bank (SW4) to match Table 4–2 and Figure 4–2.

Figure 4–2. Switch Locations and Default Settings on the Development Board Bottom

Table 4–1. SW3 Dip Switch Settings

Switch Position

1Off

2Off

3Off

4Off

5Off

6Off

7Off

8Off

Table 4–2. SW4SW4 Dip Switch Settings (Part 1 of 2)

Switch Position

1Off

2Off

3On

4Off

5On

6On

4321

SW4

87654321

ON = 0

OFF = 1

SW6

4321

SW5

PCIe JTAG

Board

Settings

ON = 0

OFF = 1

4–4 Chapter 4: Development Board Setup

Factory Default Switch Settings

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

4. Set DIP switch bank (SW5) to match Table 4–3 and Figure 4–2.

5. Set DIP switch bank (SW6) to match Table 4–4 and Figure 4–2.

fFor more information about the FPGA board settings, refer to the Stratix IV GX FPGA

Development Board Reference Manual.

6. Set the SDI HSMC jumpers to match Table 4–5.

fFor more information about the SDI HSMC jumper settings, refer to the SDI HSMC

Reference Manual.

7On

8On

Table 4–3. SW5SW5 Dip Switch Settings

Switch Position

1Off

2Off

3Off

4Off

Table 4–4. SW6 Dip Switch Settings

Switch Position

1Off

2On

3On

4On

Table 4–2. SW4SW4 Dip Switch Settings (Part 2 of 2)

Switch Position

Table 4–5. SDI HSMC Jumper Settings

Board

Reference Name Position

J4 CD_MUTE_2 On

J5 EQ_BYPASS_2 Off

J6 CD_MUTE_1 On

J7 EQ_BYPASS_1 Off

5. Board Update Portal

Introduction

The Audio Video Development Kit, Stratix IV GX Edition ships with the Board

Update Portal example design stored in the factory portion of the flash memory on

the board. The design consists of a Nios II embedded processor, an Ethernet MAC,

and an HTML web server.

When you power up the board with the rotary switch (SW2) in the 0 position, the

Stratix IV GX FPGA configures with the Board Update Portal example design. The

design can obtain an IP address from any DHCP server and serve a web page from the

flash on your board to any host computer on the same network. The web page allows

you to upload new FPGA designs to the user portion of flash memory, and provides

links to useful information on the Altera website, including links to kit-specific and

design resources.

1After successfully updating the flash memory user design, you can load the user

design from flash memory into the FPGA. To do so, set the rotary switch (SW2) to the

1 position and power cycle the board.

The source code for the Board Update Portal design resides in the <install

dir>\kits\stratixIVGX_4sgx230_av\examples directory. If the Board Update Portal is

corrupted or deleted from the flash memory, refer to “Restoring the Flash Device to

the Factory Settings” on page A–4 to restore the board with its original factory

contents.

Connecting to the Board Update Portal Web Page

This section provides instructions to connect to the Board Update Portal web page.

1Before you proceed, ensure that you have the following:

■A PC with a connection to a working Ethernet port on a DHCP enabled network.

■A separate working Ethernet port connected to the same network for the board.

■The Ethernet and power cables that are included in the kit.

To connect to the Board Update Portal web page, perform the following steps:

1. With the board powered down, set the rotary switch (SW2) to the 0 position.

2. Attach the Ethernet cable from the board to your LAN.

3. Power up the board. The board connects to the LAN’s gateway router, and obtains

an IP address. The LCD on the board displays the IP address.

4. Launch a web browser on a PC that is connected to the same network, and enter

the IP address from the LCD into the browser address bar. The Board Update

Portal web page appears in the browser.

5–2 Chapter 5: Board Update Portal

Using the Board Update Portal to Update User Designs

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

5. Click Audio Video Development Kit, Stratix IV GX Edition on the Board Update

Portal web page and verify that you have the latest version of the development kit

software (the software version also appears on the CD-ROM).

1If you download new software, double-click the downloaded .exe file to

begin the installation process.

6. Visit the Board Update Portal web page occasionally for documentation updates

and additional new designs not included on the CD-ROM.

fIf the Board Update Portal does not connect, refer to the Audio Video Development

Kit, Stratix IV GX Edition page of the Altera website to determine if you have the

latest kit software.

Using the Board Update Portal to Update User Designs

The Board Update Portal allows you to write new designs to the user portion of flash

memory. Designs must be in the Nios II Flash Programmer File (.flash) format.

1Design files available from the Audio Video Development Kit, Stratix IV GX Edition

page of the Altera website include .flash files. You can also create .flash files from

your own custom design. Refer to “Preparing Design Files for Flash Programming”

on page A–2 for information about preparing your own design for upload.

To upload a design over the network into the user portion of flash memory on your

board, perform the following steps:

1. Perform the steps in “Connecting to the Board Update Portal Web Page” to access

the Board Update Portal web page.

2. In the Hardware File Name field specify the .flash file that you either downloaded

from the Altera website or created on your own. If there is a software component

to the design, specify it in the same manner using the Software File Name field,

otherwise leave the Software File Name field blank.

3. Click Upload. The progress bar indicates the percent complete.

4. To configure the FPGA with the new design after the flash memory upload process

is complete, set the rotary switch (SW2) to the 1 position and power cycle the

board, or press the CONFIGN button (S1).

1As long as you don’t overwrite the factory image in the flash memory device, you can

continue to use the Board Update Portal to write new designs to the user portion of

flash memory. If you do overwrite the factory image, you can restore it by following

the instructions in “Restoring the Flash Device to the Factory Settings” on page A–4.

6. Board Test System

Introduction

The kit includes an example design and application called the Board Test System to

test the functionality of the Stratix IV GX FPGA development board and SDI HSMC

daughtercard. The application provides an easy-to-use interface to alter functional

settings and observe the results. You can use the application to test board

components, modify functional parameters, observe performance, and measure

power usage. The application is also useful as a reference for designing systems. To

install the application, follow the steps in “Installing the Audio Video Development

Kit, Stratix IV GX Edition” on page 3–2.

The application provides access to the following Stratix IV GX FPGA development

board features:

■General purpose I/O (GPIO)

■SRAM

■Flash memory

■DDR3 and QDR II+ memories

■HSMC connectors

■High-definition multimedia interface (HDMI) and SDI video

The application allows you to exercise most of the board components. While using the

application, you reconfigure the FPGA several times with test designs specific to the

functionality you are testing.

A GUI runs on the PC which communicates over the JTAG bus to a test design

running in the Stratix IV GX device. Figure 6–1 shows the initial GUI for a board that

is in the factory configuration.

6–2 Chapter 6: Board Test System

Introduction

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

Several designs are provided to test the major board features. Each design provides

data for one or more tabs in the application. The Configure menu identifies the

appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, the appropriate tab appears and allows you to

exercise the related board features. Highlights appear in the board picture around the

corresponding components.

The Power Monitor button starts the Power Monitor application that measures and

reports current power and temperature information for the board. Because the

application communicates over the JTAG bus to the MAX II device, you can measure

the power of any design in the FPGA, including your own designs.

1The Board Test System and Power Monitor share the JTAG bus with other

applications like the Nios II debugger and the SignalTap® II Embedded Logic

Analyzer. Because the Quartus II programmer uses most of the bandwidth of the

JTAG bus, other applications using the JTAG bus might time out. Be sure to close the

other applications before attempting to reconfigure the FPGA using the Quartus II

Programmer.

Figure 6–1. Board Test System Graphical User Interface

Chapter 6: Board Test System 6–3

Preparing the Board

With the power to the board off, perform the following steps:

1. Connect the USB cable to the board.

2. Verify the settings for the board settings DIP switch bank (SW4) match Table 4–2

on page 4–3.

3. Set the rotary switch (SW2) to the 1 position.

4. Verify the settings for the JTAG DIP switch bank (SW6), located on the back of the

board, match Table 4–4 on page 4–4. These settings determine the devices to

include in the JTAG chain.

fFor more information about the board’s DIP switch and jumper settings,

refer to the Stratix IV GX FPGA Development Board Reference Manual.

5. Turn the power to the board on. The board loads the design stored in the user

portion of flash memory into the FPGA. If your board is still in the factory

configuration or if you have downloaded a newer version of the Board Test

System to flash memory through the Board Update Portal, the design that tests the

GPIO, SRAM, and flash memory loads.

cTo ensure operating stability, keep the USB cable connected and the board

powered on when running the demonstration application. The application

cannot run correctly unless the USB cable is attached and the board is on.

Running the Board Test System

To run the application, navigate to the <install

dir>\kits\stratixIVGX_4sgx230_av\examples\board_test_system directory and run

the BoardTestSystem.exe application.

1On Windows, click Start > All Programs > Altera > Audio Video Development Kit,

Stratix IV GX Edition <version> > Board Test System to run the application.

A GUI appears, displaying the application tab that corresponds to the design running

in the FPGA. The Stratix IV GX FPGA development board’s flash memory ships

preconfigured with the design that corresponds to the Config, GPIO, and

SRAM&Flash tabs.

1If you power up your board with the rotary switch (SW2) in a position other than the

1 position, or if you load your own design into the FPGA with the Quartus II

Programmer, you receive a message prompting you to configure your board with a

valid Board Test System design. Refer to “The Configure Menu” for information about

configuring your board.

Using the Board Test System

This section describes each control in the Board Test System application.

6–4 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

The Configure Menu

Each test design tests different functionality and corresponds to one or more

application tabs. Use the Configure menu to select the design you want to use.

Figure 6–2 shows the Configure menu.

To configure the FPGA with a test system design, perform the following steps:

1. On the Configure menu, click the configure command that corresponds to the

functionality you wish to test.

2. In the dialog box that appears, click Download Start to download the

corresponding design’s SRAM Object File (.sof) to the FPGA. The download

process usually takes about a minute.

3. When configuration finishes, close the Quartus II ProgrammerThe design begins

running in the FPGA. The corresponding GUI application tab that interfaces with

the design in the FPGA comes to the front.

The Config Tab

The Config tab shows information about the board’s current configuration.

Figure 6–1 on page 6–2 shows the Config tab. The tab displays the contents of the

MAX II registers, the MAX II code version, the JTAG chain, the board’s MAC address,

and the flash memory map.

The following sections describe the controls on the Config tab.

MAX II Registers

The MAX II registers control allow you to view and change the current MAX II

take effect immediately. For example, writing a 0 to SRST resets the board.

Figure 6–2. The Configure Menu

Chapter 6: Board Test System 6–5

Using the Board Test System

■PSO—Sets the MAX II PSO register. The following options are available:

■Use PSR—Allows the PSR to determine the page of flash memory to use for

FPGA reconfiguration.

■Use PSS—Allows the PSS to determine the page of flash memory to use for

FPGA reconfiguration.

■PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to

the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1

for more information.

■PSS—Displays the MAX II PSS register value. Refer to Table 6–1 for the list of

available options.

■SRST—Resets the system and reloads the FPGA with a design from flash memory

based on the other MAX II register values. Refer to Table 6–1 for more information.

1Because the Config tab requires that a specific design is running in the FPGA, writing

a 0 to SRST or changing the PSO value can cause the Board Test System to stop

running.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain. The Stratix

IV GX device is always the first device in the chain.

1Setting DIP switch SW6.1 to the off position includes the MAX II device in the JTAG

chain.

Board Information

The Board information controls display static information about your board.

■MAX II ver—Indicates the version of MAX II code currently running on the board.

The MAX II code resides in the <install

dir>\kits\stratixIVGX_4sgx230_av\examples directory. Newer revisions of this

code might be available on the Audio Video Development Kit, Stratix IV GX

Edition page of the Altera website.

Table 6–1. MAX II Registers

Read/Write

Capability Description

System Reset

(SRST)

Write only Set to 0 to initiate an FPGA reconfiguration.

Page Select Register

(PSR)

Read / Write Determines which of the up to eight (0-7) pages of flash

memory to use for FPGA reconfiguration. The flash memory

ships with pages 0 and 1 preconfigured.

Page Select Override

(PSO)

Read / Write When set to 0, the value in PSR determines the page of

flash memory to use for FPGA reconfiguration. When set to

1, the value in PSS determines the page of flash memory to

use for FPGA reconfiguration.

Page Select Switch

(PSS)

Read only Holds the current value of the rotary switch (SW2).

6–6 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

■MAC—Indicates the MAC address of the board.

Flash Memory Map

The Flash memory map control shows the memory map of the flash memory device

on your board.

The GPIO Tab

The GPIO tab allows you to interact with all the general purpose user I/O

components on your board. You can write to the LCD, read DIP switch settings, turn

LEDs on or off, and detect push button presses. Figure 6–3 shows the GPIO tab.

The following sections describe the controls on the GPIO tab.

LCD

The LCD controls allow you to display text strings on the LCD on your board. Type

text in the text boxes and then click Write.

Figure 6–3. The GPIO Tab

Chapter 6: Board Test System 6–7

Using the Board Test System

1If you exceed the 16 character display limit on either line, a warning message appears.

User DIP Switch

The read-only User DIP switch control displays the current positions of the switches

in the user DIP switch bank (SW3). Change the switches on the board to see the

graphical display change accordingly.

User LEDs

The User LEDs control displays the current state of the user LEDs. Click on the

graphical representation of the LEDs to turn the board LEDs on and off.

Push Button Switches

The read-only Push button switches control displays the current state of the board

user push buttons. Press a push button on the board to see the graphical display

change accordingly.

The SRAM&Flash Tab

The SRAM&Flash tab allows you to read and write SRAM and flash memory on your

board. Figure 6–4 shows the SRAM&Flash tab.

6–8 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

The following sections describe the controls on the SRAM&Flash tab.

SRAM

The SRAM control allows you to read and write the SRAM on your board. Type a

starting address in the text box and click Read. Values starting at the specified address

appear in the table. The SRAM addresses display in the format the Nios II processor

within the FPGA uses, that is, each SRAM address is offset by 0x00400000. Thus, the

first location in SRAM appears as 0x00400000 in the GUI.

1If you enter an address outside of the 0x00400000 to 0x005FFFFF SRAM address

space, a warning message identifies the valid SRAM address range.

To update the SRAM contents, change values in the table and click Write. The

application writes the new values to SRAM and then reads the values back to

guarantee that the graphical display accurately reflects the memory contents.

Figure 6–4. The SRAM&Flash Tab

Chapter 6: Board Test System 6–9

Using the Board Test System

Flash

The Flash control allows you to read and write the flash memory on your board. Type

a starting address in the text box and click Read. Values starting at the specified

address appear in the table. The flash memory addresses display in the format the

Nios II processor within the FPGA uses, that is, each flash memory address is offset

by 0x04000000. Thus, the first location in flash memory appears as 0x04000000 in the

GUI.

1If you enter an address outside of the 0x04000000 to 0x07FFFFFF flash memory

address space, a warning message identifies the valid flash memory address range.

To update the flash memory contents, change values in the table and click Write. The

application writes the new values to flash memory and then reads the values back to

guarantee that the graphical display accurately reflects the memory contents.

1To prevent overwriting the dedicated portions of flash memory, the application limits

the writable flash memory address range to 0x07FE0000 to 0x07FFFFFF (which

corresponds to the unused flash memory address range of 0x03FE0000 - 0x03FFFFFF

shown in Figure 6–1 on page 6–2 and Table A–1 on page A–1).

The DDR3 Tab

The DDR3 tab allows you to read and write the DDR3 memory on your board.

Figure 6–5 shows the DDR3 tab.

6–10 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

The following sections describe the controls on the DDR3 tab.

Port

The Port control directs communication to one of two DDR3 memory ports on your

board. A 16-bit interface connects to the top bank of the Stratix IV GX FPGA and a 64-

bit interface connects to the bottom banks of the FPGA.

Start

The Start control initiates DDR3 memory transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected

since you last pressed Start:

Figure 6–5. The DDR3 Tab

Chapter 6: Board Test System 6–11

Using the Board Test System

■Write, Read, and Tot a l performance bars—Show the percentage of maximum data

rate that the requested transactions are able to achieve.

■Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of

data analyzed per second.

Error Control

The Error control controls track transaction errors detected during analysis:

■Detected errors—Displays the number of transaction errors detected in the

hardware.

■Inserted errors—Displays the number of errors inserted into the transaction

stream.

■Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance

analysis.

■Clear—Resets the Detected Errors and Inserted Errors counters to zeros.

Number of Addresses to Write andRead

The Number of addresses to write andread control determines the number of

addresses to use in each iteration of reads and writes. Valid values range from 2 to

524,288.

Data Type

The Data type control specifies the type of data contained in the transactions. The

following data types are available for analysis:

■PRBS—Selects pseudo-random bit sequences.

■Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV GX device.

■Math—Selects data generated from a simple math function within the FPGA

fabric.

Read and Write Control

The Read and write control control specifies the type of transactions to analyze. The

following transaction types are available for analysis:

■Write then read—Selects read and write transactions for analysis.

■Read only—Selects read transactions for analysis.

■Write only—Selects write transactions for analysis.

The QDRII+ Tab

The QDRII+ tab allows you to read and write the QDR II+ memory on your board

and independently test each QDR II+ port. Figure 6–6 shows the QDRII+ tab.

6–12 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

The following sections describe the controls on the QDRII+ tab.

Port

The Port control directs communication to one of two QDR II+ ports on your board.

Start

The Start control initiates QDR II+ memory transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected

since you last clicked Start:

■Write and Read performance bars—Show the percentage of maximum data rate

that the requested transactions are able to achieve.

Figure 6–6. The QDRII+ Tab

Chapter 6: Board Test System 6–13

Using the Board Test System

■Write (MBps) and Read (MBps)—Show the number of bytes of data analyzed per

second.

Error Control

The Error control controls track transaction errors detected during analysis:

■Detected errors—Displays the number of transaction errors detected in the

hardware.

■Inserted errors—Displays the number of errors inserted into the transaction

stream.

■Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance

analysis.

■Clear—Resets the Detected Errors and Inserted Errors counters to zeros.

Number of Addresses to Write and Read

The Number of addresses to write and read control determines the number of

addresses to use in each iteration of reads and writes. Valid values range from 2 to

524,288.

Data Type

The Data type control specifies the type of data contained in the transactions. The

following data types are available for analysis:

■PRBS—Selects pseudo-random bit sequences.

■Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV GX device.

■Math—Selects data generated from a simple math function within the FPGA

fabric.

The HSMC Tab

The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B

ports. Figure 6–7 shows the HSMC tab.

6–14 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

1You must have the loopback HSMC installed on the HSMC connector that you are

testing for this test to succeed.

The following sections describe the controls on the HSMC tab.

Status

The Status control displays the following status information during the loopback test:

■PLL lock—Shows the PLL locked or unlocked state.

■Channel lock—Shows the channel locked or unlocked state. When locked, all

lanes are aligned and bonded.

■Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

Port

The Port control allows you to specify the type of test to run on the HSMC ports. The

following HSMC port tests are available:

Figure 6–7. The HSMC Tab

Chapter 6: Board Test System 6–15

Using the Board Test System

■HSMA x4 Tranceivers [0..3]

■HSMA x4 Tranceivers [4..7]

■HSMB x4 Tranceivers [0..3]

■HSMB x2 Tranceivers [4..5]

■HSMA x17 LVDS SERDES

■HSMB x17 LVDS SERDES

■HSMA x3 Single Ended Loopback

■HSMB x3 Single Ended Loopback

Data Type

The Data type control specifies the type of data contained in the transactions. The

following data types are available for analysis:

■PRBS—Selects pseudo-random bit sequences.

■Memory—Selects a generic data pattern stored in the on chip memory of the

Stratix IV GX device.

■Math—Selects data generated from a simple math function within the FPGA

fabric.

Error Control

The Error control controls track transaction errors detected during analysis.

■Detected errors—Displays the number of transaction errors detected in the

hardware.

■Inserted errors—Displays the number of errors inserted into the transaction

stream.

■Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance

analysis.

■Clear—Resets the Detected errors and Inserted errors counters to zeros.

Start

The Start control initiates HSMC transaction performance analysis.

Stop

The Stop control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected

since you last clicked Start:

■TX and RX performance bars—Show the percentage of maximum data rate that

the requested transactions are able to achieve.

■Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per

second.

6–16 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

The Video Tab

The Video tab allows you to test the HDMI and SDI video interfaces on your board.

Figure 6–8 shows the Video tab.

The following sections describe the controls on the Video tab.

HDMI

Testing the HDMI requires connecting a monitor with at least UXGA (1600 × 1200)

resolution to your board. Once connected, the following controls define the output to

the monitor:

Figure 6–8. The Video Tab

Chapter 6: Board Test System 6–17

Using the Board Test System

■Color bar test pattern—Specifies the test pattern to output to the monitor. The

following choices are available:

■Color bar

■Red

■Green

■Blue

Table 6–2 shows the color bar test pattern and corresponding color names and

RGB values.

■Resolution—Specifies the resolution to output to the monitor. The following

choices are available:

■1080p—1920 × 1080 progressive

■720p—1280 × 720 progressive

■Start—Initiates the test.

■Stop—Terminates the test.

■Get EDID—Reads the extended display information data (EDID) from the

monitor and displays the results.

SDI

Testing the SDI requires connecting a SMB loopback cable as shown in Figure 6–9.

Table 6–2. HDMI Color Bar Test Pattern

Color Bars Color RGB Values

White/Grey 180,180,180

Yellow 180,180,16

Cyan 16,180,180

Green 16,180,16

Magenta 180,16,180

Red 180,16,16

Blue 16,16,180

Black 16,16,16

6–18 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

Once connected, the following controls are available:

■Reset—Restarts the test.

■Load—Passes a new seed value to the PRBS generator on the device.

■Status—Displays the following status information during the loopback test:

■Tx PLL—Shows whether the Tx PLL is locked or unlocked.

■Rx PLL—Shows whether the Rx PLL is locked or unlocked.

■Error status—Shows “No Error Detected” when the test is running correctly;

otherwise shows pertinent error.

■Error control—Provides the following controls to track transaction errors detected

during analysis:

■Errors—Displays the number of errors detected in the hardware.

■Insert Error—Inserts a one-word error into the transaction stream each time

you click the button.

■Clear—Resets the Errors counter to zero.

The SDI HSMC - PRBS Tab

The SDI HSMC - PRBS tab allows you test the functionality of the SDI video and AES

audio transmit and receive pairs. The tests are PRBS data pattern loopback tests using

the two AES digital audio ports and the two SDI digital video ports on the SDI HSMC.

AES audio channel tests run at 24 Mbps and SDI tests run at 2.97 Gbps.

To monitor results of each test, connect a BNC loopback cable between the

corresponding transmit and receive connectors. Tests run on all channels

simultaneously, but only channels with loopback cables display accurate information.

Figure 6–10 shows the SDI HSMC - PRBS tab.

Figure 6–9. Board with SMB Loopback Cable

Chapter 6: Board Test System 6–19

Using the Board Test System

The following sections describe the controls on the SDI HSMC - PRBS tab.

Start

The Start control initiates the loopback tests.

Stop

The Stop control terminates the loopback tests.

AES in1

The AES in1 controls track transmit errors detected during analysis of AES channel 1.

To track the test results, connect a BNC loopback cable between AES OUT 1 (J3) and

AES IN 1 (J10).

■Errors—Displays the number of errors detected in the hardware.

■Insert Error—Inserts a bit error into the transmit data stream each time you click

the button.

Figure 6–10. The SDI HSMC - PRBS Tab

6–20 Chapter 6: Board Test System

Using the Board Test System

Audio Video Development Kit, Stratix IV GX Edition User Guide © November 2009 Altera Corporation

■Clear—Resets the Errors counter to zero.

AES in2

The AES in2 controls track transmit errors detected during analysis of AES channel 2.

To track the test results, connect a BNC loopback cable between AES OUT 2 (J14) and

AES IN 2 (J15).

■Errors—Displays the number of errors detected in the hardware.

■Insert Error—Inserts a bit error into the transmit data stream each time you click

the button.

■Clear—Resets the Errors counter to zero.

SDI in1

The SDI in1 controls track transmit errors detected during analysis of SDI channel 1.

To track the test results, connect a BNC loopback cable between SDI OUT 1 (J8) and

SDI IN 1 (J9).

■Errors—Displays the number of errors detected in the hardware.

■PLL lock—Shows the receiver PLL locked or unlocked state.

■Insert Error—Inserts a bit error into the transmit data stream each time you click

the button.

■Clear—Resets the Errors counter to zero.

SDI in2

The SDI in1 controls track transmit errors detected during analysis of SDI channel 2.

To track the test results, connect a BNC loopback cable between SDI OUT 2 (J1) and

SDI IN 2 (J2).

■Errors—Displays the number of errors detected in the hardware.

■PLL lock—Shows the receiver PLL locked or unlocked state.

■Insert Error—Inserts a bit error into the transmit data stream each time you click

the button.

■Clear—Resets the Errors counter to zero.

The SDI HSMC - Video Tab

The SDI HSMC - Video tab allows you to generate video patterns, and send and

receive SDI video through the SDI HSMC. Figure 6–11 shows the SDI HSMC - Video

tab.

Chapter 6: Board Test System 6–21

Using the Board Test System

The following sections describe the controls on the SDI HSMC - Video tab.

Pattern Generator

The SDI HSMC has two transmitter channels (CH1 Tx and CH2 Tx) and two receiver

channels (CH1 Rx and CH2 Rx). When a receiver channel has valid video input, the

corresponding transmitter channel transmits the input video stream. When no valid

video input is present, the each transmitter outputs a video pattern based on the

following settings:

■Pattern—Specifies the test pattern to output to the monitor. The following choices

are available:

■Color bar—Specifies a video color bar pattern with eight vertical color bars.

(Refer to Table 6–2)

■Pathological—Specifies a video color bar pattern with two horizontal color

bars that stresses the receive PLL.

Figure 6–11. The SDI HSMC - Video Tab

6–22 Chapter 6: Board Test System

The Power Monitor

■Clock source—Specifies the clock the SDI HSMC PLL locks to. The following

choices are available:

■Lock to host—Locks the SDI HSMC PLL to the local reference on the Stratix IV

GX FPGA development board.

■Lock to input—Locks the SDI HSMC PLL to the SDI input stream.

■Intensity—Specifies the color intensity of the transmitted color bar pattern.

■SDI standard—Specifies the video standard the pattern generator uses on the SDI

video stream. The following choices are available:

■SD—Specifies a 270 Mbps data rate

■HD—Specifies a 1.485 Gbps data rate

■3G HD—Specifies a 2.97 Gbps data rate

Receiver Status

These controls show the settings for each receiver channel on the SDI HSMC. Both

receiver channels (CH1 RX and CH2 RX) operate independently but must have the

same clock source or be synchronized with each other.

■CH1 Rx status and CH2 Rx status—Show the status of the following receiver

channel attributes:

■Alignment—Shows the alignment locked or unlocked state. "Locked" indicates

that the TRS pattern has been received and data is word aligned.

■TRS—Shows the TRS locked or unlocked state. "Locked" indicates the six TRS

patterns have been received with the same timing.

■Frame—Shows the frame locked or unlocked state. "Locked" indicates the

frame sync patterns have been received.

■Standard—Shows the type of video input (SD, HD, or 3G) the channel is

receiving.

The Power Monitor

The Power Monitor measures and reports current power and temperature

information for the board. To start the application, click Power Monitor in the Board

Test System application.

1You can also run the Power Monitor as a stand-alone application. PowerMonitor.exe

resides in the <install

dir>\kits\stratixIVGX_4sgx230_av\examples\board_test_system directory. On

Windows, click Start > All Programs > Altera > Audio Video Development Kit,

Stratix IV GX Edition <version> > Power Monitor to start the application.

The Power Monitor communicates with the MAX II device on the board through the

JTAG bus. A power monitor circuit attached to the MAX II device allows you to

measure the power that the Stratix IV GX FPGA device is consuming regardless of the

design currently running. Figure 6–12 shows the Power Monitor.

Chapter 6: Board Test System 6–23

The Power Monitor

The following sections describe the Power Monitor controls.

General Information

The General information controls display the following information about the

MAX II device:

■MAX II version—Indicates the version of MAX II code currently running on the

board. The MAX II code resides in the <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery directory. Newer revisions

of this code might be available on the Audio Video Development Kit,

Stratix IV GX Edition page of the Altera website.

■Power rail—Indicates the currently-selected power rail. The rotary switch (SW2)

on your board controls which rail to measure. After setting the switch for the

desired rail, click Reset to refresh the screen with new board readings.

fA table with the power rail switch positions is available in the

Stratix IV GX FPGA Development Board Reference Manual.

Figure 6–12. The Power Monitor

6–24 Chapter 6: Board Test System

The Power Monitor

Temperature Information

The Temperature information controls display the following temperature readings

for the board and the FPGA on the board:

■FPGA—Indicates the temperature of the FPGA device.

■Board—Indicates the overall board temperature.

Power Information

The Power information control displays current, maximum, and minimum power

readings for the following units:

■mVolt

■mAmp

■mWatt

12V Power Consumption

The 12V Power consumption control displays 12-V power consumption readings for

the following units:

■mA

■mW

Power Graph

The Power graph control displays the mWatt power consumption of your board over

time. The green line indicates the current value. The red line indicates the maximum

value read since the last reset. The yellow line indicates the minimum value read since

the last reset.

Graph Settings

The following Graph settings controls allow you to define the look and feel of the

power graph:

■Scale select—Specifies the amount to scale the power graph. Select a smaller

number to zoom in to see finer detail. Select a larger number to zoom out to see the

entire range of recorded values.

■Update speed—Specifies how often to refresh the graph.

Reset

This Reset control clears the graph, resets the minimum and maximum values, and

restarts the Power Monitor.

Chapter 6: Board Test System 6–25

The Clock Control

Calculating Power

The Power Monitor calculates power by measuring two different voltages with the

LT2418 A/D and applying the equation P = V × I to determine the power

consumption. The LT2418 measures the voltage after the appropriate sense resistor

(Vsense) and the voltage drop across that sense resistor (Vdif). The current (I) is

calculated by dividing the measured voltage drop across the resistor by the value of

the sense resistor (I = Vdif/R). Through substitution, the equation for calculating

power becomes P = V × I = Vsense × (Vdif/R) = (Vsense) × (Vdif) × (1/.003).

You can verify the power numbers shown in the Power Monitor with a digital

multimeter that is capable of measuring microvolts to ensure you have enough

significant digits for an accurate calculation. Measure the voltage on one side of the

resistor (the side opposite the power source) and then measure the voltage on the

other side. The first measurement is Vsense and the difference between the two

measurements is Vdif. Plug the values into the equation to determine the power

consumption.

The Clock Control

The Clock Control sets the Si570 programmable oscillator to any frequency between

10 MHz and 810 MHz with eight digits of precision to the right of the decimal point.

The oscillator drives a 2-to-4 buffer that drives a copy of the clock to all four edges of

the FPGA.

The Clock Control runs as a stand-alone application. ClockControl.exe resides in the

<install dir>\kits\stratixIVGX_4sgx230_av\examples\board_test_system directory.

On Windows, click Start > All Programs > Altera > Audio Video Development Kit,

Stratix IV GX Edition <version> > Clock Control to start the application.

fFor more information about the Si570 and the Stratix IV GX development board’s

clocking circuitry and clock input pins, refer to the Stratix IV GX FPGA Development

Board Reference Manual.

The Clock Control communicates with the MAX II device on the board through the

JTAG bus. The Si570 programmable oscillator is connected to the MAX II device

through a 2-wire serial bus. Figure 6–13 shows the Clock Control.

6–26 Chapter 6: Board Test System

The Clock Control

The following sections describe the Clock Control controls.

Serial Port Registers

The Serial port registers control shows the current values from the Si570 registers.

fFor more information about the Si570 registers, refer to the Si570/Si571 datasheet

available on the Silicon Labs website (www.silabs.com).

fXTAL

The fXTAL control shows the calculated internal fixed-frequency crystal based on the

serial port register values.

fFor more information about the fXTAL value and how it is calculated, refer to the

Si570/Si571 datasheet available on the Silicon Labs website (www.silabs.com).

Disable Oscillator

The Disable oscillator enables and disables the Si570 output buffer. Turn on Disable

oscillator to power down the Si570 output buffer. Turn off the Disable oscillator to

drive the Si570 output buffer normally.

Target Frequency

The Target frequency control allows you to specify the frequency of the clock. Legal

values are between 10 and 810 MHz with eight digits of precision to the right of the

decimal point. For example, 421.31259873 is possible within 100 parts per million

(ppm). The Target frequency control works in conjunction with the Set New

Frequency control.

Figure 6–13. The Clock Control

Chapter 6: Board Test System 6–27

Configuring the FPGA Using the Quartus II Programmer

Reset Si570

The Reset Si570 control sets the Si570 programmable oscillator to the default

frequency of 100 MHz.

Set New Frequency

The Set New Frequency control sets the Si570 programmable oscillator frequency to

the value in the Target frequency control. Frequency changes might take several

milliseconds to take effect. You might see glitches on the clock during this time.

Altera recommends resetting the FPGA logic after changing frequencies.

Configuring the FPGA Using the Quartus II Programmer

You can use the Quartus II Programmer to configure the FPGA with a specific .sof.

Before configuring the FPGA, ensure that the Quartus II Programmer and the

USB-Blaster driver are installed on the host computer, the USB cable is connected to

the development board, power to the board is on, and no other applications that use

the JTAG chain are running.

To configure the Stratix IV GX FPGA, perform the following steps:

1. Start the Quartus II Programmer.

2. Click Add File and select the path to the desired .sof.

3. Turn on the Program/Configure option for the added file.

4. Click Start to download the selected file to the FPGA. Configuration is complete

when the progress bar reaches 100%.

6–28 Chapter 6: Board Test System

Configuring the FPGA Using the Quartus II Programmer

A. Programming the Flash Memory

Device

Introduction

As you develop your own project using the Altera tools, you can program the flash

memory device so that your own design loads from flash memory into the FPGA on

power up. This appendix describes the preprogrammed contents of the common flash

interface (CFI) flash memory device on the Stratix IV GX FPGA development board

and the Nios II EDS tools involved with reprogramming the user portions of the flash

memory device.

The Stratix IV GX FPGA development board ships with the CFI flash device

preprogrammed with a default factory FPGA configuration for running the Board

Update Portal example design and a default user configuration for running the Board

Test System demonstration. There are several other factory software files written to

the CFI flash device to support the Board Update Portal. These software files were

created using the Nios II EDS, just as the hardware design was created using the

Quartus II software.

fFor more information about Altera development tools, refer to the Design Software

page of the Altera website.

CFI Flash Memory Map

Table A–1 shows the default memory contents of the 512-Mb (64-MB) Intel

PC48F4400P0VB00 CFI flash device. For the Board Update Portal to run correctly and

update designs in the user memory, this memory map must not be altered.

Table A–1. Byte Address Flash Memory Map

Block Description Size Address Range

Unused 32 KB 0x03FF8000 - 0x03FFFFFF

Unused 32 KB 0x03FF0000 - 0x03FF7FFF

Unused 32 KB 0x03FE8000 - 0x03FEFFFF

Unused 32 KB 0x03FE0000 - 0x03FE7FFF

User software 24,320 KB 0x02820000 - 0x03FDFFFF

Factory software 8,192 KB 0x02020000 - 0x0281FFFF

zipfs (html, web content) 8,192 KB 0x01820000 - 0x0201FFFF

User hardware 12,288 KB 0x00C20000 - 0x0181FFFF

Factory hardware 12,288 KB 0x00020000 - 0x00C1FFFF

PFL option bits 32 KB 0x00018000 - 0x0001FFFF

Board information 32 KB 0x00010000 - 0x00017FFF

Ethernet option bits 32 KB 0x00008000 - 0x0000FFFF

User design reset vector 32 KB 0x00000000 - 0x00007FFF

A–2 Appendix A: Programming the Flash Memory Device

Preparing Design Files for Flash Programming

cAltera recommends that you do not overwrite the factory hardware and factory

software images unless you are an expert with the Altera tools or deliberately

overwriting the factory design. If you unintentionally overwrite the factory hardware

or factory software image, refer to “Restoring the Flash Device to the Factory Settings”

on page A–4.

Preparing Design Files for Flash Programming

You can obtain designs containing prepared .flash files from the Audio Video

Development Kit, Stratix IV GX Edition page of the Altera website or create .flash

files from your own custom design.

The Nios II EDS sof2flash command line utility converts your Quartus II-compiled

.sof into the .flash format necessary for the flash device. Similarly, the Nios II EDS

elf2flash command line utility converts your compiled and linked Executable and

Linking Format File (.elf) software design to .flash. After your design files are in the

.flash format, use the Board Update Portal or the Nios II EDS nios2-flash-

programmer utility to write the .flash files to the user hardware and user software

locations of the flash memory.

fFor more information about Nios II EDS software tools and practices, refer to the

Embedded Software Development page of the Altera website.

Creating Flash Files Using the Nios II EDS

If you have an FPGA design developed using the Quartus II software, and software

developed using the Nios II EDS, follow these instructions:

1. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II

Command Shell.

2. In the Nios II command shell, navigate to the directory where your design files

reside and type the following Nios II EDS commands:

■For Quartus II .sof files:

sof2flash --input=<yourfile>_hw.sof --output =<yourfile>_hw.flash --offset=0xC20000 r

■For Nios II .elf files:

elf2flash --base=0x0A000000 --end=0x0BFFFFFF --reset=0x0A820000

--input=<yourfile>_sw.elf --output=<yourfile>_sw.flash

--boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec r

The resulting .flash files are ready for flash device programming. If your design uses

additional files such as image data or files used by the runtime program, you must

first convert the files to .flash format and concatenate them into one .flash file before

using the Board Update Portal to upload them.

1The Board Update Portal standard .flash format conventionally uses either

<filename>_hw.flash for hardware design files or <filename>_sw.flash for software

design files.

Appendix A: Programming the Flash Memory Device A–3

Programming Flash Memory Using the Board Update Portal

Once you have the necessary .flash files, you can use the Board Update Portal to

reprogram the flash memory. Refer to “Using the Board Update Portal to Update User

Designs” on page 5–2 for more information.

1If you have generated a .sof that operates without a software design file, you can still

use the Board Update Portal to upload your design. In this case, leave the Software

File Name field blank.

Programming Flash Memory Using the Nios II EDS

The Nios II EDS offers a nios2-flash-programmer utility to program the flash memory

directly. To program the .flash files or any compatible S-Record File (.srec) to the

board using nios2-flash-programmer, perform the following steps:

1. Set the rotary switch (SW2) to the 0 position to load the Board Update Portal

design from flash memory on power up.

2. Attach the USB-Blaster cable and power up the board.

3. If the board has powered up and the LCD displays either "Connecting..." or a valid

IP address (such as 152.198.231.75), proceed to step 8. If no output appears on the

LCD is seen or if the CONF DONE LED (D5) does not illuminate, continue to step

4 to load the FPGA with a flash-writing design.

4. Launch the Quartus II Programmer to configure the FPGA with a .sof capable of

flash programming. Refer to “Configuring the FPGA Using the Quartus II

Programmer” on page 6–27 for more information.

5. Click Add File and select <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery\s4gx230_av_bup.sof.

6. Turn on the Program/Configure option for the added file.

7. Click Start to download the selected configuration file to the FPGA. Configuration

is complete when the progress bar reaches 100%. The CONF DONE LED (D5) and

the eight lower user LEDs (D16-D23) illuminate indicating that the flash device is

ready for programming.

8. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II

Command Shell.

9. In the Nios II command shell, navigate to the <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery directory (or to the

directory of the .flash files you created in “Creating Flash Files Using the Nios II

EDS” on page A–2) and type the following Nios II EDS command:

nios2-flash-programmer --base=0x08000000 <yourfile>_hw.flash r

10. After programming completes, if you have a software file to program, type the

following Nios II EDS command:

nios2-flash-programmer --base=0x0A000000 <yourfile>_sw.flash r

11. Set the rotary switch (SW2) to the 1 position and power cycle the board, or press

the CONFIGN button (S1) to load and run the user design.

Programming the board is now complete.

A–4 Appendix A: Programming the Flash Memory Device

Restoring the Flash Device to the Factory Settings

fFor more information about the nios2-flash-programmer utility, refer to the Nios II

Flash Programmer User Guide.

Restoring the Flash Device to the Factory Settings

This section describes how to restore the original factory contents to the flash memory

device on the development board. Make sure you have the Nios II EDS installed, and

perform the following instructions:

1. Set the board switches to the factory default settings described in “Factory Default

Switch Settings” on page 4–2.

2. Launch the Quartus II Programmer to configure the FPGA with a .sof capable of

flash programming. Refer to “Configuring the FPGA Using the Quartus II

Programmer” on page 6–27 for more information.

3. Click Add File and select <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery\s4gx230_av_bup.sof.

4. Turn on the Program/Configure option for the added file.

5. Click Start to download the selected configuration file to the FPGA. Configuration

is complete when the progress bar reaches 100%. The CONF DONE LED (D5) and

the eight lower user LEDs (D16-D23) illuminate indicating that the flash device is

ready for programming.

6. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II

Command Shell.

7. In the Nios II command shell, navigate to the <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery directory and type the

following command to run the restore script:

./restore.sh r

Restoring the flash memory might take several minutes. Follow any instructions

that appear in the Nios II command shell.

8. After all flash programming completes, cycle the POWER switch (SW1) off then

on.

9. Using the Quartus II Programmer, click Add File and select <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery\s4gx230_av_bup.sof.

10. Turn on the Program/Configure option for the added file.

11. Click Start to download the selected configuration file to the FPGA. Configuration

is complete when the progress bar reaches 100%. The CONF DONE LED (D5) and

the eight lower user LEDs (D16-D23) illuminate indicating the flash memory

device is now restored with the factory contents.

12. Cycle the POWER switch (SW1) off then on to load and run the restored factory

design.

13. The restore script cannot restore the board’s MAC address automatically. In the

Nios II command shell, type the following Nios II EDS command:

Appendix A: Programming the Flash Memory Device A–5

Restoring the MAX II CPLD to the Factory Settings

nios2-terminal r

and follow the instructions in the terminal window to generate a unique MAC

address.

fTo ensure that you have the most up-to-date factory restore files and information

about this product, refer to the Altera Development Kits page of the Altera website.

Restoring the MAX II CPLD to the Factory Settings

This section describes how to restore the original factory contents to the MAX II CPLD

on the development board. Make sure you have the Nios II EDS installed, and

perform the following instructions:

1. Set the board switches to the factory default settings described in “Factory Default

Switch Settings” on page 4–2.

1Setting DIP switch SW6.1 to the off position includes the MAX II device in

the JTAG chain.

2. Launch the Quartus II Programmer.

3. Click Auto Detect.

4. Click Add File and select <install

dir>\kits\stratixIVGX_4sgx230_av\factory_recovery\max2.pof.

5. Turn on the Program/Configure option for the added file.

6. Click Start to download the selected configuration file to the MAX II CPLD.

Configuration is complete when the progress bar reaches 100%.

fTo ensure that you have the most up-to-date factory restore files and information

about this product, refer to the Audio Video Development Kit, Stratix IV GX Edition

page of the Altera website.

A–6 Appendix A: Programming the Flash Memory Device

Restoring the MAX II CPLD to the Factory Settings

Additional Information

Revision History

The following table displays the revision history for this user guide.

How to Contact Altera

For the most up-to-date information about Altera products, refer to the following

table.

Typographic Conventions

This document uses the typographic conventions shown in the following table.

Date & Document

Version Changes Made Summary of Changes

November 2009

v2.0

■Revised BTS screen shots to reflect minor GUI revisions.

■The Configure menu now offers options to determine how to pass

data through the JTAG chain.

■The Config tab MAX II controls are now more obvious.

■Changed BUP .sof name from stratixIVGX_4sgx230es_dev_bup.sof

to s4gx230_av_bup.sof.

■Changed directory path name from stratixIVGX_4sgx230es_av to

stratixIVGX_4sgx230_av.

■Changed PowerTool.exe to PowerMonitor.exe.

■Added description of the Clock Control stand-alone application.

■Added instructions in Appendix A about restoring the board’s MAC

address.

Engineering silicon to

production silicon

revisions

July 2009

v1.0

Initial release. —

Contact (Note 1)

Contact

Method Address

Technical support Website www.altera.com/support

Technical training Website www.altera.com/training

Email custrain@altera.com

Product literature Website www.altera.com/literature

Non-technical support (General) Email nacomp@altera.com

(Software Licensing) Email authorization@altera.com

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Info–2 Additional Information

Typographic Conventions

Visual Cue Meaning

Bold Type with Initial Capital

Letters

Indicates command names, dialog box titles, dialog box options, and other GUI

labels. For example, Save As dialog box.

bold type Indicates directory names, project names, disk drive names, file names, file name

extensions, and software utility names. For example, \qdesigns directory, d: drive,

and chiptrip.gdf file.

Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.

Italic type Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and

<project name>.pof file.

Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options

menu.

“Subheading Title” Quotation marks indicate references to sections within a document and titles of

Quartus II Help topics. For example, “Typographic Conventions.”

Courier type Indicates signal, port, register, bit, block, and primitive names. For example, data1,

tdi, and input. Active-low signals are denoted by suffix n. For example, resetn.

Indicates command line commands and anything that must be typed exactly as it

appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.

Also indicates sections of an actual file, such as a Report File, references to parts of

files (for example, the AHDL keyword SUBDESIGN), and logic function names (for

example, TRI).

1., 2., 3., and

a., b., c., and so on.

Numbered steps indicate a list of items when the sequence of the items is important,

such as the steps listed in a procedure.

■ ■Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention.

cA caution calls attention to a condition or possible situation that can damage or

destroy the product or your work.

wA warning calls attention to a condition or possible situation that can cause you

injury.

r The angled arrow instructs you to press Enter.

f The feet direct you to more information about a particular topic.

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