OKI Semiconductor MSM514260B/BSL 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514260B/BSL is a new generation Dynamic RAM organized as 262,144-word x 16-bit configuration. The technology used to fabricate the MSM514260B/BSL is OKI's CMOS silicon gate process technology. ; The device operates at a single 5V power supply. Its 1/O pins are TTL compatible. FEATURES * Silicon gate, quadruple polysilicon CMOS, 1 transistor memory cell * 262,144-word x 16-bit organization . * Single 5V power suppiy, +10% tolerance * Input: TTL compatible * Output: TTL compatible, tristate * Refresh: 512 cycles/8ms, 512 cycles/128ms (SL version) * Fast page mode, read madify write capability * CAS betore RAS refresh, Hidden refresh, RAS only refresh capability + CAS before RAS self-refresh capability (SL version) * Package : 40-Pin 400mil Plastic SO} = (SOJ40-P-400) PRODUCT FAMILY Family Access Time (Max.) : Cycle Time Power Dissipation ' trac taa | teac | toga, (Min.) Operating (Max.} | Standby (Max.) MSM514260B/BSL-60 | 60ns ' $0ns 15s! 15ns - 110ns 1045mw MSM514260B/BSi-70 ' 70ns 35ns 20ns | 20ns | 130ns 935mW 5.5mW/ - 1,1mW (SL version) MSM514260B/BSL-80 8Ons 40ns 20ns | 20ns 180ns 8s25mwMSM514260B/8SL OECE Semiconductor PIN CONFIGURATION (TOP VIEW) Veo [1] pat [2 | Daz (3 pas [4 | pag [5 | Vec [6] bos [7] pas [8 | po [2 bas fo! NC fit} NC [12] WE [13] RAS [tal NC [15] ao [16] Ay [17| n2 (a A3 [19] Vec Bo] Sf 1$a/d0ger LSWSW 40-PIN SOJ Pin Name Function AQ - AB ' Address input Ras ' Row Address Strobe TCAS : Lower Byte Column Address Strobe UCAS ' Upper Byte Column Address Strobe Dot - Da16 Data - input / Data - Output . Output Enable Write Enable Vee : Power Supply (5V) Ves Ground (OV) NC | No Connection ote: Same power supply voltage must be provided to every Vcc pin, and same GND voitage level must be provided to every Vcc pin.OKI Semiconductor MSM514260B/8SL FUNCTIONAL BLOCK DIAGRAM WE CE ae Timing mS | Serr 0 Tors _ ! Controller s i | Output UCKS > 10 _ Butters 2 | Controlier "7 - par - 008 Coiuma Address | 3 > Column Decoders gy _inout Butters t * _ ro Sulfers internal Retresh Sense Amps s stor Ki AG AG ncress [| Contrat Clock 5 * | + input Row a A! Butters 2 ow Row = Address ay Deco- Word Memory + 009 - 0Q16 Butters ders Drivars Cells Output 3 pl = Lp 8) Butters Vee T_ : . On-chip Veg Generator Veg __ FUNCTIONAL TABLE t . j . = Jnput Pin oOoOOOoS== Da Pin Functional Mode RAS LCAS UCAS | E | O& | DQi-Das 0aG9 - DQ16 H BT High-2 High-2 Standby L H H a High-2 High-2 Retresh L L H H +: L | Dour High-2 Lower Byte Read L H L HS bo High-Z Dour Upper Byte Read L L L ee ee Dour Dour Word Read L L : H L H i Din | Don't Care Lower Byte Write L H i L L H DontCare | Din Upper Byte Write L L L L H i Din ! Diss Word Write L L L H H | High-Z | High-z MSM514260B/BSL OKI Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating | Unit Voltage on Any Pin Relative to Vss Vr | -1.010 7.0 | Vv Short Circuit Output Current los 50 | mA Power Dissipation Pp* 1 ; Ww Operating Temperature Topr Oto 70 C Storage Temperature Tstg 55 to 150 C *Ta = 25C Recommended Operating Conditions (Ta = Oto 70C) Parameter Symbol! Min. Typ. | Max, Unit Power Supply Voltage Vee 45 $.0 $5 v Vss 0 0 0 Vv Input High Voltage Vin 24 _ 6.5 V Input Low Voltage Vit =1.6 - 0.8 Vv Capacitance (Voc = 5V + 10%, Ta = 25C, f= 1MHz} Parameter | Symbol | Typ. Max. Unit input Capacitance (AQ - AB) | Gm I _ 7 pF input Capacitance | (RAS UCAS. UCAS. WE, OE) Cine ~ 7 pF Outout Capacitance (001-0016)! Cy | _ 10 pFOE I Semiconductor DC Characteristics MSM514260B/BSL (Vee = 5V + 10%, Ta = 0 to 70C) MSM5142606'/MSM514260B]MSM514260B! Parameter | Symbol Condition fB8i.60 | /BSL-70__/BSL-80_| Unit | Note | Min. |Max.| Min, |Max.| Min. iMax.! Output High Voltage | Vou | ton = -5.0mA 2.4 | Veo | 2.4 1 Voc | 241 Veo! V Output Law Voltage = Vor | lop =4.2mA 0/04/00 l04i oO foa: Vv | OV< Vi 6.5V; hy Input Leakage Current =| 1, All other pins not -10/ 10 1-10! 10 :=10: 10) wA under test = OV Output Leakage Current Io Ove Nees sy 10) 18 }-10) 10 '-10) 10; yA Average Power = . Supply Current lec: ras. wes evclng Fl ae! 470) | 450} ma | ae (Operating) RE = Nn. Power Supp! RAS, CAS = Vin j2ta~|2j~ {2 mA 1 y | 1 1 1 Current (Standby) coz | RAS, CAS 2 = = Veco - 0.2 ~~ | 200| | 200; | 200; pA | 1,5 Average Power RAS = cycling Supply Current lecs. | CAS = Vin ; 190) |} 170; | 150] ma | 3,2 (RAS Only Refresh} tac = Min. Power Supply Ras = Vin 5 A i Current (Standby) ces nae te _~ /5)] Ss 7m Average Power . RAS = cycling Supply Current i dees | wae GaE |199) | 176; | 150] ma | 1.2 (CAS Betore RAS Retresh) CAS before RAS Average Power RAS = Vi Supply Current , leer | CAS cycling 7190; 1170) 1501 ma i 1.3 (Fast Page Mode} | tec = Min. Average Power I tac = 125us 12 Supply Current lccio | CAS beforeRAS = 300 | 300, 300| pa | Ye (Battery Backup) " tans < 1us : ' Average Power Supply | HAS <02v Current (CAS Before RAS. ipgg | RAS <0. | | 200; | 200i | 200! wa 1,5 Self-Retresn) | CAS <0.2V io I | ! Notes: Specified values are obtained with the output open. Address can be changed once or less while RAS = Vit. Veo -0.2V < Vin $ 6.5V, -1.0V < Vy S02V. SL version. 1 2. 3. Address can be changed once or less while CAS = Vie. 4. 5MSM514260B/BSL AC Characteristics (1/2) OKI Semiconductor (Vee = 5V+ 10%, Ta =0 to 70C) Note 1,2. 3 Reference to RAS Parameter | symbot seams. ansestniss 7015142606/H51-a0) Unit | Note ' | Min. | Max. | Min. | Max. : Min. | Max. : Random Read or Write Cycle Time t tac | 10 | | 130 | | is0 | |_as Read Modify Write Cycie Time | tamw | 160 | | 120 1 200) 1 ne Fast Page Mode Cycle Time | toe | 40 To | 4 | ; 50: ! os Fast Page Mode Read Modify Weite Cycle Time | tpRMW | ej 1] 8s | 100, : ns Access Time trom RAS [trac | | 6 | 17 ] 80 i ns 14.5.6 Access Time from CAS | teac | | 15 | | 2) |] 2 > ns las Access Time from Column Address [ ta | | 30 | [a } ! a0 ns 4.6 Access Time from OE | toa | fs] | 20 f | 20 | ns 4 Access Time fram CAS Precharge | tepa | | 35 |= _ 40 | | 45 1 as | 4.12 Output Low Impedance Time fram CAS. | teLz 0 _ 0 -|o 70 loons | Output Suffer Turn-off Delay Time | tore Oo {1 | 0 | 5] o | 45 [ns | 7 Tr Oe fel folslolwy) ls Transition Time tr 3.) 50} 3 | so [3 | S0 | os | Refresn Perioc trer _ 8 -_ 8 _ 8 ms | Retresh Period (SL version) | tae | | 4g) [| 128 | | 128 hms | 15 RAS Precharge Time i tree | a9 f | 50, | 60 | | ns RAS Puise Wiath | tras | 60 |10.000/ 70 10,000; 80 | 10.000] ns | FAS Pulse Width (Fast Page Mode) 1 tragp | 60 f100.000| 70 _f100,000 80 110.0001 ns RAS Hold Time fasH_| 15 i | 20) [ao] | ns RAS Hold Time Reference to OE | tROH | 20 | | 20 _ | ns | CAS Precharge Time (Fast Page Mode) | icp | + | 10 | 10 Lo ns i 14 CAS Pulse Width i teas | i oo 20_|19,000! 20 |10,000: ns. CAS Hold Time * tesn | | 7 / 71 a i ios: CAS to RAS Precharge Time | tone | a i } 10 | | 0 | Ios 12 RAS to CAS Delay Time I treo | 20 | 45 | 20 | 50 | 20 | 60 | ns | RAS to Column Address Delay Time tran: 15 | 30 | 45 | 35) 15 1 40 ions | Rosy Address Set-up Time Se Row Address Hold Time i tran | 10! | 49 [|= {| 0) i ans Column Address Set-up Time : tase 0 -[|o;-1 0! fps " Column Address Hold Time aw NS Sg og ay Column Address Hold Time from RAS tar SO. | 55 i | 6 i | ns Column Address to RAS Lead Time tea! 300: | 3s | ag i ong | Read Command Set-up Time "tres oi i Qg b | oj ons: ay Read Command Hold Time trey 0 :-jo ie Pons 1811 Read Command Hald Time tarn | 0 | =~ 0 - 0 _ ns 8 !OKI Semiconductor MSM514260B/BSL AC Characteristics (2/2) (Vcc = SV + 10%, Ta = Oto 70C) Note 1.2.3 MSM t MSM MSM Parameter Symbol! !5142608/8SL-60 514260B/GSL-701S14260B/85L-80! Wnit : Note Min. | Max. | Min. | Max. Min. | Max. | Write Command Set-up Time twes 0 _ 0 0 !ons'911 Write Command Hald Time tweu 15 _ 15 _ 15 ' os q Write Command Pulse Width twp 5} ! 56 | ' 56) | os Write Command Hold Time from RAS =| twer 45 | }| 50; : 6 / os OE Command Hold Time toeH th bom 20, | 20 | ns: Write Command to CAS Lead Time tewe 15 | | 20 | | 20 | |] ns ! 13 Write Command to RAS Lead Time tawe 15 _ 20 20 _ ns, Data-in Set-up Time tos 0 0 _ 0 _ ns 110.11 Data-in Hold Time ton 15 _ 15 _ 15 _ as | 10,11 Data-in Hold Time trom RAS touR 50 |] 55 | 60 _ ms | OE to Data-in Delay Time toed 15) 5; | 1 | | os TAS to WE Delay Time tewo 3; | 45 | + 45 | | os 9 Column Address to WE Delay Time tawo 50 | | 6 | | 6 | j{ os 9 RAS to WE Delay Time tewo | 80 | | 95 | | 105 | | os 9 CAS Active Delay Time from RAS Precharge taPc Wy | Wy | wp ~ | oa | RAS to CAS Set-up Time (CAS Betore FAS) tesr 10 _ 10 _ 10 _ ns W RAS to CAS Hold Time (CAS Betore RAS) tour 20 _ 16 _ 15 _ ns 12 CAS Precharge Time (Refresh Counter Test) cer 40} | 40 > | 40 | | ns | 14 CAS Precharge Time _ ten | 10) | 10; { 10 | | ns! ta RAS Pulse Width (CAS Betore RAS Self-refresh) ! trass | 100 | | 100; | 100 | us 15 RAS Precharge Time | | (CAS Betore RAS Selt-retresh) j tres; WO) ~ | 130 | | 150) | as | 78 TAS Hold Time (CAS Betore RAS Self-retresh} tes AD | 50] | 005 | os | 18MSM514260B/BSL OKI Semiconductor Notes: bh 10. An initial pause of 200us is required after power-up followed by any 8 RAS cycles (Example: RAS only refresh) before proper device operation is achieved. The AC characteristics assume ty = 5ns. Vin(Min.) and Vj, (Max.) are reference ievels of input signals for timing measurement. Transition times(ty) are measured between Vin and V1. Measured with a load circuit equivalent to 2 TTL loads and 100pF. Operation within the tacp(Max.) limit insures that trac(Max.) can be met. troo(Max.) is specified as a reference point only: if tpcp is greater than the specified trcp(Max.) limit, then access time is controlled exclusively by tcac. Operation within the trap(Max.) limit insures that trac(Max.) can be met. trap(Max.) is specified as a reference point only: if trap is greater than the specified trap(Max.) limit, then access time is controlled exclusively by ta a. torr(Max.) and togz(Max.) define thetime at which the outputachieves the open circuit condition and are not referenced to output voltage levels. Either tray and tc} must be satisfied for a read cycle. twos. tcwp, tpwpandt,wpare not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twos 2 twos(Min.), the cycle is an early write cycle and data out will remain open circuit (high impedance) throughout the entire cycle; if tawp 2 tcwp(Min.), trwp = trwp(Min.) and tawp=tawp(Min.), the cycle ts a read modify write cycle and data out will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out {at access time) is indeterminate. These parameters are referenced to UCAS, LCAS leading edge in an early write cycle and to WE leading edge in a OE contro! write cycle or a read modify write cycle. - tasc- tcak, tres, trcH, wes, tps, ton. tcsr and tapcaredetermined by the earlier falling edge of UCAS or LCAS. torr, tcHR and tcp, are determined by the later rising edge of UCAS or LCAS. tew1 should be satistied bv both CCAS and LCAS. tcpn. tcp and tcpy are determined bv the time that both UCAS and LCAS are high. SL version.OKI Semiconductor MSM5142608/6SL TIMING WAVEFORM Read Cycle ~ VHn- RAS Vit - tere; | UCAS Vin - LOAS Vy > fasr} [tran ao-ag Row Vii 7 we Vin- WE Vi 7 Vin 7 CE Vir ~ pai-parg Yon Valid Data-out Vor Kort Write Cycle (Early Write) \ . : tras == ~ IH = : AR . f 4 AS Vit - x : 7 igre Nee i CSH , Tcap: taco tasH _ Icas UCAS Vin m4 / ie . ine RAD LCAS Vi -_/ > tasa ta tase! tcan] 'RAL AQ - AB ve TD = CTE LM wis 1 Tage ve. - LLL oo MAM wo ____!wen tawi ane MMMM Ul 1 tos tow Vin - . ta+ Vi 4 Valid Data-inp DQ1 - 0016 H orLMSM514260B/8SL OKI Semiconductor Write Cycle (OE Control Write) . lac - tH t | RAS yy - < Vi tere IN tespi _ | one | taco | tasy | , , | teas UCAS = Vin > rae Vie _ _f 1. trap tse haan tase! itean| taaL ee | | | o-aa UX = Xe CZ TTT tom trwie we yee AI me Ym UNL Vin ~ OGi-po16 yy mh Read Modify Write Cycle tras nw RPL a= (IH K se tan vi = | ga RAS oy, - N fy; cre. tt : t i Tonp: cSH Pf | taco ' tasy i | ! ! teas - UCAS Vin - - x \ f 7 LOAS Vip -__/ , fash tran = tasc.i toa ,-_= | | M098 i Ul Pom YOKE covurm ee lawo =_____tcwn a "as = + II. tag AC foe dos: | ow bO1 - pa16 vor : Tas Yor, : vai oan YT, HorOKI Semiconductor MSM514260B/BSL Fast Page Mode Read Cycle RAS AQ - A8 WE OE BQ1 - DQ16 trasp . RP | | Vin - Vin = tcp li ' teas 1 if: Vin Vin tcaH Vin ~ Vit - Row Column Cotumn tacs Vin - Vie ~ | Vin - Vir 7 Vou Vor ~ Valid Data-out "H or'L Fast Page Mode Write Cycle (Early Write) 0Q1 - 0016 Vin ~ . tar : Vn - \ | fa -! tec tas | CRP tracy ; el | : 2 cP a | ee Vin a Vit , K H i | ; tase, ; Vin ~ Vit > i anak om MMMM TTT LMM tos, | tou, tos| [ton tosi {tow poe} "WorkMSM5142608/BSL ORE Semiconductor Fast Page Mode Read Modify Write Cycle RAS ] Pa CA | AO - A& DQ: - 0Q16 Vin - Vi = Vin - Vi 7 Vin - Vi > Viq - Vi 7 Vin ~ Vi 7 Won ~ IN Vii te1z toLz H orl" RAS-only Refresh Cycle AG - AB 0O1 - 0016 tac we / | lasa tran ee ee Open Note: WE. OE = Hor 'L WorlOKI Semiconductor MSM514260B/BSL CAS Before RAS Auto Refresh Cycle tac ! tap 7 tas IR _ Lt i mas Kf N | IL i tarc | | tees I toon tesa i tcHA , pate, UCAS Mi IN VIEL. LCAS hen ary Vou po1-paig = (O47 P Open Voi Note: WE, OE, AO - AB ="H' orL H orL" Hidden Refresh Read Cycle Rag YM Viv UCAS Vin LCAS Vit V Ac: Ag (4 Vit we Vin WE Vit oe Ym mol tac atcuZ, | LtOe2.| . Vor - }____ DO1 - 0O16 Vo Open _ix- Valid Data-out WHA Hor L"MSM514260B/BSL OKI Semiconductor Hidden Refresh Write Cycle =a > | UCAS [CAS mons Yee sac Tei IO tsp a "= = TTT twer i oe ne LLL LLM LLM HMM oe H" orL al CAS Before RAS Self-retresh Cycle i. _tre taass .__[nes Vin - a > RAS Vii - A tape ee yy NO teeny | OSA. apc teen tens TCAS Vy - __/ * lore pot-paig Yor~ * 0 VoL - soo Open Note: WE. TE, AQ-A8= "Hort PAH or'L SL versionOKI Semiconductor MSM514260B/BSL CAS Before RAS Refrash Counter Test Cycle i be thas tar RAS Vin - 7 | t A Vir - x. \ tesa tour tcpt irs UCAS Vw - [CAS VL {ea Ao-ag iq - Column Vii > : Read Cycie tac we VM - Vin 7 Vin - Vir 7 Vou - Dai-pare 4H Open Valid Oata-out fawe i ~t P| ee MMMM: tpg | | tow 2 par-oa16 = YH - Open X Vin i Valid Data-in Read Modity Write Cycte : two : : 00 SA = * II Vv - 001-po1g =| YOK ~ Open Vue WH orL