VBUS54ED-FBL
www.vishay.com Vishay Semiconductors
Rev. 1.1, 17-Aug-12 1Document Number: 82414
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
4-Line BUS-Port ESD Protection - Flow Through Design
MARKING (example only)
Dot = pin 1 marking
YY = type code (see table below)
XX = date code
FEATURES
• Compact LLP2510-10L package
• Low package height < 0.6 mm
• 4-line ESD-protection
• Low leakage current IR < 0.1 μA
• Low capacitance between I/O lines: 0.3 pF
• Ideal for high speed data line like
- HDMI, DisplayPort, eSATA
- USB, 1394/firewire
- Thunderbolt
• ESD-protection acc. IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
• Soldering can be checked by standard vision inspection.
No X-ray necessary
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
22551
nc.GND
GND D2+
12345
9876
nc.nc. nc.
D2-D1+ D1-
22552
10
YYXX
20720
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY
VBUS54ED-FBL VBUS54ED-FBL-G4-08 3000 15 000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VBUS54ED-FBL LLP2510-10L L5 3.9 mg UL 94 V-0 MSL level 1
(according J-STD-020) 260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current Acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 2A
Peak pulse power Acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 25 W
ESD immunity Contact discharge acc. IEC 61000-4-2; 10 pulses VESD
± 15 kV
Air discharge acc. IEC 61000-4-2; 10 pulses ± 15
Operating temperature Junction temperature TJ- 40 to + 125 °C
Storage temperature TSTG - 55 to + 150 °C
VBUS54ED-FBL
www.vishay.com Vishay Semiconductors
Rev. 1.1, 17-Aug-12 2Document Number: 82414
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
The VBUS54ED-FBL is a four-line ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a
very low capacitance which makes it usable for high frequency applications like USB2.0, USB3.0 or HDMI.
With the VBUS54ED-FBL four high speed data lines can be protected against transient voltage signals like ESD (Electro Static
Discharge). Connected to the data line (pin 1, 2 and pin 4, 5) and to ground (pin 3 and 8) negative transients will be clamped
close below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping
behaviour of the VBUS54ED-FBL is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications
running up to 5.5 V.
Pin configuration:
• Pin 3 and 8 are internally shorted and have to be connected to ground
• Pin 1, 2 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2-
• Pin 6, 7 and 9, 10 are not connected internally
FLOW THROUGH DESIGN
Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI).
At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding
their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated
depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected
to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and
distances.
With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the
VBUS54ED-FBL is placed on top without any vias or loops.
ELECTRICAL CHARACTERISTICS (pin 1, 2, 4 or 5 to pin 3)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of lines which can be protected Nchannel --4lines
Reverse stand-off voltage Max. reverse working voltage VRWM --5.5V
Reverse voltage at IR = 0.1 μA VR5.5 - - V
Reverse current at VRWM = 5.5 V IR- 0.02 0.1 μA
Reverse breakdown voltage at IR = 1 mA VBR 6.9 7.5 8.7 V
Reverse clamping voltage at IPP = 1 A VC-9.111V
at IPP = IPPM = 2 A VC- 10.3 12.5 V
Forward clamping voltage at IPP = 1 A VF-1.92.2V
at IPP = 2 A VF-2.53.1V
Capacitance at VR = 0 V; f = 1 MHz CD
-0.70.8pF
at VR = 3.3 V; f = 1 MHz - 0.6 0.8 pF
Capacitance between I/O lines at VR = 3.3 V; f = 1 MHz CDD -0.30.4pF
nc.GND
GND D2+
12345
9876
nc.nc. nc.
D2-D1+ D1-
22552
10
matched pair
matched pair
12345
10 9 8 7 6
USB / HDMI Interface
D2+ D2-D1+ D1-
GND D2+ D2-D1+ D1-
I/O Port Connector
------
22553
VBUS54ED-FBL
www.vishay.com Vishay Semiconductors
Rev. 1.1, 17-Aug-12 3Document Number: 82414
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
CONNECTION DIAGRAM EXAMPLE FOR THUNDERBOLT DATA PORT
CONNECTION DIAGRAM EXAMPLE FOR USB 3.0 DATA PORT
CONNECTION DIAGRAM EXAMPLE FOR HDMI DATA PORT
22652
3 x VBUS54ED-FBL
CFG1
CFG2
DP3+
DP3-
AUX+
AUX-
DP0+
DP0-
DP1+
DP1-
DP2+
DP2-
Display Port
mode
Connector
12345
109876
12345
109876
12345
109876
Cio0_RX-
Cio0_RX+
-
-
Cio1_RX-
Cio1_RX+
Cio0_TX-
Cio0_TX+
Lsx_tx-ctrl
Lsx_rx-ctrl
Cio1_TX-
Cio1_TX+
Thunderbolt
mode
Pin 4
Pin 6
Pin 10
Pin 12
Pin 16
Pin 18
Pin 3
Pin 5
Pin 9
Pin 11
Pin 15
Pin 17
VBUS54ED-FBL VBUS052CD-FAH
22653
D-
D+
GND
VBUS
Pwr Gnd
SSRX-
SSRX+
SSTX-
SSTX+
USB 3.0
Transmitter
USB 3.0
Connector
12345
10 9 8 7 6
123
654
7
VBUS
D-
D+
Pwr Gnd
SSRX-
SSRX+
GND
SSTX-
SSTX+
2 x VBUS54ED-FBL
22654
TMDS D2+
TMDS D2-
TMDS D1+
TMDS D1-
TMDS D0+
TMDS D0-
TMDS Clock+
TMDS Clock-
HDMI
Transmitter
HDMI
Connector
12345
109876
12345
109876
TMDS D2+
TMDS D2-
TMDS D1+
TMDS D1-
TMDS D0+
TMDS D0-
TMDS Clock+
TMDS Clock-
VBUS54ED-FBL
www.vishay.com Vishay Semiconductors
Rev. 1.1, 17-Aug-12 4Document Number: 82414
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs.
Reverse Current IR
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
0 %
20 %
40 %
60 %
80 %
100 %
120 %
- 10 0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Discharge Current IESD
Rise time = 0.7 ns to 1 ns
53 %
27 %
20557
0 %
20 %
40 %
60 %
80 %
100 %
010203040
Time (µs)
I
PPM
20 µs to 50 %
8 µs to 100 %
20548
f = 1 MHz
Pin 1, 2, 4 or 5 to Pin 3 and 8
0.001
0.01
0.1
1
10
100
0.5 0.6 0.7 0.8 0.9 1 1.1
22555 VF (V)
IF (mA)
BiAs-mode
0
1
2
3
4
5
6
7
8
0.01 0.1 1 10 100 1000 10 000
Pin 1, 2, 4 or 5 to Pin 3
22556
IR (µA)
VR (V)
- 6
- 4
- 2
0
2
4
6
8
10
12
14
0123
VC
Pin 1, 2, 4 or 5 to Pin 3
(reverse)
Pin 3 to Pin 1, 2, 4 or 5
(forward)
Measured acc. IEC 61000-4-5
(8/20 μs - wave form)
I
PP
(A)
V
C
(V)
VBUS54ED-FBL
www.vishay.com Vishay Semiconductors
Rev. 1.1, 17-Aug-12 5Document Number: 82414
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Clamping Performance at 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 8 - Typical Clamping Performance at 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 9 - Typical Peak Clamping Voltage at ESD
Contact Discharge (acc. IEC 61000-4-2)
- 20
0
20
40
60
80
100
- 10 0 10 20 30 40 50 60 70 80 90
t (ns)
V
C-ESD
(V)
22558
Acc. IEC 61000-4-2
+ 8 kV
contact discharge
- 120
- 100
- 80
- 60
- 40
- 20
0
20
- 10 010 20 30 40 50 60 70 80 90
t (ns)
VC-ESD (V)
22559
Acc. IEC 61000-4-2
- 8 kV
contact discharge
- 40
- 30
- 20
- 10
0
10
20
30
40
50
60
0 5 10 15 20
Clamping voltage measured
after 30 ns
Acc. IEC 61000-4-2
contact discharge
V
ESD
(kV)
V
C-ESD
(V)
VBUS54ED-FBL
www.vishay.com Vishay Semiconductors
Rev. 1.1, 17-Aug-12 6Document Number: 82414
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PACKAGE DIMENSIONS in millimeters: LLP2510-10L
foot print recommendation:
Created - Date: 08. July 2011
Document no.: S8-V-3906.04-027 (4)
Package = Chip Dimensions in mm
solder
resist mask
solder pad
0.5 0.25
4 x 0.5 = 2
0.5
0.35
PIN 1 marking
b
e
L
A1
A3
PIN 1 identication
Chamfer
D
E
Millimeters
A
A1
A3
D
E
e
L
min. nom. max.
0.50
2.45
0.95
0.30
0.55
0.15
2.50
1.00
0.50
0.35
0.60
0.05
2.55
1.05
0.40
0.00 -
--
b0.15 0.20 0.25
--
L
A
1
0.15
22587
LLP2510
Top view pad layout - view from top
seen at bottom side
Pin 1 - Location
S8-V-3906.04-029 (4)
date: 07.07.2011
22588
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 02-Oct-12 1Document Number: 91000
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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