LC04-6 Dual Low Capacitance TVS Array for Telecom Linecard Applications PROTECTION PRODUCTS Description Features The LC04-6 has been specifically designed to protect sensitive components which are connected to highspeed telecommunications lines from over voltages caused by lightning, electrostatic discharge (ESD), cable discharge events (CDE), and electrical fast transients (EFT). Transient protection for high-speed data lines to The device is in a JEDEC SO-16 NB package. It is designed to provide metallic surge protection for two tip and ring line pairs. The low capacitance topology means signal integrity is preserved on high-speed lines. The high surge capability (1000W, tp=10/1000s) makes the LC04-6 suitable for telecommunications systems operating in harsh transient environments. Mechanical Characteristics The LC04-6 is designed to meet the lightning surge requirements of Bellcore GR-1089 (Intra-building) , FCC Part 68, ITU K.20, and IEC 61000-4-5. The features of the LC04-6 are ideal for protecting T1/E1 transceivers in WAN applications. Circuit Diagram RING JEDEC SO-16 package Molding compound flammability rating: UL 94V-0 Marking : Part number, date code, logo Packaging : Tube or Tape and Reel per EIA 481 Applications TIP Bellcore GR-1089 IPP=70A (10/1000s) Bellcore GR 1089 IPP=100A (2/10s) ITU K.20 IPP=100A (5/310s) IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 100A (8/20s) Protects two tip and ring line pairs Low capacitance for high-speed interfaces High surge capability Low clamping voltage Solid-state silicon avalanche technology T1/E1 Line Cards Base Stations WAN Equipment CSU/DSU Multiplexers Routers ISP Equipment Customer Premise Equipment Schematic & PIN Configuration Pin 1 - 4 Pin 13 - 16 SO-16 (Top View) Revision 04/12/05 1 www.semtech.com LC04-6 PROTECTION PRODUCTS Absolute Maximum Rating R ating Symbo l Value Units Peak Pulse Power (tp = 10/1000 s) Pp k 1000 Watts Peak Pulse Current (tp = 10/1000 s) IP P 70 A Peak Pulse Current (tp = 8/20 s) IP P 200 A Peak Pulse Current (tp = 10/560 s) IP P 100 A Lead Soldering Temp erature TL 260 (10 sec.) C Op erating Temp erature TJ -55 to +125 C TSTG -55 to +150 C Storage Temp erature Electrical Characteristics LC04-6 Par ame te r Symbo l Co nditio ns Minimum Typical Maximum Units 6 V Reverse Stand-Off Voltage VRWM Reverse Breakdown Voltage V BR It = 1mA IR VRWM = 6V, T=25C 15 A VRWM = 3V, T=25C 2 A Reverse Leakage Current 6.8 V Clamp ing Voltage VC IPP = 10A, tp = 10/1000s 12.5 V Clamp ing Voltage VC IPP = 70A, tp = 10/1000s 15 V Clamp ing Voltage VC IPP = 100A, tp = 8/20s 20 V Junction Cap acitance Cj Each Line VR = 0V, f = 1MHz 15 pF 2005 Semtech Corp. 2 www.semtech.com LC04-6 PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 110 100 % of Rated Power or PI P Peak Pulse Power - Ppk (kW) 100 10 90 80 70 60 50 40 30 20 10 0 1 0.1 1 10 100 0 1000 25 50 75 100 125 150 Ambient Temperature - TA (o C) Pulse Duration - tp (s) Pulse Waveform Clamping Voltage vs. Peak Pulse Current 110 80 70 e 60 -t 50 40 12 Clamping Voltage - VC (V) 90 Percent of IPP 14 Waveform Parameter tr = 8s td = 20s 100 td = IPP/2 30 20 10 8 6 Waveform Parameters: tr = 10s td = 1000s 4 2 10 0 0 0 5 10 15 20 25 0 30 10 20 40 50 60 70 80 Clamping Voltage vs. Peak Pulse Current Capacitance vs. Reverse Voltage 25 14 Clamping Voltage - VC (V) 12 Capacitance - Cj (pF) 30 Peak Pulse Current - IPP (A) Time (s) 10 8 6 4 2 20 15 10 Waveform Parameters: tr = 8s td = 20s 5 f=1MHz 0 0 0 1 2 3 4 5 6 7 0 Reverse Voltage - VR (V) 2005 Semtech Corp. 20 40 60 80 100 120 140 160 180 200 Peak Pulse Current - IPP (A) 3 www.semtech.com LC04-6 PROTECTION PRODUCTS Applications Information Device Connection Options for Protection of Two High-Speed Line Pairs Figure 1 - Connection for Differential (Line-to-Line) Protection of two Tip/Ring Line Pairs The LC04-6 is designed to protect four high-speed data lines (two differential pairs) from transient over-voltages which result from lightning and ESD. Protection of two line pairs is achieved by connecting the device as follows: Pins 1-4 are connected to line 1 of the first pair (i.e. Tip 1) and pins 13-16 are connected to line 2 of the first pair (i.e. Ring 1). Pins 5-8 are connected to line 1 of the second pair (i.e. Tip 2) and pins 9-12 are connected to line two of the second pair (i.e. Ring 2). All pins should be connected for best results. Minimize parasitic inductance in the protection circuit path by keeping the trace length between the protected line and the LC04-6 as short as possible. TIP 1 RING 1 TIP 2 RING 2 T1/E1 Linecard Protection A typical T1/E1 linecard protection circuit is shown in Figure 2. The LC04-6 is connected between Tip and Ring on the transmit and receive line pairs. It provides protection to metallic (line-to-line) lightning and ESD surges. It is designed to meet the intra-building requirements of Bellcore GR-1089. This design takes advantage of the isolation of the transformer to suppress common mode surges. The LC04-6 may also be configured to meet metallic surges of FCC Part68 when used in conjunction with a 5 (minimum) PTC or line feed resistor (LFR). The PTC (or LFR + fuse) are required to meet the AC power cross requirements, but will also reduce the effective surge current to levels within the capability of the LC04-6 (Table 1). To complete the protection circuit, the SRDA05-4 (or SRDA3.3-4 for 3.3V supplies) is employed as the IC side protection element. This device helps prevent the transceiver from latching up by providing fine clamping of transients that are coupled through the transformer. The versatility of the LC04-6 makes it ideal for use with combination long haul/short haul T1/E1 transceivers. 2005 Semtech Corp. Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint. 4 www.semtech.com LC04-6 PROTECTION PRODUCTS Typical Applications Figure 2 - T1/E1 Line Card protection Immunity Standar d Pe ak Ope n Cir cuit Sur ge Vo ltage Cur r e nt Wave fo r m (s) Pe ak Sho r t Cir cuit Sur ge Cur r e nt (A) Sur ge Ge ne r ato r So ur ce R e sistance (W) To tal So ur ce R e sistance (w ith 5W PTC o r LFC) (W) Effe ctive Sho r t Sir cuit Cur r e nt (A) ( V) Be llco r e GR -1089 Intr a-Building 800 2/10 100 8 13 61.5 FCC Par t 68 1500 10/160 200 7.5 12.5 120 Table 1 2005 Semtech Corp. 5 www.semtech.com LC04-6 PROTECTION PRODUCTS Outline Drawing - SO-16 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX h A D e N h H 2X E/2 E1 E c GAGE PLANE 0.25 ccc C 1 L (L1) DETAIL 3 2 01 A e/2 2X N/2 TIPS B D SEE DETAIL SIDE VIEW aaa C A A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc .053 .069 .004 .010 .049 .065 .012 .020 .007 .010 .386 .390 .394 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 16 0 8 .004 .010 .008 1.35 1.75 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 9.80 9.90 10.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 16 0 8 0.10 0.25 0.20 A2 A SEATING PLANE C A1 bxN bbb C A-B D NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AC. Land Pattern - SO-16 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 304A. 2005 Semtech Corp. 6 www.semtech.com LC04-6 PROTECTION PRODUCTS Ordering Information Part Number Lead Finish Qty per Reel Reel Size LC04-6.TB SnPb 500 7 Inch LC04-6 SnPb 48/Tube N/A Contact Information Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 7 www.semtech.com Semtech ProductsApplicationsDesign SupportQualityCompany InvestorsCareersOrderingContact Us SEARCH Advanced Search Power Management ICs Circuit Protection Advanced Communications Test & Measurement Power Discretes Wireless & Sensing Printable Version Home \\ Products \\ LC04-6 LC04-6: Dual Low-Capacitance TVS Array for Telecom Linecard Applications The LC04-6 has been specifically designed to protect sensitive components which are connected to high-speed telecommunications lines from over voltages caused by lightning, electrostatic discharge (ESD), cable discharge events (CDE), and electrical fast transients (EFT). Collapse All Features Transient protection for high-speed data lines to Bellcore GR-1089 IPP = 70 A (10/1000 s) Bellcore GR 1089 IPP = 100 A (2/10 s) ITU K.20 IPP=100A (5/310 s) IEC 61000-4-2 (ESD) 15 kV (air), 8 kV (contact) IEC 61000-4-4 (EFT) 40 A (5/50 ns) IEC 61000-4-5 (Lightning) 100 A (8/20 s) Protects two tip-and-ring line pairs Low capacitance for high-speed interfaces High surge capability Low clamping voltage Solid-state silicon-avalanche technology Diagrams Circuit Diagram Click diagram to enlarge Schematic & PIN Configuration Click diagram to enlarge Applications T1/E1 line cards Base stations WAN equipment CSU/DSU Multiplexers Routers ISP equipment Customer premise equipment Packaging SO-16 Order Codes LC04-6.TBT: Lead-free, RoHS and WEEE compliant, 500 pcs. Tape & Reel Datasheets LC04-6 Datasheet (PDF 170KB, 9/06) Application Matrices TVS Applications Matrix - Telecom (PDF 50KB, 9/05) TVS Applications Matrix - Standards (PDF 49KB, 9/05) Application Notes Calculating Transient Energy - SI97-02 (PDF 61KB, 4/08) Low Capacitance Devices - SI96-07 (PDF 40KB, 5/06) TVS Diode Selection - SI96-02 (PDF 64KB, 4/08) Disadvantage of On-Chip Transient Protection - SI97-04 (PDF 107KB, 4/08) TVS Peak Pulse Power vs. Pulse Duration - SI96-03 (PDF 49KB, 4/06) PCB Design Guidelines for ESD Suppression - SI99-01 (PDF 118KB, 4/08) Unidirectional and Bidirectional Operation - SI96-05 (PDF 35KB, 4/06) Transient Immunity Standards: Bellcore TR-NWT-001089 and FCC Part 68 - AN96-08 (PDF 83KB, 4/08) Transient Immunity Standards: IEC 61000-4-x - AN96-07 (PDF 48KB, 4/08) Lightning Immunity Requirements of ITU-T K.20 and K.21 - SI99-03 (PDF 104KB, 4/08) Calculating Clamping Voltage at Different Peak Pulse Currents - SI97-03 (PDF 54KB, 4/06) TVS Diode Loading Capacitance vs. Data Transmission Rate - SI96-08 (PDF 76KB, 4/08) What are TVS Diodes? - SI96-01 (PDF 59KB, 5/08) Surge Protection of ISDN S/T-Interfaces - SI96-15 (PDF 92KB, 4/08) Sources of Transients: Lightning - SI96-09 (PDF 61KB, 5/06) TVS Power Derating vs. Temperature - SI96-04 (PDF 41KB, 4/06) (c) 2008 SemtechPrivacy PolicyTerms of UseSite MapFeedbackMedia Center