PWM Controller and Transformer
Driver with Quad-Channel Isolators
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
FEATURES
Isolated PWM controller
Integrated transformer driver
Regulated adjustable output: 3.3 V to 24 V
2 W output power
70% efficiency at guaranteed load of 400 mA at 5.0 V output
Quad dc-to-25 Mbps (NRZ) signal isolation channels
20-lead SSOP package
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/µs
200 kHz to 1 MHz adjustable oscillator frequency
Soft start function at power-up
Pulse-by-pulse overcurrent protection
Thermal shutdown
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
Qualified for automotive applications
APPLICATIONS
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Power supply start-up bias and gate drives
Isolated sensor interfaces
Process controls
Automotive
GENERAL DESCRIPTION
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/
ADuM3474 devices1 are quad-channel digital isolators with an
integrated PWM controller and transformer driver for an isolated
dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler®
technology, the dc-to-dc converter provides up to 2 W of regulated,
isolated power at 3.3 V to 24 V from a 5.0 V input supply or from
a 3.3 V supply. This eliminates the need for a separate, isolated
dc-to-dc converter in 2 W isolated designs. The iCoupler chip scale
transformer technology is used to isolate the logic signals, and the
integrated transformer driver with isolated secondary side control
provides higher efficiency for the isolated dc-to-dc converter. The
result is a small form factor, total isolation solution. The ADuM347x
isolators provide four independent isolation channels in a variety of
channel configurations and data rates (see the Ordering Guide).
FUNCTIONAL BLOCK DIAGRAMS
ADuM3470/ADuM3471/
ADuM3472/ADuM3473/
ADuM3474
09369-001
PRIMARY
CONVERTER
DRIVER
PRIMARY
DATA
I/O
4CH
SECONDARY
DATA
I/O
4CH
SECONDARY
CONTROLLER
CH A
FB
T1
CH B
CH C
CH D
V
DD2
OC
FB
V
REG
V
IA
/V
OA
V
DD1
V
DDA
X2
X1
V
IB
/V
OB
V
IC
/V
OC
V
ID
/V
OD
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
ID
/V
OD
GND
1
GND
2
REG
RECT
5V
V
ISO
Figure 1. Functional Block Diagram
09369-003
ADuM3470 ADuM3471
ADuM3472
ADuM3473 ADuM3474
Figure 2. Block Diagrams of I/O Channels
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Primary Input Supply/
5 V Secondary Isolated Supply ................................................... 3
Electrical Characteristics—3.3 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 5
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 7
Electrical Characteristics—5 V Primary Input Supply/
15 V Secondary Isolated Supply ................................................. 9
Package Characteristics ............................................................. 11
Regulatory Approvals ................................................................. 11
Insulation and Safety-Related Specifications .......................... 11
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics .......................................................... 12
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings .......................................................... 13
ESD Caution ................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 19
Terminology .................................................................................... 24
Applications Information .............................................................. 25
Application Schematics ............................................................. 25
Transformer Design ................................................................... 26
Transformer Turns Ratio ........................................................... 26
Transformer ET Constant ......................................................... 27
Transformer Primary Inductance and Resistance ................. 27
Transformer Isolation Voltage .................................................. 27
Switching Frequency .................................................................. 27
Transient Response .................................................................... 27
Component Selection ................................................................ 27
Printed Circuit Board (PCB) Layout ....................................... 28
Thermal Analysis ....................................................................... 28
Propagation Delay-Related Parameters ................................... 28
DC Correctness and Magnetic Field Immunity ..................... 29
Power Consumption .................................................................. 30
Power Considerations ................................................................ 30
Insulation Lifetime ..................................................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 33
Automotive Products ................................................................. 33
REVISION HISTORY
5/14—Rev. A to Rev. B
Change to Table 4 ............................................................................. 9
7/13—Rev. 0 to Rev. A
Changed VDD1 Pin to NC Pin ....................................... Throughout
Changes to Features Section, Applications Section,
General Description Section, and Figure 1 ................................... 1
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section ................................................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 4 ............................................................................ 9
Changes to Regulatory Approvals Section .................................. 11
Changes to Figure 3 and Table 9 ................................................... 12
Changes to Figure 4 and Table 12 ................................................. 14
Changes to Figure 5 and Table 13 ................................................. 15
Changes to Figure 6 and Table 14................................................. 16
Changes to Figure 7 and Table 15................................................. 17
Changes to Figure 8, Table 16, and Table 17 ............................... 18
Change to Figure 9 ......................................................................... 19
Changes to Terminology Section ................................................. 24
Changes to Applications Information Section, Application
Schematics Section, Figure 38, Figure 39, and Figure 40 .......... 25
Changes to Transformer Turns Ratio Section ............................ 26
Changes to Transformer ET Constant Section,
Transient Response Section, and Table 19 .................................. 27
Changes to Figure 41 ...................................................................... 28
Changes to Power Consumption Section and Figure 45 ........... 30
Changes to Insulation Lifetime Section and Figure 48 ............. 31
Changes to Ordering Guide .......................................................... 33
Added Automotive Products Section .......................................... 33
10/10—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VDD2 = VREG = VISO = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 5.0 V.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage
V
ISO
4.5
5.0
5.5
V
I
ISO
= 0 mA, V
ISO
= V
FB
× (R1 + R2)/R2
Feedback Voltage Setpoint VFB 1.125 1.25 1.375 V IISO = 0 mA
Line Regulation VISO (LINE) 1 10 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1 2 % IISO = 50 mA to 200 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Output Noise
V
ISO (N)
100
mV p-p
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Switching Frequency fSW 1000 kHz ROC = 50 kΩ
200 kHz ROC = 270 kΩ
192 318 515 kHz VOC = VDD2 (open loop)
Switch On Resistance RON 0.5 Ω
Undervoltage Lockout, VDD1, VDD2
Supplies
Positive Going Threshold VUV+ 2.8 V
Negative Going Threshold VUV− 2.6 V
Hysteresis VUVH 0.2 V
DC to 2 Mbps Data Rate
1
f ≤ 1 MHz
Maximum Output Supply Current2 IISO (MAX) 400 mA VISO = 5.0 V
Efficiency at Maximum Output
Supply Current3
70 % IISO = IISO (MAX)
i
COUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
I
DD1
Supply Current, No V
ISO
Load
I
DD1 (Q)
I
ISO
= 0 mA, f ≤ 1 MHz
ADuM3470 14 30 mA
ADuM3471 15 30 mA
ADuM3472 16 30 mA
ADuM3473 17 30 mA
ADuM3474 18 30 mA
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load IDD1 (D) IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
ADuM3470 44 mA
ADuM3471 46 mA
ADuM3472 48 mA
ADuM3473
50
mA
ADuM3474 52 mA
Available VISO Supply Current4 IISO (LOAD) CL = 15 pF, f = 12.5 MHz
ADuM3470 390 mA
ADuM3471 388 mA
ADuM3472 386 mA
ADuM3473 384 mA
ADuM3474 382 mA
IDD1 Supply Current, Full VISO Load IDD1 (MAX) 550 mA CL = 0 pF, f = 0 MHz, VDD1 = 5 V,
IISO = 400 mA
Rev. B | Page 3 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
I/O Input Currents IIA, IIB, IIC, IID −20 +0.01 +20 µA
Logic High Input Threshold VIH 2.0 V
Logic Low Input Threshold VIL 0.8 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
VDD1 − 0.3,
VISO − 0.3
5.0 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.5,
VISO − 0.5
4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
AC SPECIFICATIONS
A Grade CL = 15 pF, CMOS signal levels
Minimum Pulse Width PW 1000 ns
Maximum Data Rate
1
Mbps
Propagation Delay tPHL, tPLH 55 100 ns
Pulse Width Distortion, |tPLH − tPHL| PWD 40 ns
Propagation Delay Skew tPSK 50 ns
Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns
C Grade
C
L
= 15 pF, CMOS signal levels
Minimum Pulse Width PW 40 ns
Maximum Data Rate 25 Mbps
Propagation Delay tPHL, tPLH 30 45 60 ns
Pulse Width Distortion, |tPLH − tPHL| PWD 8 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
t
PSK
15
ns
Channel-to-Channel Matching
Codirectional Channels tPSKCD 8 ns
Opposing Directional Channels tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity VCM = 1000 V, transient
magnitude = 800 V
At Logic High Output |CMH| 25 35 kV/µs VIx = VDD1 or VISO
At Logic Low Output |CML| 25 35 kV/µs VIx = 0 V
Refresh Rate fr 1.0 Mbps
1 The contributions of supply current values for all four channels are combined at identical data rates.
2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
Rev. B | Page 4 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V ≤ VDD1 = VDDA ≤ 3.6 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 3.3 V, VDD2 = VREG = VISO = 3.3 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage VISO 3.0 3.3 3.6 V IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
Feedback Voltage Setpoint VFB 1.125 1.25 1.375 V IISO = 0 mA
Line Regulation VISO (LINE) 1 10 mV/V IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
Load Regulation VISO (LOAD) 1 2 % IISO = 20 mA to 100 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Output Noise VISO (N) 100 mV p-p 20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Switching Frequency
f
SW
1000
kHz
R
OC
= 50 kΩ
200 kHz ROC = 270 kΩ
192 318 515 kHz VOC = VDD2 (open loop)
Switch On Resistance RON 0.6 Ω
Undervoltage Lockout, VDD1, VDD2
Supplies
Positive Going Threshold VUV+ 2.8 V
Negative Going Threshold VUV− 2.6 V
Hysteresis VUVH 0.2 V
DC to 2 Mbps Data Rate1 f ≤ 1 MHz,
Maximum Output Supply Current2 IISO (MAX) 250 mA VISO = 3.3 V
Efficiency at Maximum Output
Supply Current3
70
%
I
ISO
= I
ISO
(MAX)
i
COUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load IDD1 (Q) IISO = 0 mA, f ≤ 1 MHz
ADuM3470 9 20 mA
ADuM3471
10
20
mA
ADuM3472 11 20 mA
ADuM3473 11 20 mA
ADuM3474 12 20 mA
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load IDD1 (D) IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
ADuM3470
28
mA
ADuM3471 29 mA
ADuM3472 31 mA
ADuM3473 32 mA
ADuM3474 34 mA
Available V
ISO
Supply Current4
I
ISO (LOAD)
C
L
= 15 pF, f = 12.5 MHz
ADuM3470 244 mA
ADuM3471 243 mA
ADuM3472 241 mA
ADuM3473 240 mA
ADuM3474 238 mA
I
DD1
Supply Current, Full V
ISO
Load
I
DD1 (MAX)
350
mA
CL = 0 pF, f = 0 MHz, VDD1 = 3.3 V,
IISO = 250 mA
I/O Input Currents IIA, IIB, IIC, IID −10 +0.01 +10 µA
Rev. B | Page 5 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Logic High Input Threshold VIH 1.6 V
Logic Low Input Threshold VIL 0.4 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
VDD1 − 0.3,
VISO − 0.3
5.0 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.5,
VISO − 0.5
4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
AC SPECIFICATIONS
A Grade CL = 15 pF, CMOS signal levels
Minimum Pulse Width PW 1000 ns
Maximum Data Rate 1 Mbps
Propagation Delay
t
PHL
, t
PLH
60
100
ns
Pulse Width Distortion, |tPLH − tPHL| PWD 40 ns
Propagation Delay Skew tPSK 50 ns
Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns
C Grade CL = 15 pF, CMOS signal levels
Minimum Pulse Width
PW
40
ns
Maximum Data Rate 25 Mbps
Propagation Delay tPHL, tPLH 30 60 75 ns
Pulse Width Distortion, |tPLH − tPHL| PWD 8 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew tPSK 45 ns
Channel-to-Channel Matching
Codirectional Channels tPSKCD 8 ns
Opposing Directional Channels tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity VCM = 1000 V, transient
magnitude = 800 V
At Logic High Output |CMH| 25 35 kV/µs VIx = VDD1 or VISO
At Logic Low Output |CML| 25 35 kV/µs VIx = 0 V
Refresh Rate fr 1.0 Mbps
1 The contributions of supply current values for all four channels are combined at identical data rates.
2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
Rev. B | Page 6 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 3.3 V.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage VISO 3.0 3.3 3.6 V IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
Feedback Voltage Setpoint VFB 1.125 1.25 1.375 V IISO = 0 mA
Line Regulation VISO (LINE) 1 10 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1 2 % IISO = 50 mA to 200 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Output Noise VISO (N) 100 mV p-p 20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Switching Frequency
f
SW
1000
kHz
R
OC
= 50 kΩ
200 kHz ROC = 270 kΩ
192 318 515 kHz VOC = VDD2 (open loop)
Switch On Resistance RON 0.5 Ω
Undervoltage Lockout, VDD1, VDD2
Supplies
Positive Going Threshold VUV+ 2.8 V
Negative Going Threshold VUV− 2.6 V
Hysteresis VUVH 0.2 V
DC to 2 Mbps Data Rate1 f ≤ 1 MHz
Maximum Output Supply Current2 IISO (MAX) 400 mA VISO = 3.3 V
Efficiency at Maximum Output
Supply Current3
70
%
I
ISO
= I
ISO
(MAX)
i
COUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load IDD1 (Q) IISO = 0 mA, f ≤ 1 MHz
ADuM3470 9 30 mA
ADuM3471
9
30
mA
ADuM3472 10 30 mA
ADuM3473 10 30 mA
ADuM3474 10 30 mA
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load IDD1 (D) IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
ADuM3470
33
mA
ADuM3471 33 mA
ADuM3472 33 mA
ADuM3473 33 mA
ADuM3474 33 mA
Available V
ISO
Supply Current4
I
ISO (LOAD)
C
L
= 15 pF, f = 12.5 MHz
ADuM3470 393 mA
ADuM3471 392 mA
ADuM3472 390 mA
ADuM3473 389 mA
ADuM3474 388 mA
I
DD1
Supply Current, Full V
ISO
Load
I
DD1 (MAX)
375
mA
CL = 0 pF, f = 0 MHz, VDD1 = 5 V,
IISO = 400 mA
I/O Input Currents IIA, IIB, IIC, IID −20 +0.01 +20 µA
Rev. B | Page 7 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Logic High Input Threshold VIH 2.0 V
Logic Low Input Threshold VIL 0.8 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
VDD1 − 0.3,
VISO − 0.3
5.0 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.5,
VISO − 0.5
4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
AC SPECIFICATIONS
A Grade CL = 15 pF, CMOS signal levels
Minimum Pulse Width PW 1000 ns
Maximum Data Rate 1 Mbps
Propagation Delay
t
PHL
, t
PLH
55
100
ns
Pulse Width Distortion, |tPLH − tPHL| PWD 40 ns
Propagation Delay Skew tPSK 50 ns
Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns
C Grade CL = 15 pF, CMOS signal levels
Minimum Pulse Width
PW
40
ns
Maximum Data Rate 25 Mbps
Propagation Delay tPHL, tPLH 30 50 70 ns
Pulse Width Distortion, |tPLH − tPHL| PWD 8 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew tPSK 15 ns
Channel-to-Channel Matching
Codirectional Channels tPSKCD 8 ns
Opposing Directional Channels tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity VCM = 1000 V, transient
magnitude = 800 V
At Logic High Output |CMH| 25 35 kV/µs VIx = VDD1 or VISO
At Logic Low Output |CML| 25 35 kV/µs VIx = 0 V
Refresh Rate fr 1.0 Mbps
1 The contributions of supply current values for all four channels are combined at identical data rates.
2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
Rev. B | Page 8 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/15 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VREG = VISO = 15 V; VDD2 = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 39). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VREG = VISO = 15 V, VDD2 = 5.0 V.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage VISO 13.5 15 16.5 V IISO = 0 mA, VISO = VFB × (R1 + R2)/R2
Feedback Voltage Setpoint VFB 1.125 1.25 1.375 V IISO = 0 mA
VDD2 Linear Regulator
Regulator Voltage
V
DD2
4.6
5.0
5.7
V
VREG = 7 V to 15 V, IDD2 = 0 mA
to 50 mA
Dropout Voltage VDD2 (DO) 0.5 1.5 V IDD2 = 50 mA
Line Regulation VISO (LINE) 1 20 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1 3 % IISO = 20 mA to 100 mA
Output Ripple
V
ISO (RIP)
200
mV p-p
20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Output Noise VISO (N) 500 mV p-p 20 MHz bandwidth,
COUT = 0.1 µF||47 µF, IISO = 100 mA
Switching Frequency fSW 1000 kHz ROC = 50 kΩ
200 kHz ROC = 270 kΩ
192
318
515
kHz
V
OC
= V
DD2
(open loop)
Switch On Resistance RON 0.5 Ω
Undervoltage Lockout, VDD1, VDD2 Supplies
Positive Going Threshold VUV+ 2.8 V
Negative Going Threshold VUV− 2.6 V
Hysteresis VUVH 0.2 V
DC to 2 Mbps Data Rate1 f ≤ 1 MHz
Maximum Output Supply Current2 IISO (MAX) 100 mA VISO = 5.0 V
Efficiency at Maximum Output
Supply Current3
70 % IISO = IISO (MAX)
i
COUPLER DATA CHANNELS
DC to 2 Mbps Data Rate1
IDD1 Supply Current, No VISO Load IDD1 (Q) IISO = 0 mA, f ≤ 1 MHz
ADuM3470 25 45 mA
ADuM3471 27 45 mA
ADuM3472 29 45 mA
ADuM3473 31 45 mA
ADuM3474 33 45 mA
25 Mbps Data Rate (C Grade Only)
IDD1 Supply Current, No VISO Load IDD1 (D) IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
ADuM3470 73 mA
ADuM3471 83 mA
ADuM3472
93
mA
ADuM3473 102 mA
ADuM3474 112 mA
Available VISO Supply Current4 IISO (LOAD) CL = 15 pF, f = 12.5 MHz
ADuM3470 91 mA
ADuM3471 89 mA
ADuM3472
86
mA
ADuM3473 83 mA
ADuM3474 80 mA
IDD1 Supply Current, Full VISO Load IDD1 (MAX) 425 mA CL = 0 pF, f = 0 MHz, VDD1 = 5 V,
IISO = 100 mA
Rev. B | Page 9 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
I/O Input Currents IIA, IIB, IIC, IID −20 +0.01 +20 µA
Logic High Input Threshold VIH 2.0 V
Logic Low Input Threshold VIL 0.8 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
VDD1 − 0.3,
VISO − 0.3
5.0 V IOx = −20 µA, VIx = VIxH
VDD1 − 0.5,
VISO − 0.5
4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
AC SPECIFICATIONS
A Grade CL = 15 pF, CMOS signal levels
Minimum Pulse Width PW 1000 ns
Maximum Data Rate
1
Mbps
Propagation Delay tPHL, tPLH 55 100 ns
Pulse Width Distortion, |tPLH − tPHL| PWD 40 ns
Propagation Delay Skew tPSK 50 ns
Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns
C Grade
C
L
= 15 pF, CMOS signal levels
Minimum Pulse Width PW 40 ns
Maximum Data Rate 25 Mbps
Propagation Delay tPHL, tPLH 30 45 60 ns
Pulse Width Distortion, |tPLH − tPHL| PWD 8 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
t
PSK
15
ns
Channel-to-Channel Matching
Codirectional Channels tPSKCD 8 ns
Opposing Directional Channels tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity VCM = 1000 V, transient
magnitude = 800 V
At Logic High Output |CMH| 25 35 kV/µs VIx = VDD1 or VISO
At Logic Low Output |CML| 25 35 kV/µs VIx = 0 V
Refresh Rate fr 1.0 Mbps
1 The contributions of supply current values for all four channels are combined at identical data rates.
2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
Rev. B | Page 10 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
PACKAGE CHARACTERISTICS
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RESISTANCE AND CAPACITANCE
Resistance (Input to Output)1 RI-O 1012 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Ambient Thermal
Resistance
θJA 50.5 °C/W Thermocouple is located at the center of
the package underside; test conducted on
a 4-layer board with thin traces3
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD 150 °C TJ rising
Thermal Shutdown Hysteresis TSSD-HYS 20 °C
1 The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together, and Pin 11 to Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
3 See the Thermal Analysis section for thermal model definitions.
REGULATORY APPROVALS
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 are approved by the organizations listed in Table 6. Refer to Tabl e 11
and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation
waveforms and insulation levels.
Table 6.
UL CSA VDE
Recognized under the UL 1577 component
recognition program1
Approved under CSA Component Acceptance
Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Single protection, 2500 V rms isolation
voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 600 V rms (848 V peak) maximum
working voltage
Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying an insulation test voltage of ≥3000 V rms
for 1 sec (current leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying
an insulation test voltage of ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 7.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) >5.1 mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) >5.1 mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Distance (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>400
V
DIN IEC 112/VDE 0303, Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. B | Page 11 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking branded on the component denotes DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
Table 8.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1050 V peak
Input-to-Output Test Voltage, Method A VPR
After Environmental Tests Subgroup 1
V
IORM
× 1.6 = V
PR
, t
m
= 60 sec, partial discharge < 5 pC
896
V peak
After Input and/or Safety Tests Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 3)
Case Temperature TS 150 °C
Side 1 Current IS1 1.25 A
Insulation Resistance at TS VIO = 500 V RS >109 Ω
0
0.25
0.50
0.75
1.00
1.25
1.50
050 100 150 200
CASE TEMPERATURE (°C)
SAFE OPERATING V
DD1
CURRENT ( A)
09369-002
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 9.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages1
VDD1 at VISO = 3.3 V VDD1 3.0 3.6 V
VDD1 at VISO = 5.0 V VDD1 3.0 3.6 V
V
DD1
at V
ISO
= 5.0 V
V
DD1
4.5
5.5
V
Minimum Load IISO (MIN) 10 mA
1 All voltages are relative to their respective grounds.
Rev. B | Page 12 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 10.
Parameter Rating
Storage Temperature Range (TST) −55°C to +150°C
Ambient Operating Temperature
Range (TA)
−40°C to +105°C
Supply Voltages1
VDD1,2 VDDA, VDD2 −0.5 V to +7.0 V
VREG, X1, X2 −0.5 V to +20.0 V
Input Voltage (V
IA
, V
IB
, V
IC
, V
ID
)1, 3
−0.5 V to V
DDI
+ 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)1, 3 −0.5 V to VDDO + 0.5 V
Average Output Current per Pin4 −10 mA to +10 mA
Common-Mode Transients5 −100 kV/µs to +100 kV/µs
1 All voltages are relative to their respective grounds.
2 VDD1 is the power supply for the push-pull transformer.
3 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the Printed Circuit Board (PCB) Layout section.
4 See Figure 3 for maximum rated current values for various temperatures.
5 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 11. Maximum Continuous Working Voltage
Supporting 50-Year Minimum Lifetime1
Parameter Max Unit
Applicable
Certification
AC Voltage, Bipolar
Waveform
565 V peak All certifications
AC Voltage, Unipolar
Waveform
Basic Insulation 848 V peak Working voltage
per IEC 60950-1
DC Voltage
Basic Insulation 848 V peak Working voltage
per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
ESD CAUTION
Rev. B | Page 13 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Rev. B | Page 14 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
X1
NOTES
1. NC = NO INT E RN
A
L CON N E CTION.
2
. P IN 2 AND PIN 10 ARE I N TER NALLY CONNECTE D TO E ACH OTHER; IT I S
RECO MME NDED T HAT BOTH PINS BE CO N NE CTE D TO A COM MON GRO UND .
PI N 11 AND PIN 1 9 ARE INTERNALLY CONNE CTED TO E ACH OT HE R; I T IS
RECO MME NDED T HAT BOTH PINS BE CO N NE CTE D TO A COM MON GRO UND .
1
*GND
12
NC
3
X2
4
V
REG
20
GND
2
*
19
V
DD2
18
FB
17
V
IA 5
V
IB 6
V
IC 7
V
OA
16
V
OB
15
V
OC
14
V
ID 8
V
OD
13
V
DDA 9
OC
12
*GND
110
GND
2
*
11
ADuM3470
TOP VIEW
(Not to Scale)
09369-004
Figure 4. ADuM3470 Pin Configuration
Table 12. ADuM3470 Pin Function Descriptions
Pin No. Mnemonic Description
1 X1 Transformer Driver Output 1.
2, 10 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
3 NC No Internal Connection.
4 X2 Transformer Driver Output 2.
5 VIA Logic Input A.
6 VIB Logic Input B.
7 VIC Logic Input C.
8 VID Logic Input D.
9 VDDA Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
11, 19 GND2 Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
12 OC Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in open-
loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
13 VOD Logic Output D.
14 VOC Logic Output C.
15 VOB Logic Output B.
16 VOA Logic Output A.
17 FB Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
18 VDD2 Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
20 VREG Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Rev. B | Page 15 of 36
X1
1
*GND
12
NC
3
X2
4
V
REG
20
GND
2
*
19
V
DD2
18
FB
17
V
IA 5
V
IB 6
V
IC 7
V
OA
16
V
OB
15
V
OC
14
V
OD 8
V
ID
13
V
DDA 9
OC
12
*GND
110
GND
2
*
11
ADuM3471
TOP VIEW
(Not to Scal e)
09369-005
NOTES
1. NC = NO INT E RN
A
L CONNECTI O N .
2
. P IN 2 AND PIN 10 ARE INT E RN ALLY CONNE CTE D TO EAC H OT H E R; IT IS
RECO MME NDED THAT BOTH PINS BE CO NN E CTED TO A COMMON G ROUND.
PI N 11 AND P IN 19 ARE INT E R NALLY CONNECTE D TO EA CH OTHER; IT IS
RECO MME NDED THAT BOTH PINS BE CO NN E CTED TO A COMMON G ROUND.
Figure 5. ADuM3471 Pin Configuration
Table 13. ADuM3471 Pin Function Descriptions
Pin No. Mnemonic Description
1 X1 Transformer Driver Output 1.
2, 10 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
3 NC No Internal Connection.
4 X2 Transformer Driver Output 2.
5 VIA Logic Input A.
6 VIB Logic Input B.
7 VIC Logic Input C.
8 VOD Logic Output D.
9 VDDA Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
11, 19 GND2 Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
12 OC Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in open-
loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
13 VID Logic Input D.
14 VOC Logic Output C.
15 VOB Logic Output B.
16 VOA Logic Output A.
17 FB Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
18 VDD2 Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
20 VREG Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Rev. B | Page 16 of 36
X1
1
*GND
12
NC
3
X2
4
V
REG
20
GND
2
*
19
V
DD2
18
FB
17
V
IA 5
V
IB 6
V
OC 7
V
OA
16
V
OB
15
V
IC
14
V
OD 8
V
ID
13
V
DDA 9
OC
12
*GND
110
GND
2
*
11
ADuM3472
TOP VIEW
(Not to Scale)
09369-006
NOTES
1. NC = NO INT E RN
A
L CON N E CTION.
2
. P IN 2 AND PIN 10 ARE I N TER NALLY CONNECTE D TO E ACH OTHER; IT I S
RECO MME NDED THAT BOTH P INS BE CO N NE CTE D TO A COM MON GRO UND .
PI N 11 AND PIN 1 9 ARE INTERNALLY CONNE CTED TO E ACH OT HE R; I T IS
RECO MME NDED THAT BOTH P INS BE CO N NE CTE D TO A COM MON GRO UND .
Figure 6. ADuM3472 Pin Configuration
Table 14. ADuM3472 Pin Function Descriptions
Pin No. Mnemonic Description
1 X1 Transformer Driver Output 1.
2, 10 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
3 NC No Internal Connection.
4 X2 Transformer Driver Output 2.
5 VIA Logic Input A.
6 VIB Logic Input B.
7 VOC Logic Output C.
8 VOD Logic Output D.
9 VDDA Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
11, 19 GND2 Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
12 OC Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in open-
loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
13 VID Logic Input D.
14 VIC Logic Input C.
15 VOB Logic Output B.
16 VOA Logic Output A.
17 FB Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
18 VDD2 Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
20 VREG Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Rev. B | Page 17 of 36
X1
1
*GND
12
NC
3
X2
4
V
REG
20
GND
2
*
19
V
DD2
18
FB
17
V
IA 5
V
OB 6
V
OC 7
V
OA
16
V
IB
15
V
IC
14
V
OD 8
V
ID
13
V
DDA 9
OC
12
*GND
110
GND
2
*
11
ADuM3473
TOP VIEW
(Not to Scale)
09369-007
NOTES
1. NC = NO INT E RN
A
L CON N E CTION.
2
. P IN 2 AND PIN 10 ARE I N TER NALLY CONNECTE D TO E ACH OTHER; IT I S
RECO MME NDED THAT BOTH P INS BE CO N NE CTE D TO A COM MON GRO UND .
PI N 11 AND PIN 1 9 ARE INTERNALLY CONNE CTED TO E ACH OT HE R; I T IS
RECO MME NDED THAT BOTH P INS BE CO N NE CTE D TO A COM MON GRO UND .
Figure 7. ADuM3473 Pin Configuration
Table 15. ADuM3473 Pin Function Descriptions
Pin No. Mnemonic Description
1 X1 Transformer Driver Output 1.
2, 10 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
3 NC No Internal Connection.
4 X2 Transformer Driver Output 2.
5 VIA Logic Input A.
6 VOB Logic Output B.
7 VOC Logic Output C.
8 VOD Logic Output D.
9 VDDA Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
11, 19 GND2 Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
12 OC Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in open-
loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
13 VID Logic Input D.
14 VIC Logic Input C.
15 VIB Logic Input B.
16 VOA Logic Output A.
17 FB Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
18 VDD2 Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
20 VREG Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Rev. B | Page 18 of 36
X1
1
*GND
12
NC
3
X2
4
V
REG
20
GND
2
*
19
V
DD2
18
FB
17
V
OA 5
V
OB 6
V
OC 7
V
IA
16
V
IB
15
V
IC
14
V
OD 8
V
ID
13
V
DDA 9
OC
12
*GND
110
GND
2
*
11
ADuM3474
TOP VIEW
(Not to Scale)
09369-008
NOTES
1. NC = NO INT E RN
A
L CON N E CTION.
2
. P IN 2 AND PIN 10 ARE I N TER NALLY CONNECTE D TO E ACH OTHER; IT I S
RECO MME NDED THAT BOTH P INS BE CO N NE CTE D TO A COM MON GRO UND .
PI N 11 AND PIN 1 9 ARE INTERNALLY CONNE CTED TO E ACH OT HE R; I T IS
RECO MME NDED THAT BOTH P INS BE CO N NE CTE D TO A COM MON GRO UND .
Figure 8. ADuM3474 Pin Configuration
Table 16. ADuM3474 Pin Function Descriptions
Pin No. Mnemonic Description
1 X1 Transformer Driver Output 1.
2, 10 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 10 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
3 NC No Internal Connection.
4 X2 Transformer Driver Output 2.
5 VOA Logic Output A.
6 VOB Logic Output B.
7 VOC Logic Output C.
8 VOD Logic Output D.
9 VDDA Supply Voltage for the Primary Side, 3.0 V to 5.5 V. Connect a 0.1 μF bypass capacitor from VDDA to GND1.
11, 19 GND2 Ground Reference for the Secondary Side of the Isolator. Pin 11 and Pin 19 are internally connected to each other;
it is recommended that both pins be connected to a common ground.
12 OC Oscillator Control Pin. When the OC pin is connected high to the VDD2 pin, the secondary controller runs in open-
loop (unregulated) mode. To regulate the output voltage, connect a resistor between the OC pin and GND2; the
secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value.
13 VID Logic Input D.
14 VIC Logic Input C.
15 VIB Logic Input B.
16 VIA Logic Input A.
17 FB Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from the VISO output to the FB pin
to set the VFB voltage equal to the 1.25 V internal reference level using the formula VISO = VFB × (R1 + R2)/R2. The
resistor divider is required even in open-loop mode to provide soft start.
18 VDD2 Internal Supply Voltage for the Secondary Side Controller and the Side 2 Data Channels. When a sufficient external
voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the
3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2.
20 VREG Input of the Internal Regulator to Power the Secondary Side Controller and the Side 2 Data Channels. VREG should
be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V.
Table 17. Truth Table (Positive Logic)
VIx Input1 V
DD1 State VDD2 State VOxOutput1 Notes
High Powered Powered High Normal operation, data is high
Low Powered Powered Low Normal operation, data is low
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
TYPICAL PERFORMANCE CHARACTERISTICS
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0050 100 150 200 250 300 350 400 450 500
f
SW ( kHz )
ROC (kΩ)
09369-009
Figure 9. Switching Frequency (fSW) vs. ROC Resistance
80
70
60
50
40
30
20
10
00500450
400
350
300
250200
15010050
EFFI CIENCY ( %)
LO AD CURRE NT (mA)
09369-010
1MHz
700kHz
500kHz
200kHz
Figure 10. Typical Efficiency at Various Switching Frequencies with
Coilcraft Transformer, 5 V Input to 5 V Output
80
70
60
50
40
30
20
10
00500450400350300250200
15010050
EFFI CIENCY ( %)
LO AD CURRE NT (mA)
09369-011
1MHz
700kHz
500kHz
200kHz
Figure 11. Typical Efficiency at Various Switching Frequencies with
Halo Transformer, 5 V Input to 5 V Output
80
00500
09369-012
EFFI CIENCY ( %)
LO AD CURRE NT (mA)
70
60
50
40
30
20
10
45040035030025020015010050
–40°C
+25°C
+105°C
Figure 12. Typical Efficiency over Temperature with Coilcraft Transformer,
fSW = 500 kHz, 5 V Input to 5 V Output
80
70
60
50
40
30
20
10
0050045040035030025020015010050
EF FICIENCY ( %)
LOAD CURRENT ( mA)
09369-013
V
DD1
= 5V, V
ISO
= 5V
V
DD1
= 5V, V
ISO
= 3.3V
V
DD1
= 3.3V , V
ISO
= 3.3V
Figure 13. Single-Supply Efficiency with Coilcraft Transformer, fSW = 500 kHz
80
70
60
50
40
30
20
10
0014090 1001101201308070605040302010
EFFI CIENCY ( %)
LOAD CURRENT (mA)
09369-014
1MHz
700kHz
500kHz
200kHz
Figure 14. Typical Efficiency at Various Switching Frequencies with
Coilcraft Transformer, 5 V Input to 15 V Output
Rev. B | Page 19 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
80
70
60
50
40
30
20
10
00140901001101201308070
60
50
4030
20
10
EFFI CIENCY ( %)
LOAD CURRENT (mA)
09369-026
1MHz
700kHz
500kHz
200kHz
Figure 15. Typical Efficiency at Various Switching Frequencies with
Halo Transformer, 5 V Input to 15 V Output
80
70
60
50
40
30
20
10
0014090 100 110 120 1308070605040302010
EF FICIENCY ( %)
LOAD CURRENT ( mA)
09369-027
–40°C
+25°C
+105°C
Figure 16. Typical Efficiency over Temperature with Coilcraft Transformer,
fSW = 500 kHz, 5 V Input to 15 V Output
80
70
60
50
40
30
20
10
0014090 100 110 1201308070605040302010
EFFICIENCY (%)
LOAD CURRENT (mA)
09369-028
V
DD1
= 5V, V
ISO
= 15V
V
DD1
= 5V, V
ISO
= 12V
Figure 17. Double-Supply Efficiency with Coilcraft Transformer, fSW = 500 kHz
15
10
5
00 252015105 DATA RATE (Mbps)
09369-029
V
DD1
= 5V, V
ISO
= 5V
V
DD1
= 5V, V
ISO
= 3.3V
V
DD1
= 3.3V, V
ISO
= 3.3V
I
CH
(mA)
Figure 18. Typical Single-Supply ICH Supply Current per Forward Data Channel
(15 pF Output Load)
15
10
5
00 252015105 DATA RATE (Mbps)
09369-030
I
CH
(mA)
V
DD1
= 5V, V
ISO
= 5V
V
DD1
= 5V, V
ISO
= 3.3V
V
DD1
= 3.3V, V
ISO
= 3.3V
Figure 19. Typical Single-Supply ICH Supply Current per Reverse Data Channel
(15 pF Output Load)
5
4
3
2
1
00252015105
I
ISO (D)
(mA)
DATA RATE (Mbp s)
09369-031
V
DD1
= 5V, V
ISO
= 5V
V
DD1
= 5V, V
ISO
= 3.3V
V
DD1
= 3.3V, V
ISO
= 3.3V
Figure 20. Typical Single-Supply IISO (D) Dynamic Supply Current
per Output Channel (15 pF Output Load)
Rev. B | Page 20 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
5
4
3
2
1
00252015105DATA RATE (Mb p s)
09369-032
I
ISO (D)
(mA)
V
DD1
= 5V, V
ISO
= 5V
V
DD1
= 5V, V
ISO
= 3.3V
V
DD1
= 3.3V, V
ISO
= 3.3V
Figure 21. Typical Single-Supply IISO (D) Dynamic Supply Current
per Input Channel
30
25
20
15
10
5
00252015105
I
CH
(mA)
DATA RATE (Mbp s)
09369-033
V
DD1
= 5V, V
ISO
= 15V
V
DD1
= 5V, V
ISO
= 12V
Figure 22. Typical Double-Supply ICH Supply Current per Forward Data
Channel (15 pF Output Load)
30
25
20
15
10
5
00252015105
ICH ( mA)
DATA RATE (M bp s)
09369-034
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
Figure 23. Typical Double-Supply ICH Supply Current per Reverse Data
Channel (15 pF Output Load)
5
4
3
2
1
00252015105
IISO (D) (mA)
DATA RATE (M bp s)
09369-035
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
Figure 24. Typical Double-Supply IISO (D) Dynamic Supply Current
per Output Channel (15 pF Output Load)
5
4
3
2
1
00252015105
IISO (D) (mA)
DATA RATE (M bp s)
09369-036
VDD1 = 5V, V ISO = 15V
VDD1 = 5V, V ISO = 12V
Figure 25. Typical Double-Supply IISO (D) Dynamic Supply Current
per Input Channel
6
4
5
3
2
1
0030
20 251510
5
VISO (V)
TIME (ms)
09369-037
VISO AT 10mA
VISO AT 50mA
VISO AT 400mA
Figure 26. Typical VISO Startup with 10 mA, 50 mA, and 400 mA Output Load,
5 V Input to 5 V Output
Rev. B | Page 21 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
5
4
3
2
1
003020 2515
105
V
ISO
(V)
TIME (ms)
09369-038
V
ISO
AT 10mA
V
ISO
AT 50mA
V
ISO
AT 400mA
Figure 27. Typical VISO Startup with 10 mA, 50 mA, and 400 mA Output Load,
5 V Input to 3.3 V Output
5
4
3
2
1
003020 251510
5
V
ISO
(V)
TIME (ms)
09369-039
V
ISO
AT 10mA
V
ISO
AT 50mA
V
ISO
AT 250mA
Figure 28. Typical VISO Startup with 10 mA, 50 mA, and 250 mA Output Load,
3.3 V Input to 3.3 V Output
18
16
14
12
10
8
6
4
2
003020 2515105
V
ISO
(V)
TIME (ms)
09369-040
V
ISO
AT 10mA
V
ISO
AT 20mA
V
ISO
AT 100mA
Figure 29. Typical VISO Startup with 10 mA, 20 mA, and 100 mA Output Load,
5 V Input to 15 V Output
6.0
5.5
5.0
4.5
4.5
1.0
0.5
6.0
5.5
5.0
0–2 0 2 4 6 8 10 12 14
VISO (V)ILOAD ( A)
TIME (ms)
09369-041
90% LO AD 10% LOAD
COUT = 47µ F, L1 = 100µ H
COUT = 47µ F, L1 = 47µ H
Figure 30. Typical VISO Load Transient Response at 10% to 90% of 400 mA Load,
fSW = 500 kHz, 5 V Input to 5 V Output
4.0
3.5
3.0
1.0
0.5
4.0
3.5
3.0
0–2 0 2 4 6 8 10 12 14
VISO (V)ILOAD ( A)
TIME (ms)
09369-042
COUT = 47µ F, L1 = 47µ H
90% LO AD 10% LOAD
COUT = 47µ F, L1 = 100µ H
Figure 31. Typical VISO Load Transient Response at 10% to 90% of 400 mA Load,
fSW = 500 kHz, 5 V Input to 3.3 V Output
4.0
3.5
3.0
1.0
0.5
4.0
3.5
3.0
0–2 0 2 4 6 8 10 12 14
VISO (V)ILOAD ( A)
TIME (ms)
09369-044
COUT = 47µ F, L1 = 47µ H
90% LO AD 10% LOAD
COUT = 47µ F, L1 = 100µ H
Figure 32. Typical VISO Load Transient Response at 10% to 90% of 250 mA Load,
fSW = 500 kHz, 3.3 V Input to 3.3 V Output
Rev. B | Page 22 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
18
16
14
12
18
16
14
12
200
100
0–2 2610 14 18 22 26 30 34
VISO (V)ILOAD ( A)
TIME (ms)
09369-043
COUT = 47µ F, L1 = 47µ H, L 2 = 47µH
COUT = 47µ F, L1 = 100µ H, L 2 = 100µH
10% LOAD 90% LOAD
Figure 33. Typical VISO Load Transient Response at 10% to 90% of 100 mA Load,
fSW = 500 kHz, 5 V Input to 15 V Output
20
10
0–2
VISO (V)X1 (V)
TIME (µs)
09369-045
4.98
5.00
5.02
5.04
–1 01 2
X1 ON
X2 ON
Figure 34. Typical VISO Output Voltage Ripple at 400 mA Load,
fSW = 500 kHz, 5 V Input to 5 V Output
20
10
0–2
VISO (V)X1 (V)
TIME (µs)
09369-046
3.28
3.30
3.32
3.34
–1 0 1 2
X2 ON
X1 ON
Figure 35. Typical VISO Output Voltage Ripple at 400 mA Load,
fSW = 500 kHz, 5 V Input to 3.3 V Output
20
10
0–2
VISO (V)X1 (V)
TIME (µs)
09369-047
3.28
3.30
3.32
3.34
–1 0 1 2
X2 ON
X1 ON
Figure 36. Typical VISO Output Voltage Ripple at 250 mA Load,
fSW = 500 kHz, 3.3 V Input to 3.3 V Output
20
10
0–2
VISO (V)X1 (V)
TIME (µs)
09369-048
14.6
14.8
15.0
15.2
15.4
–1 0 1 2
X2 ON
X1 ON
Figure 37. Typical VISO Output Voltage Ripple at 100 mA Load,
fSW = 500 kHz, 5 V Input to 15 V Output
Rev. B | Page 23 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
TERMINOLOGY
IDD1 (Q)
IDD1 (Q) is the minimum operating current drawn at the VDD1 power
input when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic supply
current.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps with
the full capacitive load representing the maximum dynamic
load conditions. Treat resistive loads on the outputs separately
from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
tPHL Propagation Delay
The tPHL propagation delay is measured from the 50% level of
the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal.
tPLH Propagation Delay
The tPLH propagation delay is measured from the 50% level of
the rising edge of the VIx signal to the 50% level of the rising
edge of the VOx signal.
Propagation Delay Skew (tPSK)
tPSK is the magnitude of the worst-case difference in tPHL and/or
tPLH that is measured between units at the same operating temper-
ature, supply voltages, and output load within the recommended
operating conditions.
Channel-to-Channel Matching
Channel-to-channel matching is the absolute value of the differ-
ence in propagation delays between two channels when operated
with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. B | Page 24 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM347x uses a
secondary side controller architecture with isolated pulse-width
modulation (PWM) feedback. VDD1 power is supplied to an oscillat-
ing circuit that switches current to the primary side of an external
power transformer using internal push-pull switches at the X1
and X2 pins. Power transferred to the secondary side of the trans-
former is full wave rectified with external Schottky diodes (D1
and D2), filtered with the L1 inductor and COUT capacitor, and
regulated to the isolated power supply voltage from 3.3 V to 15 V.
The secondary (VISO) side controller regulates the output using
a feedback voltage, VFB, from a resistor divider on the output to
create a PWM control signal that is sent to the primary (VDD1) side
by a dedicated iCoupler data channel labeled VFB. The primary side
PWM converter varies the duty cycle of the X1 and X2 switches
to modulate the oscillator circuit and control the power being
sent to the secondary side. This feedback allows for significantly
higher power and efficiency.
The ADuM347x devices implement undervoltage lockout
(UVLO) with hysteresis on the VDDA power input. This feature
ensures that the converter does not go into oscillation due to
noisy input power or slow power-on ramp rates.
A minimum load current of 10 mA is recommended to ensure
optimum load regulation. Smaller loads can generate excess noise
on the output due to short or erratic PWM pulses. Excess noise
generated in this way can cause regulation problems in some
circumstances.
APPLICATION SCHEMATICS
The ADuM347x devices have three main application schematics,
as shown in Figure 38 to Figure 40. Figure 38 has a center-tapped
secondary and two Schottky diodes that provide full wave
rectification for a single output, typically for power supplies of
3.3 V, 5 V, 12 V, and 15 V. For single supplies when VISO = 3.3 V
or 5 V, VREG, VDD2, and VISO can be connected together.
Figure 39 shows a voltage doubling circuit that can be used for a
single supply with an output that exceeds 15 V; 15 V is the largest
supply that can be connected to the regulator input, VREG (Pin 20).
In the circuit shown in Figure 39, the output voltage can be as high
as 24 V, and the voltage at the VREG pin can be as high as 12 V.
When using the circuit shown in Figure 39 to obtain an output
voltage lower than 10 V (for example, VDD1 = 3.3 V, VISO = 5 V),
connect VREG to VISO directly.
Figure 40, which also uses a voltage doubling secondary circuit,
is an example of a coarsely regulated, positive power supply and
an unregulated, negative power supply for outputs of approxi-
mately ± 5 V, ±12 V, and ±15 V.
For all the circuits shown in Figure 38 to Figure 40, the isolated
output voltage (VISO) can be set with the voltage dividers, R1
and R2 (values 1 kΩ to 100 kΩ) using the following equation:
VISO = VFB × (R1 + R2)/R2
where VFB is the internal feedback voltage (approximately 1.25 V).
09369-015
ADuM3470/
ADuM3471/
ADuM3472/
ADuM3473/
ADuM3474
1 X1
2 GND
1
3 NC
4 X2
5 V
IA
/V
OA
6 V
IB
/V
OB
7 V
IC
/V
OC
8 V
ID
/V
OD
9 V
DDA
10 GND
1
20 V
REG
19 GND
2
18 V
DD2
17 FB
16 V
IA
/V
OA
15 V
IB
/V
OB
14 V
IC
/V
OC
13 V
ID
/V
OD
12 OC
11 GND
2
D1
T1 L1
C
OUT
D2
V
DD1
V
DD1
0.1µF
C
IN
0.1µF
+5V
R1
R2
R
OC
V
FB
V
ISO
= V
FB
× (R1 + R2) /R2
FOR V
ISO
= 3.3V OR 5V, CONNECT V
REG
, V
DD2
,AND V
ISO
.
V
ISO
=
+3.3V
TO +15V
47µF
47µH
100kΩ
Figure 38. Single Power Supply
09369-016
ADuM3470/
ADuM3471/
ADuM3472/
ADuM3473/
ADuM3474
D1
T1 L1
L2
C
OUT1
C
OUT2
D2
D3
D4
V
DD1
V
DD1
0.1µF
C
IN
0.1µF
+5V
R1
R2
V
FB
R
OC
V
ISO
= V
FB
× (R1 + R2) /R2
FOR V
ISO
= 15V OR LESS, V
REG
CAN CONNECT TO V
ISO
.
V
ISO
=
+12V TO
+24V
UNREGULATED
+6V TO
+12V
100kΩ
47µH
47µH 47µF
47µF
1 X1
2 GND
1
3 NC
4 X2
5 V
IA
/V
OA
6 V
IB
/V
OB
7 V
IC
/V
OC
8 V
ID
/V
OD
9 V
DDA
10 GND
1
20 V
REG
19 GND
2
18 V
DD2
17 FB
16 V
IA
/V
OA
15 V
IB
/V
OB
14 V
IC
/V
OC
13 V
ID
/V
OD
12 OC
11 GND
2
Figure 39. Doubling Power Supply
09369-017
ADuM3470/
ADuM3471/
ADuM3472/
ADuM3473/
ADuM3474
D1
T1 L1
L2
C
OUT1
C
OUT2
D2
D3
D4
V
DD1
V
DD1
0.1µF
C
IN
0.1µF
+5V
R1
R2
R
OC
V
FB
V
ISO
= V
FB
× (R1 + R2) /R2
V
ISO
=
COARSELY
REGULATED
+5V TO +15V
UNREGULATED
–5V TO –15V
47µF47µH
47µH
47µF
100kΩ
1 X1
2 GND
1
3 NC
4 X2
5 V
IA
/V
OA
6 V
IB
/V
OB
7 V
IC
/V
OC
8 V
ID
/V
OD
9 V
DDA
10 GND
1
20 V
REG
19 GND
2
18 V
DD2
17 FB
16 V
IA
/V
OA
15 V
IB
/V
OB
14 V
IC
/V
OC
13 V
ID
/V
OD
12 OC
11 GND
2
Figure 40. Positive Supply and Unregulated Negative Supply
Rev. B | Page 25 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
TRANSFORMER DESIGN
Custom transformers were designed for use in the circuits shown
in Figure 38, Figure 39, and Figure 40 (see Table 18). The trans-
formers designed for use with the ADuM347x differ from other
transformers used with isolated dc-to-dc converters that do not
regulate the output voltage. The output voltage is regulated by a
PWM controller in the ADuM347x that varies the duty cycle of
the primary side switches in response to a secondary side feed-
back voltage, VFB, received through an isolated digital channel.
The internal controller has a maximum duty cycle of 40%.
TRANSFORMER TURNS RATIO
To determine the transformer turns ratio—taking into account
the losses for the primary switches and the losses for the secondary
diodes and inductors—the external transformer turns ratio for
the ADuM347x can be calculated using Equation 1.
2
)( ××
+
=
DV
VV
N
N
MINDD1
D
ISO
P
S
(1)
where:
NS/NP is the primary to secondary turns ratio.
VISO is the isolated output supply voltage.
VD is the Schottky diode voltage drop (0.5 V maximum).
VDD1 (MIN) is the minimum input supply voltage.
D is the duty cycle = 0.30 for a 30% typical duty cycle (40% is
the maximum duty cycle).
2 is a multiplier factor used for the push-pull switching cycle.
For the circuit shown in Figure 38 using the 5 V to 5 V reference
design in Table 18 and with VDD1 (MIN) = 4.5 V, the turns ratio is
NS/NP = 2.
For a 3.3 V input to 3.3 V output isolated single power supply
and with VDD1 (MIN) = 3.0 V, the turns ratio is also NS/NP = 2.
Therefore, the same transformer turns ratio, NS/NP = 2, can be
used for the three single power applications: 5 V to 5 V, 5 V to
3.3 V, and 3.3 V to 3.3 V.
The circuit shown in Figure 39 uses double windings and diode
pairs to create a doubler circuit; therefore, half the output voltage,
VISO/2, is used, as shown in Equation 2.
2
2
)(
××
+
=
DV
V
V
N
N
MINDD1
D
ISO
P
S
(2)
where:
NS/NP is the primary to secondary turns ratio.
VISO is the isolated output supply voltage. VISO/2 is used because
the circuit uses two pairs of diodes, creating a doubler circuit.
VD is the Schottky diode voltage drop (0.5 V maximum).
VDD1 (MIN) is the minimum input supply voltage.
D is the duty cycle = 0.30 for a 30% typical duty cycle (40% is
the maximum duty cycle).
2 is a multiplier factor used for the push-pull switching cycle.
For the circuit shown in Figure 39 using the 5 V to 15 V reference
design in Table 18 and with VDD1 (MIN) = 4.5 V, the turns ratio is
NS/NP = 3.
The circuit shown in Figure 40 also uses double windings and
diode pairs to create a doubler circuit. However, because a
positive and negative output voltage are created, VISO is used,
and the external transformer turns ratio can be calculated using
Equation 3.
2
)( ××
+
=
DV
VV
N
N
MINDD1
D
ISO
P
S
(3)
where:
NS/NP is the primary to secondary turns ratio.
VISO is the isolated output supply voltage.
VD is the Schottky diode voltage drop (0.5 V maximum).
VDD1 (MIN) is the minimum input supply voltage.
D is the duty cycle = 0.35 for a 35% typical duty cycle (40% is
the maximum duty cycle).
2 is a multiplier factor used for the push-pull switching cycle.
For the circuit shown in Figure 40, the duty cycle, D, is set to 0.35
for a 35% typical duty cycle to reduce the maximum voltages seen
by the diodes for a ±15 V supply.
For the circuit shown in Figure 40 using the +5 V to ±15 V refer-
ence design in Table 18 and with VDD1 (MIN) = 4.5 V, the turns
ratio is NS/NP = 5.
Table 18. Transformer Reference Designs
Part No. Manufacturer
Turns Ratio,
PRI:SEC
ET Constant
(V × µs Min)
Total Primary
Inductance (µH)
Total Primary
Resistance (Ω)
Isolation
Voltage (rms)
Isolation
Type Reference
JA4631-BL Coilcraft 1CT:2CT 18 255 0.2 2500 Basic Figure 38
JA4650-BL Coilcraft 1CT:3CT 18 255 0.2 2500 Basic Figure 39
KA4976-AL Coilcraft 1CT:5CT 18 255 0.2 2500 Basic Figure 40
TGSAD-260V6LF
Halo Electronics
1CT:2CT
14
389
0.8
2500
Supplemental
Figure 38
TGSAD-290V6LF Halo Electronics 1CT:3CT 14 389 0.8 2500 Supplemental Figure 39
TGSAD-292V6LF Halo Electronics 1CT:5CT 14 389 0.8 2500 Supplemental Figure 40
TGAD-260NARL Halo Electronics 1CT:2CT 14 389 0.8 1500 Functional Figure 38
TGAD-290NARL Halo Electronics 1CT:3CT 14 389 0.8 1500 Functional Figure 39
TGAD-292NARL Halo Electronics 1CT:5CT 14 389 0.8 1500 Functional Figure 40
Rev. B | Page 26 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
TRANSFORMER ET CONSTANT
The next transformer design factor to consider is the ET constant.
This constant determines the minimum V × µs constant of the
transformer over the operating temperature. ET values of 14 V × µs
and 18 V × µs were selected for the ADuM347x transformer
designs listed in Tabl e 18 using the following equation:
2
)(
)(
)(
×
=
MINSW
MAXDD1
f
V
MINET
where:
VDD1 (MAX) is the maximum input supply voltage.
fSW (MIN) is the minimum primary switching frequency = 300 kHz
in startup.
2 is a multiplier factor used for the push-pull switching cycle.
TRANSFORMER PRIMARY INDUCTANCE AND
RESISTANCE
Another important characteristic of the transformer for designs
with the ADuM347x is the primary inductance. Transformers
for the ADuM347x are recommended to have between 60 µH to
100 µH of inductance per primary winding. Values of primary
inductance in this range are needed for smooth operation of the
ADuM347x pulse-by-pulse current-limit circuit, which can help
protect against a build-up of saturation currents in the transformer.
If the inductance is specified for the total of both primary wind-
ings, for example, as 400 µH, the inductance of one winding is
one-fourth of two equal windings, or 100 µH.
Another important characteristic of the transformer for designs
with the ADuM347x is primary resistance. Primary resistance as
low as is practical (less than 1 Ω) helps to reduce losses and
improves efficiency. The dc primary resistance can be measured
and specified, and is shown for the transformers in Table 18.
TRANSFORMER ISOLATION VOLTAGE
Isolation voltage and isolation type should be determined for
the requirements of the application and then specified. The
transformers in Table 18 have been specified for 2500 V rms
for supplemental or basic isolation and for 1500 V rms functional
isolation. Other isolation levels and isolation voltages can be
specified and requested from the transformer manufacturers
listed in Table 18 or from other manufacturers.
SWITCHING FREQUENCY
The ADuM347x switching frequency can be adjusted from
200 kHz to 1 MHz by changing the value of the ROC resistor
shown in Figure 38, Figure 39, and Figure 40. The value of the
ROC resistor needed for the desired switching frequency can be
determined from the switching frequency vs. ROC resistance curve
shown in Figure 9. The output filter inductor value and output
capacitor value for the ADuM347x application schematics have
been designed to be stable over the switching frequency range of
500 kHz to 1 MHz, when loaded from 10% to 90% of the maxi-
mum load.
The ADuM347x devices also have an open-loop mode where
the output voltage is not regulated and is dependent on the
transformer turns ratio, NS/NP, and the conditions of the output
including output load current and the losses in the dc-to-dc
converter circuit. This open-loop mode is selected when the OC
pin is connected high to the VDD2 pin. In open-loop mode, the
switching frequency is 318 kHz.
TRANSIENT RESPONSE
The load transient response of the ADuM347x output voltage for
10% to 90% of the full load is shown in Figure 30 to Figure 33
for the application schematics in Figure 38 and Figure 39. The
response shown is slow but stable and can have more output
change than desired for some applications. The output voltage
change with load transient is reduced, and the output is shown
to remain stable by adding more inductance to the output circuits,
as shown in the second VISO output waveform in Figure 30 to
Figure 33. For additional improvement in transient response,
add a 0.1 µF ceramic capacitor (CFB) in parallel with the high
feedback resistor. This value helps to reduce the overshoot and
undershoot during load transients.
COMPONENT SELECTION
The ADuM347x digital isolators with 2 W dc-to-dc converters
require no external interface circuitry for the logic interfaces.
Power supply bypassing is required at the input and output supply
pins. Note that a low ESR ceramic bypass capacitor of 0.1 µF is
required on Side 1 between Pin 9 and Pin 10, and on Side 2
between Pin 18 and Pin 19, as close to the chip pads as possible.
The power supply section of the ADuM347x uses a high oscillator
frequency to efficiently pass power through the external power
transformer. In addition, normal operation of the data section of
the iCoupler introduces switching transients on the power supply
pins. Bypass capacitors are required for several operating frequen-
cies. Noise suppression requires a low inductance, high frequency
capacitor; ripple suppression and proper regulation require a large
value capacitor. To suppress noise and reduce ripple, large value
ceramic capacitors of X5R or X7R dielectric type are recom-
mended. The recommended capacitor value is 10 µF for VDD1 and
47 µF for VISO. These capacitors have a low ESR and are available
in moderate 1206 or 1210 sizes for voltages up to 10 V. F o r output
voltages larger than 10 V, t w o 2 2 µF ceramic capacitors can be
used in parallel. See Table 19 for recommended components.
Table 19. Recommended Components
Part No. Manufacturer Value
GRM32ER71A476KE15L Murata 47 µF, 10 V, X7R, 1210
GRM32ER71C226KEA8L Murata 22 µF, 16 V, X7R, 1210
GRM31CR71A106KA01L Murata 10 µF, 10 V, X7R, 1206
MBR0540T1G ON Semiconductor Schottky, 0.5 A, 40 V,
SOD-123
LQH3NPN470MM0
Murata
47 µH, 0.41 A, 1212
ME3220-104KL Coilcraft 100 µH, 0.34 A, 1210
LQH6PPN470M43 Murata 47 µH, 1.10 A, 2424
LQH6PPN101M43 Murata 100 µH, 0.80 A, 2424
Rev. B | Page 27 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Rev. B | Page 28 of 36
Inductors must be selected based on the value and supply
current needed. Most applications with switching frequencies
between 500 kHz and 1 MHz and load transients between 10%
and 90% of full load are stable with the 47 μH inductor value
listed in Table 19. Values as large as 200 μH can be used for power
supply applications with a switching frequency as low as 200 kHz
to help stabilize the output voltage or for improved load transient
response (see Figure 30 to Figure 33). Inductors in a small 1212
or 1210 size are listed in Table 19 with a 47 μH value and a 0.41 A
current rating to handle the majority of applications below a
400 mA load, and with a 100 μH value and a 0.34 A current
rating to handle a load up to 300 mA.
Recommended Schottky diodes have low forward voltage to
reduce losses and high reverse voltage of up to 40 V to withstand
the peak voltages available in the doubling circuits shown in
Figure 39 and Figure 40.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Figure 41 shows the recommended PCB layout for the
ADuM347x. Note that the total lead length between the ends
of the low ESR capacitor and the VDDx and GNDx pins must not
exceed 2 mm. Installing a bypass capacitor with traces more
than 2 mm in length can result in data corruption.
X1
GND
1
NC
X2
V
REG
GND
2
V
DD2
FB
V
IA
/V
OA
V
IB
/V
OB
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
IC
/V
OC
V
ID
/V
OD
V
ID
/V
OD
V
DDA
OC
GND
1
GND
2
09369-025
Figure 41. Recommended PCB Layout
In applications that involve high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between pins
that exceed the absolute maximum ratings specified in Table 10,
thereby leading to latch-up and/or permanent damage.
The ADuM3470/ADuM3471/ADuM3472/ADuM3473/
ADuM3474 are power devices that dissipate approximately 1 W
of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation device,
the devices primarily depend on heat dissipation into the PCB
through the GNDx pins. If the devices are used at high ambient
temperatures, provide a thermal path from the GNDx pins to the
PCB ground plane.
The board layout in Figure 41 shows enlarged pads for Pin 2
and Pin 10 (GND1) on Side 1 and Pin 11 and Pin 19 (GND2)
on Side 2. Large diameter vias should be implemented from the
pad to the ground planes and power planes to increase thermal
conductivity and to reduce inductance. Multiple vias in the
thermal pads can significantly reduce temperatures inside the
chip. The dimensions of the expanded pads are left to the discre-
tion of the designer and depend on the available board space.
THERMAL ANALYSIS
The ADuM347x parts consist of two internal die attached to a
split lead frame with two die attach paddles. For the purposes
of thermal analysis, the die are treated as a thermal unit, with
the highest junction temperature reflected in the θJA value from
Table 5. The value of θJA is based on measurements taken with
the parts mounted on a JEDEC standard, 4-layer board with
fine width traces and still air.
Under normal operating conditions, the ADuM347x devices
operate at full load across the full temperature range without
derating the output current. However, following the recom-
mendations in the Printed Circuit Board (PCB) Layout section
decreases thermal resistance to the PCB, allowing increased
thermal margins at high ambient temperatures.
The ADuM347x devices have a thermal shutdown circuit
that shuts down the dc-to-dc converter and the outputs of the
ADuM347x when a die temperature of approximately 160°C
is reached. When the die cools below approximately 140°C, the
ADuM347x dc-to-dc converter and outputs turn on again.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a compo-
nent (see Figure 42). The propagation delay to a logic low output
can differ from the propagation delay to a logic high output.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
09369-018
Figure 42. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM347x component.
Propagation delay skew refers to the maximum amount that the
propagation delay differs between multiple ADuM347x compo-
nents operating under the same conditions.
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 µs, periodic sets of
refresh pulses indicative of the correct input state are sent to ensure
dc correctness at the output. If the decoder receives no internal
pulses for more than approximately 5 µs, the input side is assumed
to be unpowered or nonfunctional, and the isolator output is forced
to a default state by the watchdog timer circuit (see Table 17).
This situation should occur in the ADuM347x devices only
during power-up and power-down operations.
The limitation on the magnetic field immunity of the ADuM347x
is set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur.
The 3.3 V operating condition of the ADuM347x is examined
because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of approximately 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM347x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 43.
MAG NETI C FI E LD F RE QUENCY ( Hz )
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSI TY ( kgau ss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
09369-019
Figure 43. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approxi-
mately 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event occurs during a
transmitted pulse (and is of the worst-case polarity), it reduces
the received pulse from >1.0 V to 0.75 V—still well above the
0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM347x transformers. Figure 44 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 44, the ADuM347x is extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example, a 0.5 kA current must be placed 5 mm away
from the ADuM347x to affect the operation of the component.
MAG NETI C FI E LD F RE QUENCY ( Hz )
MAXI MUM AL LO WABL E CURRE NT (kA)
1k
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
09369-020
Figure 44. Maximum Allowable Current
for Various Current-to-ADuM347x Spacings
At combinations of strong magnetic field and high frequency, any
loops formed by PCB traces can induce error voltages sufficiently
large to trigger the thresholds of succeeding circuitry. Care should
be taken in the layout of such traces to avoid this possibility.
Rev. B | Page 29 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
Rev. B | Page 30 of 36
POWER CONSUMPTION
The VDD1 power supply provides power to the iCoupler data
channels, as well as to the power converter. For this reason,
the quiescent currents drawn by the power converter and the
primary and secondary I/O channels cannot be determined
separately. All of these quiescent power demands are combined
in the IDD1 (Q) current (see the simplified diagram in Figure 45).
The total IDD1 supply current is equal to the sum of the quiescent
operating current; the dynamic current, IDD1 (D), demanded by
the I/O channels; and any external IISO load.
CONVERTER
PRIMARY
PRIMARY
DATA
I/O
4CH
I
DD P (D)
FB
SECONDARY
DATA
I/O
4CH
I
ISO (D)
I
ISO
I
DD1 (Q)
I
DD1 ( D)
0
9369-024
SECONDARY
CONTROLLER
Figure 45. Power Consumption Within the ADuM347x
Dynamic I/O current is consumed only when operating a channel
at speeds higher than the refresh rate of fr. The dynamic current
of each channel is determined by its data rate. Figure 18 and
Figure 22 show the current for a channel in the forward direction,
meaning that the input is on the primary side of the part. Figure 19
and Figure 23 show the current for a channel in the reverse direc-
tion, meaning that the input is on the secondary side of the part.
Figure 18, Figure 19, Figure 22, and Figure 23 assume a typical
15 pF output load.
The following relationship allows the total IDD1 current to be
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4 (1)
where:
IDD1 is the total supply input current.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at the given output load from
Figure 13 or Figure 17 at the VISO and VDD1 condition of interest.
ICHn is the current drawn by a single channel, determined from
Figure 18, Figure 19, Figure 22, or Figure 23, depending on
channel direction.
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4 (2)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an
output or input channel, as shown for a single supply in Figure 20
or Figure 21 or for a double supply in Figure 24 or Figure 25.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
Soft Start Mode and Current-Limit Protection
When the ADuM347x device first receives power from VDD1, it is
in soft start mode, and the output voltage, VISO, is increased
gradually while it is below the start-up threshold. In soft start
mode, the width of the PWM signal is increased gradually by
the primary converter to limit the peak current during VISO
power-up. When the output voltage is larger than the start-up
threshold, the PWM signal can be transferred from the second-
ary controller to the primary converter, and the dc-to-dc converter
switches from soft start mode to the normal PWM control mode.
If a short circuit occurs, the push-pull converter shuts down for
approximately 2 ms and then enters soft start mode. If, at the end
of soft start, a short circuit still exists, the process is repeated,
which is called hiccup mode. If the short circuit is cleared, the
ADuM347x device enters normal operation.
The ADuM347x devices also have a pulse-by-pulse current
limit, which is active in startup and normal operation. This
current limit protects the primary switches, X1 and X2, from
exceeding approximately 1.2 A peak and also protects the
transformer windings.
Data Channel Power Cycle
The ADuM347x data input channels on the primary side and
the data input channels on the secondary side are protected from
premature operation by UVLO circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive,
and all input channel drivers and refresh circuits are idle. Outputs
are held in a low state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that time,
the data channels are initialized to their default low output state
until they receive data pulses from the secondary side.
The primary side input channels sample the input and send a
pulse to the inactive secondary output. The secondary side
converter begins to accept power from the primary, and the VISO
voltage starts to rise. When the secondary side UVLO is reached,
the secondary side outputs are initialized to their default low state
until data, either a transition or a dc refresh pulse, is received from
the corresponding primary side input. It can take up to 1 μs after
the secondary side is initialized for the state of the output to
correlate with the primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid one propagation delay after the
secondary side becomes active.
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Because the rate of charge of the secondary side is dependent
on the soft start cycle, loading conditions, input voltage, and
output voltage level selected, care should be taken in the design
to allow the converter to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side until either the UVLO level is
reached and the outputs are placed in their default low state,
or the outputs detect a lack of activity from the inputs and the
outputs are set to their default value before the secondary power
reaches UVLO.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insu-
lation degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM347x devices.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing calcu-
lation of the time to failure at the working voltage of interest.
The values shown in Table 11 summarize the peak voltages for
50 years of service life in several operating conditions. In many
cases, the working voltage approved by agency testing is higher
than the 50-year service life voltage. Operation at working
voltages higher than the service life voltage listed in Table 11
leads to premature insulation failure.
The insulation lifetime of the ADuM347x depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates, depending on
whether the waveform is bipolar ac, dc, or unipolar ac. Figure 46,
Figure 47, and Figure 48 illustrate these different isolation
voltage waveforms.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines the
maximum working voltage recommended by Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 11 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases. Treat any cross-
insulation voltage waveform that does not conform to Figure 47
or Figure 48 as a bipolar ac waveform, and limit its peak voltage
to the 50-year lifetime voltage value listed in Table 11.
The voltage presented in Figure 48 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
0V
RATED P E AK V OL TAG E
09369-021
Figure 46. Bipolar AC Waveform
0V
RATED P E AK V OL TAG E
09369-023
Figure 47. DC Waveform
0V
RATED P E AK V OL TAG E
09369-022
Figure 48. Unipolar AC Waveform
Rev. B | Page 31 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MO-150- AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M I N
0.65 BSC
2.00 M AX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 49. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
Rev. B | Page 32 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ORDERING GUIDE
Model1, 2, 3
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VISO Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range (°C)
Package
Description
Package
Option
ADuM3470ARSZ 4 0 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3470CRSZ 4 0 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3470WARSZ 4 0 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3470WCRSZ
4
0
25
60
8
−40 to +105
20-Lead SSOP
RS-20
ADuM3471ARSZ 3 1 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3471CRSZ 3 1 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3471WARSZ
3
1
1
100
40
−40 to +105
20-Lead SSOP
RS-20
ADuM3471WCRSZ 3 1 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3472ARSZ 2 2 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3472CRSZ 2 2 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3472WARSZ 2 2 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3472WCRSZ 2 2 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3473ARSZ 1 3 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3473CRSZ 1 3 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3473WARSZ 1 3 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3473WCRSZ 1 3 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3474ARSZ 0 4 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3474CRSZ 0 4 25 60 8 −40 to +105 20-Lead SSOP RS-20
ADuM3474WARSZ 0 4 1 100 40 −40 to +105 20-Lead SSOP RS-20
ADuM3474WCRSZ 0 4 25 60 8 −40 to +105 20-Lead SSOP RS-20
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Tape and reel are available. The addition of an RL7 suffix designates a 7” (500 units) tape and reel option.
AUTOMOTIVE PRODUCTS
The ADuM3470W, ADuM3471W, ADuM3472W, ADuM3473W, and ADuM3474W models are available with controlled manufacturing
to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications
that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the
automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative
for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. B | Page 33 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet
NOTES
Rev. B | Page 34 of 36
Data Sheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
NOTES
Rev. B | Page 35 of 36
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Analog Devices Inc.:
ADUM3471ARSZ ADUM3472CRSZ-RL7 ADUM3473CRSZ ADUM3470ARSZ-RL7 ADUM3471ARSZ-RL7
ADUM3473CRSZ-RL7 ADUM3474CRSZ ADUM3474CRSZ-RL7 ADUM3472ARSZ-RL7 ADUM3471CRSZ
ADUM3470CRSZ-RL7 ADUM3473ARSZ-RL7 ADUM3474ARSZ-RL7 ADUM3471CRSZ-RL7 ADUM3472CRSZ
ADUM3473ARSZ ADUM3470CRSZ ADUM3474ARSZ ADUM3472ARSZ ADUM3470ARSZ ADUM3474WARSZ
ADUM3473WCRSZ ADUM3473WARSZ ADUM3470WARSZ-RL7 ADUM3473WARSZ-RL7 ADUM3471WCRSZ-RL7
ADUM3474WCRSZ-RL7 ADUM3471WARSZ-RL7 ADUM3472WCRSZ ADUM3472WCRSZ-RL7 ADUM3470WCRSZ-
RL7 ADUM3471WCRSZ ADUM3474WCRSZ ADUM3472WARSZ-RL7 ADUM3473WCRSZ-RL7 ADUM3470WARSZ
ADUM3471WARSZ ADUM3472WARSZ ADUM3474WARSZ-RL7 ADUM3470WCRSZ
