© Semiconductor Components Industries, LLC, 2010
September, 2010 − Rev. 0
1Publication Order Number:
NCP2824/D
NCP2824
Non-Clip and Power Limit
Mono Class D Amplifier
with AGC
Description
The NCP2824 is a Filterless Class D amplifier capable of delivering
up to 2.4 W to a 4 W load with a 5 V supply voltage. With the same
battery voltage, it can deliver 1.2 W to an 8 W load with less than 1%
THD+N. The non−clipping function automatically adjusts the output
voltage in order to control the distortion when an excessive input is
applied to the amplifier. This adjustment is done thanks to an
Automatic Gain Control circuitry (AGC) built into the chip. A simple
Single wire interface allows to the non Clipping function to be enabled
and disabled. It also allows the maximum distortion level in the output
to be configured. A programmable power limit function is also
embedded in order to protect speakers from damage caused by an
excessive sound level.
Features
•Non Clipping Function with Automatic Gain Control Circuitry
•Programmable Power Limit Function
•Single Wire Interface. No Need for Additional Components
•Max THD+N Configurable by Swire Interface
•Only One Capacitor Required
•Fully Differential Architecture: Better RF Immunity
•No Need for Input Capacitors in Fully Differential Configuration
•High Efficiency: up to 90%
•Low Quiescent Current: 2.2 mA Typ
•Large Output Power Capability
•High PSRR: up to −80 dB
•Fully Differential Capability: RF Immunity
•Thermal and Auto Recovery Short−Circuit Protection
•CMRR (−80 dB) Eliminates Two Input Coupling Capacitors
•Pb−Free and Halide−Free Device
Typical Applications
Audio Amplifier for:
•Cellular Phones
•Digital Cameras
•Personal Digital Assistant and Portable Media Player
•GPS
Demo Board Available:
•The NCP2824GEVB/D evaluation board configures the device in
typical application.
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9 PIN FLIP−CHIP
FC SUFFIX
CASE 499AL
PIN CONFIGURATION
(Top View)
A1
Device Package Shipping†
ORDERING INFORMATION
NCP2824FCT2G WCSP−9
(Pb−Free)
3000/Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
MRA = Specific Device Code
F = Assembly Location
Y = Year
WW = Work Week
G or G= Pb−Free Package
MRAG
FYWW
A1 A3
C1
MARKING DIAGRAM
A2 A3
B1 B2 B3
C1 C2 C3
A1 = INP
A2 = VDD
A3 = OUTP
B1 = AGND
B2 = NC
B3 = PGND
C1 = INM
C2 = CNTL
C3 = OUTM
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Figure 1. Simplified Block Diagram
PWM
Modulator
Auto Gain control
H
BRIDGE
Auto Gain control
CNTL
INN
INP
GND
VDD
OUTP
OUTN
C1
Single
Wire
Interface
PreAmplificator
4.7 mF/6.3 V
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Table 1. PIN FUNCTION DESCRIPTION
Pin
Pin
Name Type Description
A1 INP Input Positive Input
C1 INN Input Negative Input
A2 PVDD POWER Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must
bypass this input to the ground. This capacitor should be placed as close a possible to this input.
B2 NC −Non−connected: reserved for production. Must be kept floating in the final application
A3 OUTP Output Positive output: Special care must be observed at layout level. See the Layout consideration section
C3 OUTN Output Negative output: Special care must be observed at layout level. See the Layout consideration section
C2 CNTL Input Control: This pin is dedicated to the control of the chip via the Single wire protocol
B3 PGND POWER Power Ground: This pin is the power ground and carries the high switching current. A high quality
ground must be provided to avoid any noise spikes/uncontrolled operation. Care must be observed to
avoid high−density current flow in a limited PCB copper track.
B1 AGND POWER Analog Ground: This pin is the analog ground of the device and must be connected to GND plane.
Table 2. MAXIMUM RATINGS
Rating Symbol Value Unit
AVDD, PVDD Pins: Power Supply Voltage (Note 2) VDD −0.3 to +6.0 V
INP/N Pins: Input (Note 2) VINP/N −0.3 to +VDD V
Digital Input/Output: EN Pin:
Input Voltage
Input Current
VDG
IDG
−0.3 to VDD + 0.3
1
V
mA
Human Body Model (HBM) ESD Rating are (Note 3) ESD HBM 2000 V
Machine Model (MM) ESD Rating are (Note 3) ESD MM 200 V
WCSP 1.5 x 1.5 mm package (Notes 6 and 7)
Thermal Resistance Junction to Case RqJC 90
°C/W
Operating Ambient Temperature Range TA−40 to +85 °C
Operating Junction Temperature Range TJ−40 to +125 °C
Maximum Junction Temperature (Note 6) TJMAX +150 °C
Storage Temperature Range TSTG −65 to +150 °C
Moisture Sensitivity (Note 5) MSL Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins.
4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
6. The thermal shutdown set to 150°C (typical) avoids irreversible damage on the device due to power dissipation.
7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max
output current and external components selected.
RqCA +
125 *TA
PD
*RqJC
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Table 3. ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between −40°C to +85°C and for VDD between 2.5 V
to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VDD = 3.6 V. (see Note 8))
Symbol Parameter Conditions Min Typ Max Unit
GENERAL PERFORMANCES
VDD Operational Power Supply 2.5 5.5 V
FOSC Oscillator Frequency 250 300 350 kHz
Idd Supply current VDD = 3.6 V, No Load
VDD = 5.5 V, No Load, TA = 85°C
2.2
4.2
mA
Isd Shutdown current VDD = 3.6 V, VCNTL = 0 V
VDD = 5.5 V, VCNTL = 0 V, TA = 85°C
0.01
1
mA
TON Turn ON Time Single Wire Activation 7.4 ms
TOFF Turn Off Time Single Wire Deactivation 5 ms
Zsd Class D Output impedance
in shutdown mode
VENL = 0 V 20 kW
RDS(ON) Static drain−source on−state
resistance of power Mosfets
250 mW
hEfficiency VDD = 3.6 V, Po = 800 mW, RL = 8 W,
F = 1 kHz
86 %
VDD = 3.6 V, Po = 1.3 W, RL = 4 W,
F = 1 kHz
79
FLP −3 dB Cut off Frequency of
the Built in Low Pass Filter 30
kHz
TSD Thermal Shut Down
Protection
150 °C
TSDH Thermal Shut Down
Hysteresis
20 °C
AGC SECTION
Av Voltage gain Single Wire 4 12 dB
Av Voltage gain Single Wire 5 18 dB
Aa Max AGC attenuation −15 dB
Avn AGC Gain step resolution 0.5 dB
TAAttack time 0.033 ms/Step
TRRelease Time 0.013 s/Step
THHold Time 0.013 s/Step
S−WIRE INTERFACE (see Note 9)
VIH Rising Voltage Input Logic
High
1.2 −5.5 V
VIL Falling Voltage Input Logics
Low
0−0.4 V
VIHYS Input Voltage Hysteresis 100 mV
RPLD Pull Down Resistor 20 kW
TRSwire Rising time 200 ns
TFSwire Falling time 200 ns
TSWH Swire High 5 10 45 ms
TSWL Swire Low 5 10 75 ms
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at
TJ = TA = 25°C.
9. Single Wire performances is guaranteed by design and characterized
10.Audio performances are given for Vdd = 3.6 V, TA = 25°C and characterized
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Table 3. ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between −40°C to +85°C and for VDD between 2.5 V
to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VDD = 3.6 V. (see Note 8))
Symbol UnitMaxTypMinConditionsParameter
S−WIRE INTERFACE (see Note 9)
FSWF Input S−wire Frequency 100 kHz
TEHDT Enable High Delay Time 0 400 ms
TSDD Time to Shunt Down Delay 300 400 ms
TWAKE−UP Time to Wake up from
shutdown
500 ms
TVALID Time to Valid Data 300 400 ms
AUDIO PERFORMANCES (see Note 10)
voo Output offset Av = 12 dB 0.3 mV
PSRRDC Power supply rejection ratio From VDD = 2.5 V to 5.5 V −80 dB
PSRRAC Power supply rejection ratio F = 217 Hz, Input ac grounded, Av = 12 dB −70 dB
F = 1 kHz, Input ac grounded Av = 12 dB −70
SNR Signal to noise ratio Vp = 5 V, Pout = 600 mW (A. Weighted)
Av = 12 dB
96 dB
CMRR Common mode rejection
ratio
Input shorted together
VIC = 1 Vpp, f = 217 Hz
−80 dB
Vn Output Voltage noise Input ac grounded, Av = 12 dB
20 Hz < f < 20 kHz
A. Weighted
34 mV
Po Output Power RL = 8 W
F = 1 kHz
THD+N<1% VDD = 5 V 1.2 W
VDD = 3.6 V 0.6
VDD = 2.5 V 0.22
THD+N<10% VDD = 5 V 1.5
VDD = 3.6 V 0.8
VDD = 2.5 V 0.4
RL = 4 W
F = 1 kHz
THD+N<1% VDD = 5 V 2
VDD = 3.6 V 1
VDD = 2.5 V 0.4
THD+N<10% VDD = 5 V 2.4
VDD = 3.6 V 1.3
VDD = 2.5 V 0.6
THD+N Total harmonic distortion
plus noise
VDD = 3.6 V, Po = 0.5 W 0.06 %
VDD = 5 V, Po = 1 W 0.09
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at
TJ = TA = 25°C.
9. Single Wire performances is guaranteed by design and characterized
10.Audio performances are given for Vdd = 3.6 V, TA = 25°C and characterized
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90%
10%
Figure 2. S−Wire Logic Diagram
Tvalid
S−Wire /
CNTL
Amplifier
Mode
Tsdd
Initial Stage
Ton
Change
configuration
T_Wake up
Amplifier Off
Off
Toff
On default
configuration
Figure 3. S−Wire / Enable Timing Diagram
TR
TF
VIH
VIL
TSWH TSWL
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TYPICAL OPERATING CHARACTERISTICS
Figure 4. Efficiency vs. Pout Figure 5. Efficiency vs. Pout
Pout (mW) Pout (mW)
10008006004002000
0
10
30
40
60
70
90
100
1500125010007505002500
0
10
20
40
50
70
80
100
Figure 6. THD+N vs. Pout, RL = 8 WFigure 7. THD+N vs. Pout, RL = 4 W
Pout (mW)
1 k10010
0.01
0.1
1
10
100
Figure 8. THD+N vs. Frequency, Vdd = 2.5 V Figure 9. THD+N vs. Frequency, Vdd = 3.6 V
FREQUENCY (Hz) FREQUENCY (Hz)
100 k10 k1 k10010
0.01
0.1
1
10
100 k10 k1 k10010
0.001
0.01
0.1
1
EFFICIENCY (%)
EFFICIENCY (%)
THD (%)THD+N (%)
THD+N (%)
20
50
80
RL = 8 W
Vdd = 3.6 V
30
60
90
RL = 4 W
Vdd = 3.6 V
Pout = 250 mW
Pout = 250 mW
Pout = 500 mW
10 k
Pout (mW)
1 k10010
0.01
0.1
1
10
100
THD (%)
10 k
Vdd = 4.2 V
Vdd = 5.0 V
Vdd = 5.5 V
Vdd = 3.6 V
Vdd = 3.0 V
Vdd = 2.7 V
Vdd = 2.5 V
Vdd = 4.2 V
Vdd = 5.0 V
Vdd = 5.5 V
Vdd = 3.6 V
Vdd = 3.0 V
Vdd = 2.7 V
Vdd = 2.5 V
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TYPICAL OPERATING CHARACTERISTICS
Figure 10. THD+N vs. Frequency, Vdd = 5 V Figure 11. PSRR vs. Frequency
(Inputs Grounded, Gain = 12 dB, Cin = 1 mF)
FREQUENCY (Hz) FREQUENCY (Hz)
100 k10 k1 k10010
0.001
0.01
0.1
1
100 k10 k1 k10010
−80
−70
−60
−50
−30
−20
−10
0
Figure 12. PSRR vs. Frequency
(Inputs Grounded, Gain = 18 dB, Cin = 1 mF)
Figure 13. Peak Output Voltage in Power Limit
vs. Input Voltage (rms) and Power Limit
Settings, Av = 12 dB
FREQUENCY (Hz) Vin (V)
100 k10 k1 k10010
−80
−70
−60
−50
−40
−20
−10
0
1.21.00.80.60.40.20
0
0.5
1.0
1.5
2.5
3.0
3.5
4.0
Figure 14. THD+N vs. Input Voltage (rms) and
Non Clip Settings, RL = 8 W, Av = 12 dB
Figure 15. THD+N vs. Input Voltage (rms) and
Non Clip Settings, RL = 4 W, Av = 12 dB
Vin (V)
1.21.00.80.60.40.20
0
5
10
15
20
25
THD+N (%)
PSRR (dB)
PSRR (dB)
PEAK VOLTAGE (V)THD+N (%)
−40
−30
Vdd = 3.0 V
Vdd = 3.6 V
Vdd = 5.0 V
Vin (V)
1.21.00.80.60.40.20
0
5
10
15
20
25
THD+N (%)
2.0
Pout = 999 mW
Pout = 250 mW
Pout = 500 mW
THD+N Target = 20%
15%
10%
8%
4%
2%
1%
6%
THD+N Target = 20%
15%
10%
8%
4%
2%
1%
6%
Vpeak Target = 3.6 V
3.15 V
2.70 V
2.25 V
1.80 V
1.35 V
0.9 V
0.45 V
Vdd = 3.0 V
Vdd = 3.6 V
Vdd = 5.0 V
PVDD = 3.6 V
Temp = 25°C
VDD = 5 V
Temp = 25°C
PVDD = 3.6 V
Temp = 25°C
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Detailed Operating Description
General Description
The NCP2824 is a Mono class D audio amplifier featuring
a preamplifier stage, a PWM stage and an H−Bridge stage
with an automatic Gain control circuitry which performs the
non clipping function.
Non Clipping Function
In the presence of an exceeded input signal, when the
audio signal is going to be clipped, the gain of the audio
amplifier automatically decreases as defined by the AGC
operation. The maximum level of THD is programmable
and can be set by a final user through the single wire
interface (see table n°1).
At the same time, the battery voltage is continuously
monitored. The output signal is adapted to the dynamic
battery voltage (Vdd) in order to avoid distortion due to
supply voltage fluctuation like GSM burst.
This function solution allows the chip to maximize the
sound pressure level while maintaining a controlled THD
level.
The following picture depicts the non clipping operation.
VP
VP/2
Figure 16. Output of the Amplifier during a Line
Transient on the Battery Voltage
Power Limit Function: Speaker Protection
In addition to the non clipping function, a Power limit
function is embedded in the NCP2824 in order to protect
speakers from excessive output signal levels. When the
output signal exceed this limit, the ???
Thus, the final user can use the Single Wire interface to
program the maximum voltage rated by the speaker or to
disable this power limit protection.
AGC Operation
The AGC operation defines the timings when the non
clipping function is engaged.
The typical values are described in the Electrical Table
(“AGC Section”).
Attack time (Ta): is defined as the minimum time between
two gain decrease.
Hold time (Th): is defined as the minimum time between
a gain increase after a gain decrease.
Release time (Tr): is defined as the minimum time between
two gain increase.
The following pictures depict the NCP2824 non clipping
operation.
Ta
Th Tr
Without Non clip
function
With Non clip
function
Single Wire Interface Operation
The single wire interface allows changing the default
configuration of the NCP2824.
After Wake up, the NCP2824 is configured with:
•AGC enable
•Non Clip + Power limit
•Gain = 18 dB
•THD max = 1%
The following table described all the NCP2824
configurations.
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Table 4. NCP2824 CONFIGURATION
Pulse
Counting Register Description
01 AGC AGC disable
02 AGC Enable
03 Reset Reset configuration
04 Gain
Control
Gain = 12 dB
05 Gain = 18 dB
06 THD
Control
1%
07 2%
08 4%
09 6%
10 8%
11 10%
12 15%
13 20%
14 NC+L Non Clip + Power limit
15 NC Non Clip only
16 Power
Limit
Control
0.45 VPeak
17 0.9 VPeak
18 1.35 VPeak
19 1.8 VPeak
20 2.25 VPeak
21 2.7 VPeak
22 3.15 VPeak
23 3.6 VPeak
NOTE: The given values are typical for Vdd = 3.6 V and
TA = 25°C characterized
Built−in Low Pass Filter
This filter allows the user to connect a DAC or a CODEC
directly to the NCP2824 input without increasing the output
noise by mixing frequency with the DAC/CODEC output
frequency. Consequently, optimized operation with DACs
or CODECs is guaranteed without additional external
components.
Decoupling Capacitors
The NCP2824 requires a correct decoupling of the power
supply in order to guarantee the best operation in terms of
audio performances. To achieve optimum performance, it is
necessary to place a 4.7 mF low ESR ceramic capacitor as
close as possible to the VDD pin in order to reduce high
frequency transient spikes due to parasitic inductance (see
Layout considerations).
Input Capacitors Cin
Thanks to its fully differential architecture, the NCP2824
does not require input capacitors. However, it is possible to
use input capacitors when the differential source is not
biased or in single ended configuration. In this case it is
necessary to take into account the corner frequency which
can influence the low frequency response of the NCP2824.
The following equation will help choose the adequate input
capacitor.
fc+1
2@p@75 @103@Cin
Over Current Protection
This protection allows an over current in the H−Bridge to
be detected. When the current is higher than 2 A, the
H−Bridge is positioned in high impedance. When the short
circuit is removed or the current is lower, the NCP2824 goes
back to normal operation. This protection avoids over
current due to a bad assembly (Output shorted together, to
Vdd or to ground).
Layout Recommendations
For Efficiency and EMI considerations, it is strongly
recommended to use Power and ground plane in order to
reduce parasitic resistance and inductance.
For the same reason, it is recommended to keep the output
traces short and well shielded in order to avoid them to act
as antenna.
The level of EMI is strongly dependent upon the
application. However, ferrite beads placed close to the
NCP2824 will reduce EMI radiation when it is needed.
Ferrite value is strongly dependent upon the application.
Figure 17. Example of PCB Layout
Components Selection
To achieve optimum performance, one 4.7 mF 6.3 V X5R
should be used to bypass the power input supply (VDD).
Also particular care must be observed for DC−bias effects
in the ceramic capacitor selection. Smaller case−size and
higher DC bias voltage is preferred.
Some recommended capacitors include but are not limited
to:
4.7 mF 6.3 V 0603
TDK: C1608X5R0J475MT 0.95 mm max.
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Example of Application Schematic
Figure 18. Differential Configuration
INN
INP
CNTL
PGND AGND
VDD
OUTP
OUTN
BATTERY
Differential Audio Input
Output from microcontroller
C1
U1
NCP2824
Figure 19. Single Ended Configuration
INN
INP
CNTL
PGND AGND
VDD
OUTP
OUTN
BATTERY
Single Ended Audio Input
Output
from microcontroller
C1
U1
NCP2824
4.7 mF/6.3 V
4.7 mF/6.3 V
NCP2824
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PACKAGE DIMENSIONS
9 PIN FLIP−CHIP
CASE 499AL−01
ISSUE O
DIM MIN MAX
MILLIMETERS
A0.540 0.660
A1 0.210 0.270
A2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
D
−A−
−B−
0.10 C
A2
A
A1
−C−
0.05 C
0.10 C
4 X
SEATING
PLANE
D1
e
E1
e
0.05 C
0.03 C
A B
9 X b
C
B
A
12 3
D1.450 BSC
E
0.330 0.390
b0.290 0.340
e0.500 BSC
D1 1.000 BSC
E1 1.000 BSC
1.450 BSC
SIDE VIEW
TOP VIEW
BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NCP2824/D
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