SLOS099E − O C TOBER 1983 − REVISED MAY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Noise
DNo External Components Required
DReplace Chopper Amplifiers at a Lower
Cost
DWide Input-Voltage Range
...0 to ±14 V Typ
DWide Supply-Voltage Range
...±3 V to ±18 V
description/ordering information
These devices offer low offset and long-term stability by means of a low-noise, chopperless,
bipolar-input-transistor amplifier circuit. For most applications, external components are not required for offset
nulling and frequency compensation. The true d i fferential input, with a wide input-voltage range and outstanding
common-mode rejection, provides maximum flexibility and performance in high-noise environments and in
noninverting applications. Low bias currents and extremely high input impedances are maintained over the
entire temperature range. The OP07 is unsurpassed for low-noise, high-accuracy amplification of very-low-level
signals.
These devices are characterized for operation from 0°C to 70°C.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (P)
Tube of 50 OP07CP OP07CP
PDIP (P) Tube of 50 OP07DP OP07DP
0°C to 70°C
Tube of 75 OP07CD
OP07C
0
°
C to 70
°
C
SOIC (D)
Reel of 2500 OP07CDR OP07C
SOIC (D)
Tube of 75 OP07DD
OP07D
Reel of 2500 OP07DDR
OP07D
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
symbol
OUT
−
+
OFFSET N2
IN−
IN+
OFFSET N1 1
3
2
8
6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
OFFSET N1
IN−
IN+
VCC−
OFFSET N2
VCC+
OUT
NC
D OR P PACKAGE
(TOP VIEW)
NC−No internal connection
Copyright 2004, Texas Instruments Incorporated
!" #$
# % &
## '($ # ) # "( "#
) "" $
SLOS099E − O C TOBER 1983 − REVISED MAY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic
7
6
4
VCC+
OUT
VCC−
OFFSET N1
OFFSET N2
IN+
IN−
1
8
3
2
COMPONENT COUNT
Resistors
Transistors
Capacitors
28
39
4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage: VCC+ (see Note 1) 22 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC− (see Note 1) −22 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage (see Note 2) ±30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (either input, see Note 3) ±22 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of output short circuit (see Note 4) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 5 and 6): D package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC−.
2. Differential voltages are at IN+ with respect to IN−.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either power supply.
5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
SLOS099E − O C TOBER 1983 − REVISED MAY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
VCC±Supply voltage ±3±18 V
VIC Common-mode input voltage VCC± = ±15 V −13 13 V
TAOperating free-air temperature 0 70 °C
*+
**
SLOS099E − OCTOBER 1983 − REVISED MAY 2004
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
TA
OP07C OP07D
UNIT
PARAMETER
TEST CONDITIONS†
T
AMIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
VO = 0,
RS = 50 Ω
25°C 60 150 60 150
V
VIO Input offset voltage VO = 0, RS = 50 Ω0°C to 70°C85 250 85 250 µV
aVIO Temperature coefficient of input offset voltage VO = 0, RS = 50 Ω0°C to 70°C 0.5 1.8 0.7 2.5 µV/°C
Long-term drift of input offset voltage See Note 6 0.4 0.5 µV/mo
Offset adjustment range RS = 20 kΩ,See Figure 1 25°C±4±4 mV
IIO
Input offset current
25°C 0.8 6 0.8 6
nA
IIO Input offset current 0°C to 70°C 1.6 8 1.6 8 nA
aIIO Temperature coefficient of input offset current 0°C to 70°C 12 50 12 50 pA/°C
IIB
Input bias current
25°C±1.8 ±7±2±12
nA
IIB Input bias current 0°C to 70°C±2.2 ±9±3±14 nA
aIIB Temperature coefficient of input bias current 0°C to 70°C 18 50 18 50 pA/°C
VICR
Common-mode input voltge range
25°C±13 ±14 ±13 ±14
V
VICR Common-mode input voltge range 0°C to 70°C±13 ±13.5 ±13 ±13.5 V
RL ≥ 10 kΩ ±12 ±13 ±12 ±13
VOM
Peak output voltage
RL ≥ 2 kΩ25°C±11.5 ±12.8 ±11.5 ±12.8
V
VOM Peak output voltage RL ≥ 1 kΩ
25 C
±12 ±12 V
RL ≥ 2 kΩ0°C to 70°C±11 ±12.6 ±11 ±12.6
AVD
Large-signal differential voltage amplification
VCC±= ±3 V,
RL ≥ 500 kΩVO = ±0.5 V, 25°C 100 400 400
V/mV
AVD Large-signal differential voltage amplification
VO = ±10 V,
RL = 2 kΩ
25°C 120 400 120 400 V/mV
VO = ±10 V, RL = 2 kΩ0°C to 70°C100 400 100 400
B1Unity-gain bandwidth 25°C 0.4 0.6 0.4 0.6 MHz
riInput resistance 25°C 8 33 7 31 MΩ
CMRR
Common-mode rejection ratio
VIC = ±13 V,
RS = 50 Ω
25°C 100 120 94 110
dB
CMRR Common-mode rejection ratio VIC = ±13 V
,
RS = 50 Ω0°C to 70°C97 120 94 106 dB
kSVS
Supply-voltage sensitivity (∆VIO/∆VCC)
VCC± =
±
3 V to
±
18 V,
25°C 7 32 7 32
V/V
kSVS Supply-voltage sensitivity (∆VIO/∆VCC)
VCC± = ±3 V to ±18 V,
RS = 50 Ω0°C to 70°C 10 51 10 51 µV/V
VO = 0, No load 80 150 80 150
PDPower dissipation VCC±= ±3 V, VO = 0,
No load 25°C4 8 4 8 mW
†All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise noted.
NOTE 7: Since long-term drift cannot be measured on the individual devices prior to shipment, this specification is not intended to be a warranty. It is an engineering estimate of the
averaged trend line of drift versus time over extended periods after the first 30 days of operation.
SLOS099E − O C TOBER 1983 − REVISED MAY 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VCC± = ±15 V, TA = 25°C
PARAMETER
TEST †
OP07C OP07D
UNIT
PARAMETER
TEST
CONDITIONS†TYP TYP
UNIT
f = 10 Hz 10.5 10.5
V
n
Equivalent input noise voltage f = 100 Hz 10.2 10.3 nV/√Hz
Vn
Equivalent input noise voltage
f = 1 kHz 9.8 9.8
nV/√Hz
VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 0.38 0.38 µV
f = 10 Hz 0.35 0.35
I
n
Equivalent input noise current f = 100 Hz 0.15 0.15 pA/√Hz
In
Equivalent input noise current
f = 1 kHz 0.13 0.13
pA/√Hz
IN(PP) Peak-to-peak equivalent input noise current f = 0.1 Hz to 10 Hz 15 15 pA
SR Slew rate RL≥ 2 kΩ0.3 0.3 V/µs
†All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise noted.
APPLICATION INFORMATION
OUT
VCC−
VCC+
IN−
IN+ +
−
OFFSET N1
3
2
4
76
20 kΩ
N2
OFFSET
8
1
Figure 1. Input Offset-Voltage Null Circuit
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jun-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OP-07DPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP-07DPSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP-07DPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
OP07CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
OP07DD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07DDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07DDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07DDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07DDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07DDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OP07DP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jun-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OP07DPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OP-07DPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
OP07CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OP07DDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OP-07DPSR SO PS 8 2000 367.0 367.0 38.0
OP07CDR SOIC D 8 2500 340.5 338.1 20.6
OP07DDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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