Low Jitter Clock Generator with Eight LVPECL Outputs AD9525 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated ultralow noise synthesizer 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs 2 differential reference inputs and 1 single-ended reference input APPLICATIONS REFA AD9525 REFA REFB PLL /S REFB SYNC_OUT SYNC_OUT OUT7 REFC OUT7 OUT6 LTE and multicarrier GSM base stations Clocking high speed ADCs, DACs ATE and high performance instrumentation 40/100 Gb/sec OTN line side clocking Cable/DOCSIS CMTS clocking Test and measurement OUT6 OUT5 OUT5 CLKIN OUT4 DIVIDERS OUT4 CLKIN OUT3 OUT3 OUT2 OUT2 OUT1 OUT1 SPI CONTROL OUT0 10011-001 OUT0 Figure 1. GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 offers a dedicated output that can be used to provide a programmable signal for resetting or synchronizing a data converter. The output signal is activated by a SPI write. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6. The AD9525 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The external VCXO or VCO can have an operating voltage of up to 5.5 V. Rev. A The AD9525 operates over the extended industrial temperature range of -40C to +85C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9525 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 12 Applications ....................................................................................... 1 Thermal Resistance .................................................................... 12 Functional Block Diagram .............................................................. 1 ESD Caution................................................................................ 12 General Description ......................................................................... 1 Pin Configuration and Function Descriptions........................... 13 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 15 Specifications..................................................................................... 3 Terminology .................................................................................... 18 Conditions ..................................................................................... 3 Detailed Block Diagram ................................................................ 19 Supply Current .............................................................................. 3 Theory of Operation ...................................................................... 20 Power Dissipation ......................................................................... 3 Configuration of the PLL .......................................................... 20 REFA and REFB Input Characteristics ...................................... 4 Clock Distribution ..................................................................... 23 REFC Input Characteristics ........................................................ 4 SYNC_OUT ................................................................................ 23 Clock Inputs .................................................................................. 5 Reset Modes ................................................................................ 25 PLL Characteristics ...................................................................... 5 Power-Down Modes .................................................................. 26 PLL Digital Lock Detect .............................................................. 6 Serial Control Port ......................................................................... 27 Clock Outputs ............................................................................... 6 Pin Descriptions ......................................................................... 27 Timing Characteristics ................................................................ 7 General Operation of Serial Control Port ............................... 27 Clock Output Absolute Time Jitter (Clock Generation Using External 122.88 MHz VCXO).......................................... 8 The Instruction Word (16 Bits) ................................................ 28 Clock Output Absolute Time Jitter (Clock Generation Using External 1475 MHz VCO) ............................................... 8 Control Registers ............................................................................ 31 Clock Output Absolute Time Jitter (Clock Generation Using External 2.05 GHz VCO) ................................................. 9 Register Map Descriptions ............................................................ 33 Clock Output Absolute Time Jitter (Clock Generation Using External 3 GHz VCO) ...................................................... 9 Applications Information .............................................................. 45 Frequency Planning Using the AD9525 .................................. 45 Clock Output Additive Phase Noise (Distribution Only; Clock Input to Distribution Output, Including VCO Divider) .......................................................................................... 9 Using the AD9525 Outputs for ADC Clock Applications .... 45 PD, RESET, and REF_SEL Pins ................................................ 10 STATUS and REF_MON Pins .................................................. 10 Serial Control Port ..................................................................... 11 MSB/LSB First Transfers ........................................................... 28 Control Register Map Overview .............................................. 31 LVPECL Clock Distribution ..................................................... 46 SYNC_OUT Distribution ......................................................... 46 Outline Dimensions ....................................................................... 47 Ordering Guide............................................................................... 47 REVISION HISTORY 4/13--Rev. 0 to Rev. A Changes to One Channel, One Driver and One Channel, Two Drivers Parameters, Table 3.............................................................. 4 Change to Figure 18 ........................................................................19 Changes to Register 0x01A, Table 28 ............................................31 Change to Register 0x000, Bit 6, Table 28 .................................... 33 Changes to Table 35 ........................................................................ 38 Changes to Table 38 ........................................................................ 40 10/12--Revision 0: Initial Version Rev. A | Page 2 of 48 Data Sheet AD9525 SPECIFICATIONS Typical is given for VDD3 = 3.3 V 5%; VDD3 VDD_CP 5.25 V; TA = 25C; OUT_RSET resistor = 4.12 k; CP_RSET resistor (CPRSET) = 5.1 k, unless otherwise noted. Minimum and maximum values are given over full VDD3 and TA (-40C to +85C) variation as listed in Table 1. REFA at 122.88 MHz, CLKIN frequency = 2949.12 MHz. CONDITIONS Table 1. Parameter SUPPLY VOLTAGE VDD3 VDD_CP OUT_RSET PIN RESISTOR CP_RSET PIN RESISTOR (CPRSET RESISTOR) Min TEMPERATURE RANGE, TA -40 Typ Max 3.3 VDD3 5.25 4.12 5.1 +25 Unit Test Conditions/Comments V V k k 3.3 V 5% Nominally 3.3 V to 5.0 V 5% Sets internal biasing currents; connect to ground Sets internal CP current range, nominally 4.8 mA (CP_LSB = 600 A); actual current calculated by CP_LSB = 3.06/CPRSET, connect to ground; CPRSET range = 2.7 k to10 k +85 C Typ Max Unit 310 369 mA 98 107 mA 6.6 53 45 7.6 63.4 54 mA mA mA Typ Max Unit Power-On Default Typical Operation 1 782 1.15 871 1.23 mW W Typical Operation 2 1.17 1.25 W PD Power-Down PD Power-Down, Maximum Sleep 51 13.2 56.4 19.1 mW mW VDD_CP Supply 22 25 mW SUPPLY CURRENT Table 2. Parameter SUPPLY CURRENT FOR VDD3 and VDD_CP PINS Min VDD3 (Pin 3, Pin 36, Pin 41, Pin 46), Total Supply Voltage for Outputs VDD3 (Pin 9), Supply Voltage for M Divider, CLK Inputs and Distribution VDD_CP (Pin 13), Supply Voltage for Charge Pump VDD3 (Pin 20), Supply Voltage for PLL VDD3 (Pin 32), Supply Voltage for SYNC_OUT Test Conditions/Comments fCLK = 2949.12 MHz; REFA and REFB enabled at 122.88 MHz; R dividers = 2; M divider = 2; PFD = 61.44 MHz; eight LVPECL outputs at 1474.56 MHz; LVPECL 780 mV mode Outputs terminated with 50 to VDD3 - 2 V POWER DISSIPATION Table 3. Parameter POWER DISSIPATION, CHIP Min Rev. A | Page 3 of 48 Test Conditions/Comments Does not include power dissipated in external resistors; all LVPECL outputs terminated with 50 to VDD3 - 2 V; LVPECL 780 mV mode No programming; default register values fCLK = 2949.12 MHz; REFA and REFB enabled at 122.88 MHz; R dividers = 2; M divider = 2; PFD = 61.44 MHz; eight LVPECL outputs at 1474.56 MHz fCLK = 2949.12 MHz; PLL on; REFA enabled at 122.88 MHz; M divider = 1; PFD = 122.88MHz; eight LVPECL outputs at 2949.12 MHz PD pin pulled low PD pin pulled low; power-down distribution reference, Reg. 0x230[1] = 1b; note that powering down distribution reference disables safe powerdown mode (see Power-Down Modes section) PLL operating; typical closed-loop configuration AD9525 Parameter POWER DELTAS, INDIVIDUAL FUNCTIONS M Divider On/Off P Divider On/Off B Divider On/Off REFB On PLL On/Off Data Sheet Min Typ Max Unit 5 3 16 15 254 8.7 5.7 23.1 25 300.5 mW mW mW mW mW One Channel, One Driver 107 132 mW One Channel, Two Drivers 184 233 mW Typ Max Unit 500 MHz 1.78 1.61 4.9 5.4 mV p-p V V k k Test Conditions/Comments Power delta when a function is enabled/disabled M divider bypassed P divider bypassed B divider bypassed Delta from powering down REFB differential input PLL off to PLL on, normal operation; no reference enabled No LVPECL output on to one LVPECL output on at 2949.12 MHz; same output pair No LVPECL output on to two LVPECL outputs on at 2949.12 MHz; same output pair REFA AND REFB INPUT CHARACTERISTICS Table 4. Parameter DIFFERENTIAL MODE (REFA, REFA; REFB, REFB) Min Input Frequency 0 Input Sensitivity Self-Bias Voltage, REFA and REFB Self-Bias Voltage, REFA and REFB Input Resistance, REFA and REFB Input Resistance, REFA and REFB 200 1.52 1.38 4.5 4.9 1.65 1.50 4.7 5.2 DUTY CYCLE Pulse Width Low Pulse Width High 1 Test Conditions/Comments Differential mode (can accommodate singleended input by ac grounding unused input) Frequencies below ~1 MHz should be dc-coupled; be careful to match self-bias voltage Frequency at 122.88 MHz Self-bias voltage of REFA and REFB inputs 1 Self-bias voltage of REFA and REFB inputs1 Self-biased1 Self-biased1 Duty cycle bounds are set by pulse width high and pulse width low 500 500 ps ps The differential pairs of REFA and REFA, REFB and REFB self-bias points are offset slightly to avoid chatter on an open input condition. REFC INPUT CHARACTERISTICS Table 5. Parameter REFC INPUT Input Frequency Range Input High Voltage Input Low Voltage Input Current Duty Cycle Pulse Width Low Pulse Width High Min Typ Max Unit Test Conditions/Comments 300 MHz V V A DC-coupled input (not self-biased) 2.0 0.8 1 Duty cycle bounds are set by pulse width high and pulse width low 1 1 ns ns Rev. A | Page 4 of 48 Data Sheet AD9525 CLOCK INPUTS Table 6. Parameter Input Frequency Min 0 Typ Input Sensitivity Input Level 150 Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Resistance Input Capacitance 1.55 1.3 6.7 1.64 Min Typ 7 2 Max 3.6 Unit GHz 2 mV p-p V p-p Test Conditions/Comments Frequencies below ~1 MHz should be dc-coupled; be careful to match self-bias voltage Measured at 3.1 GHz Larger voltage swings can turn on the protection diodes and can degrade jitter performance Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled Self-biased 1.74 1.8 7.4 V V k pF Max Unit Test Conditions/Comments 125 45 MHz MHz Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns VDD_CP (Pin 13); VCP is the voltage of the charge pump pin (CP, Pin 14) Programmable With CPRSET = 5.1 k; higher ICP is possible by changing CPRSET; VCP = VDD_CP/2 V With CPRSET = 5.1 k; lower ICP is possible by changing CPRSET, VCP = VDD_CP/2 V VCP = VDD_CP/2 V PLL CHARACTERISTICS Table 7. Parameter PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency CHARGE PUMP (CP) ICP Sink/Source High Value 4.5 4.9 5.4 mA Low Value 0.57 0.61 0.67 mA Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature P DIVIDER (PART OF N DIVIDER) Input Frequency P = 1 Input Frequency P = 2 Input Frequency P = 3 Input Frequency P = 4 Input Frequency P = 5 Input Frequency P = 6 B DIVIDER (PART OF N DIVIDER) Input Frequency M DIVIDER Input Frequency NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) At 61.44 MHz PFD Frequency At 122.88 MHz PFD Frequency PLL Figure of Merit (FOM) 2.5 2.7 10 3.5 2 1.5 2 % k A % % % 1500 3000 3600 3600 3600 3600 MHz MHz MHz MHz MHz MHz 1500 MHz 3600 MHz VDD_CP = 5 V 0.5 V < VCP < VDD_CP - 0.5 V 0.5 V < VCP < VDD_CP - 0.5 V VCP = VDD_CP/2 V B counter input frequency (N Divider input frequency divided by P) PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) -144 -141 -222 dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 5 of 48 Reference slew rate > 0.25 V/ns; FOM +10 log (fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20 log(N) AD9525 Data Sheet PLL DIGITAL LOCK DETECT Table 8. Parameter PLL DIGITAL LOCK DETECT WINDOW 1 Min Typ Max Unit Lock Threshold (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns) Unlock Threshold (Hysteresis)1 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns) 1 4 7 3.5 ns ns ns 8.3 16.9 11 ns ns ns Test Conditions/Comments Signal available at the STATUS and REF_MON pins when selected by appropriate register settings; lock detect window settings can be varied by changing the CPRSET resistor Selected by Reg. 0x010[1:0] and Reg. 0x019[1], which is the threshold for transitioning from unlock to lock Reg. 0x010[1:0] = 00b, 01b,11b; Reg. 0x019[1] = 1b Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b Selected by Reg. 0x017[1:0] and Reg. 0x019[1], which is the threshold for transitioning from unlock to lock Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 1b Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. CLOCK OUTPUTS Table 9. Parameter LVPECL CLOCK OUTPUTS Output Frequency, Maximum Rise Time/Fall Time (20% to 80%) Duty Cycle M=1 M = 2, 4, 6 M = 3, 5 Output Differential Voltage, Magnitude Common-Mode Output Voltage Min Typ Max Unit 105 162 GHz ps 47 45 47 45 32 750 50 50 49 49 32 830 53 55 51 55 33 984 % % % % % mV VDD3 - 1.42 VDD3 - 1.37 VDD3 - 1.32 V 3.6 Rev. A | Page 6 of 48 Test Conditions/Comments Input duty cycle = 50/50 FOUT = 2800 MHz FOUT < 3000 MHz FOUT = 1400 MHz FOUT < 1500 MHz FOUT = 933.33 MHz Voltage across pins, output driver static; Termination = 50 to VDD3 - 2 V Output driver static; VDD3 (Pin 3, Pin 36, Pin 41, Pin 46); Termination = 50 to VDD3 - 2 V Data Sheet AD9525 TIMING CHARACTERISTICS Table 10. Parameter PROPAGATION DELAY, tPECL, CLKIN TO LVPECL OUTPUT For All M Divider Values Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS1 All LVPECL Outputs Temperature Coefficient All LVPECL Outputs Across Multiple Parts OUTPUT SKEW, LVPECL-TO-SYNC_OUT1 SYNC_OUT LVPECL Mode All LVPECL Outputs Temperature Coefficient All LVPECL Outputs Across Multiple Parts SYNC_OUT CMOS Mode All LVPECL Outputs All LVPECL Outputs Across Multiple Parts PROPAGATION DELAY, REF TO LVPECL OUTPUT 1 Min Typ Max Unit 461 522 388 600 ps fs/C 13.5 14 25.2 ps fs/C ps Across temperature and VDD per device Across temperature and VDD per device 417 ps fs/C ps 2.34 2.46 924 ns ns ps Across temperature and VDD per device 144 189 543 1.64 267 581 298 Test Conditions/Comments Termination as shown in Figure 35 High frequency clock distribution configuration REF refers to either REFA/REFA or REFB/REFB pairs The output skew is the difference between any two paths while operating at the same voltage and temperature. Timing Diagrams tCLK CLK DIFFERENTIAL tPECL 80% LVPECL tRP tFP Figure 3. LVPECL Timing, Differential Figure 2. CLK/CLK to Clock Output Timing, M Divider = 1 Rev. A | Page 7 of 48 10011-003 tCMOS 10011-002 20% AD9525 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 122.88 MHZ VCXO) Table 11. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min FOUT = 122.88 MHz Typ Max 107 69 108 107 FOUT = 61.44 MHz Unit fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.88 MHz; R divider = 1; LBW = 40 Hz Integration BW = 1 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 1 kHz to 20 MHz Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 1475 MHZ VCO) Table 12. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min FOUT = 1474.56 MHz Typ Max 99 77 74 68 -93 104 87 75 -98 Reference Sideband Spurs FOUT = 245.76 MHz Reference Sideband Spurs Unit fs rms fs rms fs rms fs rms dBc fs rms fs rms fs rms dBc Test Conditions/Comments Application example based on a typical setup using an external 1475 MHz VCO (Bowei Model MVCO-1475); reference = 122.88 MHz; R divider = 1; PLL LBW = 18 kHz Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 100 MHz Integration BW = 10 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 100 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz Table 13. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER FOUT = 1474.56 MHz Reference Sideband Spurs FOUT = 245.76 MHz Reference Sideband Spurs Min Typ 72 40 33 28 -94 83 61 46 -93 Max Unit fs rms fs rms fs rms fs rms dBc fs rms fs rms fs rms dBc Rev. A | Page 8 of 48 Test Conditions/Comments Application example based on a typical setup using an external 1475 MHz VCO (Z-Communications CRO1474-LF); reference = 122.88 MHz; R divider = 1; PLL LBW = 8 kHz Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 100 MHz Integration BW = 10 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz Data Sheet AD9525 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 2.05 GHZ VCO) Table 14. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min FOUT = 2048.867 MHz Typ Max 19 21 87 -105 Reference Sideband Spurs Unit fs rms fs rms fs rms dBc Test Conditions/Comments Application example based on a typical setup using an external 2.05 MHz VCO (Bowei Model MVCO2050A); reference = 122.054215 MHz; R divider = 12; PLL LBW = 5 kHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz 10.671MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 3 GHZ VCO) Table 15. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min FOUT = 2949.12 MHz; PLL LBW = 7 kHz Typ Max 63 38 34 28 -99 62 36 31 25 -100 78 60 44 33 -96 Reference Sideband Spurs FOUT = 1474.56 MHz; PLL LBW = 7 kHz Reference Sideband Spurs FOUT = 491.52 MHz; PLL LBW = 7 kHz Reference Sideband Spurs Unit fs rms fs rms fs rms fs rms dBc fs rms fs rms fs rms fs rms dBc fs rms fs rms fs rms fs rms dBc Test Conditions/Comments Application example based on a typical setup using an external 2950 MHz VCO (Z-Communications Model CRO-2950); reference = 122.88 MHz; R divider = 1 Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 100 MHz Integration BW = 10 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 100 MHz Integration BW = 10 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz Integration BW = 1 kHz to 100 MHz Integration BW = 10 kHz to 100 MHz Integration BW = 10 kHz to 40 MHz Integration BW = 12 kHz to 20 MHz 122.88 MHz CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; CLOCK INPUT TO DISTRIBUTION OUTPUT, INCLUDING VCO DIVIDER) Table 16. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 2949.12 MHz, FOUT = 2949.12 MHz Divider = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 800 kHz Offset At 1 MHz Offset At 10 MHz Offset At 100 MHz Offset Min Typ Max -112 -122 -133 -141 -146 -148 -148 -149 -151 Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 9 of 48 Test Conditions/Comments Distribution section only; does not include PLL and VCO AD9525 Parameter CLK = 1474.56 MHz, FOUT = 1474.56 MHz Divider = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 800 kHz Offset At 1 MHz Offset At 10 MHz Offset CLK = 122.88 MHz, FOUT = 122.88 MHz Divider = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 800 kHz Offset At 1 MHz Offset At 10 MHz Offset Data Sheet Min Typ Max Unit -114 -125 -134 -144 -149 -151 -151 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -134 -145 -153 -159 -161 -161 -161 -161 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments PD, RESET, AND REF_SEL PINS Table 17. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current PD, RESET Logic 0 Current REF_SEL Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming Min Typ Max 2.0 Unit 1 -112 V V A A 1 2 A pF 0.8 50 100 Test Conditions/Comments The minus sign indicates that current is flowing out of the AD9525, which is due to the internal pull-up resistor ns ns STATUS AND REF_MON PINS Table 18. Parameter OUTPUT CHARACTERISTICS Output Voltage High, VOH Output Voltage Low, VOL MAXIMUM TOGGLE RATE Min Typ Max Unit 0.4 V V MHz 2.7 200 Rev. A | Page 10 of 48 Test Conditions/Comments 1 mA output load Applies when mux is set to any divider or counter output or PFD up/down pulse; usually debug mode only; beware that spurs can couple to output when any of these pins is toggling Data Sheet AD9525 SERIAL CONTROL PORT Table 19. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup and Hold, tS, tH CS Minimum Pulse Width High, tPWH Min Typ Max Unit 0.8 2.5 -112 V V A A 2 pF 112 V V A A pF 2.0 Test Conditions/Comments CS has an internal 30 k pull-up resistor The minus sign indicates that current is flowing out of the AD9525, which is due to the internal pull-up resistor SCLK has an internal 30 k pull-down resistor 2.0 0.8 1 2 2.0 0.8 10 20 2 V V nA nA pF 1 mA load current 2.7 0.4 31 16 16 2 1.1 12 2 3.6 V V MHz ns ns ns ns ns ns ns Rev. A | Page 11 of 48 AD9525 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 20. Parameter VDD3 to GND VDD_CP, CP to GND REFA, REFA, REFB, REFB, REFC to GND OUT_RSET to GND CP_RSET to GND CLKIN, CLKIN to GND CLKIN to CLKIN SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, SYNC_OUT, SYNC_OUT to GND RESET, PD, STATUS, REF_MON to GND Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating -0.3 V to +3.6 V -0.3 V to +5.8 V -0.3 V to VDD3 + 0.3 V -0.3 V to VDD3 + 0.3 V -0.3 V to VDD3 + 0.3 V -0.3 V to VDD3 + 0.3 V -1.2 V to +1.2 V -0.3 V to VDD3 + 0.3 V -0.3 V to VDD3 + 0.3 V -0.3 V to VDD3 + 0.3 V 150C -65C to +150C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 21. Thermal Resistance (Simulated) Package Type 48-Lead LFCSP Airflow Velocity (m/sec) 0 1.0 2.5 JA1, 2 27.3 23.9 21.4 JC1, 3 2.1 JB1, 4 14.7 JT1, 2 0.2 0.3 0.4 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 1 2 See Table 21 for JA. ESD CAUTION Rev. A | Page 12 of 48 Unit C/W C/W C/W Data Sheet AD9525 48 47 46 45 44 43 42 41 40 39 38 37 OUT2 OUT2 VDD3 OUT3 OUT3 OUT4 OUT4 VDD3 OUT5 OUT5 OUT6 OUT6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9525 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VDD3 OUT7 OUT7 REF_MON VDD3 SYNC_OUT SYNC_OUT GND SDO SDIO SCLK CS NOTES 1. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 10011-004 VDD_CP CP GND CP_RSET REFA REFA GND VDD3 REFB REFB PD RESET 13 14 15 16 17 18 19 20 21 22 23 24 OUT1 1 OUT1 2 VDD3 3 OUT0 4 OUT0 5 OUT_RSET 6 CLKIN 7 CLKIN 8 VDD3 9 STATUS 10 REFC 11 REF_SEL 12 Figure 4. Pin Configuration Table 22. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic OUT1 OUT1 VDD3 OUT0 OUT0 OUT_RSET CLKIN CLKIN Type O O P O O O I I 9 10 11 12 13 VDD3 STATUS REFC REF_SEL VDD_CP P O I I P 14 CP O 15 16 GND CP_RSET GND O 17 18 19 20 21 22 23 24 25 26 27 REFA REFA GND VDD3 REFB REFB PD RESET CS SCLK SDIO I I GND P I I I I I I I Description LVPECL Complementary Output 1. LVPECL Output 1. 3.3 V Power Supply for Channel OUT0 and Channel OUT1. LVPECL Complementary Output 0. LVPECL Output 0. Clock Distribution Current Set Resistor. Connect a 4.12 k resistor from this pin to GND. Along with CLKIN, this pin is the differential input for the clock distribution section. Along with CLKIN, this pin is the differential input for the clock distribution section. If a single-ended input is connected to the CLKIN pin, connect a 0.1 F bypass capacitor from CLKIN to ground. 3.3 V Power Supply for CLK Inputs, M Divider, and Output Distribution. Lock Detect and Other Status Signals. Reference Clock Input C. This pin is a CMOS input for the PLL reference. Reference Input Select. Logic high = REFB. No internal pull-up or pull-down resistor on this pin. Power Supply for Charge Pump (CP). VDD3 < VDD_CP < 5.0 V. VDD_CP must still be connected to 3.3 V if the PLL is not used. Charge Pump (Output). This pin connects to an external loop filter. This pin can be left unconnected if the PLL is not used. Ground for Charge Pump VDD_CP Supply. Connect to ground. Charge Pump Current Set Resistor. Connect a 5.1 k resistor from this pin to GND. This resistor can be omitted if the PLL is not used. Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Ground for PLL Power Supply. Connect to ground. 3.3 V Power Supply for PLL. Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Chip Power-Down, Active Low. This pin has an internal 30 k pull-up resistor. Chip Reset, Active Low. This pin has an internal 30 k pull-up resistor. Serial Control Port Chip Select; Active Low. This pin has an internal 30 k pull-up resistor. Serial Control Port Clock Signal. This pin has an internal 30 k pull-down resistor. Serial Control Port Bidirectional Serial Data In/Out. Rev. A | Page 13 of 48 AD9525 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 EP Mnemonic SDO GND SYNC_OUT SYNC_OUT VDD3 REF_MON OUT7 OUT7 VDD3 OUT6 OUT6 OUT5 OUT5 VDD3 OUT4 OUT4 OUT3 OUT3 VDD3 OUT2 OUT2 EP, GND Data Sheet Type I GND O O P O O O P O O O O P O O O O P O O GND Description Serial Control Port Unidirectional Serial Data Out. Connect to ground. LVPECL Complementary Output for Programmable Sync Signal. LVPECL Output for Programmable Sync Signal. Power Supply for SYNC_OUT Driver. Reference Monitor (Output). This pin has multiple selectable outputs. LVPECL Complementary Output 7. LVPECL Output 7. 3.3 V Power Supply for Channel OUT6 and Channel OUT7. LVPECL Complementary Output 6. LVPECL Output 6. LVPECL Complementary Output 5. LVPECL Output 5. 3.3 V Power Supply for Channel OUT4 and Channel OUT5. LVPECL Complementary Output 4. LVPECL Output 4. LVPECL Complementary Output 3. LVPECL Output 3. 3.3 V Power Supply for Channel OUT2 and Channel OUT3. LVPECL Complementary Output 2. LVPECL Output 2. Exposed Paddle. The exposed pad is a ground connection on the chip that must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. Rev. A | Page 14 of 48 Data Sheet AD9525 TYPICAL PERFORMANCE CHARACTERISTICS 6 CURRENT FROM CP PIN (mA) 5 PUMP UP PUMP DOWN 4 1 3 2 0 1 2 VOLTAGE ON CP PIN (V) 3 4 CH1 500mV Figure 5. Charge Pump Characteristics at VDD_CP = 3.3 V 2.5 PUMP UP PUMP DOWN 4 3 2 1 0 1 2 3 4 5 6 VOLTAGE ON CP PIN (V) -218.5 -219.0 -219.5 -220.0 -220.5 -221.0 -221.5 -222.5 0.6 0.8 1.0 1.2 10011-007 -222.0 0.4 600mV p-p 1.5 1.3 400mV p-p 1.1 0.9 0.7 500 1000 1500 2000 2500 3000 Figure 9. LVPECL Differential Voltage Swing vs. Frequency -218.0 SLEW RATE OF REFA (V/ns) 1.7 FREQUENCY (MHz) -217.5 0.2 780mV p-p 1.9 0 Figure 6. Charge Pump Characteristics at VDD_CP = 5.0 V 0 960mV p-p 2.1 0.5 10011-006 0 2.3 Figure 7. PLL Figure of Merit (FOM) vs. Slew Rate at REFA Rev. A | Page 15 of 48 10011-009 DIFFERENTIAL VOLTAGE SWING (V p-p) 5 CURRENT FROM CP PIN (mA) 40.0mV Figure 8. LVPECL Output (Differential) at 122.88 MHz 6 PLL FIGURE OF MERIT (dBc/Hz) A CH1 2.5ns/DIV 40.0GS/s 10011-008 0 10011-005 1 AD9525 Data Sheet -80 -20 -90 -40 1: 2: 3: 4: 5: 6: 7: -30 -50 -60 -130 -140 -90 -100 -130 -150 -160 -160 -170 20M 10011-010 10M 1M 100k 10k 1k 100 10 -20 -90 -30 -40 -100 -50 -60 -110 -70 -80 -130 -140 -150 -160 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 11. Additive (Residual) Phase Noise, CLK-to-LVPECL at 1500 MHz, Divide-by-1 -110 -120 -50 1kHz, -103.4dBc/Hz 10kHz, -109.2dBc/Hz 100kHz, -130.6dBc/Hz 800kHz, -147.3dBc/Hz 1MHz, -148.5dBc/Hz 10MHz, -152.9dBc/Hz 100MHz, -154.4dBc/Hz 7 1k 10k 100k 1M -90 -110 1 2 -120 3 -130 NOISE: ANALYSIS RANGE X: START 1kHz STOP 100MHz INTG NOISE: -63.7dBc/100MHz RMS NOISE: 919.9RAD 52.7mdeg RMS JITTER: 99.3fsec -180 100 1k 10k 100k 1: 2: 3: 4: 5: 6: 7: -60 -100 7 -80 -90 -100 -110 -120 -130 1 5 2 -160 6 FREQUENCY (Hz) Figure 12. Phase Noise (Absolute), External VCO (Bowei Model MVCO-1475) at 1474.56 MHz; PFD = 122.88 MHz; LBW = 18 kHz; LVPECL Output = 1474.56 MHz -180 100 7 3 4 -170 100M 100M 1kHz, -136.9dBc/Hz 10kHz, -150.3dBc/Hz 100kHz, -156.4dBc/Hz 800kHz, -161.1dBc/Hz 1MHz, -160.9dBc/Hz 10MHz, -161.7dBc/Hz 100MHz, -161.8dBc/Hz -150 4 10M 10M NOISE: ANALYSIS RANGE X: START 12kHz STOP 20MHz INTG NOISE: -88.6dBc/20.0MHz RMS NOISE: 52.8RAD 3.0mdeg RMS JITTER: 68.4fsec -70 -140 5 1M 6 RMS NOISE: 575.9RAD 33.0mdeg RMS JITTER: 62.2fsec -50 -80 -170 5 4 -40 -70 -160 2 -130 3 -140 NOISE: -150 ANALYSIS RANGE X: START 1kHz STOP 100MHz -160 INTG NOISE: -67.8dBc/100MHz -30 10011-012 PHASE NOISE (dBc) -60 100M Figure 14. Phase Noise (Absolute), External VCO (Z-Communications Model CRO-2950) at 2949.12 MHz; PFD = 122.88 MHz; LBW = 8k Hz; LVPECL Output = 1474.56 MHz PHASE NOISE (dBc) -40 10M 1 -20 1: 2: 3: 4: 5: 6: 7: -30 -150 1M FREQUENCY (Hz) -20 -140 100k 1: 1kHz, -109.3936dBc/Hz 2: 10kHz, -113.5616dBc/Hz 3: 100kHz, -143.3042dBc/Hz 4: 800kHz, -150.5212dBc/Hz 5: 1MHz, -150.7666dBc/Hz 6: 10MHz, -152.9127dBc/Hz 7: 100MHz, -156.0506 dBc/Hz -180 100 10011-011 10 10k -90 -100 -170 -170 1k 7 6 Figure 13. Phase Noise (Absolute), External VCO (Z-Communications Model CRO-2950) at 2949.12 MHz; PFD = 122.88 MHz; LBW = 8 kHz; LVPECL Output = 2949.12 MHz -80 -120 5 4 FREQUENCY (Hz) PHASE NOISE (dBc) PHASE NOISE (dBc) Figure 10. Additive (Residual) Phase Noise, CLK-to-LVPECL at 122.88 MHz, Divide-by-1 3 NOISE: ANALYSIS RANGE X: START 1kHz STOP 100MHz INTG NOISE: -59.5dBc/100MHz RMS NOISE: 1.5mRAD 86.2mdeg RMS JITTER: 81.2fsec -180 100 -170 FREQUENCY (Hz) 2 -120 -140 -150 1 -110 10011-013 -120 -70 -80 1k 10k 100k FREQUENCY (Hz) 1M 6 10M 10011-014 -110 10011-112 PHASE NOISE (dBc) PHASE NOISE (dBc) -100 1kHz, -96.0dBc/Hz 10kHz, -106.3dBc/Hz 100kHz, -137.2dBc/Hz 800kHz, -144.5dBc/Hz 1MHz, -144.6dBc/Hz 10MHz, -147.7dBc/Hz 100MHz, -152.4dBc/Hz Figure 15. Phase Noise (Absolute), External VCXO (122.88 MHz VCXO) (Crystek CVHD-950); Reference = 122.88 MHz; R Divider = 1); LBW = 40 Hz; LVPECL Output = 122.88 MHz Rev. A | Page 16 of 48 Data Sheet AD9525 -20 -20 -30 -40 -50 -60 -70 -80 1 2 -110 -120 -130 -140 -150 -160 -170 3 5 NOISE: ANALYSIS RANGE X: START 1kHz STOP 100MHz INTG NOISE: -62.1dBc/19.7MHz RMS NOISE: 1.1RAD 63.6mdeg RMS JITTER: 86.2fsec -180 100 1k 10k 100k FREQUENCY (Hz) 7 4 -70 -80 -90 -100 1 -110 -120 2 -130 -140 5 3 -150 -160 6 4 7 6 -170 1M 10M 100M -180 100 Figure 16. Phase Noise (Absolute), External VCO 2.05 GHz VCO (Bowei Model MVCO-2050A); at 2050 MHz; Reference = 122.054215 MHz; R Divider = 12 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 10011-017 -90 -100 10011-015 PHASE NOISE (dBc) -50 -60 1kHz, -85.0dBc/Hz 10kHz, -99.3dBc/Hz 100kHz, -123.0dBc/Hz 800kHz, -140.7dBc/Hz 1MHz, -142.0dBc/Hz 10MHz, -149.0dBc/Hz 100MHz, -153.3dBc/Hz PHASE NOISE (dBc) 1: 2: 3: 4: 5: 6: 7: -30 -40 Figure 17. Phase Noise (Absolute), External VCO (Z-Communications CRO1474-LF) at 1474.56 MHz; PFD = 122.88 MHz; LBW = 15 kHz; LVPECL Output = 1474.56 MHz Rev. A | Page 17 of 48 AD9525 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval; it can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Additive Phase Noise Additive phase noise is the amount of phase noise that can be attributed to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted, making it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that can be attributed to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. A | Page 18 of 48 Data Sheet AD9525 DETAILED BLOCK DIAGRAM REF_SEL CP VDD_CP CP_RSET CLKIN CLKIN AD9525 REFA REFA REFB REFB REFC NINE DIFFERENTIAL OUTPUTS LVPECL /RA 1, 2, 3... 32 /RB 1, 2, 3... 32 PFD SYNC GENERATION CHARGE PUMP /S SYNC_OUT SYNC_OUT OUT7 /RC 1, 2, 3... 127 /M 1, 2, 3, 4, 5, 6 OUT7 OUT6 OUT6 OUT5 OUT5 SDIO OUT4 SDO CS OUT3 OUT3 /N RESET OUT2 /B 1, 2, 3... 32 PD STATUS OUT4 CONTROL INTERFACE (SPI) STATUS MONITOR OUT2 OUT1 /P 1, 2, 3, 4, 5, 6 OUT1 OUT0 OUT0 10011-018 SCLK REF_MON Figure 18. Detailed Block Diagram Rev. A | Page 19 of 48 AD9525 Data Sheet THEORY OF OPERATION The AD9525 PLL is useful for generating clock frequencies from a supplied reference frequency. In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9525 PLL allow the part to be tailored to function in many different applications and signal environments. The AD9525 includes on-chip PLL blocks that can be used with an external VCO or VCXO to create a complete phase-locked loop. The PLL requires an external loop filter, which usually consists of a small number of capacitors and resistors. The configuration and components of the loop filter help to establish the loop bandwidth and stability of the PLL. The external loop filter that must be connected between CP and the tuning pin of the VCO/VCXO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. The AD9525 can also be configured as a clock distribution by shutting down the PLL and using CLKIN and CLKIN as the input. The M divider can be used to divide the input frequency down to the desired output frequency to each of the eight LVPECL outputs. CONFIGURATION OF THE PLL Configuration of the PLL is accomplished by programming the various settings for the R divider, N divider, PFD polarity, and charge pump current. The combination of these settings and the loop filter determines the PLL loop bandwidth and PLL stability. These are managed through programmable register settings and by the design of the external loop filter. Successful PLL operation and satisfactory PLL loop performance are highly dependent on proper configuration of the PLL settings, and the design of the external loop filter is crucial to the proper operation of the PLL. ADIsimCLKTM is a free program that can help with the design and exploration of the capabilities and features of the AD9525, including the design of the PLL loop filter. The AD9516 model found in ADIsimCLK Version 1.2 can also be used for modeling the AD9525 loop filter. It is available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R divider and the N divider and produces an output proportional to the phase and frequency difference between them. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. The antibacklash pulse width is set by Register 0x010[1:0]. An important limit to keep in mind is the maximum frequency allowed into the PFD. The maximum input frequency into the PFD is a function of the antibacklash pulse setting, as specified in the phase/frequency detector (PFD) parameter in Table 7. Charge Pump (CP) The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter). The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the external VCO to move the VCO frequency up or down. The CP can be set for high impedance (allows holdover operation), for normal operation (attempts to lock the PLL loop), for pump-up, or for pump-down (test modes). The CP current is programmable in eight steps. The exact value of the CP current LSB is set by the CPRSET resistor, which is nominally 5.1 k. The actual LSB current can be calculated by CP_LSB = 3.06/CPRSET. PLL External Loop Filter An example of an external loop filter for the PLL is shown in Figure 19. A loop filter must be calculated for each desired PLL configuration. The values of the components depend on the VCO frequency, the KVCO, the PFD frequency, the charge pump current, the desired loop bandwidth, and the desired phase margin. The loop filter affects the phase noise, the loop settling time, and the loop stability. A basic knowledge of PLL theory is necessary for understanding loop filter design. ADIsimCLK can help with the calculation of a loop filter according to the application requirements. PLL Reference Inputs The AD9525 features two fully differential PLL reference input circuits. The differential inputs are self-biased, allowing for easy ac coupling of input signals. All PLL reference inputs are off by default. The self-bias level of the two sides is offset slightly to prevent chattering of the input buffer when the reference is ac coupled and is slow or missing. The input offset increases the voltage swing required of the driver to overcome the offset. The input frequency range and common-mode voltages for the reference inputs are specified in Table 4. The reference input receiver is powered down when the PLL is powered down. It is possible to dc couple to these inputs. If the differential reference input is driven by a single-ended signal, the unused side (REFA or REFB) should be decoupled via a suitable capacitor to a quiet ground. The AD9525 provides a third single-ended CMOS reference input referred to as REFC. Rev. A | Page 20 of 48 Data Sheet AD9525 Reference Switchover M Divider The AD9525 supports two separate differential reference inputs. Manual switchover is performed between these inputs either through Register 0x01A or by using the REF_SEL pin. This feature supports networking and other applications that require redundant references. The M divider is a fixed divide (FD) of 1, 2, 3, 4, 5, or 6. Manual switchover requires that a clock be present on the reference input that is being switched to or that the switchover deglitching feature be disabled (Register 0x01A[4]). Reference Dividers R The reference inputs are routed to their respective divider, R. R can be set to any value from 1 to 32 (Both R = 0 and R = 1 give divideby-1.). The maximum input frequency to the M counter is reflected in the maximum CLKIN input frequency specified in Table 6. The M divider provides frequency division between the CLKIN input and the N feedback divider and clock distribution output channels. The M divider can also be set to static, which is useful for applications where the only desired output frequency is the CLK input frequency. P Divider The P divider is a fixed divide (FD) of 1, 2, 3, 4, 5 or 6. The division is set by the values of RLOW and RHIGH. The divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. The maximum input frequency to the P counter is reflected in the maximum CLKIN input frequency specified in Table 6. For each R divider, the frequency division (RX) is set by the values of RLOW and RHIGH (four bits each, representing Decimal 0 to Decimal 15), where The B divider is a fixed divide (FD) of 1, 2, 3, ...or 32. Number of Low Cycles = RLOW + 1 Number of High Cycles = RHIGH + 1 The high and low cycles are cycles of the clock signal currently routed to the input of the R. When a divider is bypassed, RX = 1. Otherwise, RX = (RHIGH + 1) + (RLOW + 1) = RHIGH + RLOW + 2. This allows each reference divider to divide by any integer from 1 to 32. The output of the R divider goes to a mux to select one of the references to the PFD inputs. The frequency applied to the PFD must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see Table 7). B Divider The maximum input frequency to the B counter is ~1500 MHz, as specified in Table 7. This is the prescaler input frequency (external VCO or CLKIN) divided by the P and M counters. For example, M = 1 and P = 1 mode is not allowed if the external VCO frequency is greater than 1500 MHz because the frequency going to the B divider is too high. The division is set by the values of BLOW and BHIGH. The divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. The frequency division, BX, is set by the values of BLOW and BHIGH (four bits each, representing Decimal 0 to Decimal 15), where Number of Low Cycles = BLOW + 1 Number of High Cycles = BHIGH + 1 The R divider has its own reset. The R divider can also be reset using the shared reset bit of the R and B counters. This reset bit is not self-clearing. The high and low cycles are cycles of the clock signal currently routed to the input of the B divider. The R divider in the REFC path has a division ratio programmable from 1 to 127. Otherwise, BX = (BHIGH + 1) + (BLOW + 1) = BHIGH + BLOW + 2. VCO/VCXO, M and N Feedback Dividers When a divider is bypassed, BX = 1. Although manual reset is not normally required, the B counter has its own reset bit. Note that this reset bit is not self-clearing. The feedback division is the product of the M divider and the N divider. The N divider is a combination of a prescaler (P) and a B divider. fVCO = (fREF/R) x N x M where: M =1, 2, 3, 4, 5, or 6. N = (P x B). P =1, 2, 3, 4, 5, or 6. B = 1, 2, 3, ... or 32. Rev. A | Page 21 of 48 AD9525 Data Sheet Digital Lock Detect (DLD) VCO CLKIN 50 CLKIN R2 CP R1 C3 C1 C2 AD9525 1VCO MANUFACTURERS RECOMMEND EITHER A T OR PI ATTENUATOR TO PREVENT VCO PULLING. REFER TO MANUFACTURER'S RECOMMENDATION A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference that is less than the lock detect threshold. The lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. For the lock detect to work properly, the period of the PFD frequency must be greater than the unlock threshold. The number of consecutive PFD cycles required for a lock is programmable (Register 0x018[6:5]). Note that, in certain low (<500 Hz) loop bandwidth, high phase margin cases, it is possible that the DLD can chatter during acquisition. This is normal and occurs because the PFD inputs are moving slowly in and out of the lock/unlock window during PLL loop settling. Adjustment of the lock detect counter setting (Register 0x019[3:2]) can suppress this behavior. Figure 19. CLKIN Configured as Single-Ended VCO CMOS VCXO 100k CLKIN VTUNE 100k CLKIN R2 CP R1 C3 C2 C1 AD9525 Figure 20. CLKIN Configured as Single-Ended CMOS VCXO PECL VCXO1 CLKIN External VCXO/VCO Clock Input (CLKIN/CLKIN) VTUNE This differential input is used to drive the AD9525 clock distribution section. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. For operation using a CMOS input, an external resistive divider is required to limit the swing on CLKIN (see Table 6 for the maximum input rating). Status Monitor The AD9525 contains three frequency status monitors that are used to indicate if the PLL reference (or references, in the case of single-ended mode) and the VCO have fallen below a threshold. Rev. A | Page 22 of 48 R2 CP R1 C3 C2 C1 AD9525 1PROVIDE THE PROPER VCXO MANUFACTURER PECL TERMINATION. Figure 21. CLKIN Configured as Differential LVPECL VCXO 10011-022 The CLKIN/CLKIN input can be used either as a distribution only input (with the PLL off) or as a feedback input for an external VCO/VCXO using the internal PLL. Sample configurations are illustrated in Figure 19 through Figure 21. Refer to the manufacturer's recommendation for VCO terminations; a T or PI attenuator is often recommended, as illustrated in Figure 19. CLKIN 10011-020 The lock detect window timing depends on the value of the CPRSET resistor, as well as three settings: the digital lock detect window bit (Register 0x019[1]), the antibacklash pulse width bits (Register 0x010[1:0], see Table 8), and the lock detect counter bits (Register 0x019[3:2]). The lock and unlock detection values in Table 8 are for the nominal value of CPRSET = 5.11 k. Doubling the CPRSET value to 10 k doubles the values in Table 8. ATTENUATOR1 VTUNE 10011-021 By selecting the proper output through the mux on each pin, the DLD function is available at the STATUS and REF_MON pins. The digital lock detect circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). Note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. Data Sheet AD9525 ways to activate safe power-down mode: individually set the power-down bit for each driver, power down an individual output channel, or activate sleep mode. CLOCK DISTRIBUTION The AD9525 can be used only as a clock fan out buffer by disabling the PLL circuit blocks except for the clock distribution section. The clock distribution consists of eight LVPECL clock output drivers that share a common M divider. See the M Divider section for more information on the common M divider. In total power-down mode 0x0230[1] = 1 (power down distribution reference). This mode must not be used if there is an external voltage bias network (such as Thevenin equivalent termination) on the output pins that will cause a dc voltage to appear at the powered down outputs. However, total power-down mode is allowed when the LVPECL drivers are terminated using only pull-down resistors. Duty Cycle and Duty-Cycle Correction The duty cycle of the clock signal at the output of a driver is a result of either or both of the following conditions: SW1B SW1A R2 200 R1 200 N1 OUT Table 23.Typical Output Duty Cycle with M Divider 1 M Divider Even Odd = 3 Odd = 5 QN1 N2 Output Duty Cycle (%) 50 33.3 40 QN2 OUT SW2 10011-023 * The CLKIN, CLKIN input duty cycle. If the CLKIN, CLKIN input is routed directly to the output, the duty cycle of the output is the same as the CLKIN, CLKIN input. The M divider value. An odd M divider value results in a non-50% duty cycle. 4.4mA LVPECL Output Drivers The LVPECL differential voltage (VOD) is selectable (from ~400 mV to 960 mV (see Bit 2 and Bit 1 in Register 0x0F0 to Register 0x0F7). Figure 22. LVPECL Output Simplified Equivalent Circuit SYNC_OUT SYNC_OUT provides one LVPECL output or two CMOS output signal that can used to reset or synchronize a converter. SYNC_OUT functionality block diagram is shown in Figure 23. The SYNC_OUT signal is derived from the PLL phase detector reference input clock or feedback (N-divider) clock. A programmable 16-bit S divider further divides the selected reference clock. There are three different modes of operation for SYNC_OUT: single shot, periodic, or pseudorandom. SYNC_OUT is retimed to the high speed clock. The LVPECL output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. Each LVPECL output can be powered down or powered up, as needed. Because of the architecture of the LVPECL output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions. For this reason, the LVPECL outputs have two power-down modes: total power-down and safe power-down. The primary powerdown mode is the safe power-down mode. This mode continues to protect the output devices while powered down. There are three OUT0 TO OUT7 UP REF PFD DN /M CP LOW /N 11 10 00 01 SELECT REF: REF, FB, PD DIGITAL LOCK DETECT SYNC ENABLE SYNC_OUT /S DIGITAL SYNC CONTROL D SET Q CLR Q M DIVIDER OUTPUT Figure 23. SYNC_OUT Functional Diagram Rev. A | Page 23 of 48 10011-024 * AD9525 Data Sheet Single Shot Mode Pseudorandom Mode In single shot mode one sync pulse occurs after writing SYNC ENABLE 0x192[4] = 1. An IO_UPDATE is required to complete a register write. The width of the sync pulse is determined by the value of the S divider. A divider value of 0x0000 allows a pulse whose width is equal to one half period of the phase detector rate. A divider value of 0x0001 allows a pulse whose width is equal to two half periods of the phase detector rate. In single shot mode, the sync enable bit is self-clearing and the sync circuits are ready to receive another sync enable. Pseudorandom mode is similar to periodic mode but the pulse is a PN17 sequence that is continuous until SYNC ENABLE is cleared by a register writing SYNC ENABLE 0x192[4] = 0. An IO_UPDATE is required to complete a register write. The width of the sync pulse is equal to one half period the phase detector rate. The pulse repetition rate is determined by the value of the S divider. A divider value of 0x0000 allows a pulse rate equal to the phase detector rate. A divider value of 0x0001 allows pulse rate equal to two half the phase detector rate. Periodic Mode SYNC_OUT Programming In periodic mode, the pulse is continuous until SYNC ENABLE is cleared by a register writing SYNC ENABLE 0x192[4] = 0. An IO_UPDATE is required to complete a register write. The width of the sync pulse is equal to one half period of the phase detector rate. The pulse repetition rate is determined by the value of the S divider. A divider value of 0x0000 allows a pulse rate equal to the phase detector rate. A divider value of 0x0001 allows a pulse rate equal to two half periods of the phase detector rate. The SYNC_OUT signal is resampled with the OUT clock to ensure time alignment and minimum output skew. There is a possibility in periodic mode that the SYNC_OUT could slip one half cycle of the OUT clock period. The procedure to configure the SYNC_OUT depends on the logic requirement of the converters that require synchronization. Analog Devices, Inc., converters are synchronized on the rise edge of the SYNC pulse. SYNC_OUT CMOS Driver The user can also configure the LVPECL SYNC_OUT as a pair of CMOS outputs. When the output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. Either CMOS Output A or Output B can be turned on or off independently. The user can also select the relative polarity of the CMOS outputs for any combination of inverting and noninverting (see Register 0x0F9). The user can power down each CMOS output as needed to save power. The CMOS driver is in tristate when it is powered down. S DIVIDER = 0 tSTART REF CLOCK SYNC ENABLE = HIGH (SINGLE SHOT SELF CLEARING) IO_UPDATE SYNC_OUT MODE = SINGLE SHOT SYNC_OUT MODE = PERIODIC SYNC ENABLE = LOW (SINGLE SHOT SELF CLEARING) IO_UPDATE tSTOP Figure 24. SYNC Output Timing Rev. A | Page 24 of 48 10011-025 SYNC_OUT MODE = PN17 Data Sheet AD9525 SYNC_OUT CONTROL PROGRAM: S DIVIDER, SYNC MODE USER PROGRAMS REGISTER VALUE FOR S DIVIDER AND SYNC MODE PROGRAM: SYNC ENABLE REQUEST SYNC PROGRAM: IO UPDATE NO LOCK DETECT = HIGH YES DIGITAL LOCK DETECT IS USED TO PREVENT OCCURENCE OF SYNC IF PLL IS UNLOCKED THE ANALOG CLOCK TO THE DIGITAL STATE MACHINE IS DISABLED IF SYNC IS DISABLED ENABLE_ANALOG SYNC HIGH FOR S DIVIDER + 1 REF CLOCK CYCLES SYNC LOW SYNC ENABLE LOW? NO SYNC ENABLE IS SELF CLEARING IN SINGLE SHOT MODE. OTHER MODES REQUIRE A SPI WRITE TO DISABLE SYNC_OUT YES 10011-026 END SYNC PROCESS Figure 25. SYNC_OUT Flowchart RESET MODES Hardware Reset via the RESET Pin The AD9525 has a power-on reset (POR) and several other ways to apply a reset condition to the chip. RESET, a hard reset (an asynchronous hard reset is executed by briefly pulling RESET low), restores the chip to the on-chip default register settings. It takes ~2 s for the outputs to begin toggling after RESET is issued. Power-On Reset During chip power-up, a power-on reset pulse is issued when VDD reaches ~2.6 V (<2.8 V) and restores the chip to the default on-chip setting. It takes ~70 ms for the outputs to begin toggling after the power-on reset pulse signal is internally generated. The default power-on state of the AD9525 is configured as a buffer. Soft Reset via the Serial Port The serial port control register allows for a soft reset by setting Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set, the chip enters a soft reset mode and restores the chip to the onchip setting, except for Register 0x000. Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000 retains its previous value prior to reset. These bits are self-clearing. However, the self-clearing operation does not complete until an additional serial port SCLK cycle occurs, and the AD9525 is held in reset until that happens. Rev. A | Page 25 of 48 AD9525 Data Sheet POWER-DOWN MODES PLL Power-Down Chip Power-Down via PD The PLL section of the AD9525 can be selectively powered down. In this mode, the AD9525 can be used as a 1 to 8 clock buffer by using the CLKIN as the clock input. The AD9525 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9525. The chip remains in this power-down state until PD is brought back to logic high. When taken out of power-down mode, the AD9525 returns to the settings that were programmed into its registers prior to the power-down, unless the registers are changed by new programming while the PD pin is held low. Powering down the chip shuts down the currents on the chip, except for the bias current necessary to maintain the LVPECL outputs in a safe shutdown mode. The LVPECL bias currents are needed to protect the LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. When the AD9525 is in a PD power-down, the chip is in the following state: * * * * * * The PLL is off. The CLKIN input buffer is off, but the CLKIN input dc bias circuit is on. The reference input buffer is off, but the dc bias circuit is still on. All dividers are off. All LVPECL outputs are in safe off mode. The serial control port is active, and the chip responds to commands. Distribution Power-Down The distribution section can be powered down by writing Register 0x230[4] = 1b, which turns off the bias to the distribution section. Individual Clock Output Power-Down Any of the clock distribution outputs can be powered down into safe power-down mode by individually writing to the appropriate registers. The register map details the individual power-down settings for each output. These settings are found in Register 0x0F0[0] to Register 0x0F7[0]. Individual Clock Channel Power-Down Any of the clock distribution channels can be powered down individually by writing to the appropriate registers. Powering down a clock channel is similar to powering down an individual driver, but it saves more power because additional circuits are also powered down. Powering down a clock channel also automatically powers down the drivers connected to it. The register map details the individual power-down settings for each output channel. These settings are found in Register 0x0F0[4], Register 0x0F2[4], Register 0x0F4[4], and Register 0x0F6[4]. Rev. A | Page 26 of 48 Data Sheet AD9525 SERIAL CONTROL PORT The AD9525 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9525 serial control port is compatible with most synchronous transfer formats, including Motorola(R) SPI and Intel(R) SSR protocols. The serial control port allows read/write access to all registers that configure the AD9525. During this period, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset, either by completing the remaining transfers or by returning CS low for at least one complete SCLK cycle (but fewer than eight SCLK cycles). Raising the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. PIN DESCRIPTIONS In the streaming mode (see Table 25), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the MSB/LSB First Transfers section). CS must be raised at the end of the last byte to be transferred, thereby ending streaming mode. SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 k resistor to ground. SDIO (serial data input/output) is a dual-purpose pin that acts either as an input only (unidirectional mode) or as an input/ output (bidirectional mode). The AD9525 defaults to the bidirectional I/O mode (Register 0x000[7] = 0b). SDO (serial data out) is used only in the unidirectional I/O mode (Register 0x000[7] = 1b) as a separate output pin for reading back data. SDIO AD9525 SDO SERIAL PORT CONTROL (SPI) SCLK CS 10011-027 CS (chip select bar) is an active low control that gates the read and write cycles. When CS is high, SDO and SDIO are in a high impedance state. This pin is internally pulled up by a 30 k resistor to VS. Figure 26. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT Single byte or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9525 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/SDO). By default, the AD9525 is in bidirectional mode. Short instruction mode (8-bit instruction) is not supported. Only long instruction mode (16-bit instruction) is supported. A write or a read operation to the AD9525 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred (see Table 24). In this mode, the CS pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. CS can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. Communication Cycle--Instruction Plus Data There are two parts to a communication cycle with the AD9525. The first part writes a 16-bit instruction word into the AD9525, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9525 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. Write If the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the AD9525. Data bits are registered on the rising edge of SCLK. The length of the transfer (one, two, or three bytes or streaming mode) is indicated by two bits ([W1:W0]) in the instruction byte. When the transfer is one, two, or three bytes but not streaming, CS can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CS is lowered. Raising the CS pin on a nonbyte boundary resets the serial control port. During a write, streaming mode does not skip over reserved or blank registers, and the user can write 0x00 to the reserved register addresses. Because data is written into a serial control port buffer area, not directly into the actual control registers of the AD9525, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9525, thereby causing them to become active. The update registers operation (IO_UPDATE) consists of setting Register 0x232[0] = 1b (this bit is self-clearing). Any number of bytes of data can be changed before executing an update registers. The update registers operation simultaneously actuates all register changes that have been written to the buffer since any previous update. Rev. A | Page 27 of 48 AD9525 Data Sheet Read The AD9525 supports only the long instruction mode. If the instruction word is for a read operation, the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by [W1:W0]. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. The default mode of the AD9525 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9525 to unidirectional mode (Register 0x000[7] = 1 and Register 0x000[0] = 1). In unidirectional mode, the readback data appears on the SDO pin. A readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see Figure 27). Readback of the buffer or active registers is controlled by Register 0x004[0]. SDO SERIAL CONTROL PORT UPDATE REGISTERS WRITE REGISTER 0x232 = 0x001 TO UPDATE REGISTERS 10011-028 SDIO/SDA ACTIVE REGISTERS CS SCLK/SCL BUFFER REGISTERS The AD9525 uses Register Address 0x000 to Register Address 0x232. Figure 27. Relationship Between Serial Control Port Buffer Registers and Active Registers THE INSTRUCTION WORD (16 BITS) The MSB of the instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits ([W1:W0]) indicate the length of the transfer in bytes. The final 13 bits are the address ([A12:A0]) at which to begin the read or write operation. For a write, the instruction word is followed by the number of bytes of data indicated by Bits[W1:W0] (see Table 24). Table 24. Byte Transfer Count W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 Streaming mode the range of the 0x232 registers used by the AD9525. Bits[A12:A10] must always be 0b. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address. MSB/LSB FIRST TRANSFERS The AD9525 instruction word and byte data can be MSB first or LSB first. Any data written to Register 0x000 must be mirrored; the upper four bits (Bits[7:4]) must mirror the lower four bits (Bits[3:0]). This makes it irrelevant whether LSB first or MSB first is in effect. As an example of this mirroring, see the default setting for Register 0x000, which mirrors Bit 4 and Bit 3. This sets the long instruction mode, which is the default and the only mode that is supported. The default for the AD9525 is MSB first. When LSB first is set by Register 0x000[1] and Register 0x000[6], it takes effect immediately because it affects only the operation of the serial control port and does not require that an update be executed. When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow, in order, from the high address to the low address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. When LSB first is active, the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte, followed by multiple data bytes. In a multibyte transfer cycle, the internal byte address generator of the serial port increments for each byte. The AD9525 serial control port register address decrements from the register address just written toward Register 0x000 for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the register address of the serial control port increments from the address just written toward Register 0x232 for multibyte I/O operations. Streaming mode always terminates when it reaches Register 0x232. Note that unused addresses are not skipped during multibyte I/O operations. Table 25. Streaming Mode (No Addresses Are Skipped) Write Mode LSB first MSB first Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. Only Bits[A9:A0] are needed to cover Rev. A | Page 28 of 48 Address Direction Increment Decrement Stop Sequence 0x230, 0x231, 0x232, stop 0x001, 0x000, 0x232, stop Data Sheet AD9525 Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 R/W I14 W1 I13 W0 I12 A12 = 0 I11 A11 = 0 I10 A10 = 0 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 A0 CS SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE 10011-029 SDIO DON'T CARE REGISTER (N - 1) DATA Figure 28. Serial Control Port Write--MSB First, 16-Bit Instruction, Two Bytes of Data CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE REGISTER (N) DATA REGISTER (N - 1) DATA REGISTER (N - 2) DATA REGISTER (N - 3) DATA DON'T CARE 10011-030 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 16-BIT INSTRUCTION HEADER Figure 29. Serial Control Port Read--MSB First, 16-Bit Instruction, Four Bytes of Data tHIGH tDS tS CS DON'T CARE SDIO DON'T CARE tLOW DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 10011-031 SCLK tC tCLK tDH Figure 30. Serial Control Port Write--MSB First, 16-Bit Instruction, Timing Measurements CS SCLK DATA BIT N 10011-032 tDV SDIO SDO DATA BIT N - 1 Figure 31. Timing Diagram for Serial Control Port Register Read CS SCLK DON'T CARE DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 16-BIT INSTRUCTION HEADER D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D6 REGISTER (N + 1) DATA Figure 32. Serial Control Port Write--LSB First, 16-Bit Instruction, Two Bytes of Data Rev. A | Page 29 of 48 D3 D4 D5 D7 DON'T CARE 10011-033 SDIO DON'T CARE AD9525 Data Sheet tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 33. Serial Control Port Timing--Write Table 27. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) Setup time between SCLK rising edge and the CS rising edge (end of communication cycle) Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state SCLK to valid SDIO and SDO (see Figure 31) Rev. A | Page 30 of 48 10011-034 tDH Data Sheet AD9525 CONTROL REGISTERS CONTROL REGISTER MAP OVERVIEW When writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. Register addresses that are not listed in Table 28 are not used, and writing to those registers has no effect. Registers that are marked as reserved should never have their values changed. Table 28. Control Register Map Reg. Addr. Register (Hex) Name Serial Port Configuration 0x000 SPI mode serial port configuration 0x004 Readback control PLL Configuration 0x010 PFD charge pump 0x011 R dividers 0x012 0x013 B divider 0x014 N divider (MSB) Bit 7 SD0 active Don't care Don't care 0x015 Resets Don't care 0x016 REFC 0x017 Status pin 0x018 REF_MON pin control Lock detect REFC enable Charge pump pin to VDD_CP/2 Don't care Don't care 0x019 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first/ address increase Don't care Soft reset Don't care Don't care Soft reset SD0 active 0x00 Soft reset Don't care Don't care Don't care 0x00 Don't care Don't care Don't care Don't care Soft reset Don't care LSB first/ address increase Don't care Don't care Read back active regs 0x00 CP current, Bits[2:0] CP mode, Bits[1:0] REFB divider output high cycles, Bits[3:0] REFA divider output high cycles, Bits[3:0] B divider output high cycles, Bits[3:0] Don't care B divider bypass REFB divider bypass Reserved Reserved Reserved 0x00 Don't care Lock detect counter, Bits[1:0] Digital lock detect window Digital lock det disable 0x00 Select REFB (manual register mode) Use REF_SEL pin for reference switchover Enable automatic reference switchover 0x00 Reserved = 0 Reserved = 0 0x00 R Channel B PD R Channel A PD 0x22 Status REFA Digital lock detect (DLD) N/A Reserved Reserved = 0 Reserved = 0 0x01C PLL block PD register N divider PD R Divider B ECL 2 CMOS PD 0x01F PLL readback Reserved =0 N divider ECL 2 CMOS PD Unused Unused Unused Reserved = 0 R Divider A ECL 2 CMOS PD Selected reference Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care 0x00 Don't care 0x01B LVPECL OUT3 Reset all dividers Don't care Disable switchover deglitch 0x0F3 REFA divider reset REF_MON pin control, Bits[4:0] Enable REFB present monitor LVPECL OUT2 0x00 REFB divider reset Don't care Enable REFA present monitor 0x0F2 B divider reset 0x00 0x00 0x00 0x00 Don't care Enable FB clock present monitor LVPECL OUT1 0x7D STATUS output select, Bits[5:0] STATUS pin divider enable Ref switchover and monitors 0x0F1 Antibacklash pulse width, Bits[1:0] REFB divider output low cycles, Bits[3:0] REFA divider output low cycles, Bits[3:0] B divider output low cycles, Bits[3:0] P divider prescaler, Bits[2:0] REFA divider bypass REFC divider, Bits[6:0] 0x01A PECL/CMOS Outputs 0x0F0 LVPECL OUT0 Default Value (Hex) Bit 6 PFD polarity Don't care (LSB) Bit 0 Stay on REFB Reserved = 0 R Divider B PD Status FB clock R Divider A PD Status REFB 0x00 Power down Channel 0, Channel 1 Reserved Don't care OUT0 PECL output level, Bits[1:0] Power down PECL driver 0x04 Don't care Don't care Power down PECL driver Power down PECL driver 0x04 Power down Channel 2, Channel 3 Reserved OUT1 PECL output level, Bits[1:0] OUT2 PECL output level, Bits[1:0] OUT3 PECL output level, Bits[1:0] Power down PECL driver Don't care Rev. A | Page 31 of 48 0x04 0x04 AD9525 Data Sheet Reg. Addr. (Hex) 0x0F4 Register Name LVPECL OUT4 (MSB) Bit 7 Don't care 0x0F5 LVPECL OUT5 0x0F6 LVPECL OUT6 0x0F7 LVPECL OUT7 0x0F8 Sync output 0x0F9 Sync output, other control Bit 6 Don't care Bit 5 Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Drivers Don't reserved care SYNC Control 0x190 Sync clock S divider 0x191 Sync clock S divider 0x192 Sync clock Don't control care VCO, Reference and CLK1 Inputs 0x1E0 VCO divider Don't care Other 0x230 Power-down Don't care Don't care Don't care 0x232 0x0FA IO_UPDATE Don't care Default Value (Hex) 0x04 Bit 4 Power down Channel 4, Channel 5 Reserved Bit 3 Don't care Bit 2 Bit 1 OUT4 PECL output level, Bits[1:0] (LSB) Bit 0 Power down PECL driver Don't care Don't care Power down PECL driver Power down PECL driver 0x04 Power down Channel 6, Channel 7 Reserved OUT5 PECL output level, Bits[1:0] OUT6 PECL output level, Bits[1:0] Don't care Power down PECL driver Power down PECL driver 0x04 Power down sync channel Polarity CMOS mode Don't care OUT7 PECL output level, Bits[1:0] SYNC_OUT PECL output level, Bits[1:0] Sync out resampling edge select Don't care 0x00 Don't care Enable CMOS drivers, Bits[1:0] Don't care Don't care CMOS mode Don't care 0x04 0x10 0x00 Sync clock S divider, Bits[7:0] 0x00 Sync clock S divider, Bits[15:8] 0x00 Don't care Don't care Sync enable Sync source, Bits[1:0] Don't care Don't care Don't care Don't care Don't care Don't care Dist all powerdown CLKIN powerdown Don't care Don't care Don't care Don't care Rev. A | Page 32 of 48 Sync mode, Bits[1:0] M divider, Bits[2:0] M divider powerdown Don't care 0x00 0x00 Distribution reference power-down PLL powerdown 0x00 Don't care IO_UPDATE 0x00 Data Sheet AD9525 REGISTER MAP DESCRIPTIONS Table 29 through Table 49 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Table 29. SPI Mode Serial Port Configuration Reg. Addr. (Hex) 0x000 0x004 Bits 7 Bit Name SDO active 6 LSB first/address increase 5 Soft reset 4 [3:0] Unused Mirror[7:4] 0 Read back active registers Description Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO is high impedance (default). 1: SDO used for read; SDIO used for write; unidirectional mode. SPI MSB or LSB data orientation. 0: data-oriented MSB first; addressing decrements (default). 1: data-oriented LSB first; addressing increments. Soft reset. 1 (self-clearing): soft reset; restores default values to internal registers. Unused. Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows: Bit 0 = Bit 7 Bit 1 = Bit 6 Bit 2 = Bit 5 Bit 3 = Bit 4 Select register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers. Table 30. PFD Charge Pump Reg. Addr. (Hex) 0x010 Bits 7 Bit Name PFD polarity [6:4] CP current [3:2] CP mode [1:0] Antibacklash pulse width Description Sets the PFD polarity. 0: Positive (higher control voltage produces higher frequency) (default). 1: Negative (higher control voltage produces lower frequency). Charge pump current (with CPRSET = 5.1 k). Bit 6 Bit 5 Bit 4 ICP (mA) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) Charge pump operating mode. Bit 3 Bit 2 Charge Pump Mode 0 0 High impedance state 0 1 Force source current (pump-up) 1 0 Force sink current (pump-down) 1 1 Normal operation (default) See Table 7 for the maximum operating frequency for each setting. Bit 1 Bit 0 Antibacklash Pulse Width Mode (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 Rev. A | Page 33 of 48 AD9525 Data Sheet Table 31. REFA, REFB, REFC, B, N, and P Dividers Reg. Addr. (Hex) 0x011 0x012 0x013 0x014 0x015 Bits [7:4] Bit Name REFB divider output high cycles [3:0] REFB divider output low cycles [7:4] REFA divider output high cycles [3:0] REFA divider output low cycles [7:4] B divider output high cycles [3:0] B divider output low cycles [7:6] 5 Don't care B divider bypass 4 REFB divider bypass 3 REFA divider bypass [2:0] P divider prescaler 7 6 5 4 3 Don't care Reserved Reserved Reserved B divider reset Description Divider high cycle word. Normally set to one-half desired divider division minus one: for example, D/2 - 1; therefore, for Divide = 8, set to 0x03 (8/2 - 1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). Divider low cycle word. Normally set to one-half desired divider division minus one: for example, D/2 - 1; therefore, for Divide = 8, set to 0x03 (8/2 - 1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). Divider high cycle word. Normally set to one-half desired divider division minus one: for example, D/2 - 1; therefore, for Divide = 8, set to 0x03 (8/2 - 1). Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x0). Divider low cycle word. Normally set to one-half desired divider division minus one: for example, D/2 - 1; therefore, for Divide = 8, set to 0x03 (8/2 - 1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). Divider high cycle word. Normally set to one-half desired divider division minus one: for example, D/2 - 1; therefore, for Divide = 8, set to 0x03 (8/2 - 1). Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x0). Divider low cycle word. Normally set to one-half desired divider division minus one: for example, D/2 - 1; therefore, for Divide = 8, set to 0x03 (8/2 - 1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). Don't care. Bypasses and powers down the B divider; routes input to divider output. 0: uses divider (default). 1: B divider is set to divide-by-1. Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: REFB divider is set to divide-by-1. Bypasses and powers down the divider; routes input to divider output. 0: use divider (default). 1: REFA divider is set to divide-by-1. P divider value (B divider prescaler). Bit 2 Bit 1 Bit 0 Divider Value 0 0 0 1(default) 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 Static 1 1 1 Static Don't care. 0 (default). 0 (default). 0 (default). Resets B divider. 0: normal operation (default). 1: holds B divider in reset. Rev. A | Page 34 of 48 Data Sheet Reg. Addr. (Hex) 0x016 Bits 2 Bit Name REFB divider reset 1 REFA divider reset 0 Reset all dividers 7 REFC enable [6:0] REFC divider AD9525 Description Resets REFB divider. 0: normal (default). 1: holds REFB divider in reset. Resets REFA divider. 0: normal (default). 1: holds REFA divider in reset. Resets REFA, REFB, B divider (B divider is part of N divider). 0: normal (default). 1: holds REFA, REFB, B divider in reset. Enables REFC path. 0: disabled (default). 1: enables REFC path. 7-bit REFC divider. Divide-by-1 to divide-by-127. 0000000, 0000001: both divide-by-1 (default: 0x00). Table 32. Status Pin and Other Reg. Addr. (Hex) 0x017 Bits 7 Bit Name Charge pump pin to VDD_CP/2 6 STATUS pin divider enable [5:0] STATUS output select Description Sets the charge pump pin to one-half of the VDD_CP supply voltage. 0: charge pump normal operation (default). 1: charge pump pin set to VDD_CP/2. Enables STATUS pin divider. 0: disabled (default). 1: enables divider. Selects the signal that appears at the STATUS pin. Register 0x017[6] must be set to 0 to for any mode identified as LVL. Level or Dynamic Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 0 1 DYN N divider output. 0 0 0 0 1 0 LVL Ground, dc. 0 0 0 0 1 1 LVL Ground, dc. 0 0 0 1 0 0 LVL Ground, dc. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for the REF_MON pin. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REFA clock. 1 0 0 0 1 0 DYN REFB clock. 1 0 0 0 1 1 DYN Selected reference clock to PLL. 1 0 0 1 0 0 DYN Unselected reference clock to PLL. 1 0 0 1 0 1 LVL Both REFA and REFB clocks missing (active high). 1 0 0 1 1 0 LVL Ground, dc. 1 0 0 1 1 1 LVL REFA present (active high). 1 0 1 0 0 0 LVL REFB present (active high). 1 0 1 0 0 1 LVL (REFA present) AND (REFB present). Rev. A | Page 35 of 48 AD9525 Reg. Addr. (Hex) Bits Data Sheet Bit Name Description Bit 5 1 Bit 4 0 Bit 3 1 Bit 2 0 Bit 1 1 Bit 0 0 Level or Dynamic Signal LVL 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 LVL LVL LVL LVL LVL LVL DYN DYN DYN DYN LVL 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 LVL LVL LVL LVL LVL 1 1 1 1 1 1 0 1 1 0 1 0 LVL LVL 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 LVL LVL LVL Rev. A | Page 36 of 48 Signal at STATUS Pin (DLD) AND (selected reference present) AND (feedback clock present). Feedback clock present (active high). Selected reference (low: REFA, high: REFB). DLD; active high. N/A. Ground (dc). VDD3 (PLL power supply). REFA clock. REFB clock. Selected reference to PLL. Unselected reference to PLL. Status of selected reference (status of differential reference); active low. Both reference clocks missing; active low. REFA present (active low). REFB present (active low). (REFA present) AND (REFB present). (DLD) AND (selected reference present) AND (feedback clock present); (active low). Feedback clock present Selected reference (low = REFA, high = REFB); active low. DLD (active low). N/A. VDD3 (PLL power supply). Data Sheet AD9525 Table 33. REF_MON Pin Control Reg. Addr. (Hex) 0x018 Bits [7:5] [4:0] Bit Name Don't care REF_MON pin control Description Don't care. Selects the signal that is connected to the REF_MON pin. Level or Dynamic Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Signal Signal at REF_MON Pin 0 0 0 0 0 LVL Ground (dc). 0 0 0 0 1 DYN REFA clock. 0 0 0 1 0 DYN REFB clock. 0 0 0 1 1 DYN Selected reference clock to PLL. 0 0 1 0 0 DYN Unselected reference clock to PLL. 0 0 1 0 1 LVL Both reference clocks missing (active high). 0 0 1 1 0 LVL Ground (dc). 0 0 1 1 1 LVL Status REF A frequency (active high). 0 1 0 0 0 LVL Status REF B frequency (active high). 0 1 0 0 1 LVL (Status REF A frequency) AND (status REF B frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of feedback clock). 0 1 0 1 1 LVL Status of feedback clock (active high). 0 1 1 0 0 LVL Selected reference (low: REFA, high: REFB). 0 1 1 0 1 LVL DLD; active high. 0 1 1 1 0 LVL N/A. 0 1 1 1 1 LVL Ground, dc. 1 0 0 0 0 LVL VDD3 (PLL power supply). 1 0 0 0 1 DYN REFA. 1 0 0 1 0 DYN REFB. 1 0 0 1 1 DYN Selected reference to PLL. 1 0 1 0 0 DYN Unselected reference to PLL. 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF A frequency (active low). 1 1 0 0 0 LVL Status of REF B frequency (active low). 1 1 0 0 1 LVL (Status of REFA frequency) AND (status of REFB frequency). 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of feedback clock). 1 1 0 1 1 LVL Status of feedback clock (active low). 1 1 1 0 0 LVL Selected reference (low: REFA, high: REFB); active low. 1 1 1 0 1 LVL DLD (active low). 1 1 1 1 0 LVL N/A. 1 1 1 1 1 LVL VDD3 (PLL power supply). Rev. A | Page 37 of 48 AD9525 Data Sheet Table 34. Lock Detect Reg. Addr. (Hex) 0x019 Bits [7:4] [3:2] Bit Name Don't care Lock detect counter 1 Digital lock detect window 0 Digital lock detect disable Description Don't care. Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition. Bit 3 Bit 2 PFD Cycles to Determine Lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the lossof-lock threshold. 0: high range (default). 1: low range. Digital lock detect operation. 0: normal lock detect operation (default). 1: disables lock detect. Table 35. Reference Switchover and Monitors Reg. Addr. (Hex) 0x01A Bits 7 Bit Name Enable feedback clock present monitor 6 Enable REFA present monitor 5 Enable REFB present monitor 4 Disable switchover deglitch 3 Select REFB (manual register mode) 2 Stay on REFB 1 Use REF_SEL pin for reference switchover 0 Enable automatic ref switchover Description Enables feedback clock monitor. The presence of a feedback clock is checked with the selected reference to the PLL. This monitor does not have a valid output if there is no reference to the PLL. 0: disables monitor (default). 1: enables monitor. Enables Reference A clock monitor. The presence of the REFA clock is checked with the feedback clock to the PLL. This monitor does not have a valid output if there is no feedback clock to the PLL. Register 0x01C[4] = 0 (on) for monitor to work. 0: disables monitor (default). 1: enables monitor. Enables Reference B clock monitor. The presence of the REFB clock is checked with the feedback clock to the PLL. This monitor does not have a valid output if there is no feedback clock to the PLL. Register 0x01C[5] = 0 (on) for monitor to work. 0: disables monitor (default). 1: enables monitor. Disables or enables the switchover deglitch circuit. 0: enables switchover deglitch circuit (default). 1: disables switchover deglitch circuit. If Register 0x01A[1] = 0, selects reference for PLL. 0: selects REFA. 1: selects REFB. Stays on REFB after switchover. 0: returns to REFA automatically when REFA status is good again. 1: stays on REFB after switchover. Do not automatically return to REFA. If Register 0x01A[0] = 0 (manual), sets method of PLL reference selection. 0: uses Register 0x01A[3] (default). 1: uses REF_SEL pin. Automatic or manual reference switchover. 0: manual reference switchover. 1: automatic reference switchover. Rev. A | Page 38 of 48 Data Sheet AD9525 Table 36. Reserved Reg. Addr. (Hex) 0x01B Bits [7:0] Bit Name Reserved Description Reserved. 0: default. All bits should be set to 0. Table 37. PLL Block Power-Down Reg. Addr. (Hex) 0x01C Bits 7 Name N divider ECL 2 CMOS power-down 6 N divider power-down 5 REFB Divider ECL 2 CMOS power-down 4 REFA Divider ECL 2 CMOS power-down 3 REFB divider power-down 2 REFA divider power-down 1 REFB channel power-down 0 REFA channel power-down Description Turns off the N divider's output clock. This stops the clock to the PFD and the frequency monitors. 0: clock on (default). 1: clock off. N divider power-down. 0: N divider on (default). 1: N divider off. This bit stops the clock to the frequency monitors for REFB. If this bit is disabled, the automatic reference switchover does not operate. In some configurations, enabling the REFB divider ECL 2 CMOS may increase reference spurs on clock outputs. 0: on. 1: off (default). This bit stops the clock to the frequency monitors for REFA. If this bit is disabled, the automatic reference switchover does not operate. In some configurations, enabling the REFA Divider ECL 2 CMOS may increase reference spurs on clock outputs. 0: on (default). 1: off. Powers down REFB divider. The REFB input receiver is still powered up. 0: REFB divider on (default). 1: REFB divider off. Powers down REFA divider. The REFA input receiver is still powered up. 0: REFA divider on (default). 1: REFA divider off. Powers down REFB channel. The REFB input receiver is powered down. 0: REFB channel on. 1: REFB channel off (default). Powers down REFA channel. The REFA input receiver is powered down. 0: REFA channel on (default). 1: REFA channel off. Rev. A | Page 39 of 48 AD9525 Data Sheet Table 38. PLL Readback Reg. Addr. (Hex) 0x01F Bits [7:5] 4 Bit Name Unused Selected reference 3 Status feedback clock 2 Status REFB 1 Status REFA 0 Digital lock detect (DLD) Description Unused Shows the reference used by the PLL 0: REFA 1: REFB Status of the feedback clock, does not have a valid output unless 0x01A[7] = 1 0: missing 1: present Status of Reference B clock, does not have a valid output unless 0x01A[5] = 1 and 0x01C[5] = 0 0: missing 1: present Status of Reference A clock, does not have a valid output unless 0x01A[6] = 1 and 0x01C[4] = 0 0: missing 1: present Digital lock detect 0: PLL not locked 1: PLL locked Table 39. LVPECL Drivers OUT0 Reg. Addr. (Hex) 0x0F0 Bits [7:5] 4 Bit Name Don't care Power down Channel 0 and Channel 1 3 [2:1] Don't care OUT0 level 0 OUT0 driver power-down Description Don't care Powers down Channel 0 and Channel 1 0: enabled (default) 1: power-down Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 40. LVPECL Drivers OUT1 Reg. Addr. (Hex) 0x0F1 Bits [7:5] 4 3 [2:1] Bit Name Don't care Reserved Don't care OUT1 level 0 OUT1 driver power-down Description Don't care Reserved, write 0 Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Rev. A | Page 40 of 48 Data Sheet AD9525 Table 41. LVPECL Drivers OUT2 Reg. Addr. (Hex) 0x0F2 Bits [7:5] 4 Bit Name Don't care Power down Channel 2 and Channel 3 3 [2:1] Don't care OUT2 level 0 OUT2 driver power-down Description Don't care Powers down Channel 2 and Channel 3 0: enabled (default) 1: power-down Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 42. LVPECL Drivers OUT3 Reg. Addr. (Hex) 0x0F3 Bits [7:5] 4 3 [2:1] Bit Name Don't care Reserved Don't care OUT3 level 0 OUT3 driver power-down Description Don't care Reserved, write 0 Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 43. PECL Drivers OUT4 Reg. Addr. (Hex) 0x0F4 Bits [7:5] 4 Bit Name Don't care Power down Channel 4 and Channel 5 3 [2:1] Don't care OUT4 level 0 OUT4 driver power-down Description Don't care Powers down Channel 4 and Channel 5 0: enabled (default) 1: power-down Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Rev. A | Page 41 of 48 AD9525 Data Sheet Table 44. LVPECL Drivers OUT5 Reg. Addr. (Hex) 0x0F5 Bits [7:5] 4 3 [2:1] Bit Name Don't care Reserved Don't care OUT5 level 0 OUT5 driver power-down Description Don't care Reserved, write 0 Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 45. LVPECL Drivers OUT6 Reg. Addr. (Hex) 0x0F6 Bits [7:5] 4 3 [2:1] 0 Bit Name Power down Channel 6 and Channel 7 OUT6 level OUT6 driver power-down Description Don't care Power down Channel 6 and Channel 7 0: enabled (default) 1: power-down Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 46. LVPECL Drivers OUT7 Reg. Addr. (Hex) 0x0F7 Bits [7:5] 4 3 [2:1] Bit Name Don't care Reserved Don't care OUT7 level 0 OUT7 driver power-down Description Don't care Reserved, write 0 Don't care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Rev. A | Page 42 of 48 Data Sheet AD9525 Table 47. SYNC_OUT Control Reg. Addr. (Hex) 0x0F8 Bits [7:5] 4 3 0x0F9 Bit Name Don't care SYNC_OUT channel power-down Sync polarity [2:1] SYNC_OUT level 0 SYNC_OUT driver power-down Don't care Polarity CMOS mode [7:5] 4 [3:2] Enable CMOS drivers 1 CMOS mode 0 Sync out resampling edge select Sync clock S divider 0x190 [7:0] 0x191 [7:0] 0x192 [7:5] 4 Sync clock S divider Don't care Sync enable [3:2] Sync source [1:0] Sync mode Description Don't care. Powers down SYNC_OUT channel. 0: enabled. 1: power-down (default). Polarity LVPECL mode. 0: noninverting (default). 1: inverting. Bit 1 Bit 0 VOD (mV) 0 0 400 (default) 0 1 600 1 0 780 1 1 960 0: enabled (default). 1: powers down LVPECL SYNC_OUT driver. Don't care. Polarity CMOS mode. This bit is also used in conjunction with Register 0x0F8[3] when the driver is in CMOS mode (Register 0x0F9[1] = 1). Reg. 0x0F9[4] Reg. 0x0F8[3] SYNC OUT/SYNC OUTB 0 0 Noninverting/noninverting 0 1 Inverting/inverting 1 0 Noninverting/inverting 1 1 Inverting/noninverting Sets the CMOS driver output configuration when Register 0x0F9[1] = 1. SYNC_OUT Bit 3 Bit 2 SYNC_OUT 0 0 Tristate Tristate 0 1 On Tristate 1 0 Tristate On 1 1 On On Use CMOS mode instead of LVPECL mode for SYNC_OUT. 0: LVPECL mode (default). 1: CMOS mode. SYNC_OUT resample edge select. Selects the M divider output edge used to resample the sync clock. 0: use rising edge of M clock (default). 1: use falling edge of M clock. 16-bit sync S divider, Bits[7:0] (LSB). Cycles of reference clock = S Divider Bits[15:0] + 1. For example, [15:0] = 0 is 1 reference clock cycles, [15:0] = 1 is 2 reference clock cycles ... [15:0] = 65535 is 65536 reference clock cycles. 16-bit sync S divider, Bits[15:8] (MSB). Don't care. 0: disable SYNC_OUT (default). 1: Enable SYNC_OUT. Note: Self-clearing for single shot sync. Bit 1 Bit 0 Select Reference for SYNC Clock 0 0 REF: reference input (default) 0 1 FB: PLL feedback N divider 1 0 Power-down: power down SYNC 1 1 Power-down: power down SYNC Bit 1 Bit 0 Sync Mode 0 0 Single shot (default) 0 1 Periodic 1 0 Pseudorandom 1 1 Pseudorandom Rev. A | Page 43 of 48 AD9525 Data Sheet Table 48. VCO, Reference, and CLK Inputs Reg. Addr. (Hex) 0x1E0 Bits [7:3] [2:0] Bit Name Don't care M divider Description Don't care. M divider value. Bit 2 Bit 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit 0 0 1 0 1 0 1 0 1 Divider Value 1 2 3 4 5 6 7 8 Table 49. Other Reg. Addr. (Hex) 0x230 232 Bits [7:5] 4 Name Don't care Dist all power-down 3 CLKIN power-down 2 M divider power-down 1 Distribution reference power-down 0 PLL power-down [7:1] 0 Don't care IO_UPDATE Description Don't care. Powers down all of distribution. Puts all drivers in safe power-down mode. 0 (default): enabled. 1: power-down. Powers down CLKIN, CLKIN. 0 (default): enabled. 1: power-down. Powers down M divider. 0 (default): enabled. 1: power-down. Power down distribution reference. This bit should be asserted only when the drivers do not need the safe power-down mode guidelines. 0 (default): enabled. 1: power-down. Power down PLL. 0 (default): enabled. 1: power-down. Don't care. This bit must be set to 1b to transfer the contents of the buffer registers into the active registers. This happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0. 1 (self-clearing): update all active registers to the contents of the buffer registers. Rev. A | Page 44 of 48 Data Sheet AD9525 APPLICATIONS INFORMATION 18 16 90 80 70 60 tJ = 100 fs tJ = 200 fs tJ = 400 fs tJ = 1ps tJ = 2ps 14 12 10 50 Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the PLL loop bandwidth in either direction. 40 tJ = 10p 8 s 6 30 10 100 fA (MHz) 1k Figure 34. SNR and ENOB vs. Analog Input Frequency ADIsimCLK is a powerful PLL modeling tool that can be downloaded from www.analog.com. It is very accurate in determining the optimal loop filter for a given application. For more information, see the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter, and the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, at www.analog.com. USING THE AD9525 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9525. An ADC can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution, where the step size and quantization error can be ignored, the available SNR can be expressed, approximately, by 1 SNR(dB) = 20 log 2f t A J 1 SNR = 20log 2f t A J 100 ENOB The AD9525 has three frequency dividers: the reference (or R) divider, the feedback (or N) divider, and the M divider. When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the M divider or the N divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. 110 10011-035 The AD9525 is a highly flexible PLL. When choosing the PLL settings and version of the AD9525, the following guidelines should be kept in mind. Figure 34 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). SNR (dB) FREQUENCY PLANNING USING THE AD9525 Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sampling clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. The differential LVPECL outputs of the AD9525 enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic level termination) should be considered when selecting the best clocking/converter solution. where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock. Rev. A | Page 45 of 48 AD9525 Data Sheet LVPECL CLOCK DISTRIBUTION SYNC_OUT DISTRIBUTION The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 22 shows the LVPECL output stage. The SYNC_OUT driver of the AD9525 can be configured as CMOS drivers. When selected for use as CMOS drivers, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting. Be sure to note the skew difference of using CMOS mode vs. LVPECL mode. In most applications, a LVPECL far-end Thevenin termination (see Figure 35) or Y-termination (see Figure 36) is recommended. In both cases, VS of the receiving buffer should match VS_DRV (VS_DRV = VDD3). If it does not match, ac coupling is recommended (see Figure 37). Point-to-point connections should be designed such that each driver has only one receiver, if possible. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. VS_DRV 127 SINGLE-ENDED (NOT COUPLED) 50 LVPECL 83 83 The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. Figure 35. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination VS = VS_DRV Z0 = 50 LVPECL Z0 = 50 50 50 50 LVPECL 10011-037 VS_DRV CMOS VS LVPECL 200 10011-038 200 100 DIFFERENTIAL 100 (COUPLED) 0.1nF TRANSMISSION LINE CMOS Figure 38. Series Termination of CMOS Output 0.1nF LVPECL 60.4 (1.0 INCH) MICROSTRIP Figure 36. DC-Coupled 3.3 V LVPECL Y-Termination VS_DRV 10 Figure 37. AC-Coupled LVPECL with Parallel Transmission Line LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. Thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the AD9525 should equal VS of the receiving buffer. Although the resistor combination shown results in a dc bias point of VS_DRV - 2 V, the actual common-mode voltage is VS_DRV - 1.3 V because there is additional current flowing from the AD9525 LVPECL driver through the pull-down resistor. Termination at the far end of the PCB trace is a second option. The SYNC_OUT CMOS output of the AD9525 does not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 39. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. VS CMOS 10 50 100 CMOS 100 10011-040 LVPECL 127 10011-039 50 VS 10011-036 VS_DRV When single-ended CMOS clocking is used, refer to the guidelines presented in the following paragraphs. Figure 39. CMOS Output with Far-End Termination Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9525 offers SYNC_OUT LVPECL outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. Rev. A | Page 46 of 48 Data Sheet AD9525 OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 48 37 36 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 5.20 5.10 SQ 5.00 EXPOSED PAD 12 25 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 112408-B 7.00 BSC SQ Figure 40. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm x 7 mm Body, Very Very Thin Quad CP-48-4 Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9525BCPZ AD9525BCPZ-REEL7 AD9525/PCBZ AD9525/PCBZ-VCO 1 Temperature Range -40C to +85C -40C to +85C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) Evaluation Board, No VCO Evaluation Board, 2950 MHz VCO Installed Z = RoHS Compliant Part. Rev. A | Page 47 of 48 Package Option CP-48-4 CP-48-4 AD9525 Data Sheet NOTES (c)2012-2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10011-0-4/13(A) Rev. A | Page 48 of 48 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9525BCPZ AD9525/PCBZ AD9525/PCBZ-VCO AD9525BCPZ-REEL7