PC8610VT1333NB - Freescale Semiconductor / Motorola

Freescale Semiconductor

Data Sheet

Document Number: MPC8610EC

Rev. 2, 01/2009

Features

• High-performance, 32-bit e600 core, that implements the

Power Architecture™ technology

– Eleven execution units and three register file s

– Two s eparate 32-Kby te ins truct ion and dat a lev el 1 (L1)

caches

– In tegrated 2 56-Kbyt e, eight- way set -assoc iati ve unifi ed

instruction and data level 2 (L2) cache with ECC

– 36-bit real addressing

– Multiprocessing support features

– Power and thermal management

• MPX coherency modul e (MCM)

• Address translation and mapping units (ATMUs)

• DDR/DDR2 memory controller

– 64- or 32-bit data path (72-bit with ECC)

– Up to 533-MHz DDR2 dat a rat e and up to 400 MHz

DDR data rate

– Up to 16 Gbytes me mo ry

• Enha nced local bus controller (eLBC)

– Operating at up to 133 MHz

– Eight chip selects

• D isplay in ter f a c e uni t

– Maxim um displa y res olution: 1280 ×1024

– Maximum dis play refres h rate: 60 Hz

– Display color depth: up to 24 bpp

– Display interface: parallel TTL

• OpenPIC-complia nt programmable interrupt controller

(PIC)

– Supp orts 16 progra mmable interr upt and proce ssor task

pr ior ity levels

– Supp orts 12 disc rete extern al interrupts and 48 int ernal

interrupts

– Eight glob al high resolution timers/counters that can

generate int errupts

– Support for PCI Express messa ge-shared interrupts

(MSIs)

•Dual I

2C controllers

– Master or slave I2C mode support

– Boot se quencer

– Optiona ll y loads confi gurati on data fro m serial ROM at

reset vi a I2C interface

– Can be used to init ialize config uratio n registers and/or

memory

– Suppo rts extende d I 2C addressing mode

• DUART

• Fast InfraRed interface

• Serial pe ripheral interface

– Master or slave suppor t

• Dual integrate d four-channel DMA control lers

– All channels accessible by both local and remote masters

– Suppo rts trans fers to or from any local memor y or I/O

port

– Ability to start and flow control each DMA channe l

from extern al 3-pin int erface

• Wa tchdog timer

• Dual global timer mo dules

• 32-bit PCI interface, 33 or 66 MHz bus frequency

• Dual PCI Express® cont rollers

– PCI Expres s 1.0a compatib le

– PCI Express controller 1 supports x1, x2, and x4 link

widths; PCI Express controller 2 supports x1, x2, x4, and

x8 link widths

– 2.5 Gbaud, 2.0 Gbps lane

• Device performanc e monitor

– Suppo rts e ight 32 -bit count ers t hat count th e occ urrence

of selected events

– Ability to count up to 512 counter-s pecific events

– Suppo rts 6 4 refer ence events tha t can be c ount ed on any

of the 8 counters

– Supports dura tion and quantity threshol d counting

– Burst iness feature that permits counting of burst event s

with a progra mmable time be tween bursts

– Tri ggering and cha ining capability

– Ability to genera te an interrupt on ove rflow

• IEEE S td 1149.1™ compliant, JTAG boundary scan

• Ava ilable as 783-pin, flip-chip, pl as tic ball grid array

(FC-PBGA)

MPC8610 Integrated Host Processor

Hardware Specifications

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor2

Table of Contents

1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4

2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .15

2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.6 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . .25

2.7 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.8 Display Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.9 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI). . . . . . . . . . .42

2.12 Synchronous Serial Interface (SSI). . . . . . . . . . . . . . . .42

2.13 Global Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . .48

2.14 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.15 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . .50

2.16 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.17 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .54

2.18 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

2.19 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .72

3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.2 Power Supply Design and Sequencing . . . . . . . . . . . . 76

3.3 Decoupling Recommendations . . . . . . . . . . . . . . . . . . 77

3.4 SerDes Block Power Supply Decoupling

Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.5 Connection Recommendations . . . . . . . . . . . . . . . . . . 77

3.6 Pull-Up and Pull-Down Resistor Requirements . . . . . . 78

3.7 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . . 78

3.8 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . . 79

3.9 JTAG Configuration Signals. . . . . . . . . . . . . . . . . . . . . 80

3.10 Guidelines for High-Speed Interface Termination . . . . 83

3.11 Guidelines for PCI Interface Termination. . . . . . . . . . . 84

3.12 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.1 Part Numbers Fully Addressed by This Document . . . 90

4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.1 Package Parameters for the MPC8610 . . . . . . . . . . . . 92

5.2 Mechanical Dimensions of the MPC8610 FC-PBGA. . 93

6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 3

Figure 1 shows the major functional units within the MPC8610.

Figure 1. MPC8610 Block Diagram

DDR/DDR2

SDRAM

IRQs

MPC8610

MPX Bus

ROM, NAND Flash,

NOR Flash, GPIO

Serial

IrDA

SPI

Peripherals

LCD

Timer

Control

PCI Express

x1,x2,x4,x8

External

Control

PCI Express

x1,x2,x4

32-Bit PCI

External

Control

32-Bit PCI

Interface

Four-Channel

DMA Controller 1

Four-Channel

DMA Controller 2

PCI Express

Interface 2 (×8)

PCI Express

Interface 1 (×4)

OCeaN

Switch

Fabric 1

OCeaN

Switch

Fabric 2

Programmable Interrupt

Controller

(PIC)

DDR/DDR2

SDRAM Controller

2 x I

C Controller

2 x Dual Universal

Asynchronous

Receiver/Transmitter

(DUART)

2 x Fast/Serial

Infra-Red Interface

(FIRI/SIRI)

Serial Peripheral

Interface

Display Interface Unit

2 x Global Timer Module

Local Bus Controller

(eLBC)

256-Kbyte

Cache

e600 Core Block

32-Kbyte

L1 Instruction Cache

32-Kbyte

L1 Data Cache

e600 Core w/ AltiVec

MPX Coherency Module (MCM)

S/AC97 Audio

2 x Synchronous Serial

Interface (SSI)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Pin Assignments and Reset States

Freescale Semiconductor4

1 Pin Assignments and Reset States

Table 1 provides the pin assignments for the signa ls.

Table 1. Signal Reference by Functional Block

Name1Package Pin Number Pin Type Power Supply Notes

Clocking Signals4

SYSCLK D28 I OVDD

RTC A25 I OVDD 17

DDR Memory Interface Signals2

MA[15:0] AH28, AH25, AH6, AH24, AH22, AG13,

AG22, AG19, AH21, AH19, AH18, AG16,

AH16, AG15, AH15, AH14

OGV

MBA[2:0] AG25, AH13, AH12 O GVDD

MCS[0:3] AH10, AG7, AH9, AG4 O GVDD

MDQ[0:63] W26, Y26, AB24, AC28, W27, Y28, AB27,

AB26 AD27, AE27, AD25, AF25, AC26,

AD28, AC25, AD24, AG24, AF23, AE21,

AG21, AE24, AE23, AF22, AD21, AH20,

AC19, AG18, AF17, AE20, AF20, AE18,

AC17, AC13, AD12, AG9, AE9, AD13,

AE12, AD10, AC10, AF8, AE8, AD6, AH5,

AD9, AH8, AG6, AE6, AF4, AD4, AC3, AC1,

AF5, AE5, AD2, AC4, AB1, AB2, Y1, Y6,

AB6, AA6, Y3, Y4

I/O GVDD

MECC[0:7] AD16, AF16, AC15, AF15, AH17, AE17,

AA15, AB15

I/O GVDD

MDM[0:8] Y25, AE26, AH23, AD19, AF11, AF7, AE3,

AB4, AC16

OGV

MDQS[0:8] AA25, AF26, AD22, AD18, AF10, AC7, AD3,

AA5, Y15

I/O GVDD

MDQS[0:8] AA27, AF28, AC22, AF19, AE11, AD7, AE2,

AB5, AB16

I/O GVDD

MCAS AG10 O GVDD

MWE AH11 O GVDD

MRAS AG12 O GVDD

MCK[0:5] AF14, AG28, AH3, AD15, AH27, AG2 O GVDD

MCK[0:5] AF13, AG27, AH2, AD14, AH26, AG1 O GVDD

MCKE[0:3] AB28, AA28, AE28, W28 O GVDD 18

MDIC[0:1] AD1, AE1 I/O GVDD 19

MODT[0:3] AH7, AH4, AG3, AF1 O GVDD

Enhanced Local Bus Signals4

Pin Assignments and Reset States

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 5

LAD[0:31] AA21, AA22, AA23, Y21, Y22, Y23, Y24,

W23, W24, W25, V28, V27, V25, V23, V21,

W22, U28, U26, U24, U22, U23, U20, U21,

W20, V20, T24, T25, T27, T26, T21, T22,

T23

I/O BVDD 20

LDP[0:3]/LA[6:9] N28, M28, L28, P25 I/O BVDD

LA10/SSI1_TXD P19 O BVDD 20, 23

LA11/SSI1_TFS M27 O BVDD 23

LA12/SSI1_TCK U18 O BVDD 23

LA13/SSI1_RCK P28 O BVDD 23

LA14/SSI1_RFS R18 O BVDD 23

LA15/SSI1_RXD R19 O BVDD 23

LA16/SSI2_TXD R20 O BVDD 23

LA17/SSI2_TFS M18 O BVDD 23

LA18/SSI2_TCK N18 O BVDD 23

LA19/SSI2_RCK N27 O BVDD 23

LA20/SSI2_RFS P20 O BVDD 23

LA21/SSI2_RXD P21 O BVDD 23

LA[22:31] M19, M21, M22, M23, N23, N24, M26, N20,

N21, N22

OBV

DD 20

LCS[0:4] R24, R22, P23, P24, P27 O BVDD 21

LCS5/DMA2_DREQ0 R23 O BVDD 21, 22, 23

LCS6/DMA2_DACK0 N26 O BVDD 21, 23

LCS7/DMA2_DDONE0 R26 O BVDD 21, 23

LWE0/LFWE/LBS0 T19 O BVDD 20

LWE1/LBS1 T20 O BVDD 20

LWE2/LBS2 W19 O BVDD 20

LWE3/LBS3 T18 O BVDD 20

LBCTL T28 O BVDD 20

LALE R28 O BVDD 20

LGPL0/LFCLE L19 O BVDD 20

LGPL1/LFALE L20 O BVDD 20

LGPL2/LOE/LFRE L21 O BVDD 20

LGPL3/LFWP L22 O BVDD 20

LGTA/LFRB/LGPL4/

LUPWAIT/LPBSE

L23 I/O BVDD 24

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Pin Assignments and Reset States

Freescale Semiconductor6

LGPL5 L24 O BVDD

LCLK[0:2] R25, M25, L26 O BVDD

DIU/LCD Signals4

DIU_LD[23:16]/

GPIO1[15:8]

R3, R10, T10, N7, N4, P6, P5, P4 O OVDD 5, 23

DIU_LD[15:0]/

GPIO1[31:16]

T3, R9, T9, R8, R7, R6, R4, T7, U5, T6, T5,

W4, W5, W6, V4, V6

OOV

DD 5, 14, 20, 23

DIU_VSYNC V7 O OVDD 20

DIU_HSYNC U7 O OVDD 20

DIU_DE U4 O OVDD 20

DIU_CLK_OUT N6 O OVDD

Programmable Interrupt Controller (PIC) Signals4

IRQ[0:5] L25, J23, K26, E23, K28, K22 I OVDD

IRQ6/DMA1_DREQ0 G27 I OVDD 22, 23

IRQ7/DMA1_DACK0 J25 I OVDD 23

IRQ8/DMA1_DDONE0 J27 I OVDD 23

IRQ9/DMA1_DREQ3 H26 I OVDD 22, 23

IRQ10/DMA1_DACK3 J26 I OVDD 23

IRQ11/DMA1_DDONE3 K27 I OVDD 23

IRQ_OUT K23 O OVDD 21, 25

MCP A24 I OVDD

SMI B24 I OVDD

I2C Signals

IIC1_SDA/GPIO2[10] D24 I/O OVDD 21, 23, 25

IIC1_SCL/GPIO2[9] E24 I/O OVDD 21, 23, 25

IIC2_SDA/SPISEL/

GPIO2[12]

E27 I/O OVDD 21, 23, 25

IIC2_SCL/SPICLK/

GPIO2[11]

E28 I/O OVDD 21, 23, 25

DUART Signals4

UART_SIN0/SPIMOSI/

GPIO2[5]

K24 I OVDD 23

UART_SOUT0/SPIMISO H25 O OVDD 23

UART_CTS0/GPIO2[6] G24 I OVDD 23

UART_RTS0 G26 O OVDD 20

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

Pin Assignments and Reset States

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 7

UART_SIN1/IR2_RXD/

GPIO2[7]

F25 I OVDD 23

UART_SOUT1/IR2_TXD H24 O OVDD 23

UART_CTS1/GPIO2[8] C23 I OVDD 23

UART_RTS1D23 OOV

IrDA Signals4

IR1_TXD/GPIO2[13] F27 O OVDD 23

IR1_RXD/GPIO2[14] E26 I OVDD 23

IR_CLKIN F28 I OVDD

IR2_TXD/UART_SOUT1 H24 O OVDD 23

IR2_RXD/UART_SIN1/

GPIO2[7]

F25 I OVDD 23

SPI Signals

SPIMOSI/UART_SIN0/

GPIO2[5]

K24 I/O OVDD 23

SPIMISO/UART_SOUT0 H25 I/O OVDD 23

SPISEL/IIC2_SDA/

GPIO2[12]

E27 I OVDD 23

SPICLK/IIC2_SCL/

GPIO2[11]

E28 I OVDD 23

SSI Signals3, 6

SSI1_RXD/LA15 R19 I BVDD 23

SSI1_TXD/LA10 P19 O BVDD 23

SSI1_RFS/LA14 R18 I/O BVDD 23

SSI1_TFS/LA11 M27 I/O BVDD 23

SSI1_RCK/LA13 P28 I/O BVDD 23

SSI1_TCK/LA12 U18 I/O BVDD 23

SSI2_RXD/LA21 P21 I BVDD 23

SSI2_TXD/LA16 R20 O BVDD 23

SSI2_RFS/LA20 P20 I/O BVDD 23

SSI2_TFS/LA17 M18 I/O BVDD 23

SSI2_RCK/LA19 N27 I/O BVDD 23

SSI2_TCK/LA18 N18 I/O BVDD 23

DMA Signals4

DMA1_DREQ0/IRQ6/

GPIO2[24]

G27 I OVDD 22, 23

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Pin Assignments and Reset States

Freescale Semiconductor8

DMA1_DREQ3/IRQ9/

GPIO2[26]

H26 I OVDD 23

DMA1_DACK0/IRQ7/

GPIO2[25]

J25 O OVDD 23

DMA1_DACK3/IRQ10/

GPIO2[27]

J26 O OVDD 23

DMA1_DDONE0/IRQ8 J27 O OVDD 23

DMA1_DDONE3/IRQ11/

GPIO2[28]

K27 O OVDD 23

DMA2_DREQ0/LCS5 R23 I OVDD 23

DMA2_DREQ3/ GPIO2[29] H27 I OVDD 23

DMA2_DACK0/LCS6 N26 O OVDD 23

DMA2_DACK3/ GPIO2[30] H28 O OVDD 23

DMA2_DDONE0/LCS7 R26 O OVDD 23

DMA2_DDONE3/

GPIO2[31]

J28 O OVDD 23

General-Purpose Timer Signals4

GTM1_TIN1/GPIO2[15] U3 I OVDD 23

GTM1_TIN3/GPIO2[21] W2 I OVDD 23

GTM1_TGATE1/

GPIO2[16]

V2 I OVDD 23

GTM1_TGATE3/

GPIO2[22]

U1 I OVDD 23

GTM1_TOUT1/GPIO2[17] W3 O OVDD 23

GTM1_TOUT3/GPIO2[23] U2 O OVDD 23

GTM2_TIN1/GPIO2[18] V1 I OVDD 23

GTM2_TGATE1/

GPIO2[19]

W1 I OVDD 23

GTM2_TOUT1/GPIO2[20] V3 O OVDD 23

PCI Signals4

PCI_AD[31:0] M1, M2, M3, M4, M5,M7, L1, L6, J1, K2, K3,

K4, K5, K6, K7, H1, H7, G1, G2, G3, G4, G5,

G6, F1, F4, F6, F7, F8, D2, D3, E1, E2

I/O OVDD

PCI_C/BE[3:0] L2, J2, H6, F2 I/O OVDD

PCI_PAR H5 I/O OVDD

PCI_FRAME J3 I/O OVDD

PCI_TRDY J6 I/O OVDD

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

Pin Assignments and Reset States

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 9

PCI_IRDY J5 I/O OVDD

PCI_STOP E4 I/O OVDD

PCI_DEVSEL J7 I/O OVDD

PCI_IDSEL L5 I OVDD

PCI_PERR H2 I/O OVDD

PCI_SERR H3 I/O OVDD

PCI_REQ0 N3 I/O OVDD

PCI_REQ1/GPIO1[0] N1 I/O OVDD 23

PCI_REQ2/GPIO1[2] P3 I/O OVDD 23

PCI_REQ3/GPIO1[4] P1 I/O OVDD 23

PCI_REQ4/GPIO1[6] P2 I/O OVDD 23

PCI_GNT0 N2 I/O OVDD

PCI_GNT1/GPIO1[1] T1 I/O OVDD 23

PCI_GNT2/GPIO1[3] T2 I/O OVDD 23

PCI_GNT3/GPIO1[5] R1 I/O OVDD 23

PCI_GNT4/GPIO1[7] R2 I/O OVDD 23

PCI_CLK C1 I OVDD

SerDes 1 Signals

SD1_TX[3:0] J13, G12, F10, H9 O X1VDD

SD1_TX[3:0] H13, F12, G10, J9 O X1VDD

SD1_RX[3:0] B9, D8, D5, B4 I S1VDD

SD1_RX[3:0] A9, C8, C5, A4 I S1VDD

SD1_REF_CLK A7 I S1VDD

SD1_REF_CLK B7 I S1VDD

SD1_PLL_TPD C7 O X1VDD 9, 10

SD1_PLL_TPA B6 Analog S1VDD 9, 11

SD1_IMP_CAL_TX E11 Analog X1VDD 7

SD1_IMP_CAL_RX B3 Analog S1VDD 8

SerDes 2 Signals

SD2_TX[7:0] F22, J21, F20, H19, J17, G16, H15, G14 O X2VDD

SD2_TX[7:0] G22, H21, G20, J19, H17, F16, J15, F14 O X2VDD

SD2_RX[7:0] B22, D21, B20, D19, C15, B14, C13, A12 I S2VDD

SD2_RX[7:0] A22, C21, A20, C19, D15, A14, D13, B12 I S2VDD

SD2_REF_CLK A18 I S2VDD

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Pin Assignments and Reset States

Freescale Semiconductor10

SD2_REF_CLK B18 I S2VDD

SD2_PLL_TPD D17 O X2VDD 9, 10

SD2_PLL_TPA C17 Analog S2VDD 9, 11

SD2_IMP_CAL_TX E21 Analog X2VDD 7

SD2_IMP_CAL_RX B11 Analog S2VDD 8

System Control Signals4

HRESET B23 I OVDD

HRESET_REQ J22 O OVDD

SRESET A26 I OVDD

CKSTP_IN C27 I OVDD

CKSTP_OUT F24 O OVDD 21, 25

Power Management Signals4

ASLEEP B26 O OVDD 20

Debug Signals4

TRIG_IN K20 I OVDD

TRIG_OUT/READY/

QUIESCE

C28 O OVDD 14

MSRCID[0:4] Y20, AB23, AB20, AB21, AC23 O BVDD 14, 20

MDVAL AC20 O BVDD 20

CLK_OUT G28 O OVDD 18

Test Signals4

LSSD_MODE G23 I OVDD 26

TEST_MODE[0:1] K12, K10 I OVDD 26

JTAG Signals4

TCK D26 I OVDD

TDI B25 I OVDD 27

TDO D27 O OVDD 18

TMS C25 I OVDD 27

TRST A28 I OVDD 27

Additional Analog Signals

TEMP_ANODE C11 Thermal —

TEMP_CATHODE C10 Thermal —

Special Connection Requirement Pins

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

Pin Assignments and Reset States

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 11

No Connects B1, B10, C2, C3, E22, F18, G11, G18, H8,

H11, H14, J11, AA1, AA2, AA3, AA4

——16

Power and Ground Signals

MVREF AE14 DDR2 reference

voltage

GVDD/2

OVDD C24, C26, D1, E25, F3, G7, G25, H4, J24,

K1, L4, L7, N5, P10, P7, T4, T8, V5, V8

LCD, general

purpose timer,

PCI, MPIC, I2C,

DUART, IrDA,

SPI, DMA,

system control,

clocking, debug,

test, JTAG, &

power

management

I/O supply

OVDD

GVDD Y2, Y16, AA7, AA24, AA26, AB14, AB17,

AC2, AC5, AC6, AC9, AC12, AC18, AC21,

AC24, AC27, AE4, AE7, AE10, AE13, AE16,

AE19, AE22, AE25, AF2, AG5, AG8, AG11,

AG14, AG17, AG20, AG23, AG26, AH1

DDR SDRAM

I/O supply

GVDD

BVDD L27, M20, M24, P18, P22, P26, U19, U27,

V24, W21, AA20

eLBC & SSI I/O

voltage

BVDD

S1VDD A3, A10, B5, B8, D4, D7 Receiver and

SerDes core

power supply for

port 1

S1VDD

S2VDD A11, A15, A19, A23, B13, B17, B21, C14,

C18, D12, D16, D20

Receiver and

SerDes core

power supply for

port 2

S2VDD

X1VDD F11, G9, H12, J10, K13 Transmitter

power supply for

SerDes port 1

X1VDD

X2VDD F13, F17, F21, G15, G19, H18, H22, J16,

J20

Transmitter

power supply for

SerDes port 2

X2VDD

L1VDD K14 Digital logic

power supply for

SerDes port 1

L1VDD

L2VDD K16, K18 Digital logic

power supply for

SerDes port 2

L2VDD

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Pin Assignments and Reset States

Freescale Semiconductor12

VDD_Core L8, L10, M9, M11, M13, M15, N8, N10, N12,

N14, N16, P9, P11, P13, P15, R12, R14,

R16, T11, T13, T15, U10, U12, U14, U16,

V9, V11, V13, V15, W8, W10, W12, W14,

W16, Y9, Y11, Y13, Y7, AA8, AA10, AA12,

AB9, AB11, AC8

Core voltage

supply

VDD_Core

VDD_PLAT L12, L14, L16, L18, M17, P17, T17, V17,

V19, W18, Y17, Y19, AA18

Platform supply

voltage

VDD_PLAT

AVDD_Core A27 Core PLL supply AVDD_Core

AVDD_PLAT B28 Platform PLL

supply

AVDD_PLAT

AVDD_PCI A2 AVDD_PCI

SD1AVDD A6 SD1AVDD

SD2AVDD A16 SD2AVDD

SENSEVDD AC11 VDD_Core

sensing pin

SENSEVSS AB12 Core GND

sensing pin

GND B2, B27, D25, E3, F26, F5, G8, H23, J4,

K25, L11, L13, L15, L17, L3, L9, M10, M12,

M14, M16, M6, M8, N11, N13, N15, N17,

N19, N25, N9, P12, P14, P16, P8, R11, R13,

R15, R17, R21, R27, R5, T12, T14, T16,

U11, U13, U15, U17, U25, U6, U8, U9, V10,

V12, V14, V16, V18, V22, V26, W11, W13,

W15, W17, W7, W9, Y10, Y12, Y14, Y18,

Y27, Y5, Y8, AA11AA13, AA14, AA16,

AA17, AA19, AA9, AB10, AB13, AB18,

AB19, AB22, AB25, AB3, AB7, AB8, AC14,

AD11, AD17, AD20, AD23, AD26, AD5,

AD8, AE15, AF12, AF18, AF21, AF24,

AF27, AF3, AF6, AF9

GND

SD1AGND C6 SerDes port 1

ground pin for

SD1AVDD

SD2AGND B16 SerDes port 2

ground pin for

SD2AVDD

SGND A5, A8, A13, A17, A21, B15, B19, C4, C9,

C12, C16, C20, C22, D6, D9, D10, D11,

D14, D18, D22, E5, E6, E7, E8, E9, E10,

E13, E14, E15, E16, E17, E18, E19, E20

Ground pins for

SVDD

XGND E12, F9, F15, F19, F23, G13, G17, G21,

H10, H16, H20, J8, J12, J14, J18, K8, K9,

K11, K15, K17, K19, K21

Ground pins for

XVDD

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

Pin Assignments and Reset States

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 13

Reset Configuration Signals15

LAD[0:31]

cfg_gpinout[0:31]

AA21, AA22, AA23, Y21, Y22, Y23, Y24,

W23, W24, W25, V28, V27, V25, V23, V21,

W22, U28, U26, U24, U22, U23, U20, U21,

W20, V20, T24, T25, T27, T26, T21, T22,

T23

—BV

LA10/SSI1_TXD

cfg_ssi_la_sel

P19 — BVDD

LA[25:26]

cfg_elbc_clkdiv[0:1]

M23, N23 — BVDD

LA27

cfg_cpu_boot

N24 — BVDD

DIU_LD[10], LA[28:31]

cfg_sys_pll[0:4]

R6, M26, N20, N21, N22 — BVDD

LWE0/LFWE/LBS0

cfg_pci_speed

T19 — BVDD

LWE/LBS[1:3]

cfg_host_agt[0:2]

T20, W19, T18 — BVDD

LBCTL, LALE,

LGPL2/LOE/LFRE,

DIU_LD4

cfg_core_pll[0:3]

T28, R28, L21, W4 — BVDD

LGPL0/LFCLE

cfg_net2_div

L19 — BVDD 12

LGPL1/LFALE

cfg_pci_clk

L20 — BVDD

LGPL3/LFWP, LGPL5

cfg_boot_seq[0:1]

L22, L24 — BVDD

DIU_LD[0]

cfg_elbc_ecc

V6 — OVDD

DIU_LD[7:9]

cfg_io_ports[0:2]

U5, T7, R4 — OVDD

DIU_LD[11:12]

cfg_dram_type[0:1]

R7, R8 — OVDD

DIU_DE, DIU_LD[13:15]

cfg_rom_loc[0:3]

U4, T9, R9, T3 — OVDD

DIU_VSYNC

cfg_pci_impd

V7 — OVDD

DIU_HSYNC

cfg_pci_arb

U7 — OVDD

UART_RTS0

cfg_wdt_en

G26 — OVDD

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Pin Assignments and Reset States

Freescale Semiconductor14

ASLEEP

cfg_core_speed

B26 — OVDD 13

MSRCID0

cfg_mem_debug

Y20 — BVDD

MDVAL

cfg_boot_vector

AC20 — BVDD

Notes:

1. Multi-pin signals such as LDP[0:3] have their physical package pin numbers listed in order corresponding to the signal names.

2. Stub series terminated logic type pins.

3. All SSI signals are multiplexed with eLBC signals.

4. Low voltage transistor-transistor logic (LVTTL) type pins.

5. DIU_LD[23:16] = RED[7:0].

DIU_LD[15:8] = GREEN[7:0].

DIU_LD[7:0] = BLUE[7:0].

6. The pins for the SSI interface on the device are multiplexed with certain eLBC signals, which have the ability to operate at a

different voltage than the other standard I/O signals. If the device is configured such that the eLBC uses a different voltage

than standard I/O and an SSI port on the device is used, then level shifters are required on the SSI signals to ensure they

correctly interface to other devices on the board at the proper voltage.

7. This pin should be pulled to ground with a 100-Ω resistor.

8. This pin should be pulled to ground with a 200-Ω resistor.

9. These pins should be left floating.

10.This is a SerDes PLL/DLL digital test signal and is only for factory use.

11.This is a SerDes PLL/DLL analog test signal and is only for factory use.

12.This pin should be pulled down if the platform frequency is 400 MHz or below.

13.This pin should be pulled down if the core frequency is 800 MHz or below.

14.MSRCID[1:2], DIU_LD[5:6] and TRIG_OUT/READY should NOT be pulled down (or driven low) during reset.15. The pins in

this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when the

processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down

resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down

the value of the net at reset, then a pullup or active driver is needed.

16.These pins should be left floating.

17.Must be tied low if unused.

18.This output is actively driven during reset rather than being tri-stated during reset.

19.MDIC[0] should be connected to ground with an 18-Ω resistor ± 1 Ω and MDIC[1] should be connected to GVDD with an 18-Ω

resistor ± 1 Ω. These pins are used for automatic calibration of the DDR IOs.

20.This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset

Configuration Signals section of this table for config name and connection details.

21.Recommend a weak pull-up resistor (1–10 kΩ) be placed from this pin to its power supply.

22.This multiplexed pin has input status in one mode and output in another.

23.This pin is a multiplexed signal for different functional blocks and appears more than once in this table.

24.For systems which boot from local bus (GPCM)-controlled flash, a pullup on LGPL4 is required.

25.This pin is open drain signal.

26.These are test signals for factory use only and must be pulled up (100 Ω to 1 kΩ) to OVDD for normal machine operation.

27.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

28.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve

tracking and regulation.

Table 1. Signal Reference by Functional Block (continued)

Name1Package Pin Number Pin Type Power Supply Notes

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 15

2 Electrical Characteristics

This section provides the AC and DC electrical specifications for the MPC8610. The MPC8610 is currently targe ted to the se

specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ra tings, condit ions, and other chara cteristics .

2.1.1 Absolute Maximum Ratings

Table 2 provides the absol ute maximum ratings.

Table 2. Absolute Maximum Ratings1

Characteristic Symbol Recommended

Value Unit Notes

Core supply voltages VDD_Core –0.3 to 1.21 V

Core PLL supply AVDD_Core –0.3 to 1.21 V

SerDes receiver and core power supply (ports 1 and 2) S1VDD

S2VDD

–0.3 to 1.21 V

SerDes transmitter power supply (ports 1 and 2) X1VDD

X2VDD

–0.3 to 1.21 V

SerDes digital logic power supply (ports 1 and 2) L1VDD

L2VDD

–0.3 to 1.21 V

Serdes PLL supply voltage (ports 1 and 2) SD1AVDD

SD2AVDD

–0.3 to 1.21 V

Platform supply voltage VDD_PLAT –0.3 to 1.21 V

PCI and platform PLL supply voltage AVDD_PCI

AVDD_PLAT

–0.3 to 1.21 V

DDR/DDR2 SDRAM I/O supply voltages GVDD –0.3 to 2.75 V

Local bus and SSI I/O voltage BVDD –0.3 to 3.63 V

LCD, PCI, general purpose timer, MPIC, IrDA, DUART, DMA,

interrupts, system control and clocking, debug, test, JTAG, power

management, I2C, SPI, and miscellaneous I/O voltage

OVDD –0.3 to 3.63 V

Input voltage DDR/DDR2 SDRAM signals MVIN (GND – 0.3) to

(GVDD +0.3)

DDR/DDR2 SDRAM reference MVREF (GND – 0.3) to

(GVDD/2 + 0.3)

Local bus I/O voltage BVIN (GND – 0.3) to

(BVDD +0.3)

LCD, PCI, general purpose, MPIC, IrDA, DUART,

DMA, interrupts, system control and clocking,

debug, test, JTAG, power management, I2C, SPI

and miscellaneous I/O voltage

OVIN (GND – 0.3) to

(OVDD +0.3)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor16

2.1.2 Recommended Operating Conditions

Table 3 provid es the re commen ded oper ating condi tions for the MPC861 0. Note that the value s in Table 3 are the recommended

and tested operatin g conditions. Prope r device operation outside of these condition s is not guaranteed. For details on order

inform ation and spec ific operat ing conditions for parts, se e Sectio n 4, “Ordering Information.”

Storage temperature range TSTG –55 to 150 °C

Notes:

1Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2During run time (M, B, O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in

Ta b le 2 .

Table 3. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit Notes

Core supply voltages VDD_Core 1.025 ± 50 mV V 1

1.00 ± 50 mV 2

Core PLL supply AVDD_Core 1.025 ± 50 mV V 1, 3

1.00 ± 50 mV 2, 3

SerDes receiver and core power supply (ports 1 and 2) S1VDD

S2VDD

1.025 ± 50 mV V 1, 4

1.00 ± 50 mV 2

SerDes transmitter power supply (ports 1 and 2) X1VDD

X2VDD

1.025 ± 50 mV V 1

1.00 ± 50 mV 2

SerDes digital logic power supply (ports 1 and 2) L1VDD

L2VDD

1.025 ± 50 mV V 1

1.00 ± 50 mV 2

Serdes PLL supply voltage (ports 1 and 2) SD1AVDD

SD2AVDD

1.025 ± 50 mV V 1, 3

1.00 ± 50 mV 2, 3

Platform supply voltage VDD_PLAT 1.025 ± 50 mV V 1

1.00 ± 50 mV 2

PCI and platform PLL supply voltage AVDD_PCI

AVDD_PLAT

1.025 ± 50 mV V 1, 3

1.00 ± 50 mV 2, 3

DDR and DDR2 SDRAM I/O supply voltages GVDD 2.5 V ± 125 mV,

1.8 V ± 90 mV

Local bus and SSI I/O voltage BVDD 3.3 V ± 165 mV

2.5 V ± 125 mV

1.8 V ± 90 mV

Table 2. Absolute Maximum Ratings1 (continued)

Characteristic Symbol Recommended

Value Unit Notes

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 17

LCD, PCI, general timer, MPIC, IrDA, DUART, DMA, interrupts, system

control and clocking, debug, test, JTAG, power management, I2C, SPI,

and miscellaneous I/O voltage

OVDD 3.3 V ± 165 mV V 6

Input voltage DDR and DDR2 SDRAM signals MVIN (GND – 0.3) to

(GVDD +0.3)

V7, 5

DDR and DDR2 SDRAM reference MVREF (GND – 0.3) to

(GVDD/2 + 0.3)

Local Bus I/O voltage BVIN (GND – 0.3) to

(BVDD +0.3)

LCD, PCI, general purpose timer, MPIC, IrDA,

DUART, DMA, interrupts, system control and

clocking, debug, test, JTAG, power management,

I2C, SPI, and miscellaneous I/O voltage

OVIN (GND – 0.3) to

(OVDD +0.3)

V7, 6

Junction temperature range TJ0 to 105 °C

–40 to 105 8

Notes:

1Applies to devices marked with a core frequency of 1333 MHz. Refer to Table Part Numbering Nomenclature to determine if

the device has been marked for a core frequency of 1333 MHz.

2Applies to devices marked with a core frequency below 1333 MHz. Refer to Table Part Numbering Nomenclature to determine

if the device has been marked for a core frequency below 1333 MHz.

3AVDD measurements are made at the input of the R/C filter described in Section 3.2.1, “PLL Power Supply Filtering,” and not

at the processor pin.

4PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. Refer to Section 2.18.4.3, “Differential

Receiver (RX) Input Specifications,” for more information.

5Caution: MVIN must meet the overshoot/undershoot requirements for GVDD as shown in Figure 2.

6Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2.

7Timing limitations for (M, B, O) VIN and MVREF during regular run time is provided in Figure 2.

8Applies to devices marked MC8610TxxyyyyMz for extended temperature range. Note that MC8610Txx1333Jz is not offered.

Table 3. Recommended Operating Conditions (continued)

Characteristic Symbol Recommended

Value Unit Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor18

Figure 2 shows the und ershoot and overshoot voltages at the interface s of the MPC8610.

Figure 2. Overshoot/Undershoot Voltage for M/B/OVIN

The MPC8 610 core volta ge must a lways be provide d at nominal VDD_Core (see Table 3 for actual re commended core voltage).

Voltage to the exte rnal int erface I/Os are provided through separate set s of supply pins and must be prov ided at the voltages

shown in Table 3. The input voltage threshold scales with respect to the associat ed I/O sup p ly voltage. OV DD-based receivers

are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a

single-ended di fferen tial rece iver ref erenced to each exte r n ally supplied MVREF s i gn al ( no minally se t to GVDD/2) as is

appropriate for the (SSTL-18 and SSTL-2) electrical signaling standards.

2.1.3 Output Driver Characteristics

Table 4 provides informati on on the characteris tics of the output driver stre ngths . The valu es are prelimi nary esti ma tes.

Table 4. Output Drive Capability

Driver Type

Programmable

Output Impedance

(Ω)

Supply

Vol ta ge Notes

DDR signals 18

36 (half strength mode)

GVDD = 2.5 V 1, 4, 6

DDR2 signals 18

36 (half strength mode)

GVDD = 1.8 V 1, 5, 6

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

G/O/B/X/SVDD + 20%

G/O/B/X/SVDD

G/O/B/X/SVDD + 5%

of tCLK1

1. tCLK references clocks for various functional blocks as follows:

VIH

VIL

Note:

For DDR, tCLK references MCK.

For LBIU, tCLK references LCLK.

For PCI, tCLK references PCI_CLK or SYSCLK.

For I2C and JTAG, tCLK references SYSCLK.

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 19

2.2 Power Sequencing

The MPC8610 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These

req u ir e ment s are as foll o w s:

The chronological order of power up is:

1. OVDD, BVDD

2. VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, SDnAVDD (this rail must reach

90% of its value be fore the rail for GVDD and MVREF reaches 10% of its value)

3. GVDD, MV REF

4. SYSCLK

The order of power down is as fol lows:

1. SYSCLK

2. GVDD, MV REF

3. VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, SDnAVDD

4. ODD, BVDD

NOTE

AVDD type s uppl ies sh ould be del ayed wi th r espe ct to their s ou rce suppl ie s by t he RC ti me

cons tant of the PLL filter circuit descri bed in Section 3.2, “Power Supply Design and

Sequencing.”

Local bus 25

BVDD = 3.3 V

BVDD = 2.5 V

45 (default)

125

BVDD = 3.3 V

BVDD = 2.5 V

BVDD = 1.8 V

PCI, DUART, DMA, interrupts, system control and clocking, debug,

test, JTAG, power management, and miscellaneous I/O voltage

45 OVDD = 3.3 V

I2C150 OVDD = 3.3 V

PCI Express 100 XVDD = 1.0 V 3

Notes:

1. See the DDR control driver registers in the

MPC8610 Integrated Host Processor Reference Manual,

for more information.

2. See the POR impedance control register in the

MPC8610 Integrated Host Processor Reference Manual,

for more information

about local bus signals and their drive strength programmability.

3. See Section 1, “Pin Assignments and Reset States,” for details on resistor requirements for the calibration of

_IMP_CAL_TX and SD

_IMP_CAL_RX transmit and receive signals.

4. Stub series terminated logic (SSTL-25) type pins.

5. Stub series terminated logic (SSTL-18) type pins.

6. The drive strength of the DDR interface in half strength mode is at Tj = 105°C and at GVDD (min).

Table 4. Output Drive Capability (continued)

Driver Type

Programmable

Output Impedance

(Ω)

Supply

Vol ta ge Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor20

Figure 3 illus trates the power up sequence as described above.

Figure 3. MPC8610 Power Up Sequencing

VDD_PLAT, AVDD_PLAT

OVDD

Time

2.5 V

3.3 V

DC Power Supply Voltage

Reset

Configuration Pins

HRESET (& TRST)

Asserted for

100 μs4

VDD Stable

Power Supply Ramp Up 2

Notes:

1. Dotted waveforms correspond to optional supply values for a specified power supply. See Ta b le 3.

2. Ther recommended maximum ramp up time for power supplies is 20 milliseconds.

3. Refer to Section 2.5, “RESET Initialization” for additional information on PLL relock and reset signal

assertion timing requirements.

4. Refer to Table 9 for additional information on reset configuration pin setup timing requirements. In

addition see Figure 53 regarding HRESET and JTAG connection details including TRST.

5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.

6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration

inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles

after HRESET has negated (hold requirement). See Section 2.5, “RESET Initialization,” for more

information on setup and hold time of reset configuration signals.

7. The rail for VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, and SDnAVDD

must reach 90% of its value before the rail for GVDD and MVREF reaches 10% of its value.

8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.

9. The reset configuration signals for DRAM types must be valid before HRESET is asserted.

e600

_PCI, S

, X

VDD_Core, AVDD_Core

AVDD

1.8 V

GVDD, = 1.8/2.5 V

MVREF

SYSCLK8

(not drawn to scale)

PLL

Cycles Setup and Hold Time 6

100 µs Platform PLL

Relock Time3

1.0 V

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 21

2.3 Power Characteristics

The power dissipa tion for the MPC8 610 device is shown in Table 5.

The estimated m aximum power dis si pation for individual power su pplies of the MPC86 10 is shown in Table 6.

Table 5. MPC8610 Power Dissipation

Power Mode

Core/Platform

Frequency

(MHz)

VDD_Core,

VDD_PLAT

(V)

Junction

Temperature

(°C)

Power

(Watts) Notes

Typ ical

1333/533 1.025

65 10.7 1, 2

Thermal

105

12.1 1, 3

Maximum 16 1, 4

Typ ical

1066/533 1.00

65 8.4 1, 2

Thermal

105

9.8 1, 3

Maximum 13 1, 4

Typ ical

800/400 1.00

65 5.8 1, 2

Thermal

105

7.2 1, 3

Maximum 9.5 1, 4

Notes:

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Core) and 65°C junction

temperature (see Ta b le 3 ) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with the core

at 100% efficiency. This parameter is not 100% tested but periodically sampled.

3. Thermal power is the average power measured at nominal core voltage (VDD_Core) and maximum operating junction

temperature (see Ta b le 3 ) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on the core

and a typical workload on platform interfaces. This parameter is not 100% tested but periodically sampled.

4. Maximum power is the maximum power measured at nominal core voltage (VDD_Core) and maximum operating junction

temperature (see Table 3) while running a test which includes an entirely L1-cache-resident, contrived sequence of

instructions which keep all the execution units maximally busy on the core.

Table 6. MPC8610 Individual Supply Maximum Power Dissipation1

Component Description Supply Voltage

(V)

Est. Power

(Watts) Notes

Core voltage supply VDD_Core = 1.025 V @ 1333 MHz 14.0

VDD_Core = 1.00 V @ 1066 MHz 12.0

Core PLL voltage supply AVDD_Core = 1.025 V @ 1333 MHz 0.0125

AVDD_Core = 1.00 V @ 1066 MHz 0.0125

Platform source supply VDD_PLAT = 1.025 V @ 1333 MHz 4.5

VDD_PLAT = 1.00 V @ 1066 MHz 4.3

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor22

2.3.1 Frequency Derating

To reduce power consumpt ion, these dev ices support fre quency deratin g if the reduc ed maximum process or core frequency and

reduced maximum pl atform frequency requirements are observed. The reduced maximum proce ssor core frequency, result ing

maxim um pl atform freq uency and powe r consumption are provided in Table 7. Only thos e par ameters in Table 7 are affected;

all other parameter specifications are unaffected.

2.4 Input Clocks

Table 8 provides the system clock (SYSCLK) DC specificati ons for the MPC8610.

Platform PLL voltage supply AVDD_PLAT = 1.025 V @ 1333 MHz 0.0125

AVDD_PLAT = 1.00 V @ 1066 MHz 0.0125

Notes:

1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are

based on 100% utilization for each component. The components listed are not expected to have 100% usage simultaneously

for all components. Actual numbers may vary based on activity. Note that the production parts should have a total maximum

power value based on Table 5. The ‘Est.’ in the Est. Power column is to emphasize that these numbers are based on

theoretical estimates. The device is tested to ensure that the sum of all four supplies does not exceed the power stated in

Tab le 5 . No specific supply should ever exceed its individual amount estimated in Ta bl e 6 .

Table 7. Core Frequency, Platform Frequency and Power Consumption Derating

Maximum Rated

Core Frequency

(Device Marking)

Maximum Derated

Core/Platform

Frequency

(MHz)

VDD_Core,

VDD_PLAT

(V)

Typical Power

(Watts)

Thermal Power

(Watts)

Maximum Power

(Watts)

1333J N/A

1066J 1000/400 1.00 8.0 9.4 12.5

800G 667/333 1.00 5.0 6.4 8.5

Table 8. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD)

1Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3.

IIN —±5μA

Table 6. MPC8610 Individual Supply Maximum Power Dissipation1 (continued)

Component Description Supply Voltage

(V)

Est. Power

(Watts) Notes

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 23

2.4.1 System Clock Timing

Table 9 provides the system clock (SYSCLK) AC timi ng specifications for the MPC8610.

2.4.1.1 SYSCLK and Spread Spectrum Sources

Spread spectr um cloc k sources are a pop ular way to control electr om agnetic interfere nce emissions (EMI) by spreading the

emitted noise over a wider spectr um an d reducing the pe ak noise magnitude. Th es e c lock sources inte ntionally add long-ter m

jit ter in order to di f fuse th e EMI spect ral con tent. The jit te r specifi cati on giv en in Table 9 conside rs short-t er m (cycle-to-c ycle)

jitter only a nd the clock generator ’s cycle-to-cycle output jitter should m eet the MPC8610 input cycle-to-cycle jitte r

requiremen t. Frequency m odulation an d spre ad are separate concerns, and the MPC8 610 is compatible with sp read spectrum

sources if the rec om me ndati ons listed in Table 10 are o bs er v ed .

It i s im perative t o note that the proc essor’ s minimum and maximum SYSCLK, core, a nd VCO freque ncies must no t be exc eeded

regardles s of the type of clock s ource. Therefore, syste m s in which the proc essor is operated at its ma xim um ra ted e600 core

frequency should avoid violating the stated limits by using down-spreading only.

Table 9. SYSCLK AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

SYSCLK frequency fSYSCLK 33 — 133 MHz 1

SYSCLK cycle time tSYSCLK 7.5 — — ns —

SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2

SYSCLK duty cycle tKHK/tSYSCLK 40 — 60 % 3

SYSCLK jitter — — — ±150 ps 4, 5

Notes:

All specifications at recommended operating conditions (see Tab le 3 ) with OVDD = 3.3 V ± 165 mV.

1. Caution: The platform to SYSCLK clock ratio and e600 core to platform clock ratio settings must be chosen such that the

resulting SYSCLK, platform, and e600 (core) frequencies do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio” and Section 3.1.3, “e600 Core to MPX/Platform

Clock PLL Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the short term jitter only and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation

for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on

design.

Table 10. Spread Spectrum Clock Source Recommendations

Parameter Min Max Unit Notes

Frequency modulation — 50 kHz 1

Frequency spread — 1.0 % 1, 2

Notes:

All specifications at recommended operating conditions (see Tab le 3 ).

1. Guaranteed by design.

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Ta b l e 1 0 .

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor24

SDn_REF_CL K and S Dn_REF_CLK was designe d to wo rk with a sprea d spectru m cloc k (+0 to 0.5 % spreadi ng at 30– 33 kHz

rate is al lowed), as su mi ng both ends ha ve sam e re ference c lock. For better res ults use a source without significant unint ended

modulation.

2.4.2 Real Time Clock Timing

The R T C input is sample d by the pla tform cloc k. The ou tput of t he sa mpling latc h is t hen u sed as an input to t he coun te rs of th e

PIC. There is no ji tter specification. The minimum pulse width of the RTC signa l should be greater than 2× the peri od of the

plat form clo ck. That is , minim um clock high time is 2 × tMPX, and mi nimum cloc k low tim e is 2 × tMPX. There is no minimum

RTC freque ncy; RTC may be grounde d if not needed.

2.4.3 PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the re ference clock for the PCI/PCI-X controller is

not the SYSCLK input, but inste ad the PCIn_CLK. Table 11provide s the PCI/PCI-X refe ren ce clock AC tim ing specifi cations

for the MPC8610.

2.4.4 Platform Frequency Requirements for PCI-Express

The MPX platform clock freque ncy must be conside r ed for proper operatio n of the hi gh-speed PCI Expr ess interfa ce as

described below.

For prop er PCI Exp r ess operati on, the MPX clock frequency must be greate r than or equal to:

527 MHz x (PCI-Express link width)

16 / (1 + cfg_net2_div)

Note tha t at MPX = 333 - 400 MHz, cfg_net2_div = 0 and at MPX > 400 MHz, cfg_net2_div = 1. Therefore, when operating

PCI Express in x8 link width, the MPX platform frequency must be 333-400 MHz wit h cfg_net2_div = 0 or greater than or

equal to 527 MHz with cfg_net2_div = 1.

Table 11. PCI

_CLK AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Notes

PCI

_CLK frequency fPCICLK 16 — 133 MHz —

PCI

_CLK cycle time tPCICLK 7.5 — 60 ns —

PCI

_CLK rise and fall time tPCIKH, tPCIKL 0.6 1.0 2.1 ns 1, 2

PCI

_CLK duty cycle tPCIKHKL/tPCICLK 40 — 60 % 2

Notes:

1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

2. Timing is guaranteed by design and characterization.

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 25

2.4.5 Other Input Clocks

For in formation on the inpu t clocks of other functio nal blocks of the platfo rm such as SerDes see the specific section of this

document.

2.5 RESET Initialization

Table 12 describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8610.

Table 13 provides the PLL lock times.

2.6 DDR and DDR2 SDRAM

This s ecti on describe s the DC and AC electri cal specifi cati ons for the DDR SDRAM inte rface of the MPC8610. Note that DDR

SDRAM is GVDD = 2.5 V and DDR2 SDRAM is GVDD = 1.8 V.

Table 12. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET 100 — μs

Minimum assertion time for SRESET 3 — SYSCLKs 1

Platform PLL input setup time with stable SYSCLK before HRESET

negation

100 — μs2

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

4 — SYSCLKs 1

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

2 — SYSCLKs 1

Maximum valid-to-high impedance time for actively driven POR configs

with respect to negation of HRESET

— 5 SYSCLKs 1

Notes:

1. SYSCLK is he primary clock input for the device.

2. This is related to HRESET assertion time.

Table 13. PLL Lock Times

Parameter/Condition Min Max Unit Notes

PLL lock times (platform, PCI and e600 core) — 100 μs1

Notes:

1. The PLL lock time for the e600 core PLL requires an additional 255 platform clock cycles.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor26

2.6.1 DDR SDRAM DC Electrical Characteristics

Table 14 provides the recom mended operating conditions for the DDR2 SDRAM component ( s) of the MPC861 0 when

GVDD(typ) = 1.8 V.

Table 15 prov ides the DDR capacitance when GVDD(typ) = 1.8 V.

Table 16 provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5 V.

Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 1.71 1.89 V 1

I/O reference voltage MVREF 0.49 ×GVDD 0.51 × GVDD V2

I/O termination voltage VTT MVREF –0.04 MV

REF + 0.04 V 3

Input high voltage VIH MVREF +0.125 GV

DD +0.3 V

Input low voltage VIL –0.3 MVREF – 0.125 V

Output leakage current IOZ –50 50 μA4

Output high current (VOUT = 1.420 V) IOH –13.4 — mA

Output low current (VOUT = 0.280 V) IOL 13.4 — mA

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD

Table 15. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 16. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GVDD 2.375 2.625 V 1

I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V2

I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3

Input high voltage VIH MVREF + 0.15 GVDD + 0.3 V

Input low voltage VIL –0.3 MVREF – 0.15 V

Output leakage current IOZ –50 50 μA4

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 27

Table 17 prov ides the DDR capacitance when GVDD (typ)=2.5 V.

Table 18 provides the cu rrent d raw character istic s for MVREF.

2.6.2 DDR SDRAM AC Electrical Characteristics

This sec tion provides the AC electrical char acter istics for the DDR/DDR2 SDRAM in terface.

2.6.2.1 DDR SDRAM Input AC Timing Specifications

Table 19 provides the input AC timing spe cific ations for the DDR 2 SDRAM when GVDD(typ)=1.8 V.

Output high current (VOUT = 1.95 V) IOH –16.2 — mA

Output low current (VOUT = 0.35 V) IOL 16.2 — mA

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

. This rail should track variations in the DC level of MVREF

4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD

Table 17. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA =25°C, V

OUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 18. Current Draw Characteristics for MVREF

Parameter/Condition Symbol Min Max Unit Notes

Current draw for MVREF IMVREF — 500 μA1

Note:

1. The voltage regulator for MVREF must be able to supply up to 500 μA current.

Table 19. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions.

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.25 V

AC input high voltage VIH MVREF + 0.25 — V

Table 16. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V (continued)

Parameter/Condition Symbol Min Max Unit Notes

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor28

Table 20 provides the input AC timing spe cific ations for the DDR SDRAM when GVDD(typ)=2 .5 V.

Table 21 prov ides the input AC timing specific ations for the DDR SDRAM interface.

Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).

Figure 4. DDR Input Timing Diagram for tDISKEW

Table 20. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions.

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.31 V

AC input high voltage VIH MVREF + 0.31 — V

Table 21. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions.

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS—MDQ/MECC tCISKEW ps 1, 2

533 MHz

400 MHz

333 MHz

–300

–365

–390

300

365

390

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[

] and any corresponding bit that

will be captured with MDQS[

]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

3. Maximum DDR1 frequency is 400 MHz.

MCK[

]

MCK[

]tMCK

MDQ[x]

MDQS[

]

tDISKEW

D1D0

tDISKEW

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 29

2.6.2.2 DDR SDRAM Output AC Timing Specifications

Table 22. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

Parameter Symbol1Min Max Unit Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 310ns2

MCK duty cycle

533 MHz

400 MHz

333 MHz

tMCKH/tMCK

ADDR/CMD output setup with respect to MCK tDDKHAS ns 3

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

ADDR/CMD output hold with respect to MCK tDDKHAX ns 3

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output setup with respect to MCK tDDKHCS ns 3

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output hold with respect to MCK tDDKHCX ns 3

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4

MDQ/MECC/MDM output setup with respect

to MDQS

tDDKHDS,

tDDKLDS

ps 5

533 MHz

400 MHz

333 MHz

590

700

900

—

MDQ/MECC/MDM output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

ps 5

533 MHz

400 MHz

333 MHz

590

700

900

—

MDQS preamble start tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK +0.6 ns 6

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor30

NOTE

For the ADDR/C MD setup a nd ho ld specifi catio ns in Table 22, it is assum ed that the clock

control reg is ter is se t to adjust the memory clo cks by 1/2 applied cycl e.

Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measu r ement (tDDKHMH).

Figure 5. Timing Diagram for tDDKHMH

MDQS epilogue end tDDKHME –0.6 0.6 ns 6

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in

the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the

MPC8610 Integrated Host Processor Reference Manual,

for a description and understanding of

the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[

] at the pins of the microprocessor. Note that tDDKHMP follows the

symbol conventions described in note 1.

7. Maximum DDR1 frequency is 400 MHz.

8. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.

Table 22. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions.

Parameter Symbol1Min Max Unit Notes

MDQS

MCK[

]

MCK[

]

tMCK

tDDKHMHmax) = 0.6 ns

tDDKHMH(min) = –0.6 ns

MDQS

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 31

Figure 6 shows the DDR SDRAM output timing diagram.

Figure 6. DDR SDRAM Output Timing Diagram

Figure 7 provides the AC test load for the DDR bus.

Figure 7. DDR AC Test Load

2.7 Local Bus

This s ectio n des cribes th e DC and AC electrical specifications for the local bus interface of the MPC8610 .

2.7.1 Local Bus DC Electrical Characteristics

Table 23 provides the DC electrical characteristics for the local bus interface operating at BVDD =3.3V.

Table 23. Local Bus DC Electrical Characteristics (BVDD = 3.3 V)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2BV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (VIN1 = 0 V or VIN = BVDD)I

IN —±5 μA

High-level output voltage (BVDD = min, IOH = –2 mA) VOH BVDD – 0.2 — V

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

MCK[n] tMCK

tDDKLDX

tDDKHDX

D1D0

tDDKHAX ,tDDKHCX

Write A0 NOOP

tDDKHME

tDDKHMP

Output Z0 = 50 Ω

RL = 50 Ω

GVDD/2

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor32

Table 24 provides the DC electrical characteristics for the local bus interface operating at BVDD =2.5VDC.

Table 25 provides the DC electrical characteristics for the local bus interface operating at BVDD =1.8V.

2.7.2 Local Bus AC Electrical Specifications

Table 26 describes the general timing parameters of the loca l bus interf ac e at BVDD = 3.3 V, 2.5 V and 1.8 V. For inform ation

about the freque ncy range of loca l bus se e Sectio n 3 . 1 .1 , “C lo ck Ran g es.”

Low-level output voltage (BVDD = min, IOL = 2 mA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3.

Table 24. Local Bus DC Electrical Characteristics (BVDD = 2.5 V)

Parameter Symbol Min Max Unit

High-level input voltage VIH 1.70 BVDD + 0.3 V

Low-level input voltage VIL –0.3 0.7 V

Input current (VIN1 = 0 V or VIN = BVDD)I

IN —±15μA

High-level output voltage (BVDD = min, IOH = –1 mA) VOH 2.0 — V

Low-level output voltage (BVDD = min, IOL = 1 mA) VOL —0.4V

Note:

1. The symbol VIN, in this case, represents the BVIN symbol referenced in Table 2 and Ta b l e 3 .

Table 25. Local Bus DC Electrical Characteristics (BVDD = 1.8 V)

Parameter Symbol Min Max Unit

High-level input voltage VIH 1.3 BVDD + 0.3 V

Low-level input voltage VIL -0.3 0.8 V

Input current (VIN1 = 0 V or VIN = BVDD)I

IN —±15μA

High-level output voltage (BVDD = min, IOH = –1 mA) VOH 1.42 — V

Low-level output voltage (BVDD = min, IOL = 1 mA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the BVIN symbol referenced in Table 2 and Ta b l e 3 .

Table 26. Local Bus Timing Parameters (BVDD = 3.3 V, 2.5 V and 1.8 V)

Parameter Symbol1Min Max Unit Notes

Local bus cycle time tLBK 7.5 — ns

Local bus duty cycle tLBKH/tLBK 45 55 %

LCLK[n] skew to LCLK[m] tLBKSKEW — 100 ps 2, 7

Table 23. Local Bus DC Electrical Characteristics (BVDD = 3.3 V) (continued)

Parameter Symbol Min Max Unit

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 33

Figure 8 provides the AC test load for the local bus.

Figure 8. Local Bus AC Test Load

Figure 9 to Figure 11 show the local bus signa ls .

Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 4.5 — ns 3, 4

LGTA/LUPWAIT input setup to local bus clock tLBIVKL2 4.3 — ns 3, 4

Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 — 0.8 ns 3, 4

LGTA/LUPWAIT input hold from local bus clock tLBIXKL2 — 0.7 ns 3, 4

LALE output transition to LAD/LDP output transition

(LATCH hold time)

tLBOTOT 0.75 — ns 5

Local bus clock to output valid (except LAD/LDP and LALE) tLBKLOV1 —1.1ns

Local bus clock to data valid for LAD/LDP tLBKLOV2 —1.2ns3

Local bus clock to address valid for LAD, and LALE tLBKLOV3 —1.2ns3

Local bus clock to LALE assertion tLBKLOV4 —1.4ns

Output hold from local bus clock (except LAD/LDP and

LALE)

tLBKLOX1 -0.6 — ns 3

Output hold from local bus clock for LAD/LDP tLBKLOX2 -0.6 — ns 3

Local bus clock to output high Impedance (except

LAD/LDP and LALE)

tLBKLOZ1 —2.5ns6

Local bus clock to output high Impedance for LAD/LDP tLBKLOZ2 —2.5ns6

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for

clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to

the output (O) going invalid (X) or output hold time.

2. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2. Skew number is valid only when LCLK[m] and LCLK[n] have the same load.

3. All signals are measured from BVDD/2 of the edge of local bus clock to 0.4 ×BVDD

of the signal in question for 3.3-V signaling

levels.

4. Input timings are measured at the pin.

5. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD.

6. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

7. Guaranteed by design.

Table 26. Local Bus Timing Parameters (BVDD = 3.3 V, 2.5 V and 1.8 V) (continued)

Parameter Symbol1Min Max Unit Notes

Output Z0 = 50 ΩBVDD/2

RL = 50 Ω

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor34

NOTE

Output s ignals a re latc hed at the fa ll ing edge of LCLK a nd input sign als a re captu red at the

ris ing edge of LCLK, with the exception of the LGTA/LUPWAIT sign al , whic h is capt ured

at the falling edge of LCLK.

Figure 9. Local Bus Signals

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LFCLE/LFALE/LFRE/

LFWP/LLWE

tLBKLOV2

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal:

LAD[0:31]

tLBIVKH1

tLBIXKL2

tLBIVKL2

tLBKLOX1

tLBKLOZ2

tLBOTOT

tLBKLOX2

tLBKLOV1

tLBKLOV3

LBKLOZ1

tLBKLOV4

LUPWAIT

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 35

Figure 10. Local Bus Signals, GPCM/UPM/FCM Signals for LCRR[CLKDIV] = 2 (Clock Ratio of 4)

tLBIVKH1

tLBIXKL2

UPM Mode Input Signal:

LUPWAIT

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Mode Output Signals:

LCS[0:7]/LWE

tLBKLOV1

tLBKLOZ1

LCLK

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA

tLBIVKL2

GPCM/FCM

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor36

Figure 11. Local Bus Signals, GPCM/UPM/FCM Signals for LCRR[CLKDIV] = 4 or 8 (Clock Ratio of 8 or 16)

2.8 Display Interface Unit

This section describes the DIU DC and AC electrical specifications.

2.8.1 DIU DC Electrical Characteristics

Table 27 prov ides the DI U DC electrical character istics.

Table 27. DIU DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL – 0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD) IIN —±5 μA

High-level output voltage (OVDD = mn, IOH = –100 μA) VOH OVDD – 0.2 — V

tLBIXKL2

tLBIVKH1

UPM Mode Input Signal:

LUPWAIT

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Mode Output Signals:

LCS[0:7]/LWE

Input Signals:

LAD[0:31]/LDP[0:3]

LCLK

tLBKLOV1

tLBKLOZ1

tLBKLOX1

tLBIXKH1

GPCM Mode Input Signal:

LGTA

tLBIVKL2

GPCM/FCM

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 37

2.8.2 DIU AC Timing Specifications

Figure 12 depic ts the horizontal timing (timi ng of one line), including both the horizont al sync pulse and the data . All

parameters shown in the diagram are progr am mable. This timin g diagram corres ponds to positive polarity of the

DIU_CLK_OUT si gnal and acti ve-high polarity of the DIU_HSYNC, DIU_VSYNC, and DIU_DE signals. By defa ult, all

control signals and the display data are generat ed at the rising edge of the inter nal pixel clock, and the DIU_CLK_OUT out put

to drive the panel has the same polarity with the internal pixe l clock. User can select the polarity of the DIU_HSYNC and

DIU_VSYNC signa l (via the SYN_POL register) , whether act ive-hig h or act ive-lo w, the default is acti ve-high. The DIU_DE

signal is always active-high.

Figure 12. TFT DIU/LCD Interface Timing Diagram—Horizontal Sync Pulse

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 2 and Ta bl e 3 .

Table 27. DIU DC Electrical Characteristics (continued)

Parameter Symbol Min Max Unit

123 DELTA_X

tPWH tBPH tSW tFPH

DIU_CLK_OUT

DIU_LD

DIU_HSYNC

DIU_DE

tPCP

Invalid Data Invalid Data

Start of Line

tHSP

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor38

Figure 13 depi cts the vertic al ti mi ng (timing of one frame), including both the vertical sync pulse and the data. All paramet ers

shown in the diagram are progra mmable.

Figure 13. TFT DIU/LCD Interface Timing Diagram—Vertical Sync Pulse

Table 28 shows timing parameters of signals presented in Figure 12 an d Figure 13.

Table 28. DIU Interface AC Timing Parameters—Pixel Level

Parameter Symbol Value Unit Notes

Display pixel clock period tPCP 7.5 (minimum) ns 1, 2

1Display interface pixel clock period immediate value (in nanoseconds).

2Display pixel clock frequency must also be less than or equal to 1/3 the platform clock.

HSYNC width tPWH PW_H ×tPCP ns

HSYNC back porch width tBPH BP_H ×tPCP ns

HSYNC front porch width tFPH FP_H ×tPCP ns

Screen width tSW DELTA_X ×tPCP ns

HSYNC (line) period tHSP (PW_H + BP_H + DELTA_X + FP_H) ×tPCP ns

VSYNC width tPWV PW_V ×tHSP ns

HSYNC back porch width tBPV BP_V ×tHSP ns

HSYNC front porch width tFPV FP_V ×tHSP ns

Screen height tSH DELTA_Y ×tHSP ns

VSYNC (frame) period tVSP (PW_V + BP_V + DELTA_Y + FP_H) ×tHSP ns

Notes:

123DELTA_Y

Tpwv Tbpv Tsh Tfpv

DIU_HSYNC

DIU_LD

DIU_VSYNC

DIU_DE

Thsp

(Line Data)

Start of Frame

Invalid Data

Tvsp

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 39

The DELTA_X and DELTA_Y parameters are progra mmed via the DISP_SIZE register. The PW_H, BP_H, and FP _H

parameters are programmed via the HSYN_PA RA register; and the PW_V, BP_V, and FP_V parameters are progra mmed via

the VSYN_PARA register.

Figure 14 depic ts the synchron ous displa y interface timin g f or acces s level, and Table 29 list s th e ti m i n g par am eter s .

Figure 14. LCD Interface Timing Diagram—Access Level

NOTE

The DIU_OUT_CLK e dge an d p hase de la y is selec tabl e via t he Glob al Uti li ties C KDVDR

2.9 I2C

This sectio n descr ibes the DC and AC electri cal cha r acteristics for th e I2C in terfaces of the MPC8610.

2.9.1 I2C DC Electrical Characteristics

Table 30 provides the DC electrical characteristics for the I2C inter faces .

Table 29. LCD Interface Timing Parameters—Access Level

Parameter Symbol Min Typ Max Unit

LCD interface pixel clock high time tCKH 0.35 ×tPCP 0.5 ×tPCP 0.65 ×tPCP ns

LCD interface pixel clock low time tCKL 0.35 ×tPCP 0.5 ×tPCP 0.65 ×tPCP ns

LCD interface pixel clock to ouput valid tDIUKHOV —— 2ns

LCD interface output hold from pixel clock tDIUKHOX tPCP – 2 — — ns

Table 30. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter Symbol Min Max Unit Notes

Input high voltage level VIH 0.7 × OVDD OVDD +0.3 V

Input low voltage level VIL –0.3 0.3 × OVDD V

Low level output voltage VOL 00.2 × OVDD V1

Pulse width of spikes which must be suppressed by the

input filter

tI2KHKL 050ns2

tCKH

DIU_HSYNC

DIU_VSYNC

DIU_DE

DIU_CLK_OUT

tDIUKHOV

tCKL

DIU_LD

tDIUKHOX

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor40

2.9.2 I2C AC Electrical Specifications

Table 31 provides the AC timing parameters for the I2C interfaces.

Input current each I/O pin (input voltage is between

0.1 ×OVDD and 0.9 × OVDD(max)

II–10 10 μA3

Capacitance for each I/O pin CI—10pF

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the

MPC8610

Integrated Host Processor Reference Manual

, for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

Table 31. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Ta b le 3 0 ).

Parameter Symbol1Min Max Unit

SCL clock frequency fI2C 0400kHz

Low period of the SCL clock tI2CL41.3 — μs

High period of the SCL clock tI2CH40.6 — μs

Setup time for a repeated START condition tI2SVKH40.6 — μs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

tI2SXKL40.6 — μs

Data setup time tI2DVKH4100 — ns

Data input hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

μs

Data ouput delay time tI2OVKL —0.9

3μs

Setup time for STOP condition tI2PVKH 0.6 — μs

Bus free time between a STOP and START condition tI2KHDX 1.3 — μs

Noise margin at the LOW level for each connected device (including

hysteresis)

VNL 0.1 × OVDD —V

Noise margin at the HIGH level for each connected device (including

hysteresis)

VNH 0.2 × OVDD —V

Table 30. I2C DC Electrical Characteristics (continued)

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter Symbol Min Max Unit Notes

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 41

Figure 15 pr ov id es th e AC test load f or th e I2C.

Figure 15. I2C AC Test Load

Figure 16 shows the AC timi ng diagram for the I2C bus.

Figure 16. I2C Bus AC Timing Diagram

Capacitive load for each bus line Cb — 400 pF

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8610 provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

When MPC8610 acts as the I2C bus master while transmitting, MPC8610 drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, MPC8610 would not cause unintended generation of Start or Stop condition. Therefore, the

300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required

for MPC8610 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both

the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock

frequency is 400 kHz and the digital filter sampling rate register (I2CDFSRR) is programmed with its default setting of 0x10

(decimal 16):

I2C source clock frequency 533 MHz 400 MHz 333 MHz 266 MHz

FDR bit setting 0x0A 0x07 0x2A 0x05

Actual FDR divider selected 1536 1024 896 704

Actual I2C SCL frequency generated 347 kHz 391 kHz 371 kHz 378 kHz

For the detail of I2C frequency calculation, refer to Freescale application note AN2919,

Determining the I2C Frequency

Divider Ratio for SCL

. Note that the I2C source clock frequency is equal to the MPX clock frequency for MPC8610.

3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. Guaranteed by design.

Table 31. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Ta b le 3 0 ).

Parameter Symbol1Min Max Unit

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

SrS

SDA

SCL

tI2CF

tI2SXKL

tI2CL

tI2CH

tI2DXKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2CR

tI2CF

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor42

2.10 DUART

This section describes the DC and AC electrical spec ifications for the DUART interfa ce of the MPC861 0.

2.10.1 DUART DC Electrical Characteristics

Table 32 provides the DC electrical characteristics for the DUART interface.

2.10.2 DUART AC Electrical Specifications

Table 33 provides the AC timing paramete rs for the DUART interface.

2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI)

The fast/serial infrared interfaces (FIRI/ SIRI) implement s asynchron ous infra red protoc ols (FIR, MIR, SIR) that are def ined by

IrD A (Infra red Data Association). Refer to http://www.IrDA.org for de tails on FIR and SIR protocols.

2.12 Synchronous Serial Interface (SSI)

This section describes th e DC and AC electrical specifications for the SSI interfa ce of the MPC8610.

2.12.1 SSI DC Electrical Characteristics

Table 34 pro vi d es SSI D C el ec tr i c a l ch a r ac terist ic s .

Table 32. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL – 0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD)I

IN —±5 μA

High-level output voltage (OVDD = mn, IOH = –100 μA) VOH OVDD – 0.2 — V

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 2 and Ta bl e 3 .

Table 33. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate Platform clock/1,048,576 baud 1

Maximum baud rate Platform clock/16 baud 1, 2

Oversample rate 16 — 1, 3

Notes:

1. Guaranteed by design.

2. Actual attainable baud rate will be limited by the latency of interrupt processing.

3. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16th sample.

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 43

2.12.2 SSI AC Timing Specifications

All timings for the SSI are given for a noninverted serial clock polarity (TSCKP/RSCKP = 0) and a noninverted frame sync

(TFS I/RFSI = 0). If t he p olarit y of t he clo ck and/ or the fr ame sync have b een inv erted, all the timi ng remains vali d by i nverti ng

the cl ock signal STCK/SRCK and/or the frame sy nc STFS/S RF S shown in the following tables and figures.

For in ternal fr ame sync operation using external cloc k, the FS timing wil l be sam e as that of Tx Data.

2.12.2.1 SSI Transmitter Timing with Internal Clock

Table 35 prov ides th e tr ansmitt er timing par ameters wi th inte r n al clo ck.

Table 34. SSI DC Electrical Characteristics (3.3 V DC)

Parameter Symbol Min Max Unit

High-level input voltage VIH 2BV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (BVIN1 = 0 V or BVIN = BVDD)I

IN —±5 μA

High-level output voltage (BVDD = min, IOH = –2 mA) VOH BVDD – 0.2 — V

Low-level output voltage (BVDD = min, IOL = 2 mA) VOL —0.2V

Note:

1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3.

Table 35. SSI Transmitter with Internal Clock Timing Parameters

Parameter Symbol Min Max Unit

Internal Clock Operation

(Tx/Rx) CK clock period SS1 81.4 — ns

(Tx/Rx) CK clock high period SS2 36.0 — ns

(Tx/Rx) CK clock rise time SS3 — 6 ns

(Tx/Rx) CK clock low period SS4 36.0 — ns

(Tx/Rx) CK clock fall time SS5 — 6 ns

(Tx) CK high to FS high SS10 — 15.0 ns

(Tx) CK high to FS low SS12 — 15.0 ns

(Tx/Rx) internal FS rise time SS14 — 6 ns

(Tx/Rx) internal FS fall time SS15 — 6 ns

(Tx) CK high to STXD valid from high impedance SS16 — 15.0 ns

(Tx) CK high to STXD high/low SS17 — 15.0 ns

(Tx) CK high to STXD high impedance SS18 — 15.0 ns

STXD rise/fall time SS19 — 6 ns

Synchronous Internal Clock Operation

SRXD setup before (Tx) CK falling SS42 10.0 — ns

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor44

Figure 17 provides the SSI transmitter timing with internal clock.

Figure 17. SSI Transmitter with Internal Clock Timing Diagram

SRXD hold after (Tx) CK falling SS43 0 — ns

Loading SS52 — 25 pF

Table 35. SSI Transmitter with Internal Clock Timing Parameters (continued)

Parameter Symbol Min Max Unit

SS19

SSIn_TCK

SSIn_TFS

SS1

SSIn_TXD

SSIn_RXD

SS2 SS4

SS3SS5

SS10 SS12

SS14

SS18

SS15

SS17

SS16

SS43

SS42

Note: SRXD input in synchronous mode only.

(Output)

(Input)

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 45

2.12.2.2 SSI Receiver Timing with Internal Clock

Table 36 provides the recei ver timing parameters wit h internal clock.

Figure 18 pro vides the S SI receiv er timing with inte r n al clock.

Figure 18. SSI Receiver with Internal Clock Timing Diagram

2.12.2.3 SSI Transmitter Timing with External Clock

Table 37 prov ides the tr ansmitt er timing parameters wi th exter nal clock.

Table 36. SSI Receiver with Internal Clock Timing Parameters

Parameter Symbol Min Max Unit

Internal Clock Operation

(Tx/Rx) CK clock period SS1 81.4 — ns

(Tx/Rx) CK clock high period SS2 36.0 — ns

(Tx/Rx) CK clock rise time SS3 — 6 ns

(Tx/Rx) CK clock low period SS4 36.0 — ns

(Tx/Rx) CK clock fall time SS5 — 6 ns

(Rx) CK high to FS high SS11 — 15.0 ns

(Rx) CK high to FS low SS13 — 15.0 ns

SRXD setup time before (Rx) CK low SS20 10.0 — ns

SRXD hold time after (Rx) CK low SS21 0 — ns

Table 37. SSI Transmitter with External Clock Timing Parameters

Parameter Symbol Min Max Unit

External Clock Operation

(Tx/Rx) CK clock period SS22 81.4 — ns

(Tx/Rx) CK clock high period SS23 36.0 — ns

(Tx/Rx) CK clock rise time SS24 — 6.0 ns

SSIn_TCK

SSIn_RFS

SSIn_RXD

SS1

SS4SS2

SS20

SS21

SS11 SS13

(Output)

(Input)

SS3

SS5

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor46

Figure 19 provides the SSI transmitter timing with external clock.

Figure 19. SSI Transmitter with External Clock Timing Diagram

(Tx/Rx) CK clock low period SS25 36.0 — ns

(Tx/Rx) CK clock fall time SS26 — 6.0 ns

(Tx) CK high to FS high SS31 –10.0 15.0 ns

(Tx) CK high to FS low SS33 10.0 — ns

(Tx) CK high to STXD valid from high impedance SS37 — 15.0 ns

(Tx) CK high to STXD high/low SS38 — 15.0 ns

(Tx) CK high to STXD high impedance SS39 — 15.0 ns

Synchronous External Clock Operation

SRXD setup before (Tx) CK falling SS44 10.0 — ns

SRXD hold after (Tx) CK falling SS45 2.0 — ns

SRXD rise/fall time SS46 — 6.0 ns

Table 37. SSI Transmitter with External Clock Timing Parameters (continued)

Parameter Symbol Min Max Unit

SS45

SS33

SS24

SS26

SS25

SS23

SSIn_TCK

SSIn_TFS

SSIn_TXD

SSIn_RXD

Note: SRXD input in synchronous mode only

SS31

SS22

SS44

SS39

SS38

SS37

SS46

(Input)

(Output)

(Input)

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 47

2.12.2.4 SSI Receiver Timing with External Clock

Table 38 provides the recei ver timing param eters wit h external clock.

Figure 20 pro vides the SSI receiver timing with external clock.

Figure 20. SSI Receiver with External Clock Timing Diagram

Table 38. SSI Receiver with External Clock Timing Parameters

Parameter Symbol Min Max Unit

External Clock Operation

(Tx/Rx) CK clock period SS22 81.4 — ns

(Tx/Rx) CK clock high period SS23 36.0 — ns

(Tx/Rx) CK clock rise time SS24 — 6.0 ns

(Tx/Rx) CK clock low period SS25 36.0 — ns

(Tx/Rx) CK clock fall time SS26 — 6.0 ns

(Rx) CK high to FS high SS32 –10.0 15.0 ns

(Rx) CK high to FS low SS34 10.0 — ns

(Tx/Rx) external FS rise time SS35 — 6.0 ns

(Tx/Rx) external FS fall time SS36 — 6.0 ns

SRXD setup time before (Rx) CK low SS40 10.0 — ns

SRXD hold time after (Rx) CK low SS41 2.0 — ns

SS24

SS34

SS35

SS26

SS25

SS23

SSIn_TCK

SSIn_RFS

SSIn_RXD

SS40

SS22

SS32

SS36

SS41

(Input)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor48

2.13 Global Timer Module

This section descr ibes the DC and AC electrical spec ifications for the gl obal timer module (GTM) of the MPC8610.

2.13.1 GTM DC Electrical Characteristics

Table 39 provides the DC elect r ical characteristi cs for the MPC8610 global timer m odule pins, includi ng GTMn_TINn,

GTMn_TOUTn, GTMn_TGATEn, and RTC.

2.13.2 GTM AC Timing Specifications

Table 40 provides the GTM input and output AC timing specifi ca tions.

Figure 21 prov id es th e AC test load f or th e GT M.

Figure 21. GTM AC Test Load

Table 39. GTM DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD)I

IN —±5 μA

High-level output voltage (OVDD = min, IOH = –100 μA) VOH OVDD – 0.2 — V

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 2 and Ta bl e 3 .

Table 40. GTM Input and Output AC Timing Specification1

Characteristic Symbol2Min Unit Notes

GTM inputs—minimum pulse width tGTIWID 7.5 ns 3

GTM outputs—minimum pulse width tGTOWID 12 ns

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external

synchronous logic. Timer inputs are required to be valid for at least tGTIWID ns to ensure proper operation.

3. The minimum pulse width is a function of the MPX/platform clock. The minimum pulse width must be greater than or equal

to 4 times the MPX/platform clock period.

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 49

2.14 GPIO

This sec tion describes the DC and AC elec tr ical specif ications for the GPIO of th e MP C8610.

2.14.1 GPIO DC Electrical Characteristics

Table 41 provides the DC electrical characteristics for the GPIO.

2.14.2 GPIO AC Timing Specifications

Table 42 provides the GPIO input and output AC tim ing specif ications.

Figure 22 prov id es th e AC test load f or th e GP I O .

Figure 22. GPIO AC Test Load

Table 41. GPIO DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD)I

IN —±5 μA

High-level output voltage (OVDD = min, IOH = –100 μA) VOH OVDD – 0.2 — V

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3.

Table 42. GPIO Input and Output AC Timing Specifications1

Characteristic Symbol2Min Unit Notes

GPIO inputs—minimum pulse width tGPIWID 7.5 ns 3

GPIO outputs—minimum pulse width tGPOWID 12 ns

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.

3. The minimum pulse width is a function of the MPX/platform clock. The minimum pulse width must be greater than or equal

to 4 times the MPX/platform clock period.

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor50

2.15 Serial Peripheral Interface (SPI)

This section describes th e DC and AC electrical specifications for the SPI interfa ce of the MPC8610.

2.15.1 SPI DC Electrical Characteristics

Table 43 provides the SPI DC el ectrical charact er ist ics.

2.15.2 SPI AC Timing Specifications

Table 44 provides the SPI input and output AC timing speci f ications.

Table 43. SPI DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL – 0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD)I

IN —±5 μA

High-level output voltage (OVDD = mn, IOH = –100 μA) VOH OVDD – 0.2 — V

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 2 and Ta bl e 3 .

Table 44. SPI AC Timing Specifications1

Characteristic Symbol2Min Max Unit

SPI outputs valid—master mode (internal clock) delay tNIKHOV 1ns

SPI outputs hold—master mode (internal clock) delay tNIKHOX -0.2 ns

SPI outputs valid—slave mode (external clock) delay tNEKHOV 8ns

SPI outputs hold—slave mode (external clock) delay tNEKHOX 2ns

SPI inputs—master mode (internal clock input setup time tNIIVKH 4ns

SPI inputs—master mode (internal clock input hold time tNIIXKH 0ns

SPI inputs—slave mode (external clock) input setup time tNEIVKH 4ns

SPI inputs—slave mode (external clock) input hold time tNEIXKH 2ns

Notes:

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.

Timings are measured at the pin.

2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 51

Figure 23 pr ov id es th e AC test load f or th e SP I.

Figure 23. SPI AC Test Load

Figure 24 through Figure 25 represent the AC timings from Table 44. Note tha t alth ough th e specifi cati ons genera lly reference

the ris ing edge of the clock, these AC timing dia grams also apply when the falling edge is the active edge.

Figure 24 shows the SPI timings in slave mode (e xternal clock).

Figure 24. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 25 shows the SPI timin gs in master mode (inter nal clock).

Figure 25. SPI AC Timing in Master Mode (Internal Clock) Diagram

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

SPICLK (output)

tNEIXKH

tNEKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

tNEIVKH

tNEKHOX

Note: The clock edge is selectable on SPI.

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

tNIIVKH

tNIKHOX

Note: The clock edge is selectable on SPI.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor52

2.16 PCI Interface

This sectio n descr ibes the DC and AC elec tr ical specifications fo r th e PCI bus interface .

2.16.1 PCI DC Electrical Characteristics

Table 45 provides the DC electrical characteristics for the PCI interface.

2.16.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus. Not e that the SYSCLK signal is used as the PCI input

clock. Table 46 provides the PCI AC timing s pecif ications at 66 MHz.

Table 45. PCI DC Electrical Characteristics1

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (VIN 2 = 0 V or VIN = VDD)I

IN —±5 μA

High-level output voltage (OVDD = min, IOH = –100 μA) VOH OVDD – 0.2 — V

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Notes:

1. Ranges listed do not meet the full range of the DC specifications of the

PCI 2.2 Local Bus Specifications

2. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 2 and Ta bl e 3 .

Table 46. PCI AC Timing Specifications at 66 MHz

Parameter Symbol1Min Max Unit Notes

SYSCLK to output valid tPCKHOV 1.5 7.4 ns 2, 3, 12

SYSCLK to output high impedance tPCKHOZ — 14 ns 2, 4, 11

Input setup to SYSCLK tPCIVKH 3.7 — ns 2, 5, 10,

Input hold from SYSCLK tPCIXKH 0.8 — ns 2, 5, 10,

REQ64 to HRESET 9 setup time tPCRVRH 10 × tSYS — clocks 6, 7, 11

HRESET to REQ64 hold time tPCRHRX 050ns7, 11

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 53

Figure 15 provides the AC test load for PCI.

Figure 26. PCI AC Test Load

Figure 27 shows the PCI input AC ti mi ng conditions.

Figure 27. PCI Input AC Timing Measurement Conditions

HRESET high to first FRAME assertion tPCRHFV 10 — clocks 8, 11

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K)

going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R)

went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the

PCI 2.2 Local Bus Specifications

3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in question for

3.3-V PCI signaling levels.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The

system clock period must be kept within the minimum and maximum defined ranges. For values see Section 3.1, “System

Clocking.”

7. The setup and hold time is with respect to the rising edge of HRESET.

8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the

PCI 2.2 Local Bus

Specifications

9. The reset assertion timing requirement for HRESET is 100 μs.

10.Guaranteed by characterization.

11.Guaranteed by design.

12. The timing parameter tPCKHOV is a minimum of 1.5 ns and a maximum of 7.4 ns rather than the minimum of 2 ns and a

maximum of 6 ns in the

PCI 2.2 Local Bus Specifications

13. The timing parameter tPCIVKH is a minimum of 3.7 ns rather than the minimum of 3 ns in the

PCI 2.2 Local Bus Specifications

14. The timing parameter tPCIXKH is a minimum of 0.8 ns rather than the minimum of 0 ns in the

PCI 2.2 Local Bus Specifications

Table 46. PCI AC Timing Specifications at 66 MHz (continued)

Parameter Symbol1Min Max Unit Notes

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

tPCIVKH

CLK

Input

tPCIXKH

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor54

Figure 28 shows the PCI output AC timi ng condit ions.

Figure 28. PCI Output AC Timing Measurement Condition

2.17 High-Speed Serial Interfaces (HSSI)

The MP C 8 6 10 fe at u r es tw o S erial izer / D eseri al iz er (Ser D es) in t er f a ce s to be us ed for hi g h-speed s erial in ter co n ne ct

applications. The SerDes1 interface is dedi cated for PCI Express (x 1/x2/x4) data transfers. The SerDes2 interface is dedi cated

for PCI Expre ss (x1/x2/x4/x8) data trans fers .

This section descr ibes the common portion of SerDes DC elec trical spec ifications, which is the DC requirement for SerDes

refe renc e cl ocks. The SerDes data lane ’s transmitter and receive r refe rence circuit s are also shown.

2.17.1 Signal Terms Definition

The SerDes u tilizes di ffere ntial signali ng to transfer dat a across t he serial l ink. T his secti on defines t erms used in the de scription

and s pecification of differential signals.

Figure 29 s hows how the signals are defined. F or illustration purpose, only one SerDes la ne is us ed fo r description. The figure

shows wave form for eithe r a tran smitter output (SDn_TX and SDn_TX) or a receive r input (SDn_RX and SDn_RX). Each

signal swings between A volts and B volts where A > B.

Using this waveform, the definitions are as follows. To simpl if y illustration, the f ollowing definiti ons ass ume that the SerDes

tr ansmitter and recei ver operate in a fully sy mmet rical differentia l si gnaling environment.

1. Single- ended swing

The transmitter output signals and the rec eiver input signals SDn_TX, SDn_TX, SDn_RX, and SDn_RX each have a

peak-to- peak swing of A – B volts. This is also referred as each signal wire’s single-ende d swing.

2. Differential output voltage, VOD (or diffe r enti al output swing):

The dif ferenti al ou tput vo ltage (or swing ) of the tran smitte r , VOD, is defined as the difference of the two complimentary

outp ut voltages : VSDn_TX – VSDn_TX. The VOD value ca n be ei ther positive or negative.

3. Differential input voltage, VID (or diffe rential input s wing):

The diffe rential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentar y

input voltages: V SDn_RX –V

SDn_RX. Th e VID value can be either positive or negative.

4. Differential peak voltage, VDIFFp

The peak value of the differential tran s mitt er output signal or the differential receiver input signal is defi ned as

differential peak voltage, VDIFFp = |A – B| volts.

5. Differential peak-to-peak, VDIFFp-p

Since the differential output s ignal of the tra ns mi tter and the differential input signal of the re ce iver each range from

A – B to -(A – B) vol ts, t h e peak-to-pea k value of th e differ ential tr ans mitt er output signal or the differential receiver

input si gnal is define d as dif fer entia l peak-to-pe ak vol tage, V DIFFp-p = 2 * VDIFFp = 2 * |( A – B)| volt s, whic h is twic e

CLK

Output Delay

tPCKHOV

High-Impedance

tPCKHOZ

Output

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 55

of dif ferential swing in amplit ude, or twice of the dif f erential peak. For example, the out put differential pea k-peak

voltage can also be calculat ed as VTX-DIFFp-p = 2 * | VOD|.

6. Differential waveform

The differ ential wavefor m is constructed by subtracting the inverting signa l (S Dn_TX, for example) from the

noninverting s ignal (SDn_T X , f o r example) with in a d ifferen tial pair. There is only one signal trace curve in a

differential wave form. The voltage represen ted in the differential waveform is not reference d to ground. Refer to

Figure 38 as an examp le for differential waveform.

7. Common mode vol tage, Vcm

The common mode voltage is equal to one half of the sum of the voltages between each conduc tor of a balanced

interc hange circuit and ground. In this e xample, for Ser Des output, Vcm_out = (VSDn_TX + VSDn_TX)/2 = (A + B)/ 2 ,

which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the

common mode voltage may often differ from one component’s output to the ot her’s input. S ometimes , it may be even

dif feren t betwee n the re ceiver input and dri ver output circuit s withi n the same c omponen t. It’s also referr ed as the DC

of fset in some occasi on.

Figure 29. Differential Voltage Definitions for Transmitter or Receiver

To illus trat e these de finiti ons us ing real v alues, consi der the cas e of a CML (curre nt mod e logic ) t ransmit te r that has a common

mode volta ge of 2.25 V and each of its outputs, TD and TD, has a swi ng that goes between 2.5 and 2.0 V. Usin g these valu es,

the peak-to-peak voltage swing of ea ch signal (TD or TD) is 500 mV p-p, which is referred as the single-ende d swing for eac h

signal. In this example, since the differential signaling environment is fully symmetrical, the transmitte r output’s differential

swing (VOD) has t he same amplitude as each sig nal’ s si ngle-ended swing. The di fferenti al output signal ranges bet ween 500 mV

and –500 mV, in other wor ds, VOD is 500 m V in one pha se and –500 mV in the other phase. The peak dif f erential vol tage

(VDIFFp) is 500 mV. The peak-to-peak diffe rential voltage (VDIFFp-p) is 1000 mV p-p.

2.17.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the cloc k used by the correspond ing

SerDes lanes. The SerDes reference cloc ks inputs are SDn_REF_CLK and S D n_REF_CLK for PCI Express.

The fol lowing sections describe the SerDes re fere nce clock requirements and some appl ication information.

2.17.2.1 SerDes Reference Clock Receiver Characteristics

Figure 30 shows a receiver reference diagra m of the SerDes refere nce clocks.

• The supply volt age requireme nts for XnVDD ar e speci fi e d in Table 2 an d Table 3.

Differential Swing, VID or VOD = A – B

A Volts

B Volts

_TX or

_RX

_TX or

_RX

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak-Peak Voltage, V

DIFFpp

= 2*V

DIFFp

(not shown)

Vcm = (A + B) / 2

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor56

• SerDes reference clock receiver refer enc e circuit structure

—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differen tial inputs as sh own in Figure 30.

Each differential clock input (SDn_ REF_ C LK o r SD n_REF_CLK) ha s a 50-Ω termina tion t o SGND fol lowed b y

on-chip AC-coupling.

— T he e xternal reference cloc k driver must be able to drive this termination.

— The SerDes re ference clock input can be either differential or single-ended. Refer to the differential mode and

sin gle-ended mode de scription below for further detai led requirements.

• The maxi mu m average current requirement that als o determines the c ommon mode voltage ra nge

— When the Ser Des reference clock dif ferential inpu ts are DC coupled externally wit h the c lock drive r chip, the

max imum average curre nt all owed f or eac h input pi n i s 8 mA. In thi s ca se, the e xact com mon mode i nput voltag e

is not critical as long as it is within the range allowed by the max im um average current of 8 mA (refer to the

following bul let for more det ail), si nce the input is AC-coupl ed on-chip.

— T his curr ent limit ation set s the maximum commo n mode input volt age to be less than 0.4 V (0.4 V/50 = 8 mA)

while the min imum comm on mode input le vel is 0.1 V above SGND. For e xample, a cl ock with a 50/50 d uty cycle

can be pr oduced by a clock driver with out put driven by its curre nt source from 0 to 16 mA (0–0.8 V), such that

eac h phas e of t he dif fe rent ial i nput ha s a singl e-ende d swing from 0 V to 800 mV with th e c ommon mo de volt age

at 400 mV.

— If the devic e driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SGND DC, or it

exce eds the maximum input curre nt limita tions, then it must be AC-coupled off-chip.

• The input ampl itude requirement

— T his requirement is describ ed in detail in the following sections.

Figure 30. Receiver of SerDes Reference Clocks

2.17.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC 8610 S erDes reference cloc k inputs is differ ent depending on the signaling mode used

to connect the clock driver c hip and SerDes reference clock inputs as described below.

• D if fer ential m o d e

— T he input a mpl itude of the diffe r ential cloc k must be between 400 and 1600 mV differential peak-peak (or

between 200 and 800 mV differential peak). In other words, each si gnal wire of the differential pair must have a

sin gle-ended swing less tha n 800 mV and greater t han 200 mV. This re quirement i s the same for both exte rnal DC-

or AC-coupled connection.

— For external DC-coupled connection, as des crib ed in Section 2.17.2.1, “SerDes Reference Clock Receiver

Characteristics,” the maximum average current requirements sets the requirement for average voltage (common

mode voltage ) to be bet ween 100 a nd 400 mV. Figure 31 sho ws th e SerDes referen ce clock i nput requi rement for

DC-coupled connection scheme.

Input

Amp

50 Ω

_REF_CLK

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 57

— For external AC-coupled connec tion, there is no common mode voltage requirement for the cl ock drive r. Si nce

the ex ternal AC-cou pling cap acit or bloc ks the DC level , the cl ock driver and the SerDes refere nce clock recei ver

operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has

its common mode voltage set to S GND. Each signal wire of the differential inputs is all owed to swing below and

above the command mode voltage (S GND). Figure 32 shows the SerDes reference clock input requirem ent for

AC-coupled connection scheme.

• Si ngle-ended mode

— The referenc e clock can also be single -ended. The SDn_REF_CLK input ampl itude (sing le-ended swing) must be

betwe en 400 and 80 0 mV peak-peak (fr om Vmin to Vmax) with SDn_REF_CLK ei the r lef t unconn ec ted or tie d to

ground.

—The SDn_REF_CLK input average voltage must be between 200 and 400 m V. Figure 33 sho ws the SerDes

reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude require ment, the refe rence clock inputs might nee d to be DC- or AC-coupled

exte rnally . Fo r the best noise performance, the ref erence of the clock could be DC- or AC-coupled in to the unused

phase (SD n_REF_CLK) through the same source impedance as the clock input (SDn_REF_C LK) in use.

Figure 31. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 32. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 33. Single-Ended Reference Clock Input DC Requirements

_REF_CLK

Vmax < 800 mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

_REF_CLK

Vcm

200mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

_REF_CLK

400 mV < SD

_REF_CLK Input Amplitude < 800 mV

0 V

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor58

2.17.2.3 Interfacing With Other Differential Signaling Levels

• With on-chip termination to SGND, the differenti al reference cl ocks inputs are HCSL (high-spee d current stee ring

logic) compatible DC-coupled.

• Many other low voltage dif f ere ntial type out puts like LVDS (low vol tage differential signal ing) can be used but may

need to be AC-coupled due to the limited com mo n mode input range allowed (100 to 400 mV) for DC-coupled

connection.

• LVPECL outputs can produce signa l with too large amplitude and may ne ed to be DC-bias ed at cloc k driver output

first, then followed with series attenua tion resistor to reduce the a mpl itude, in addition to AC-coupl ing.

NOTE

Figure 34 to Figure 37 are for conceptua l reference only. Due to the fact that cloc k dr ive r

chip's inte rnal struc ture, output impedance and termina tion requirements are dif ferent

between various clock driver c hip manufacture rs, it is very possible that the clock c ircuit

reference designs provided by clock driver chip ve ndor are different from what is shown

below. They mig ht also vary from one ve ndor to the other. Ther efore, Freescale

Semiconductor c an neither provide the optimal clock driver reference circuits nor

guarantee the correc tness of the following clock driver connection referen ce circ uits. The

system designer is recommended to contact the selected clock driver chip vendor for the

optim al re ferenc e circuit s with the MPC8610 SerDes r eference clock r eceiver re qui rement

pr ovided in this document.

Figure 34 shows the SerDes reference cloc k connection referen ce circuit s for HCSL type cloc k driver. It assumes that the DC

leve ls of the cloc k driver chip is compatible with MPC8610 SerDes reference cl ock input ’s DC requirem ent.

Figure 34. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 35 shows the SerDes reference clock c onnection reference circuits for LVDS type clock driver. Since LVD S clock

dr iver’s common mode voltage is hig her than the MPC8610 SerDe s reference cl ock input ’s all owed range (100 to 400 mV),

AC- coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also

assume s that th e LVDS transmitter establishes its own common mode le vel witho u t r elying on the rece iver or other externa l

component.

50 Ω

_REF_CLK

Clock Driver 100 Ω Differential PWB Trace

Clock driver vendor dependent

source termination resistor

CLK_Out

HCSL CLK Driver Chip

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

MPC8610

CLK_Out

SerDes Refer.

CLK Receiver

Clock Driver

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 59

Figure 35. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 36 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL

dr iver’s DC levels (both common mode vol tages and output swing) are incompatible with MP C8610 SerDes refe rence cloc k

input’ s DC requirement, AC-coupling has to be used. Figure 36 assumes that the LVPECL cloc k driver’ s out put im pedance is

50 Ω. R1 is used to DC-bias t he LVPECL outputs prior to AC-cou pling. Its valu e could be ranged from 140 to 240 Ω depending

on cloc k driver ve ndor’ s req uirement . R2 is used togethe r with the SerDes refe rence cloc k receive r’s 50-Ω termin ation resistor

to attenuate the LVPECL out put’s diff erenti al peak level such that it meets the MPC8610 SerDe s reference clock’s differential

input amplitude require ment (between 200 and 800 mV diffe rential peak). For example, if the LVPECL output’s differential

peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67,

which requires R2 = 25 Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible

with a particular clock driver chip.

Figure 36. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

_REF_CLK

Clock Driver 100 Ω Differential PWB Trace

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8610

SerDes Refer.

CLK Receiver

50 Ω

Clock Driver

_REF_CLK

Clock Driver 100 Ω Differential PWB Trace SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK Driver Chip

MPC8610

10 nF

CLK_Out

Clock Driver

50 Ω

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor60

Figure 37 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC

leve ls of the cloc k driver are compa tible with MPC8610 S erDe s reference cl ock input’s DC requirement.

Figure 37. Single-Ended Connection (Reference Only)

2.17.2.4 AC Requirements for SerDes Reference Clocks

The clock driver se lected should provide a high quality reference clock with low phase nois e and cycle-to-cycle ji tter. Phase

nois e le ss t han 100 kHz can be tra cked by the PLL and dat a rec overy l oops a nd i s le ss of a pro blem. P hase no is e abo ve 15 MHz

is filtered by the PLL. The most problematic phase noise occurs in the 1–15 MHz range. The sourc e impedance of the clock

driver should be 50 Ω to match the transmission line and reduce reflec tions which are a source of noi se to the system.

Table 47 describes some AC parameters comm on to P CI Express protocols.

Table 47. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with X1VDD or X2VDD = 1.0 V ± 5% and 1.025 V ± 5%.

Parameter Symbol Min Max Unit Notes

Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3

Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3

Differential Input High Voltage VIH +200 mV 2

Differential Input Low Voltage VIL — –200 mV 2

_REF_CLK

100 Ω Differential PWB Trace

Clock Driver

CLK_Out

Single-Ended CLK

Driver Chip

MPC8610

33 Ω

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

SerDes Refer.

CLK Receiver

50 Ω

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 61

Figure 38. Differential Measurement Points for Rise and Fall Time

Figure 39. Single-Ended Measurement Points for Rise and Fall Time Matching

The ot her de tail ed AC requirements of the SerDes reference clocks is defined by each interface protocol based on app lication

usage. Refe r to the following sections for detailed informa tion:

•Section 2.18.2, “AC Require ments for PCI Express SerDes Clocks”

Rising edge rate (SD

_REF_CLK) to falling edge rate

(SD

_REF_CLK) matching

Rise-Fall

Matching

—20%1, 4

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 to +200 mV on the differential waveform (derived from SD

_REF_CLK minus SD

_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is

centered on the differential zero crossing. See Figure 38.

4. Matching applies to rising edge rate for SD

_REF_CLK and falling edge rate for SD

_REF_CLK. It is measured using a

200 mV window centered on the median cross point where SD

_REF_CLK rising meets SD

_REF_CLK falling. The median

cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge

rate of SD

_REF_CLK should be compared to the fall edge rate of SD

_REF_CLK, the maximum allowed difference should

not exceed 20% of the slowest edge rate. See Figure 39.

Table 47. SerDes Reference Clock Common AC Parameters (continued)

At recommended operating conditions with X1VDD or X2VDD = 1.0 V ± 5% and 1.025 V ± 5%.

Parameter Symbol Min Max Unit Notes

VIH = +200 mV

VIL = -200 mV

0.0 V

_REF_CLK

minus

_REF_CLK

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor62

2.17.3 SerDes Transmitter and Receiver Reference Circuits

Figure 40 shows the referenc e circuits for SerDes data lan e’s transm itter and receiver.

Figure 40. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDe s da ta lanes are de fined in each interfac e protocol section below (PCI Express) in this

document based on the application usage: ”

•Section 2.18, “PCI Express”

Note that ext ernal AC Coupling c apaci tor is require d for the above seri al transm ission pro tocols wi th th e capacitor va lue defined

in specification of each protocol section.

2.18 PCI Express

This section describes th e DC and AC elec trical specificatio ns for the PCI Express bus of the MPC8610.

2.18.1 DC Requirements for PCI Express SD

_REF_CLK and

_REF_CLK

For more informat ion, see Section 2.17.2, “SerDes Reference Clocks.”

2.18.2 AC Requirements for PCI Express SerDes Clocks

Table 48 lists AC requirements.

2.18.3 Clocking Dependencies

The ports on the two ends of a link must transmi t data at a rate tha t is within 600 parts per million (ppm) of each othe r at all

tim es . This is sp ecified to allow bit rate clock sources wit h a ±300 ppm tolerance.

Table 48. SD

_REF_CLK and SD

_REF_CLK AC Requirements

Symbol Parameter Description Min Typ Max Units

tREF REFCLK cycle time — 10 — ns

tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

——100ps

tREFPJ Phase jitter. Deviation in edge location with respect to mean

edge location

–50 — 50 ps

50 Ω

50 ΩReceiver

Transmitter

SD1_TX

SD2_TX

SD1_TX

SD2_TX

SD1_RX

SD2_RX

SD1_RX

SD2_RX

50 Ω

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 63

2.18.4 Physical Layer Specifications

The followi ng i s a summary o f th e specifi catio ns for the p hysic al la yer of PCI E xpres s on this devic e. For furt he r deta ils as well

as the s pecifications of the tr ans port and data link la yer, use the PCI Express Base Spe cification, Rev. 1.0a.

2.18.4.1 Differential Transmitter (TX) Output

Table 49 defi n es th e sp e ci f icat io n s for th e d iff e r en ti al ou t p ut at al l tr a n s mitt er s (TX s). Th e pa r am e t e rs ar e sp ecif i ed at the

com ponent pins.

Table 49. Differential Transmitter (TX) Output Specifications

Symbol Parameter Min Nom Max Units Comments

UI Unit interval 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for

spread spectrum clock dictated variations. See Note 1

VTX-DIFFp-p Differential

peak-to-peak

output voltage

0.8 1.2 V VTX-DIFFp-p = 2*|VTX-D+ –V

TX-D–| See Note 2

VTX-DE-RATIO De- emphasized

differential

output voltage

(ratio)

-3.0 -3.5 -4.0 dB Ratio of the VTX-DIFFp-p of the second and following

bits after a transition divided by the VTX-DIFFp-p of the

first bit after a transition. See Note 2

TTX-EYE Minimum TX eye

width

0.70 UI The maximum transmitter jitter can be derived as

TTX-MAX-JITTER = 1 – TTX-EYE= 0.3 UI.

See Notes 2 and 3

TTX-EYE-MEDIAN-to-

MAX-JITTER

Maximum time

between the jitter

median and

maximum

deviation from

the median.

0.15 UI Jitter is defined as the measurement variation of the

crossing points (VTX-DIFFp-p = 0 V) in relation to a

recovered TX UI. A recovered TX UI is calculated over

3500 consecutive unit intervals of sample data. Jitter

is measured using all edges of the 250 consecutive UI

in the center of the 3500 UI used for calculating the TX

UI. See Notes 2 and 3

TTX-RISE, TTX-FALL D+/D– TX output

rise/fall time

0.125 UI See Notes 2 and 5

VTX-CM-ACp RMS AC peak

common mode

output voltage

20 mV VTX-CM-ACp = RMS(|VTXD+ –V

TXD-|/2 – VTX-CM-DC)

VTX-CM-DC = DC(avg) of |VTX-D+ –V

TX-D-|/2

See Note 2

VTX-CM-DC-ACTIVE-

IDLE-DELTA

Absolute delta of

DC common

mode voltage

during LO and

electrical idle

0 100 mV |VTX-CM-DC (during LO) –V

TX-CM-Idle-DC (During Electrical

Idle)|<=100 mV

VTX-CM-DC = DC(avg) of |VTX-D+ –V

TX-D-|/2 [LO]

VTX-CM-Idle-DC = DC(avg) of |VTX-D+ –V

TX-D-|/2

[Electrical Idle]

See Note 2

VTX-CM-DC-LINE-DELTA Absolute delta of

DC common

mode between

D+ and D–

025mV|V

TX-CM-DC-D+ –V

TX-CM-DC-D–| <= 25 mV

VTX-CM-DC-D+ = DC(avg) of |VTX-D+|

VTX-CM-DC-D– = DC(avg) of |VTX-D–|

See Note 2

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor64

VTX-IDLE-DIFFp Electrical idle

differential peak

output voltage

020mVV

TX-IDLE-DIFFp = |VTX-IDLE-D+ –V

TX-IDLE-D-| <= 20 mV

See Note 2

VTX-RCV-DETECT The amount of

voltage change

allowed during

receiver

detection

600 mV The total amount of voltage change that a transmitter

can apply to sense whether a low impedance receiver

is present. See Note 6

VTX-DC-CM The TX DC

common mode

voltage

0 3.6 V The allowed DC common mode voltage under any

conditions. See Note 6

ITX-SHORT TX short circuit

current limit

90 mA The total current the transmitter can provide when

shorted to its ground

TTX-IDLE-MIN Minimum time

spent in

electrical idle

50 UI Minimum time a transmitter must be in electrical idle

utilized by the receiver to start looking for an electrical

idle exit after successfully receiving an electrical idle

ordered set

TTX-IDLE-SET-TO-IDLE Maximum time to

transition to a

valid electrical

idle after sending

an electrical idle

ordered set

20 UI After sending an electrical idle ordered set, the

transmitter must meet all electrical idle specifications

within this time. This is considered a debounce time

for the transmitter to meet electrical idle after

transitioning from LO.

TTX-IDLE-TO-DIFF-DATA Maximum time to

transition to valid

TX specifications

after leaving an

electrical idle

condition

20 UI Maximum time to meet all TX specifications when

transitioning from electrical idle to sending differential

data. This is considered a debounce time for the TX to

meet all TX specifications after leaving electrical idle

RLTX-DIFF Differential

return loss

12 dB Measured over 50 MHz to 1.25 GHz. See Note 4

RLTX-CM Common mode

return loss

6 dB Measured over 50 MHz to 1.25 GHz. See Note 4

ZTX-DIFF-DC DC differential

TX impedance

80 100 120 ΩTX DC differential mode low impedance

ZTX-DC Transmitter DC

impedance

40 ΩRequired TX D+ as well as D- DC Impedance during

all states

LTX-SKEW Lane-to-lane

output skew

500 +

2 UI

ps Static skew between any two transmitter lanes within

a single link

CTX AC coupling

capacitor

75 200 nF All transmitters shall be AC-coupled. The AC coupling

is required either within the media or within the

transmitting component itself.

Table 49. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 65

2.18.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 41 is specified using the passive compliance/test measurem ent load (see Figure 43) in place of

any real P CI Exp res s interconnect + RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter

median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a

tr ansition bit or a de-empha sized bit . The exact redu ced voltage level of the de-emphasized bit will always be re lative to the

trans it ion bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 35 00 consecu tive unit int ervals of sampl e data. The eye diagra m is created using a ll edges

of the 250 co nsecutive UI in the center of the 3500 UI used for cal culating the TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in the 3500

cons ecut ive UI inter val with a fit algorit hm using a minim izat ion merit func ti on (i.e. , least

squares and median deviation fits).

Tcrosslink Crosslink

random timeout

0 1 ms This random timeout helps resolve conflicts in

crosslink configuration by eventually resulting in only

one downstream and one upstream port. See Note 7

Notes:

1.) No test load is necessarily associated with this value.

2.) Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 43 and measured over

any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 41.)

3.) A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the

transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total

TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed

to the averaged time value.

4.) The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and

D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see Figure 43). Note that the series capacitors

CTX is optional for the return loss measurement.

5.) Measured between 20–80% at transmitter package pins into a test load as shown in Figure 43 for both VTX-D+ and VTX-D–.

6.) See Section 4.3.1.8 of the

PCI Express Base Specifications,

Rev. 1.0a.

7.) See Section 4.2.6.3 of the

PCI Express Base Specifications

, Rev. 1.0a.

Table 49. Differential Transmitter (TX) Output Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor66

Figure 41. Minimum Transmitter Timing and Voltage Output Compliance Specifications

2.18.4.3 Differential Receiver (RX) Input Specifications

Table 50 defines the specific ations for the differential input at all receivers (RXs). The parameters are specified at the

com ponent pins.

Table 50. Differential Receiver (RX) Input Specifications

Symbol Parameter Min Nom Max Units Comments

UI Unit interval 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for

Spread Spectrum Clock dictated variations.

See Note 1.

VRX-DIFFp-p Differential

peak-to-peak

output voltage

0.175 1.200 V VRX-DIFFp-p = 2*|VRX-D+ – VRX-D–|

See Note 2

TRX-EYE Minimum

receiver eye

width

0.4 UI The maximum interconnect media and transmitter

jitter that can be tolerated by the receiver can be

derived as TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.

See Notes 2 and 3

TRX-EYE-MEDIAN-to-MAX

-JITTER

Maximum time

between the jitter

median and

maximum

deviation from

the median.

0.3 UI Jitter is defined as the measurement variation of the

crossing points (VRX-DIFFp-p = 0 V) in relation to a

recovered TX UI. A recovered TX UI is calculated over

3500 consecutive unit intervals of sample data. Jitter

is measured using all edges of the 250 consecutive UI

in the center of the 3500 UI used for calculating the TX

UI. See Notes 2, 3, and 7

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

[De-Emphasized Bit]

0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)

566 mV (3 dB ) >=

TX-DIFFp-p-MIN

>= 505 mV (4 dB )

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

[Transition Bit]

TX-DIFFp-p-MIN

= 800 mV

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 67

VRX-CM-ACp AC peak

common mode

input voltage

150 mV VRX-CM-ACp = |VRXD+ – VRXD-|/2 – VRX-CM-DC

VRX-CM-DC = DC(avg) of |VRX-D+ – VRX-D-|/2

See Note 2

RLRX-DIFF Differential

return loss

15 dB Measured over 50 MHz to 1.25 GHz with the D+ and

D– lines biased at +300 and –300 mV, respectively.

See Note 4

RLRX-CM Common mode

return loss

6 dB Measured over 50 MHz to 1.25 GHz with the D+ and

D– lines biased at 0 V. See Note 4

ZRX-DIFF-DC DC differential

input impedance

80 100 120 ΩRX DC differential mode impedance. See Note 5

ZRX-DC DC input

impedance

40 50 60 ΩRequired RX D+ as well as D– DC impedance

(50 ± 20% tolerance). See Notes 2 and 5

ZRX-HIGH-IMP-DC Powered down

DC input

impedance

200 k ΩRequired RX D+ as well as D– DC Impedance when

the receiver terminations do not have power. See

Note 6

VRX-IDLE-DET-DIFFp-p Electrical idle

detect threshold

65 175 mV VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ – VRX-D–|

Measured at the package pins of the receiver

TRX-IDLE-DET-DIFF-

ENTERTIME

Unexpected

electrical idle

enter detect

threshold

integration time

10 ms An unexpected Electrical Idle (VRX-DIFFp-p <

VRX-IDLE-DET-DIFFp-p) must be recognized no longer

than TRX-IDLE-DET-DIFF-ENTERING to signal an

unexpected idle condition.

Table 50. Differential Receiver (RX) Input Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor68

2.18.5 Receiver Compliance Eye Diagrams

The RX ey e d i agram in Figure 42 is specifie d u sing the passive com p liance/t est measu rement load (see Figure 43) in place o f

any real PCI Exp ress RX component.

Not e: In g en er al, t he m ini m um re ceiv er ey e d iag ram m ea sur ed with t he com pl ian ce /tes t m eas urem e nt l oad (se e Figure 43) will

be la rger tha n the minimum recei ver eye diagram measured o ver a range of systems at the input receiver of any real PCI E xpress

com ponent. The degraded eye di agram at the input receive r is due to traces int erna l to the package as well as silicon parasiti c

char acte risti cs which ca use t he real PC I Express component to var y in impedan ce fr om the com plianc e/te st measure ment loa d.

The input rece iver eye diagram is impl ementa tion specif ic and is not specif ied. RX component designe r should pro vide

addi tio nal marg in to adequatel y compens ate for t he degraded mini mum rece iver eye diagra m (shown in Figure 42) exp ec ted at

the inp ut receiver ba sed on some adequ at e combin ation of s yst em simul at ions and th e return loss meas ured l ookin g i nto th e RX

pack age and sil icon. The RX eye diagr am must be ali gned in time us ing the jitt er median to loc ate the cente r of the eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 35 00 consecu tive unit int ervals of sampl e data. The eye diagra m is created using a ll edges

of the 250 co nsecutive UI in the center of the 3500 UI used for cal culating the TX UI.

LTX-SKEW Total skew 20 ns Skew across all lanes on a link. This includes variation

in the length of SKP ordered set (e.g., COM and one

to five symbols) at the RX as well as any delay

differences arising from the interconnect itself.

Notes:

1.)No test load is necessarily associated with this value.

2.)Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used

as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 42). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3.)A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in

which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any

250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point

in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as the reference for the eye diagram.

4.)The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The

reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by

a Vector Network Analyzer with 50-Ω probes—see Figure 43). Note that the series capacitors CTX is optional for the return

loss measurement.

5.)Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

6.)The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7.)It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated

data.

Table 50. Differential Receiver (RX) Input Specifications (continued)

Symbol Parameter Min Nom Max Units Comments

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 69

NOTE

The reference impedance for return loss measurements is 50 Ω to ground for both the D+

and D– line ( i.e., as measured by a vector network analyzer with 50- Ω probes—see

Figure 43). Note that the series capaci tors, CTX, are optional for the return loss

measurement.

Figure 42. Minimum Receiver Eye Timing and Voltage Compliance Specification

2.18.5.1 Compliance Test and Measurement Load

The AC tim ing and vol tage param eters m ust be veri fied a t the mea suremen t p oint, as s peci fied wi thi n 0.2 i nch es of the pa ckage

pins, in to a test/meas ur ement load shown in Figure 43.

NOTE

The allowance of the measure men t point to be within 0.2 in ches of the package pins is

meant to acknowledge that pac kage/board routing may benefit from D+ and D– not being

exac tly matched in length at the packa ge pin boundary.

Figure 43. Compliance Test/Measurement Load

2.19 JTAG

This section descr ibes the DC and AC electrical spec ifications for the IEEE 1149.1 (JTAG) interface of the MPC8610.

2.19.1 JTAG DC Electrical Characteristics

Table 51 provides the JTAG DC electri cal characte r i st ics for the JTAG interface.

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

RX-DIFFp-p-MIN

> 175 mV

0.4 UI = TRX-EYE-MIN

Silicon

+ Package

C = CTX

R = 50 ΩR = 50 Ω

D+ Package

D– Package

D+ Package

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Electrical Characteristics

Freescale Semiconductor70

2.19.2 JTAG AC Electrical Specifications

Table 52 prov ides the JTAG AC timing speci f icat ions as def ined in Figure 45 through Figure 47.

Table 51. JTAG DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD + 0.3 V

Low-level input voltage VIL –0.3 0.8 V

Input current (VIN1 = 0 V or VIN = VDD)I

IN —±5 μA

High-level output voltage (OVDD = mn, IOH = –100 μA) VOH OVDD – 0.2 — V

Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2V

Note:

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 2 and Ta bl e 3 .

Table 52. JTAG AC Timing Specifications (Independent of SYSCLK)1

At recommended operating conditions (see Ta ble 3 ).

Parameter Symbol2Min Max Unit Notes

JTAG external clock frequency of operation fJTG 0 33.3 MHz

JTAG external clock cycle time t JTG 30 — ns

JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns

JTAG external clock rise and fall times tJTGR & tJTGF 02ns6

TRST assert time tTRST 25 — ns 3

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

Valid times:

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 71

Figure 15 provides the AC test load for TDO and the boundary-scan outputs.

Figure 44. AC Test Load for the JTAG Interface

Figure 45 provides the JTAG clock input timing diagram.

Figure 45. JTAG Clock Input Timing Diagram

Figure 46 provides the TRST ti mi ng diagram.

Figure 46. TRST Timing Diagram

JTAG external clock to output high impedance:

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 15).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device

timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)

going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals

(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design.

Table 52. JTAG AC Timing Specifications (Independent of SYSCLK)1 (continued)

At recommended operating conditions (see Ta ble 3 ).

Parameter Symbol2Min Max Unit Notes

Output Z0 = 50 ΩOVDD/2

RL = 50 Ω

JTAG

tJTKHKL tJTGR

External Clock VMVMVM

tJTG tJTGF

VM = Midpoint Voltage (OVDD/2)

TRST

VM = Midpoint Voltage (OVDD/2)

VM VM

tTRST

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor72

Figure 47 provides the boundary-scan timing diagram.

Figure 47. Boundary-Scan Timing Diagram

3 Hardware Design Considerations

This section provides electrical and thermal design recommendations for su ccessful applica tion of the MPC8610.

3.1 System Clocking

This se ctio n de scri bes the PL L con figu rat ion of the MPC86 10. Not e that the pl atf orm c lock is id entic al t o th e in te rnal MPX bus

clock.

This device includes six PLLs, as follows:

1. The platform PLL genera tes the platform clock from th e ext ernally s upplied SYSCLK input. The frequ enc y ratio

between the pla tform and SYSCLK is selec ted using the platform PLL ratio configurati on bits as described in

Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.”

2. The e 600 core PLL generat es the core clock from the platform clock. The frequency ratio between th e e60 0 core

clock and the pla tform clock is selected us ing the e600 PLL ratio c onfiguration bits as described in Section 3.1.3,

“e600 Core to MPX/Platform Clock PLL Ratio.”

3. The PCI PLL gene rates the clocking for the PCI bus

4. Each of the two SerDes blocks has a PLL.

VM = Midpoint Voltage (OVDD/2)

VM VM

tJTDVKH

tJTDXKH

Boundary

Data Outputs

Boundary

Data Outputs

JTAG

External Clock

Boundary

Data Inputs

Output Data Valid

tJTKLDX

tJTKLDZ

tJTKLDV

Input

Data Valid

Output Data Valid

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 73

3.1.1 Clock Ranges

Table 53 provides the clocking specifications for the processor core.

Table 54 provides the clocking specificati ons for the memory bus.

Table 55 provides the clocking spec ificati ons for the loca l bus.

Table 53. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit Notes800 MHz 1066 MHz 1333 MHz

Min Max Min Max Min Max

e600 core processor frequency 666 800 666 1066 666 1333 MHz 1, 2, 3

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio” and Section 3.1.3, “e600 Core to

MPX/Platform Clock PLL Ratio,” for ratio settings.

2. The minimum e600 core frequency is based on the minimum platform clock frequency of 333 MHz.

3. The reset config pin cfg_core_speed must be pulled low if the core frequency is 800 MHz or below.

Table 54. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

Unit Notes

800, 1066, 1333 MHz

Min Max

Memory bus clock frequency 166 266 MHz 1, 2

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.”

2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.

Table 55. Local Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

Unit Notes

800, 1066, 1333 MHz

Min Max

Local bus clock speed 22 133 MHz 1

Note:

1. The local bus clock speed on LCLK[0:2] is determined by the MPX clock divided by the local bus ratio programmed in

LCRR[CLKDIV]. Refer to the

MPC8610 Integrated Host Processor Reference Manual,

for more information.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor74

Table 56 provides the clocking specifications for the Platform/MPX bus.

Table 56. Platform/MPX Bus Clocking Specifications

3.1.2 Platform/MPX to SYSCLK PLL Ratio

The t he cl ock that dri ves t he inte rnal MPX bus is c alle d the pla tform clo ck. Th e freque ncy of the platf orm clo ck is set usi ng the

following reset signa ls, as shown in Table 57:

• SYSCLK input signal

• Binary value on DIU_LD [10], LA[28:31] (cfg_sys_pll[0:4] - reset config) at power up

These signal s must be pulle d to the desired value s. Also note that the DDR data rate is the det ermining factor in s electing the

platform frequency, since the platform frequency must equal the DDR data rate.

For specific ations on the PCI_CLK, refer to the PCI 2.2 Specification.

Characteristic

Maximum Processor Core

Frequency

Unit Notes

800, 1066, 1333 MHz

Min Max

Platform/MPX bus clock speed 333 533 MHz 1, 2

Note:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.”

2. For MPX clock frequencies at 400 MHz and below, cfg_net2_div must be pulled low.

Table 57. Platform/SYSCLK Clock Ratios

Binary Value of

DIU_LD[10],

LA[28:31] Signals

Platform:SYSCLK Ratio

Binary Value of

DIU_LD[10],

LA[28:31] Signals

Platform:SYSCLK Ratio

00010 2:1 01010 10:1

00011 3:1 01100 12:1

00100 4:1 01110 14:1

00101 5:1 01111 15:1

00110 6:1 10000 16:1

00111 7:1 10001 17:1

01000 8:1 10010 18:1

01001 9:1 All others Reserved

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 75

3.1.3 e600 Core to MPX/Platform Clock PLL Ratio

The clock ratio between the e600 core and the platform clock is determined by the binary value of LBCTL, LALE,

LGPL2/LOE/LFRE, DI U_LD4 (c fg_core_pll[0:3]–rese t config) signals at power up. Table 58 descri bes the supported ratios.

Note that cfg_core_spe ed must be pulled low if the core f requency is 800 MHz or below.

3.1.4 Frequency Options

3.1.4.1 SYSCLK and Platform Frequency Options

Table 59 shows the expec ted frequency options for SYSC LK and platform frequencies.

Table 58. e600 Core/Platform Clock Ratios

Binary Value of

LBCTL, LALE,

LGPL2/LOE/LFRE,

DIU_LD4 Signals

e600 core: MPX/Platform Ratio

1000 2:1

1010 2.5:1

1100 3:1

1110 3.5:1

0000 4:1

0010 4.5:1

All Others Reserved

Table 59. SYSCLK and Platform Frequency Options

Platform:

SYSCLK

Ratio

SYSCLK (MHz)

33.33 66.66 83.33 100.00 111.11 133.33

Platform/MPX Frequency (MHz)1

1Platform/MPX Frequency values are shown rounded down to the nearest

whole number (decimal place accuracy removed)

3:1 333 400

4:1 333 400 533

5:1 333 500

6:1 400 500

8:1 533

10:1 333

12:1 400

16:1 533

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor76

3.2 Power Supply Design and Sequencing

3.2.1 PLL Power Supply Filtering

Each of the PLLs list ed above is provided with power through independent power supply pins (AVDD_Plat, AVDD_Core,

AVDD_PCI, and SDnAVDD, re sp ectively). The AVDD level should always be equivalent to VDD, and prefera bly thes e voltages

will be derived di rectly from VDD through a low fre quency filter scheme such as the following.

There are a number of ways to reliabl y pr ovide power to the PLLs, but the recommended solution is to provide inde pendent

filter circu its per PLL power supply, one to each of the AVDD type pins . By providing independent filters to each PLL the

opportunity to cause noise injection from one PLL to th e other is reduced.

This c ircuit is in te nded to fi lt er nois e in th e PLLs re sonant frequen cy range from a 500 kHz to 10 MHz range . It shoul d be built

with surface mount capacito rs with minimum effecti ve series indu cta nce (ESL). Cons istent with the recommendations of

Dr. Howa rd Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small

capa citors of equal value are rec ommended over a single large value capacitor.

Each c irc uit s hould be pla ced as clos e as pos sibl e to th e spe cific AVDD type pin b ein g suppl ied to mi nimize n oise cou pled from

nearby circuits. It should be possible to route directly from the capacitors to the AVDD type pin, which is on the periphery of

783 FC-PBGA the footprint, without the inductance of vias.

Figure 48 shows the filter circu it for the platform PLL power supplie s (AVDD_PLAT).

Figure 48. MPC8610 PLL Power Supply Filter Circuit (for Platform)

Figure 49 shows the filter circuit for the core PLL power supply (AVDD_Core).

Figure 49. MPC8610 PLL Power Supply Filter Circuit (for Core)

The SDnAVDD signals provide power for the analog portions of the SerDes P LLs. To ensure sta bilit y of the internal c lock, the

power supplie d to the PLL is filtered usi ng a circui t similar to the one shown in Figure 50. For maximum ef fectiveness, the filt er

circuit is placed as closely as possi ble to the SDnAVDD balls to ensure it filters out as much noise as possible. The ground

connection should be near the SDnAV DD balls. The 0.003-µF capa citor is closest to the balls, followed by the two 2.2-µF

capa citor s, a nd fina ll y the 1 oh m resist or t o t he boa rd supp ly plane. The capaci tors a re co nne cted f rom SDnAVDD t o the groun d

plane. Us e ceramic chip capacitors with the highest possible self-resonant frequen cy. All tr aces should be kept short , wide and

direct.

Figure 50. SerDes PLL Power Supply Filter

2.2 µF 2.2 µF

GND

Low ESL Surface Mount Capacitors

10 Ω

AVDD_PlatVDD_PLAT

VDD_Core AVDD_Core

2.2 µF 2.2 µF

GND Low ESL Surface Mount Capacitors

10 Ω

2.2 µF 10.003 µF

GND

1.0 Ω

AVDD

1. An 0805 sized capacitor is recommended for system initial bring-up.

SVDD

2.2 µF 1

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 77

Note the foll owing:

•SDnAVDD should be a filtered version of SVDD.

• Signal s on the SerDes interface are fed from the SVDD power plane.

3.3 Decoupling Recommendations

Due to la rge address and data buses , and high operat ing frequencies, the de vice can generate transient power surges and high

frequency noi se in its power supp ly , es pecially whi le driving l arge ca pacit ive lo ads. This noise mu st be prevent ed from reaching

other components in the MPC86 10 s ystem , and the de vice itself requires a clean, tigh tly regulate d source of p ower. Therefore,

it is r ecommended that the system designe r plac e at least one decoupling capacitor at eac h VDD, BVDD, OVDD, GV DD,

VDD_Core, and VDD_P LAT pin of the device. These decoupling capacitors should receiv e their power from sep ara te VDD,

BVDD, OV DD, GV DD, V DD_Core, VDD_PLAT, and GND power pla nes in the PCB, util izing short traces to minimi ze

inductance. Capa citors may be placed directly under the de vice using a standard escape pat tern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceram ic SMT (surface mount technol ogy) ca pacitors sh ould be

use d to mi nimize le ad inductance, pre ferably 0402 or 0603 sizes.

In a ddition, it is recommended that th ere be s everal bulk st orage c apac itors distrib uted aroun d the P CB, feeding the VDD, BVDD,

OVDD, GV DD, V DD_Core, and VDD_PLAT plane s, to enable quick recharging of the smalle r chip capac itors. Thes e bulk

capacitor s should have a low ESR (e quivalent series resistanc e) rati ng to ensure the qui ck response time necessary . They should

als o be connecte d to the power and ground planes through two vias to minimize inducta nce. Sugg ested bulk

capa citor s—100–330 µF (AVX TPS tantalum or Sanyo OSCON).

3.4 SerDes Block Power Supply Decoupling Recommendations

The S erDes block requir es a clean, tightly regulate d source of power ( SnVDD and XnVDD) to ensure low jit ter on tran smit an d

reliable re covery of data in the receiver. An appropriate de couplin g sc heme is outlined below.

Only surface mount te chnolo gy (SMT) capacit ors should be used to mi nimize inductance. Conn ec tions from all ca pac itors to

power and ground should be done with multiple vias to further reduce inductance.

• Fi r st, the boa rd should have at least 10 x 10-nF SMT ce ramic chip capacitors as close as possible to the supply balls

of the de vice. Where the board has blind vias, these capacitors should be pl ac ed directly below the ch ip supply and

gr ound connection s. Where t he board does not have blin d vias, these capacitors should be placed in a ring around the

device as close to the supply and ground connections as possible.

• Second, there should be a 1-µF cera mi c chip capa citor on each side of the device. This sho uld be done for all SerDes

supplies.

• Third, b etwe en the devic e a nd any Se rDes voltage regul ator there should be a 10-µF, low equivalen t series resistance

(ESR) SMT t antal um chip cap acit or and a 100-µF, low ESR SMT t antalum c hip cap acit or . This sho uld be done for all

SerDes supplies .

3.5 Connection Recommendations

To ensure r eliable operation, it is h ighly recommended to conne ct unused inp uts to an appropriate signal level. All u nused ac tive

low inpu ts should be ti ed to VDD, BVDD, OV DD, GVDD, VDD_Core, VDD_PLAT, XnVDD, and SnVDD as required. All unused

active high inputs should be conne cted to GND. All NC (no-connect) signals must remain unconnected. Power and ground

conne ction s must be made to al l external VDD, BVDD, OVDD, GVDD, VDD_Core, VDD_PL AT, XnVDD, SnVDD, and GND pins

of the device.

Sp ec ial cas es:

• Local Bus—If pa rity is not used, ti e LDP[0: 3] to ground via a 4.7-kΩ resistor, tie LPBSE to OVDD via a 4.7-kΩ resistor

(pull-up resistor). For systems which boot from local bus (GPCM)-controlled Flash, a pull up on LGPL4 is required.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor78

• SerDes —R ec eiver lanes config ured for PCI Express are allowed to be disconnected (as would occur when a PCI

Expre ss s lot i s c onnected but not po pulated). Directi ons for t ermin ating the SerDes signals is discussed in Section 3.10,

“Guide lines for High-Spee d Interface Termination. ”

3.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8610 requires weak pull-up resis tors (2–10 kΩ is recommended) on open drain type pins includin g I2C pins and PIC

interrupt pins.

Correc t operat ion of the JTAG inter face require s confi gurati on of a group of syste m control pins as demons trate d in Figure 53.

Care must be taken t o ensure t hat these pins are maintained at a vali d deasser ted state under normal oper ating c onditions as most

have asynchronous behavior and spurious assert ion will give unpredictable results.

Refer to the PCI 2.2 s pecification for all pull-ups required for PC I.

The following pins must not be pulled down during power- on reset: DIU_LD[5 :6], MSRCID[1: 2], HRESET_REQ , and

TRIG_OUT/READY.

The following are factory test pin s a nd require stro ng pull up resistors (100 Ω – 1 kΩ) to OVDD: LSSD_MODE,

TEST_MODE[0:3].

The following pins require weak pull-up resistors (2–10 kΩ) to their specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2,

LCS[6]/DMA_DACK[2], LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and

CKSTP_OUT.

The following pins should be pulled to ground with a 100-Ω resistor: SD1_IMP_CAL_TX, SD2_IMP_CAL_TX. The following

pins should be pulled to ground with a 200-Ω re sistor: SD1_IMP_CAL_RX, SD2_IMP _CAL_RX.

When the plat form frequency is 400 MHz, c fg_platform_freq mus t be pulled d own at res et. Als o, cfg_d ram_type[ 0 or 1] must

be valid at powe r-up even before HRESET assertion.

For ot her pin pull-up or pull-down recommendations of si gnals, see Se ction 1, “Pin Assignments and Rese t St ates.”

3.7 Output Buffer DC Impedance

The MPC8610 drive rs are character ize d over proces s, voltage, and temperature. For all buses, the driver is a pus h-pull

sin gle-ended dri ver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the

value of each resi st or is varied until the pa d voltage is OVDD/2 (see Figure 51). The output im pedance is the average of two

com ponents, the resis tances of th e pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 79

RP is trimmed unt il the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN

are de signed to be cl os e to each other in val ue. Then, Z0 = (RP + RN)/2.

Figure 51. Driver Impedance Measurement

Table 60 sum m arizes the s i gnal imped an c e targ et s. Th e d ri v er imped an c es ar e target ed at m in i mu m VDD, no mina l O V DD,

105°C.

3.8 Configuration Pin Muxing

The MPC8610 provides the use r with power-on configuration options which can be set through the use of exte rnal pull-up or

pull- down resi stors of 4.7 kΩ on ce rtain out put pi ns (see cus tomer vis ible c onfigurat ion pins ). These pins ar e generall y used a s

output only pins in normal operation.

While HRESET is asse rted howev er, these pins are tre ated as inputs . The valu e presented on these pins while HRESET is

as serte d, is la tched wh en HRESET deass erts , at which t ime t he input recei ver is disa bled an d the I/O c ircuit takes on its no rmal

function. Mos t of these sampled configuration pins are equipped with an on-chi p gated resistor of approximate ly 20 kΩ. This

value should permit th e 4.7-kΩ resistor to pul l the configuratio n pin to a va lid logic low level. The pull-up resistor is enabled

only during HRESET (and for platform /syste m c locks after HRESET deassertion to ensure capture of the reset value). When

the input rece iver is disabled the pul l-up is also, t hus allowing functional opera tion of the pin as an output with mi nimal signal

qual ity or delay di sruption. The de fault value fo r all configurat ion bi ts treate d thi s way has been encoded such that a hig h voltage

leve l puts the device into the default state and externa l resistors are needed only when non-default settings are required by the

user.

Careful board layout with stubless connections to these pull-down resis tors coupled with the large value of the pull-down

resistor should minimize the disruption of signal quality or speed for output pins thus configured.

The pl atform PLL ratio and e600 core PLL ratio co nfiguration pins are not equipped with thes e default pull-up devices.

Table 60. Impedance Characteristics

Impedance

Local Bus, DUART, Control,

Configuration, Power

Management

PCI Express DDR DRAM Symbol Unit

RN43 Target 25 Target 20 Target Z0W

RP43 Target 25 Target 20 Target Z0W

Note: Nominal supply voltages. See Ta bl e 3 , Tj = 105°C.

OVDD

OGND

Pad

Data

SW1

SW2

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor80

3.9 JTAG Configuration Signals

Correc t operat ion of the JTAG inter face require s confi gurati on of a group of syste m control pins as demons trate d in Figure 53.

Care must be taken t o ensure t hat these pins are maintained at a vali d deasser ted state under normal oper ating c onditions as most

have asynchronous behavior and spurious assert ion will give unpredictable results.

Boundary-sca n testing is enabled through the JTAG interface signa ls. The TRST signal is optional in the IEEE 1149.1

spe cific ation, but is provided on all processor s that implement the Power Architecture technolog y. The device r equires TRST

to be asserted during rese t condi tions to ensure the JTAG boun dary logi c does not interfere wit h normal c hip operation. While

it is possible to force the TAP controller to the res et state using only the TCK and TMS signals, more reliable power-on reset

per for mance will be ob tain ed if the TR ST sign al is assert ed during powe r -on reset . Becaus e the JTAG interfa ce is al so used for

accessing the common on-chip processor (COP) function, simply tying T RST to HRE S ET is not practic al.

The COP functi on of these processors all ows a remote computer s ystem (ty pically a P C with de dicated hardware and debugging

software) to acce ss and control the internal operations of the proc es s or. The COP port conn ects primarily th rough the JTAG

interface of the process or, with some addi tional status monitoring signals. The COP port requires the ability to independently

assert HRESET or TRST in order to fully contro l the proces sor. If the target syste m has independent reset sources, such as

volta ge monito rs, watch dog t imers, power su pply f ailure s, or p ush-but ton swi tches, the n the COP re set si gnal s must be merge d

i n to these sig nals with log ic.

The arran g ement shown in Figure 52 allo w s th e COP po r t to in depende ntly a ss e rt HRE S E T or TRST, w h il e en s u r i ng th at th e

target can drive HRESET as well.

The COP interface has a standard he ader, shown in Figure 52, for connection to the targe t s ystem, and is based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a

connector key.

The COP header adds m any benefits such as breakpoints, watchpoints, register and memory examination/modification, and

other standard debugger features. An inexpens ive option can be to leave the COP he ader unpopulated until needed.

There is no stand ardized way to number the COP header shown i n Figure 53; consequentl y, many dif f eren t pin numbers have

been observed from em ulator vendors. Some are num bered top- to-bottom then left-to-right, whi le others use le ft-to-ri ght then

top-to-bottom, while still others number the pi ns counter clockwise from pin 1 (as with an IC). Rega rdless of th e numbering,

t h e signal placement reco mmended in Figure 53 is common to al l known emulators.

3.9.1 Termination of Unused Signals

If the JTAG interface an d COP header will not be us ed, Freescale recomm ends the foll owing connect ions:

•TRST

should be tied to HRESET through a 0-kΩ isolation resistor so that it is asserted when the system reset signal

(HRESET) is assert ed, ensuri ng that the JTAG scan chai n is initialized during the power-on reset flow. Frees cale

recommends that the COP header be designed into the system as shown in Figure 53. If this is not possible, the

isolation resistor will allow future access to T RST in ca se a JTAG interface may need to be wired onto the sys tem in

future debug situations.

•Tie TCK to OV

DD through a 10-kΩ resistor. This will prevent TCK fr om changing sta te and readin g incorrect da ta

i nto the device.

• No connection is required for TDI, TMS, or TDO.

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 81

Figure 52. COP Connector Physical Pinout

KEY

No pin

COP_TDO

COP_TDI

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

GND

COP_TCK

COP_TMS

COP_SRESET

COP_HRESET

COP_CHKSTP_OUT

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor82

Figure 53. JTAG Interface Connection

HRESET HRESET

From Target

Board Sources

HRESET

SRESET

SRESET SRESET

VDD_SENSE

5 1

2 kΩ

10 kΩ

OVDD

CKSTP_IN CKSTP_IN

TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

4TRST

(if any)

COP Header

14 2

Notes:

1. RUN/STOP

, normally found on pin 5 of the COP header, is not implemented.

Connect pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

OVDD

10 kΩ

OVDD

TRST

10 kΩ

OVDD

10 kΩ

CKSTP_OUT

KEY

No pin

COP Connector

Physical Pin Out

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 83

3.10 Guidelines for High-Speed Interface Termination

3.10.1 SerDes Interface

The high-speed SerDes inte rfac e can be disa bled through the POR input cfg_io_ports[0:2] and through the DE VDISR regis ter

in software. If a SerDes port is disa bled through the POR inp ut the user can not enable it throug h the DEVDISR register in

soft ware. However, if a SerDes port is enable d through the POR input the user can disable it through the DEVDISR registe r in

soft ware. Disabling a SerDes por t through softwa re should be done on a temporary basis. Power is al ways required for the

SerDes interface, e ven if the port is dis abled through eith er mechanism. Table 61 des cribes the possible enabled/disabled

scena rios for a SerDes port. The termina tion recommenda tions must be followed for ea ch port .

If the hig h-speed SerDes por t require s comple te or parti al termin ation, the unused pin s should be te rminated as descr ibed in this

section.

The fol lowing pins mu st be left unconnected (floating):

•SDn_TX[7:0]

•SD

n_TX[7:0]

The fol lowing pins mu st be connecte d to GND:

•SDn_RX[7:0]

•SD

n_RX[7:0]

•SDn_REF_CLK

For other directi ons on reserved or no-conne cts pins, see Se ction 1, “Pin As signments and Rese t St ates.”

Table 61. SerDes Port Enabled/Disabled Configurations

Disabled through POR input Enabled through POR input

Enabled through DEVDISR SerDes port is disabled (and cannot

be enabled through DEVDISR)

Complete termination required

(Reference clock not required

SerDes port is enabled

Partial termination may be required1

(Reference clock is required)

1Partial termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the

SerDes port mode. If port 1 is in x4 PCI Express mode, no termination is required because all pins are being

used. If port 1 is in x1/x2 PCI Express mode, termination is required on the unused pins. If port 2 is in x8 PCI

Express mode, no termination is required because all pins are being used. If port 1 is in x1/x2/x4 PCI Express

mode, termination is required on the unused pins.

Disabled through DEVDISR

SerDes port is disabled (through

POR input)

Complete termination required

(Reference clock not required)

SerDes port is disabled after software

disables port

Same termination requirements as

when the port is enabled through POR

input2

(Reference clock is required)

2If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes

are required. Termination of the SerDes port should follow what is required when the port is enabled through

both POR input and DEVDISR. See Note 1 for more information.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor84

3.11 Guidelines for PCI Interface Termination

PCI termination if PCI is not used at all.

Option 1

• If PCI arbiter is enable d during POR,

— All AD pins will be driven to the stable states after POR. Therefore , all ADs pins c an be floating. This includes

PCI_AD[31:0], PCI_C/BE[3:0], and PCI_PAR signals.

— All PCI control pins can be grouped together and tied to OVDD throu gh a single 10-kΩ resis tor.

— It is optional to dis able PCI block through DEVDISR regis ter after POR reset.

Option 2

• If PCI arbiter is disabled during POR,

— All AD pins will be in the input state. Therefore, all ADs pins nee d to be grouped together and tie d to OVDD

through a single (or multiple) 10-kΩ resistor(s)

— All PCI control pins can be grouped together and tied to OVDD throu gh a single 10-kΩ resis tor

— It is optional to dis able PCI block through DEVDISR regis ter after POR reset.

3.12 Thermal

This section describes the ther mal spe cifications of the MPC8610.

3.12.1 Thermal Characteristics

Table 62 provides the package thermal char acteristics for the MPC8610.

3.12.2 Thermal Management Information

This section provid es thermal mana gem ent info rmation for the flip-chip, plasti c ball- grid array (FC_PBGA) package for

air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow ,

and thermal interfac e m ate rial. The MPC8610 implem ents several features designed to as si st with therm al managem ent,

includi ng the temperature diode. The temper ature diode allows an external dev ice to monit or the die temperature in order to

dete ct e xces sive temp erature condi ti ons an d ale rt t he s yste m; see Secti on 3.12.2 .5, “Tempera ture Dio de ,” for more i nformation .

Table 62. Package Thermal Characteristics1

Characteristic Symbol Value Unit Notes

Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board RθJA 24 °C/W 1

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board RθJA 18 °C/W 1

Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board RθJMA 18 °C/W 1

Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board RθJMA 15 °C/W 1

Junction-to-board thermal resistance RθJB 10 °C/W 2

Junction-to-case thermal resistance RθJC <0.1 °C/W 3

Notes:

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC

specification for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

3. Junction-to-case resistance is less than 0.1°C/W because the silicon die is the top of the packaging case..

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 85

To reduce the die - junction temperature, hea t si nks are required; due to the potent ial large mass of th e heat sink, attachment

through the printed-ci rcuit board is suggested. In a ny implementation of a heat sink s olution, the forc e on the die should not

exce ed te n pounds force ( 45 n ewtons) . Figure 54 s hows a spr ing cl ip thro ugh the boa rd. Oc casiona ll y the spring cl ip is attache d

to sol dered hooks or to a plastic backing s tructur e. Screw and spring arrangements ar e al so frequently us ed.

Figure 54. FC-PBGA Package Exploded Cross-Sectional View with Several Heat Sink Options

Sui table heat sinks are commercially available from the following vendors :

Aavid T herm alloy 603-224-9988

80 C om m e r ci al St.

Concord, NH 03301

Inter n et: www .aavidthermalloy.com

Advanced Thermal So lutions 781-769-2800

89 Acce ss Road #27.

Norwood, MA02062

Inter n et: www.qats.com

Alpha Nova tech 408-749-7601

473 Sapena Ct. #12

Santa Clara, CA 95054

Internet: www.alpha novatech.com

Calgreg Thermal Solutions 888-732-6100

60 Alha mbra Roa d, Suite 1

Warwick, RI 02886

Inter n et: www .calgreg.com

Interna tional Electronic Re search Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet : www.ctscorp.c om

Millennium Electronics (MEI) 408-436-8770

Loroco Sites

671 East Brokaw Road

San Jose, CA 95112

Internet: www.mei-thermal. com

Thermal

Heat Sink FC-PBGA Package

Heat Sink

Clip

Printed-Circuit Board

Interface Material

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor86

Tyco Electronics 800-522-6752

Ch ip Coolers™

P.O. Box 3668

Harris burg, PA 17105-366 8

Internet: www.chipcoolers.com

Wakefield Engine ering 603-635-5102

33 Bridge St .

Pelham, NH 03076

Internet : www.wake f ield.com

Ultimatel y, the final selection of an appropriate he at sink depends on many factors, such as thermal pe rform ance at a given air

velocity, spat ial vol ume , m as s, attachment me thod, assembl y, and cost.

3.12.2.1 Internal Package Conduction Resistance

For th e exposed-d ie pa ckaging tec hnology described in Table 62, the intrinsic conduc tion thermal resi stance paths are as

follows:

• Th e d ie junction- to-case th ermal resi sta n ce

• The di e junction-to-board thermal resista nce

Figure 55 depic ts the primary heat transfer pat h for a pac kage with an at tached hea t s ink mo unted to a printed-c ircuit board.

Figure 55. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

The heat sink rem oves mo st of the heat from the device. Heat generate d on the act ive si de of t he chip is conducted through the

silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink. The

junction-to-case thermal resistance is low enough that the heat sink at tach material a nd heat sink thermal resis tance are the

dominant terms.

3.12.2.2 Thermal Interface Materials

A th er mal interface mate r ial is recommended a t the packa ge-to-heat sink interface to mini mize the the r mal contact re sistance.

Figure 56 shows the thermal pe rforma nce of three thin-she et therma l-interface materials (silico ne, graphit e/oil , fluoroether oil),

a bare joint, and a joint with thermal grease as a function of contac t pressure. As shown, the perform ance of these the r m al

interface materials improves with increasing contact pressure. The use of the rmal gre ase significantly reduces the interface

th er mal resistance. In contrast, the bare joint r esults in a th er mal r esistan ce approximately seven t imes grea ter tha n the thermal

grease joint.

External Resistance

Internal Resistance

Radiation Convection

Heat Sink

Printed-Circuit Board

Thermal Interface Material

Package/Leads

Die Junction

Die/Package

(Note the internal versus external package resistance.)

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 87

Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 54).

Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended.

Of course, the selection of any thermal interface material depends on many factors—thermal performance requirements,

manufacturability , service temperature, dielectric properties, cost, and so on.

Figure 56. Thermal Performance of Select Thermal Interface Material

The board designer can choose between several types of thermal interface. Heat s ink adhesi ve materials should be selected

bas ed on high conductivity and mechanical strength to meet equipm ent shock/v ibrati on requirements. The r e are several

com mer cially available therm al interfaces and adhe s ive mate rials provided by the following vendors:

The Bergquist Company 80 0-347-4572

18930 West 78th St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

Chome r ics, Inc . 781-935-4850

77 Dragon Ct.

Woburn, MA 01801

Internet : www.ch ome r ics.com

Dow-Corning Corporation 800-248-2481

Corporate Ce nter

PO Box 994

Midland, MI 48686-0994

Internet: www.dowcorning.c om

Shi n-Etsu MicroSi, Inc. 888-642-7674

10028 S. 51st St.

Phoenix, AZ 85044

Internet : www.microsi.com

0.5

1.5

0 1020304050607080

Silicone Sheet (0.006 in.)

Bare Joint

Fluoroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

Contact Pressure (psi)

Specific Thermal Resistance (K-in.2/W)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Hardware Design Considerations

Freescale Semiconductor88

Thermagon Inc. 888-246-9050

4707 Detroit Ave.

Cleveland, OH 44102

Inter n et: www.therm agon.com

3.12.2.3 Heat Sink Selection Example

This section provides a heat sink selec tion example us ing one of the comme rcially available heat sinks.

For preliminary heat sink sizing, the die-junctio n temperature can be expressed as follows:

Tj = Ti + Tr + (RθJC + Rθint + Rθsa) × Pd

where:

Tj is the die - junction temperature

Ti is th e in let cabin e t am b i en t te mp erat ur e

Tr is the air tempe r ature rise w ithin the co mputer cabinet

RθJC is the junction-to-case thermal re sistance

Rθint is the adhesive or interface material thermal resistance

Rθsa is the heat sink base-to-ambient thermal resistance

Pd is th e p o w er dissi p ated by the devic e

During operation, the die-junction temperature s (Tj) should be mai n taine d less than the value specified in Table 3. Th e

tempera ture of air cooling the component greatly depends on the ambient inlet ai r temperature and the air temperature rise

within the el ectronic cabinet. An electr onic cabinet inlet- air te mperature (Ti) may range from 30° to 40°C. The air temperature

rise within a ca binet (T r) may be in the range of 5° to 10°C. The th ermal resista n ce of the th ermal inter f ace mate r i al (R θint) is

typically about 0.2°C/W. For example, ass umi ng a T i of 30°C, a Tr of 5°C, a package RθJC = 0.1, an d a typical powe r

cons um ption (Pd) of 10 W, the fol lowing expr ession for Tj is obtained:

Die-junction temperature: Tj = 30°C + 5°C + (0. 1°C/W + 0.2°C/W + θsa) × 10 W

For th is exa mple, a Rθsavalue of 6.7°C /W o r l ess i s re quired t o mainta in the di e junc ti on te mpera ture b elow t he maximu m value

of Table 3.

Though the die junction-to-ambient and the heat sink-to-ambient therma l resistances are a common figure-of-m erit used for

com paring the t hermal p erformance of vario us m icroel ectro nic pa ckagi ng tec hnol ogies, one s hou ld exe rcis e ca ution wh en only

using this metri c in determ ining thermal management bec aus e no single parameter can adequa tely desc ribe three - dimensional

heat flow. The final di e-junc ti on opera ting t emper ature is no t o nly a func tio n of the c omponent-l eve l the rmal resi stance , but t he

syste m-le vel de sign a nd its opera ting co ndit ions. In addi ti on to th e comp onent' s power con sumption, a num ber of fa ctors aff ec t

the final operating die-jun ction temp erature—airflow, board populat ion (local he at flux of adjacent components), heat sink

efficiency, heat sink placement, next-level interconnect tec hnology, system air temperature rise, altitude, and so on.

Due to the com plexit y and variety of system-level boundary conditions for today's microe lectronic equipment, the co mbi ned

effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we

recommend using conjugate heat transfer models for the board a s well as system-level designs.

3.12.2.4 Recommended Thermal Model

For system thermal modeling, the MPC8610 thermal mode l is shown in Figure 57. Four cuboids are used to represent this

device. The die is modeled as 8.5 × 9.7 mm at a thickn es s of 0.86 mm. See Section 2.3, “Power Characteristics,” for power

dissipation de tails. The substrate is modeled as a single block 29 × 29 × 1. 18 mm with orthotropic conductivity of

23.3 W/(m • K) in the xy- plane a nd 0.95 W/(m • K) in the z-di recti on. The die is ce ntere d on the subst rate. The bump/unde rfill

layer is modeled as a c ollapsed thermal resistance between the die and substrate with a conductivity of 8.1 W/(m • K) in the

thic kness dim ensi on of 0.07 mm. The C5 solder layer is modeled as a c uboid with dimensi ons 29 × 29 × 0.4 m m with orthotropic

therm al co nductiv ity of 0.034 W/(m • K) in the xy-p lane and 12. 1 W/(m • K) in the z-dire ction. An LGA sold er layer woul d be

Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 89

mode led as a colla psed t hermal resis tanc e with the rmal conduc tivit y of 12. 1 W/(m • K) and an effe ctive height of 0. 1 mm. The

therm al model uses median di me ns ions to reduce grid. Pleas e refer to the cas e outline for actual dimensions .

The therm al mo del uses appr oximat e dim ensi ons t o reduc e g rid. T he ap proxi mations use d do not im pact therm al per form ance.

Please refer to the case outline for exact dimensions.

Figure 57. MPC8610 Thermal Model

3.12.2.5 Temperature Diode

The MPC8610 has a temper ature diode on the microprocessor that can be used in conjunc tion with ot her system temp erature

moni toring devices (s uch as Analog Device s, ADT7461™) . T hese device s use t he ne gati ve temper ature coefficient of a diod e

operated at a cons tant current to determine the tempe r ature of the microprocessor and its environment . For proper oper ation,

the monitoring device used s hould auto-calibra te the device by ca nceling out the VBE varia tion of each MPC8610’ s internal

diode.

The fol lowing are the spe cific ations of the MPC8610 on-boa rd tempera ture diod e:

Vf > 0.40 V

Vf < 0.90 V

Operati ng range 2–300 μA

Diode lea kage < 10 nA @ 125°C

Bump and Underfill

Die

Substrate

Solder/Air

Die

Substrate

Side View of Model (Not to Scale)

Top View of Model (Not to Scale)

Conductivity Value Unit

Die (8.5 x 9.7 x 0.86mm)

Silicon Temperature

dependent

Bump and Underfill (8.5 × 9.7 × 0.07 mm)

Collapsed Resistance

kz8.1 W/(m • K)

Substrate (29 × 29 × 1.18 mm)

kx23.3 W/(m • K)

ky23.3

kz0.95

Solder and Air (29 × 29 × 0.4 mm)

kx0.034 W/(m • K)

ky0.034

kz12.1

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Ordering Information

Freescale Semiconductor90

An approximate value of the ide ality may be obtained by calibrating the device near the expected operating tem perature.

Ideality factor is de fined as the deviation from the ideal diode equat ion:

Another useful equation is:

Where:

Ifw = Forward current

Is = Saturation current

Vd = Volt age at di o d e

Vf = Voltage forward biased

VH = Diode voltage while IH is flowing

VL = Diode voltage while IL is flow in g

IH = Larger di ode bi as curre n t

IL = Smaller diode bias current

q = Charge of electron (1. 6 × 10 –1 9 C)

n = Ideality factor (norm ally 1.0)

K = Boltzman’s constant (1.38 × 10–23 Joules/K)

T = Temp era t u re (Kelvins)

The ratio of I H to IL is usually selected to be 10:1. The above simp lifies to the followin g:

Solving for T, the equation becomes:

4 Ordering Information

Orderi ng informati on for the parts fully covered by this specif ication document is provide d in Sectio n 4.1, “Part Numbe rs Fully

Addr es sed by This Document.”

4.1 Part Numbers Fully Addressed by This Document

Table 63 provides the Free scale part num bering nomenclature for the MPC8610. Note that the indivi dual par t num bers

corre spond to a maximum processor core frequenc y. For available freque ncies, cont act your local Freescale sales of fice. In

addi tion to the processor frequency , t he part num bering scheme als o include s an applic ation modifie r which may specify special

application conditions. Each part num ber al so contai ns a revision code which refers to the die mask revis ion num ber.

Ifw = Is e – 1

qVf___

nKT

VH – VL = n

IH__

VH – VL = 1.986 × 10–4 × nT

nT = VH – VL

__________

1.986 × 10–4

Ordering Information

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 91

Table 64 shows the parts that are ava ilable for ordering and their operating conditi ons.

Table 63. Part Numbering Nomenclature

MC nnnn w xx yyyy M z

Product

Code

Part

Identifier Temp 3 Package 1

Core Processor

Frequency2

(MHz)

DDR Speed

(MHz) Product Revision Level

MC 8610

T = –40°

to 105°C PX = Leaded sphere

FC-PBGA

VT = RoHS lead free

FC-PBGA

1066, 800

J = 533 MHz

G = 400 MHz

Revision B = 1.1

System Version Register

Value for Rev B:

0x80A0_0011—MPC8610

Blank = 0

to 105°C

1333, 1066, 800

Notes:

1. See Section 5, “Package Information,” for more information on available package types.

2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by part number specifications may support other

maximum core frequencies.

3. Extended temperature range devices are offered only with core frequencies of 1066 and 800 MHz.

Table 64. Part Offerings and Operating Conditions

Part Offerings1

1The xx in the part marking represents the package option.The ‘T’

represents the extended temperature rating. The ‘z’ represents the

revision letter. For more information see Table 63.

Operating Conditions

MC8610xx1333Jz Max CPU speed = 1333 MHz,

Max DDR = 533 MHz

MC8610xx1066Jz Max CPU speed = 1066 MHz,

Max DDR = 533 MHz

MC8610Txx1066Jz Max CPU speed = 1066 MHz,

Max DDR = 533 MHz

extended Temperature Rating

MC8610xx800Gz Max CPU speed = 800 MHz,

Max DDR = 400 MHz

MC8610Txx800Gz Max CPU speed = 800 MHz,

Max DDR = 400 MHz

Extended temperature rating

Note:

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Package Information

Freescale Semiconductor92

4.2 Part Marking

Parts are mar k ed as the exa mple shown in Figure 58.

Figure 58. Part Marking for FC-PBGA Device

5 Package Information

This section details package pa rameters and dimensions.

5.1 Package Parameters for the MPC8610

The package para meters are as provi ded in the following li st . T he package ty pe is 29 mm × 29 mm, 783 pins . Ther e are two

package opti ons: leaded flip chip-pla stic bal l grid array (FC-P BGA) and RoHS lead-free (FC-PBGA) .

Die size 8.5 mm × 9.7 mm

Package outline 29 mm × 29 mm

Interconnects 783

Pitch 1 mm

Minimum module he ight 2.18 m m

Maxim um module height 2. 7 mm

Total capacitor count 23 ca ps; 100 nF each

For leaded FC-PBGA (package option: PX)

Solder balls 63% Sn 37% Pb

Ball diameter (typical) 0.50 mm

For RoHS lead-free FC-PBGA (package option: VT)

Solder balls 96.5% Sn, 3.5% Ag

Ball diameter (typical) 0.50 mm

MC8610

wxxyyyyMz

TWLYYWW

MMMM

YWWLAZ

YWWLAZ is the assembly traceability code.

MMMM is the M00 (mask) number.

TWLYYWW is the test code.

Note:

Package Information

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 93

5.2 Mechanical Dimensions of the MPC8610 FC-PBGA

Figure 59 shows the mechanical dimensions and bottom surface nomenclature of the MPC8610 lead -free FC-PBGA.

Notes:

1All dimensions are in millimeters.

2Dimensions and tolerances per ASME Y14.5M-1994.

3Maximum solder ball diameter measured parallel to datum A.

4Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

5Capacitors may not be present on all devices.

6Caution must be taken not to short capacitors or expose metal capacitor pads on package top.

7All dimensions symmetrical about centerlines unless otherwise specified.

Figure 59. MPC8610 FC-PBGA Dimensions

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Product Documentation
Freescale Semiconductor94
6 Product Documentation
The  following documents  are  required for a complet e desc ription of the device and are needed  to desi gn properly with the part.
•MPC86 10 Integrated Host Processo r Reference Manual (document number: MPC8610RM)
•e600 P owerPC Core Reference Manual (document number: E600CORERM)
7 Revision History
Table 65 summa r izes revis ions to th is document.
Table 65. Revision History
Rev. No. Date Substantive Change(s)
2 1/2009  • Updated Table of Contents
 • Removed subheading Section 1.1. pin assignments.
 • Promoted section 4.3, “Ordering Information,” and associated subsections to Section 4, “Ordering 
Information.” Renumbered subsequent sections and subsections accordingly.
1 01/2009  • Updated Table of Contents
 • Removed Serial Rapid IO from Section 2.4.4, “Platform Frequency Requirements for PCI-Express” 
because SRIO is not available on MPC8610.
 • Removed note in Table 2 1  and Ta bl e 2 2  that states “Minimum DDR2 frequency is 400 MHz.”
 •In Ta bl e 3 1 , removed rows for ti2cr and ti2CF
. Added row for Cb.
 • Replaced 1067 with 1066 in Ta bl e 6 3 .
 • Replaced CBGA with PBGA in Section 5.1, “Package Parameters for the MPC8610.”
0 10/2008 Initial release.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 95

THIS PAGE INTENTIONALLY BLANK

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

Beijing 100022

China

+86 10 5879 8000

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or +303-675-2140

Fax: +303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale and the Freescale logo are trademarks or registered trademarks

of Freescale Semiconductor, Inc. in the U.S. and other countries. All other

product or service names are the property of their respective owners. The

Power Architecture and Power.org word marks and the Power and Power.org

logos and related marks are trademarks and service marks licensed by

Power.org. IEEE 1149.1 is a trademark of the Institute of Electrical and

Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved

by the IEEE.

Document Number: MPC8610EC

Rev. 2

01/2009

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale Semiconductor data sheets and/or specifications can and do vary

in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the design or manufacture of the part.

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality

and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.