Description
The A6277 is specifically designed for LED display
applications. Each BiCMOS device includes an 8-bit CMOS
shift register, accompanying data latches, and eight NPN
constant-current sink drivers. Two package styles and two
operating temperature ranges are available.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typical serial data-input rates are up to 20 MHz. The LED drive
current is determined by the user selection of a single resistor.
A CMOS serial data output permits cascade connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
input high. In addition, a HIGH/LOW function enables full
selected current with the application of a logic low, or 50%
selected current with the application of a logic high.
Two package styles are provided, a through-hole DIP (suffix
A), and a surface-mount SOIC (LW). The copper leadframe
and low logic-power dissipation allow the DIP to sink 122 mA
through all outputs continuously over the operating temperature
range (1.0 V drop, 85°C). Both packages are lead (Pb) free,
with 100% matte-tin leadframe plating.
26185.202F
Features and Benefits
▪ Up to 150 mA constant-current outputs
▪ Undervoltage lockout
▪ Low-power CMOS logic and latches
▪ High data input rate
▪ Similar to Toshiba TD62715FN
▪ High/low output current function
▪ Digital dimming control
8-Bit Serial Input Constant-Current Latched LED Driver
Functional Block Diagram
A6277
Packages
Not to scale
20-pin DIP
(A package)
20-pin SOICW
(LW package)
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
Supply Voltage VDD 7.0 V
Output Voltage Range VO–0.5 to 24 V
Input Voltage Voltage VI–0.4 to VDD + 0.4 V
Output Current IO150 mA
Operating Ambient Temperature T ARange E –40 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
* Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.
Selection Guide
Part Number Packing Package
A6277EA-T* 20-pin DIP 18 per tube
A6277ELWTR-T 20-pin SOICW 1000 per reel
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant
is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The
variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no
longer available. Status date change November 2, 2009. Deadline for receipt of LAST TIME BUY orders is April 30, 2010.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package A, on 1-layer PCB 60 ºC/W
Package LW, 1-layer PCB 90 ºC/W
*Additional thermal information available on the Allegro website.
50 75 100 125 150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN oo
ooC
2.0
1.5
1.0
25
SUFFIX 'A', R = 60oC/W
QJA
SUFFIX 'LW', R = 90oC/W
QJA
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = +25oC, VH/L = VDD = 5 V (unless otherwise noted).
Limits
tinU.xaM.pyT.niMsnoitidnoC tseTlobmyScitsiretcarahC
Supply Voltage Range VDD V5.50.55.4gnitarepO
Under-Voltage Lockout VDD(UV) VDD V0.4–4.3V 5 ot 0 =
Output Current IOVCE = 1.0 V, REXT = 160 7100 120 140 mA
(any single output) VCE = 0.4 V, REXT = 470 734 42 48 mA
Output Current Matching $IO0.4 V b VCE(A) = VCE(B) b 1.0 V:
Ryna neewteb ecnereffid( EXT = 160 7–p1.5 p6.0 %
two outputs at same VCE)REXT = 470 7–p1.5 p6.0 %
Output Leakage Current ICEX VOH 0.50.1–V 02 = MA
Logic Input Voltage VIH 0.7VDD ––V
VIL ––0.3V
DD V
SERIAL DATA OUT Voltage VOL IOL V4.0––Am 0.1 =
(SDO1 & SDO2)VOH IOH V––6.4Am 0.1- =
Input Resistance RIENABLE input, pull up 150 300 600 k7
LATCH & HIGH/LOW inputs, pull down 100 270 400 k7
Supply Current IDD(OFF) REXT = open, VOE = 5 V – 0.8 1.6 mA
REXT = 470 7, VOE = 5 V 3.5 6.5 9.5 mA
REXT = 160 7, VOE = 5 V 141722mA
IDD(ON) REXT = 470 7, VOE = 0 V 5.0 10 15 mA
REXT = 160 7, VOE = 0 V 202740mA
Typical Data is at VDD = 5 V and is for design information only.
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
RECOMMENDED OPERATING CONDITIONS
tinU.xaM.pyT.niMsnoitidnoClobmyScitsiretcarahC
Supply Voltage VDD 4.5 5.0 5.5 V
Output Voltage VO–1.04.0 V
Output Current IOContinuous, any one output – – 150 mA
IOH SERIAL DATA OUT – – -1.0 mA
IOL SERIAL DATA OUT – – 1.0 mA
Logic Input Voltage VIH 0.7VDD –– V
VIL ––0.3V
DD V
Clock Frequency fCK zHM01––noitarepo edacsaC
SWITCHING CHARACTERISTICS at TA = 25oC, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 77
77
7, IO = 40 mA, VL = 3 V, RL = 65 77
77
7, CL = 10.5 pF.
Limits
tinU.xaM.pyT.niMsnoitidnoC tseTlobmyScitsiretcarahC
Propagation Delay Time tpHL CLOCK-OUTn– 350 1000 ns
LATCH-OUTn– 350 1000 ns
ENABLE-OUTn– 350 1000 ns
CLOCK-SERIAL DATA OUT1–40– ns
Propagation Delay Time tpLH CLOCK-OUTn– 300 1000 ns
LATCH-OUTn– 400 1000 ns
ENABLE-OUTn– 380 1000 ns
CLOCK-SERIAL DATA OUT2–40– ns
Output Fall Time tf90% to 10% voltage 150 250 1000 ns
Output Rise Time tr10% to 90% voltage 150 250 600 ns
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CK) ............................................... 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................................ 100 ns
E. Latch Enable Pulse Width, tw(L) ................................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 Ms
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
—Max. Clock Transition Time, tr or tf.............................. 10 Ms
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
OUTPUT
ENABLE
OUTN
Dwg. WP-029-3
50%
SERIAL
DATA OUT.
1
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
SERIAL
DATA OUT.
2DATA50%
p
t
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-1A
DATA
10%
50%
pHL
t
pLH
t
HIGH = ALL OUTPUTS DISABLED (BLANKED)
f
t
r
t
90%
F
50%
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
Package LWPackage A
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-17
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
80
T
A
= +25oC
V
DD
= 5 V
RQ
JA
= 55oC/W
120
140 V
CE
= 1 V
V
CE
= 2 V
V
CE
= 4 V
V
CE
= 3 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-15
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +50oC
V
DD
= 5 V
R
Q
JA
= 55oC/W
120
140 V
CE
= 1 V
V
CE
= 2 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-14
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 4 V
80
T
A
= +50oC
V
DD
= 5 V
R
Q
JA
= 70oC/W
120
140 V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-16
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 4 V
80
T
A
= +25oC
V
DD
= 5 V
RQ
JA
= 70oC/W
120
140
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 1 V
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-13
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +85oC
V
DD
= 5 V
RQ
JA
= 55oC/W
120
140
V
CE
= 1 V
V
CE
= 0.7 V
V
CE
= 2 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-12
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +85oC
V
DD
= 5 V
R
Q
JA
= 70oC/W
120
140
V
CE
= 1 V
V
CE
= 0.7 V
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
TYPICAL CHARACTERISTICS
0.5
Dwg. GP-063-1
1.0 2.0
1.5
V
CE
IN VOLTS
0
60
40
OUTPUT CURRENT IN mA/BIT
20
0
T
A
= +25oC
R
EXT
= 470 7
Package LWPackage A
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
elbanEelbanEataDkcolCataD
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INInput I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNLP
1P2P3... PN-1 PN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
TUO ATAD LAIRESNI ATAD LAIRES dna KCOLC
LATCH ENABLE and HIGH/LOWOUTPUT ENABLE (active low)
Dwg. EP-010-11
IN
VDD
Dwg. EP-010-12
IN
VDD
Dwg. EP-010-13
IN
VDD
VDD
Dwg. EP-063-6
OUT
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
Package Power Dissipation (PD). The maximum allow-
able package power dissipation is determined as
PD(max) = (150 - TA)/RQJA.
The actual package power dissipation is
PD(act) = dc(VCE • IO • 8) + (VDD • IDD).
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage
reducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of 0.4 V
to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recom-
mended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White 3.5 – 4.0 V
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
Infrared 1.2 – 1.5 V
Pattern Layout. This device has separate logic-ground
and power-ground terminals. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
Dwg. EP-064
VLED
VDROP
VF
VCE
Applications Information
300 500 700 1 k 2 k
CURRENT-CONTROL RESISTANCE, R
EXT
IN OHMS
100
0100
Dwg. GP-061-1
OUTPUT CURRENT IN mA/BIT
5 k
200 3 k
20
40
60
80
V
CE
= 0.7 V
120
140
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TERMINAL DESCRIPTION
Terminal No. Terminal Name Function
1 LOGIC GROUND Reference terminal for control logic.
2 SERIAL DATA IN Serial-data input to the shift-register.
3 CLOCK Clock input terminal for data shift on rising edge.
4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.
5 HIGH/LOW Logic low for 100% of programmed current level;
(CURRENT) logic high for 50% of programmed current level.
6 POWER GROUND Ground.
7-14 OUT0-7 The eight current-sinking output terminals.
15 POWER GROUND Ground.
16 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
17 SERIAL OUT2CMOS serial-data output (on clock falling edge).
18 SERIAL OUT1CMOS serial-data output (on clock rising edge)
to the following shift-registers.
19 REXT An external resistor at this terminal establishes the output current for all sink
drivers.
20 LOGIC SUPPLY (VDD) The logic supply voltage. Typically 5 V.
Pin-out Diagram
(A and LW packages)
REGISTER
LATCHES
5
10 11
12
13
14
15
6
7
8
9
16
POWER
GROUND
POWER
GROUND
HIGH/LOW
(CURRENT)
OUT
1
OUT
2
OUT
0
OUT
4
OUT
6
OUT
5
OUT
3
OUT
7
LOGIC
GROUND 1
2
3
17
19
4
18
20
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCK CK
V
DD
OE
R
EXT
I
REGULATOR
L
O
SUB SUB
SERIAL
DATA OUT
2
1
FF
C
SEATING
PLANE
5.33 MAX
0.46 ±0.12
6.35 +0.76
–0.25
26.16 +0.76
–1.27
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
7.62
2.54
0.38 +0.10
–0.05
21
20
A
For Reference Only
Dimensions in millimeters
(reference JEDEC MS-001 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
Package A,20-pin DIP
Package LW, 20-pin SOICW
21
20
21
20
A
2.65 MAX
C
SEATING
PLANE
C0.10
20X
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE B
2.25
0.65
9.50
1.27
PCB Layout Reference View
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
BReference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
1.27
0.25
0.20 ±0.10
0.41 ±0.10
12.80±0.20
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
Copyright ©2001-2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
8-Bit Serial Input Constant-Current Latched LED Driver
A6277
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
