Watchdog Timer
MAX6746–MAX6751
The watchdog’s circuit monitors the μP’s activity. It the μP
does not toggle the watchdog input (WDI) within tWD (user-
selected), RESET asserts for the reset timeout period. The
internal watchdog timer is cleared by any event that asserts
RESET, by a falling transition at WDI (which can detect
pulses as short as 300ns), or by a transition at WDS. The
watchdog timer remains cleared while reset is asserted; as
soon as reset is released, the timer starts counting.
The MAX6746–MAX6751 feature two modes of watch-
dog operation: normal mode and extended mode. In
normal mode (Figure 4a), the watchdog timeout period
is determined by the value of the capacitor connected
between SWT and ground. In extended mode (Figure
4b), the watchdog timeout period is multiplied by 128. For
example, in extended mode, a 0.1μF capacitor gives a
watchdog timeout period of 65s (see the Extended-Mode
Watchdog Timeout Period vs. CSWT graph in the Typical
Operating Circuit). To disable the watchdog timer function,
connect SWT to ground.
MAX6752/MAX6753
The MAX6752 and MAX6753 have a windowed watchdog
timer that asserts RESET for the adjusted reset timeout
period when the watchdog recognizes a fast watchdog fault
(tWDI < tWD1), or a slow watchdog fault (period > tWD2).
The reset timeout period is adjusted independently of the
watchdog timeout period.
The slow watchdog period (tWD2) is calculated as follows:
tWD2 = 0.65 x 109 x CSWT
with tWD2 in seconds and CSWT in Farads.
The fast watchdog period (tWD1) is selectable as a ratio
from the slow watchdog fault period (tWD2). Select the
fast watchdog period by pin strapping SET0 and SET1,
where high is VCC and low is GND. Table 1 illustrates
the SET0 and SET1 configuration for the 8, 16, and 64
window ratio ( tWD2/tWD1).
For example, if CSWT is 1500pF, and SET0 and SET1 are
low, then tWD2 is 975ms (typ) and tWD1 is 122ms (typ).
RESET asserts if the watchdog input has two falling edges
too close to each other (faster than tWD1) (Figure 5a) or
falling edges that are too far apart (slower than tWD2)
(Figure 5b). Normal watchdog operation is displayed in
Figure 5c. The internal watchdog timer is cleared when
a WDI falling edge is detected within the valid watchdog
window or when RESET is deasserted. All WDI inputs are
ignored while RESET is asserted.
The watchdog timer begins to count after RESET is
deasserted. The watchdog timer clears and begins to
count after a valid WDI falling logic input. WDI falling
transitions within periods shorter than tWD1 or longer than
tWD2 force RESET to assert low for the reset timeout
period. WDI falling transitions within the tWD1 and tWD2
window do not assert RESET. WDI transitions between
tWD1(min) and tWD1(max) or tWD2(min) and tWD2(max)
are not guaranteed to assert or deassert RESET. To
guarantee that the window watchdog does not assert
RESET, strobe WDI between tWD1(max) and tWD2(min).
The watchdog timer is cleared when RESET is asserted
or after a falling transition on WDI, or after a state
change on SET0 or SET1. Disable the watchdog timer by
connecting SET0 high and SET1 low.
Figure 4b. Watchdog Timing Diagram, WDS = VCC
Table 1. Min/Max Watchdog Setting
SET0 SET1 RATIO
Low Low 8
Low High 16
High Low Watchdog Disabled
High High 64
tWD x 128 tRP
VCC
WDI
RESET
EXTENDED MODE (WDS = VCC)
VCC
OV
OV
MAX6746–MAX6753 μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
www.maximintegrated.com Maxim Integrated
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