a Wideband/Differential Output Transimpedance Amplifier AD8015 FUNCTIONAL BLOCK DIAGRAM FEATURES Low Cost, Wide Bandwidth, Low Noise Bandwidth: 240 MHz Pulse Width Modulation: 500 ps Rise Time/Fall Time: 1.5 ns Input Current Noise: 3.0 pA/Hz @ 100 MHz Total Input RMS Noise: 26.5 nA to 100 MHz Wide Dynamic Range Optical Sensitivity: -36 dBm @ 155.52 Mbps Peak Input Current: 6350 mA Differential Outputs Low Power: 5 V @ 25 mA Wide Operating Temperature Range: -408C to +858C PRODUCT DESCRIPTION The AD8015 is a wide bandwidth, single supply transimpedance amplifier optimized for use in a fiber optic receiver circuit. It is a complete, single chip solution for converting photodiode current into a differential voltage output. The 240 MHz bandwidth enables AD8015 application in FDDI receivers and SONET/SDH receivers with data rates up to 155 Mbps. This high bandwidth supports data rates beyond 300 Mbps. The differential outputs drive ECL directly, or can drive a comparator/ fiber optic post amplifier. 8 +VS 10k 50 IIN 2 7 +OUTPUT +1 G = 30 G=3 NC 3 6 -OUTPUT 50 +1 VBYP 4 - + 5 -VS +VS 1.7V NC = NO CONNECT 25.0E+3 DIFFERENTIAL 20.0E+3 X-RESISTANCE - APPLICATIONS Fiber Optic Receivers: SONET/SDH, FDDI, Fibre Channel Stable Operation with High Capacitance Detectors Low Noise Preamplifiers Single-Ended to Differential Conversion I-to-V Converters AD8015 NC 1 15.0E+3 SINGLE-ENDED 10.0E+3 5.0E+3 000.E+0 10.0E+6 100.0E+6 1.0E+9 FREQUENCY - Hz Figure 1. Differential/Single-Ended Transimpedance vs. Frequency EQUIVALENT INPUT CURRENT NOISE - pA Hz 5.0 In addition to fiber optic applications, this low cost, silicon alternative to GaAs-based transimpedance amplifiers is ideal for systems requiring a wide dynamic range preamplifier or singleended to differential conversion. The IC can be used with a standard ECL power supply (-5.2 V) or a PECL (+5 V) power supply; the common mode at the output is ECL compatible. The AD8015 is available in die form, or in an 8-pin SOIC package. 3.0pF 4.5 2.0pF 4.0 1.5pF 3.5 3.0 2.5 1.0pF 0.5pF 2.0 000.0E+0 20.0E+6 40.0E+6 60.0E+6 80.0E+6 100.0E+6 FREQUENCY - Hz REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Figure 2. Noise vs. Frequency (SO-8 Package with Added Capacitance) (c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8015-SPECIFICATIONS (SO Package @ T = +258C and V A S = +5 V, unless otherwise noted) AD8015AR Typ Parameter Conditions Min DYNAMIC PERFORMANCE Bandwidth Pulse Width Modulation Rise and Fall Time Settling Time1 3 dB 10 A to 200 A Peak 10% to 90% to 3%, 0.5 V Diff Output Step 180 240 500 1.5 3 MHz ps ns ns 2.5%, Nonlinearity Saturation 155 Mbps, Avg Power Die, by Design SOIC, by Design +VS to IIN and VBYP 25 200 30 350 -36 0.2 0.4 1.8 A A dBm pF pF V INPUT Linear Input Current Range Max Input Current Range Optical Sensitivity Input Stray Capacitance Input Bias Voltage NOISE Input Current Noise Total Input RMS Noise TRANSFER CHARACTERISTICS Transresistance Power Supply Rejection Ratio OUTPUT Differential Offset Output Common-Mode Voltage Voltage Swing (Differential) 1.6 Die, Single Ended at POUT, or Differential (POUT-NOUT), CSTRAY = 0.3 pF f = 100 MHz DC to 100 MHz POWER SUPPLY Operating Range 8 16 From Positive Supply Positive Input Current, RL = Positive Input Current, RL = 50 -1.5 40 TMIN to TMAX Single Supply Dual Supply 2.0 3.0 26.5 Single Ended Differential Single Ended Differential Output Impedance Max +4.5 2.25 Current Units pA/Hz nA 10 20 37.0 40 12 24 k k dB dB 6 -1.3 1.0 600 50 20 -1.1 60 mV V V p-p mV p-p +5 +11 5.5 26 V V mA 25 NOTES 1 Settling Time is defined as the time elapsed from the application of a perfect step input to the time when the output has entered and remained within a specified error band symmetrical about the final value. This parameter includes propagation delay, slew time, overload recovery, and linear settling times. Specifications subject to change without notice. NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-pin SOIC package: JA = 155C/W. ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage (+VS to -VS). . . . . . . . . . . . . . . . . . . . . . . 12 V Internal Power Dissipation2 Small Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Storage Temperature Range . . . . . . . . . . . . -65C to +125C Operating Temperature Range (TMIN to TMAX) AD8015ACHIP/AR . . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C ORDERING GUIDE Model Temperature Range Package Description Package Option AD8015AR -40C to +85C 8-Pin Plastic SOIC SO-8 AD8015ACHIPS -40C to +85C Die Form CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8015 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -2- WARNING! ESD SENSITIVE DEVICE REV. A AD8015 PIN CONFIGURATION +VS +VS 1.7V AD8015 AD8015 NC 1 1 8 +VS 2 7 +OUTPUT +1 G=3 50 - + 50 R CLOCK RECOVERY - + 4 +VS CLK DATA QUANTIZER +1 . 5 -VS +VS 6 LPF: 3dB@ 0.7 x F G=3 3 6 -OUTPUT +1 VBYP 4 +1 G = 30 G = 30 NC 3 7 LPF: R 3dB@ 0.7 x F 50 50 IIN 2 V1 8 10k 10k R > 40 C1 >100pF 4.5V < VS < 11V 5 1.7V 1.7V C1 NC = NO CONNECT Figure 3. Fiber Optic Receiver Application: Photodiode Referred to Positive Supply METALIZATION PHOTOGRAPH Dimensions shown in microns. Not to scale. OPTIONAL +VS CONNECTION +VS IIN PHOTODIODE REFERRED TO NEGATIVE SUPPLY Figure 4 shows the AD8015 used in a circuit where the photodiode is referred to the negative supply. This results in a larger back bias voltage than when referring the photodiode to the positive supply. The larger back bias voltage on the photodiode decreases the photodiode's capacitance thereby increasing its bandwidth. The R2, C2 network shown in Figure 4 is added to decouple the photodiode to the positive supply. This improves PSRR. +OUTPUT 838 998 +VS -OUTPUT +VS AD8015 1 +1 3 -VS G=3 50 - + 1.7V 973 +VS 5 R R CLOCK RECOVERY CLK DATA QUANTIZER R > 40 C1 >100pF 4.5V < VS < 11V R2 AND C2 OPTIONAL FOR IMPROVED PSRR C1 NOTE: FOR BEST PERFORMANCE ATTACH PACKAGE SUBSTRATE TO +VS. MATERIAL AT BACK OF DIE IS SILICON. USE OF +VS OR -VS FOR DIE ATTACH IS ACCEPTABLE. Figure 4. Fiber Optic Receiver Application: Photodiode Referred to Negative Supply FIBER OPTIC SYSTEM NOISE PERFORMANCE FIBER OPTIC RECEIVER APPLICATIONS The AD8015 maintains 26.5 nA referred to input (RTI) to 100 MHz. Calculations below translate this specification into minimum power level and bit error rate specifications for SONET and FDDI systems. The dominant sources of noise are: 10 k feedback resistor current noise, input bipolar transistor base current noise, and input voltage noise. In a fiber optic receiver, the photodiode can be placed from the IIN pin to either the positive or negative supply. The AD8015 converts the current from the photodiode to a differential voltage in these applications. The voltage at the VBYP pin is 1.8 V below the positive supply. This node must be bypassed with a capacitor (C1 in Figures 3 and 4 below) to the signal ground. If large levels of power supply noise exist, then connecting C1 to +VS is recommended for improved noise immunity. For optimum performance, choose C1 such that C1 > 1/(2 x 1000 x fMIN); where fMIN is the minimum useful frequency in Hz. The AD8015 has dielectrically isolated devices and bond pads that minimize stray capacitance at the IIN pin. Input voltage noise is negligible at lower frequencies, but can become the dominant noise source at high frequencies due to IIN pin stray capacitance. Minimizing the stray capacitance at the IIN pin is critical to maintaining low noise levels at high frequencies. The pins surrounding the IIN pin (Pins 1 and 3) have no internal connection and should be left unconnected in an application. This minimizes IIN pin package capacitance. It is best to have no ground plane or metal runs near Pins 1, 2, and 3 and to minimize capacitance at the IIN pin. PHOTODIODE REFERRED TO POSITIVE SUPPLY Figure 3 shows the AD8015 used in a circuit where the photodiode is referred to the positive supply. The back bias voltage on the photodiode is 1.8 V. This method of referring the photodiode provides greater power supply noise immunity (PSRR) than referring the photodiode to the negative supply. The signal path is referred to the positive rail, and the photodiode capacitance is not modulated by high frequency noise that may exist on the negative rail. REV. A +1 4 813 6 LPF: 3dB@ 0.7 x F G = 30 R2 VBYP 7 LPF: 3dB@ 0.7 x F 50 2 +VS 1.7V V1 8 10k C2 The AD8015AR (8-pin SOIC) IIN pin total stray capacitance is 0.4 pF without the photodiode. Photodiodes used for SONET or FDDI systems typically add 0.3 pF, resulting in roughly 0.7 pF total stray capacitance. -3- AD8015 SONET OC-3 SENSITIVITY ANALYSIS Sensitivity (minimum power level) = 492/0.85 nW OC-3 Minimum Bandwidth = 0.7 x 155 MHz 110 MHz = 579 nW (peak) Total Current Noise = (/2) x 26.5 nA = -32.4 dBm (peak) = 42 nA (assuming single pole response) = -35.4 dBm (average) To maintain a BER < 1 x 10-10 (1 error per 10 billion bits): The FDDI specification allows for a minimum power level of -28 dBm peak, or -31 dBm average. Using the AD8015 provides 4.4 dB margin. Minimum current level needs to be > 13 x Total Current Noise = 541 nA (peak) Assume a typical photodiode current/power conversion ratio = 0.85 A/W THEORY OF OPERATION The simplified schematic is shown in Figure 5. Q1 and Q3 make up the input stage, with Q3 running at 300 A and Q1 running at 2.7 mA. Q3 runs essentially as a grounded emitter. A large capacitor (0.01 F) placed from VBYP to the positive supply shorts out the noise of R17, R21, and Q16. The first stage of the amplifier (Q3, R2, Q4, and C1) functions as an integrator, integrating current into the IIN pin. The integrator drives a differential stage (Q5, Q6, R5, R3, and R4) with gains of +3 and -3. The differential stage then drives emitter followers (Q41, Q42, Q60 and Q61). The positive output of the differential stage provides the feedback by driving RFB. The differential outputs are buffered using Q7 and Q8. Sensitivity (minimum power level) = 541/0.85 nW = 637 nW (peak) = -32.0 dBm (peak) = -35.0 dBm (average) The SONET OC-3 specification allows for a minimum power level of -31 dBm peak, or -34 dBm average. Using the AD8015 provides 1 dB margin. FDDI SENSITIVITY ANALYSIS FDDI Minimum Bandwidth = 0.7 x 125 MHz 88 MHz 88 MHz Total Current Noise = ( / 2) x The bandwidth of the AD8015 is set to within +20% of the nominal value, 240 MHz, by factory trimming R5 to 60 . The following formula describes the AD8015 bandwidth: x 26.5 nA 100 MHz Bandwidth = 1/(2 x C1 x RFB x (R5 + 2 re)/R4) = 39 nA (assuming single pole response) To maintain a BER < 2.5 x 10 -10 where re (of Q5 and Q6) = 9 each, constant over temperature, and RFB/R4 = 43.5, constant over temperature. (1 error per 4 billion bits): The bandwidth equation simplifies, and the bandwidth depends only on the value of C1: Minimum current level needs to be > 12.6 x Total Current Noise = 492 nA (peak) Bandwidth = 1/(2 x 3393 x C1). Assume a typical photodiode current/power conversion ratio = 0.85 A/W +VS R17 635 R1 300 R2 3k R3 230 R4 230 Q4 R21 1.8k VBYP Q16 330 Q42 Q41 INPUT CLAMPS +OUTPUT Q8 R44 50 Q60 Q7 IIN Q1 Q3 Q5 Q6 C1 0.2pF 330 +VS -OUTPUT R5 60 I10 0.75MA Q61 Q56 R43 50 RFB 10k I1 1.5MA I2 3MA I3 1MA I4 3MA I5 3MA I6 1MA I7 1MA I8 1MA I9 1MA -VS Figure 5. AD8015 Simplified Schematiic -4- REV. A AD8015 1.5 9 +85C +85C + 25C 0.5 - 40C -40C AND 0C GAIN - dB OUTPUT VOLTAGE - Volts 1.0 0 5 4k -0.5 VOUT 0 IN 50 AD8015 -1.0 -1.5 -100 -80 -60 -40 -20 0 20 40 60 80 100 1 INPUT CURRENT - A 10 Figure 6. Differential Output vs. Input Current Figure 9. Gain vs. Frequency 0 10 +85C +25C PIN 7 GROUP DELAY - ns OUTPUT VOLTAGE - Volts -0.5 -1.0 -40C -1.5 1000 100 FREQUENCY - MHz -40C PIN 6 5V, +25C 0 -2.0 +25C +85C -2.5 -100 -80 -60 -40 -20 0 20 40 60 80 100 10 100 INPUT CURRENT - A 1000 FREQUENCY - MHz Figure 10. Group Delay vs. Frequency Figure 7. Single-Ended Output vs. Input Current 9.0 300 290 8.5 280 11.0V 8.0 7.5 260 GAIN - dB BANDWIDTH - MHz 270 250 240 5.0V 4.5V 7.0 6.5 230 6.0 220 210 5.5 200 -40 -30 -20 -10 0 10 20 30 40 50 60 70 5.0 10.0E+6 80 TEMPERATURE - C 100.0E+6 1.0E+9 FREQUENCY - Hz Figure 8. Bandwidth vs. Temperature REV. A Figure 11. Differential Gain vs. Supply -5- AD8015 APPLICATION 155 Mbps Fiber Optic Receiver 100 The AD8015 and AD807 can be used together for a complete 155 Mbps Fiber Optic Receiver (Transimpedance Amplifier, Post Amplifier with Signal Detect Output, and Clock Recovery and Data Retiming) as shown in Figure 16. PIN 7 The PIN diode front end is connected to a single mode, 1300 nm laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W responsivity, 0.7 pF capacitance, and 2.5 GHz bandwidth. 50 PIN 6 The AD8015 outputs (POUT and NOUT) drive a differential, constant impedance (50 ) low-pass filter with a 3 dB cutoff of 100 MHz. The outputs of the low-pass filter are ac coupled to the AD807 inputs (PIN and NIN). The AD807 PLL damping factor is set at 10 using a 0.22 F capacitor. 0 1 10 1000 100 FREQUENCY - MHz The entire circuit was enclosed in a shielded box. Table I summarizes results of tests performed using a 223-1 PRN sequence, and varying the average power at the PIN diode. Figure 12. Output Impedance vs. Frequency The circuit acquires and maintains lock with an average input power as low as -39.25 dBm. 100 30 DEVICES, 2 LOTS: (+OUT, -OUT) x (25C, -40C, 85C) x (5V, 4.5V, 11.0V) 100 90 70 80 0 POPULATION - Parts VOLTAGE - mV 80 -100 0 10 60 70 50 60 40 50 40 30 30 20 20 20 TIME - ns 10 10 0 0 200.000E+6 205.000E+6 210.000E+6 215.000E+6 220.000E+6 225.000E+6 230.000E+6 235.000E+6 240.000E+6 245.000E+6 250.000E+6 255.000E+6 260.000E+6 265.000E+6 270.000E+6 275.000E+6 280.000E+6 285.000E+6 290.000E+6 295.000E+6 300.000E+6 Figure 13. Small Signal Pulse Response 2 0 CUMULATIVE - % IMPEDANCE - 5V, +25C FREQUENCY - Hz 1pF -2 GAIN - dB Figure 15. Bandwidth Distribution Matrix -4 5pF 0pF -6 8pF 3pF -8 -10 -12 10.0E+6 100.0E+6 1.0E+9 FREQUENCY - Hz Figure 14. Differential Gain vs. Input Capacitance -6- REV. A AD8015 C1 0.1F SDOUT TP7 TP8 DATAOUTN DATAOUTP C2 R1 R2 0.1F 100 100 C3 0.1F C4 0.1F R11 R10 154 154 R5 100 R6 100 R8 100 CLKOUTP C5 0.1F C8 R4 100 R11 154 1 DATAOUTN 2 DATAOUTP 3 VCC2 4 CLKOUTN 5 CLKOUTP 6 VCC1 7 CF1 C7 R7 100 CLKOUTN R3 100 C1 100pF R12 154 C6 0.1F TP1 CD 8 TP2 DAMPING CAP,0.22F GND TP4 16 R17 3.65k SDOUT 15 C11 VEE AVCC 14 PIN 13 NIN 12 AVCC 11 THRADJ 10 CF2 AD807 R13 THRADJ TP5 C15 0.1F 10F 1 NC +VS 8 2 IIN +OUT 7 3 NC -OUT 6 -VS 5 150nH 15pF VBYP 150nH 15pF AD8015 NC = NO CONNECT 0.1F 0.01F Figure 16. 155 Mbps Fiber Optic Receiver Schematic Table I. AD8015, AD807 Fiber Optic Receiver Circuit: Output Bit Error Rate & Output Jitter vs. Average Input Power REV. A Average Optical Input Power (dBm) Output Bit Error Rate Output Jitter (ps rms) -6.4 -6.45 -6.50 -6.60 -6.70 -7.0 to -35.50 -36.00 -36.50 -37.00 -37.50 -38.00 -38.50 -39.00 -39.1 -39.20 -39.25 -39.30 Loses Lock 1.2 x 10-2 7.5 x 10-3 9.4 x 10-4 1 x 10-14 1 x 10-14 < 40 3.0 x 10-12 4.8 x 10-10 2.8 x 10-8 8.2 x 10-7 1.3 x 10-5 1.1 x 10-4 1.0 x 10-3 1.3 x 10-3 1.9 x 10-3 2.2 x 10-3 Loses Lock -7- R15 50 TP6 100 pF 0.1F 4 C13 0.1F C10 5V TP3 0.8 A/W, 0.7pF 2.5GHz R16 301 R14 50 C9 10F ABB HAFO 1A227 FC HOUSING NOTES 1. ALL CAPS ARE CHIP, 15pF ARE MICA. 2. 150 nH ARE SMT 9 AVEE C12 2.2F < 40 C14 0.1F 50 LINE 50 LINE AC COUPLED PHOTODIODE APPLICATION FOR IMPROVED DYNAMIC RANGE and typical sensitivity of -35 dBm. AC coupling the input also results in improved pulse width modulation performance. AC coupling the photodiode current input to the AD8015 (Figure 17) extends fiber optic receiver overload by 3 dB while sacrificing only 1 dB of sensitivity (increasing receiver dynamic range by 2 dB). This application results in typical overload of -4 dBm, Careful attention to minimize parasitic capacitance at the AD8015 input (from the photodetector input), RAC and CAC are critical for sensitivity performance in this application. Note that CAC of 0.01 F was chosen for a low frequency cutoff equal to 2.2 kHz. +VS +VS AD8015 1 7 LPF: R 3dB@ 0.7 x F 6 LPF: 3dB@ 0.7 x F 50 2 RAC 7k V1 8 10k CAC +1 G = 30 0.01F G=3 3 50 R CLOCK RECOVERY - + +VS CLK DATA QUANTIZER +1 4 C1973-6-1/96 AD8015 R > 40 C1 >100pF 4.5V < VS < 11V 5 1.7V C1 Figure 17. AC Coupled Photodiode Application for Improved Dynamic Range OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Small Outline IC Package (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.0098 (0.25) 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0196 (0.50) 0.0532 (1.35) 0.0099 (0.25) x 45 0.0040 (0.10) 0.0500 0.020 (0.51) (1.27) 0.013 (0.33) BSC 0.0098 (0.25) 8 0 0.0500 (1.27) 0.0075 (0.19) 0.0160 (0.41) PRINTED IN U.S.A. SEATING PLANE -8- REV. A