© 2009 Microchip Technology Inc. DS39682E
PIC18F45J10 Family
Data Sheet
28/40/44-Pin High-Performance,
RISC Microcontrollers
DS39682E-page ii © 2009 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microch ip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc. DS39682E-page 1
PIC18F45J10 FAMILY
S pecial Microcontroller Features:
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• On-Chip 2.5V Regulator
• 4x Phase Lock Loop (PLL) available for Crystal
and Internal Oscillators
• Self-Programmable under Software Control
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via
Two Pins
• Power-Managed modes with Clock Switching:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
Flexible Oscil lator Struc ture:
• Two Crystal modes, up to 40 MHz
• Two External Clock modes, up to 40 MHz
• Internal 31 kHz Oscillator
• Secondary Oscillator using Timer1 @ 32 kHz
• Two-Speed Oscillator Start-up
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
Peripheral Highl ight s:
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Three Programmable External Interrupts
• Four Input Change Interrupts
• One Capture/Compare/PWM (CCP) module
• One Enhanced Capture/Compare/PWM (ECCP)
module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Two Master Synchronous Serial Port (MSSP)
modules supporting 3-Wire SPI (all 4 modes) and
I2C™ Master and Slave modes
• One Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
• 10-Bit, up to 13-Channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
- Self-calibration feature
• Dual Analog Comparators with Input Multiplexing
Device
Program Memory SRAM Data
Memory
(bytes) I/O 10-Bit
A/D (ch)
CCP/
ECCP
(PWM)
MSSP
EUSART
Comparators
Timers
8/16-Bit
Flash
(bytes) # Single-Word
Instructions SPI Master
I2C™
PIC18F24J10 16K 8192 1024 21 10 2/0 1 Y Y 1 2 1/2
PIC18F25J10 32K 16384 1024 21 10 2/0 1 Y Y 1 2 1/2
PIC18F44J10 16K 8192 1024 32 13 1/1 2 Y Y 1 2 1/2
PIC18F45J10 32K 16384 1024 32 13 1/1 2 Y Y 1 2 1/2
28/40/44-Pin High-Per forman ce, RISC Microcontroll ers
PIC18F45J10 FAMILY
DS39682E-page 2 © 2009 Microchip Technology Inc.
Pin Diagrams
PIC18F24J10
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
VDDCORE/VCAP
RA5/AN4/SS1/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK1/SCL1
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
RC4/SDI1/SDA1
28-Pin SPDIP, SOIC, SSOP (300 MIL)
PIC18F25J10
* Pin feature is dependent on device configuration.
28-Pin QFN
PIC18F24J10
RC0/T1OSO/T1CKI
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
RC4/SDI1/SDA1
MCLR
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
VDDCORE/VCAP
RA5/AN4/SS1/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK1/SCL1
PIC18F25J10
* Pin feature is dependent on device configuration.
.
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
5
4
= Pins are up to 5.5V tolerant
= Pins are up to 5.5V tolerant
© 2009 Microchip Technology Inc. DS39682E-page 3
PIC18F45J10 FAMILY
Pin Diagrams (Continued)
44-Pin QFN(1)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
RC4/SDI1/SDA1
RD3/PSP3/SS2
RD2/PSP2/SDO2
MCLR
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
VDDCORE/VCAP
RA5/AN4/SS1/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RC3/SCK1/SCL1
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F44J10
40-Pin PDIP (600 MIL)
PIC18F45J10
* Pin feature is dependent on device configuration.
.
* Pin feature is dependent on device configuration.
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F44J10
37
MCLR
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
NC
RC6/TX/CK
RC5/SDO1
RC4/SDI1/SDA1
RD3/PSP3/SS2
RD2/PSP2/SDO2
RD1/PSP1/SDI2/SDA2
RD0/PSP0/SCK2/SCL2
RC3/SCK1/SCL1
RC2/CCP1/P1A
RC1/T1OSI/CCP2*
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS1/C2OUT
VDDCORE/VCAP
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2*
RD7/PSP7/P1D 5
4VSS
VDD
VDD
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF-
RA1/AN1
RA0/AN0
PIC18F45J10
= Pins are up to 5.5V tolerant
= Pins are up to 5.5V tolerant
PIC18F45J10 FAMILY
DS39682E-page 4 © 2009 Microchip Technology Inc.
Pin Diagrams (Continued)
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F44J10
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF-
RA1/AN1
RA0/AN0
MCLR
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RC6/TX/CK
RC5/SDO1
RC4/SDI1/SDA1
RD3/PSP3/SS2
RD2/PSP2/SDO2
RD1/PSP1/SDI2/SDA2
RD0/PSP0/SCK2/SCL2
RC3/SCK1/SCL1
RC2/CCP1/P1A
RC1/T1OSI/CCP2*
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS1/C2OUT
VDDCORE/VCAP
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2*
44-Pin TQFP
RD7/PSP7/P1D 5
4
NC
NC
PIC18F45J10
* Pin feature is dependent on device configuration.
= Pins are up to 5.5V tolerant
© 2009 Microchip Technology Inc. DS39682E-page 5
PIC18F45J10 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 23
3.0 Oscillator Configurations ............................................................................................................................................................ 27
4.0 Power-Managed Modes ............................................................................................................................................................. 35
5.0 Reset .......................................................................................................................................................................................... 41
6.0 Memory Organization ................................................................................................................................................................. 51
7.0 Flash Program Memory.............................................................................................................................................................. 71
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 81
9.0 Interrupts .................................................................................................................................................................................... 83
10.0 I/O Ports ..................................................................................................................................................................................... 97
11.0 Timer0 Module ......................................................................................................................................................................... 115
12.0 Timer1 Module ......................................................................................................................................................................... 119
13.0 Timer2 Module ......................................................................................................................................................................... 125
14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 127
15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 135
16.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 149
17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 193
18.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 215
19.0 Comparator Module.................................................................................................................................................................. 225
20.0 Comparator Voltage Reference Module................................................................................................................................... 231
21.0 Special Features of the CPU.................................................................................................................................................... 235
22.0 Instruction Set Summary.......................................................................................................................................................... 249
23.0 Development Support............................................................................................................................................................... 299
24.0 Electrical Characteristics.......................................................................................................................................................... 303
25.0 Packaging Information.............................................................................................................................................................. 337
Appendix A: Revision History............................................................................................................................................................. 349
Appendix B: Migration Between High-End Device Families............................................................................................................... 350
Index .................................................................................................................................................................................................. 353
The Microchip Web Site..................................................................................................................................................................... 363
Customer Change Notification Service .............................................................................................................................................. 363
Customer Support .............................................................................................................................................................................. 363
Reader Response .............................................................................................................................................................................. 364
PIC18F45J10 family Product Identification System ........................................................................................................................... 365
PIC18F45J10 FAMILY
DS39682E-page 6 © 2009 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer No tific atio n Syst em
Register on our web site at www.microchip.com to receive the most current information on all of our products.
© 2009 Microchip Technology Inc. DS39682E-page 7
PIC18F45J10 FAMILY
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational perfor-
mance at an economical price. The PIC18F45J10 family
introduces design enhancements that make these micro-
controllers a logical choice for many high-performance,
power sensitive applications.
1.1 Core Features
1.1.1 LOW POWER
All of the devices in the PIC18F45J10 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
•Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
•Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
•On-the-Fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate
power-saving ideas into their application’s software
design.
•Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 24.0 “Electrical Characteristics”
for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F45J10 family offer three
different oscillator options. These include:
• Two Crystal modes, using crystals or ceramic
resonators
• Two External Clock modes
• INTRC source (approximately 31 kHz)
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
•Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a refer-
ence signal provided by the internal oscillator. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.
•Two-Speed S tart-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F24J10 • PIC18LF24J10
• PIC18F25J10 • PIC18LF25J10
• PIC18F44J10 • PIC18LF44J10
• PIC18F45J10 • PIC18LF45J10
PIC18F45J10 FAMILY
DS39682E-page 8 © 2009 Microchip Technology Inc.
1.2 Other Special Features
• Communications: The PIC18F45J10 family
incorporates a range of serial communication
peripherals, including 1 independent Enhanced
USART and 2 Master SSP modules capable of
both SPI and I2C (Master and Slave) modes of
operation. Also, one of the general purpose I/O
ports can be reconfigured as an 8-bit Parallel
Slave Port for direct processor-to-processor
communications.
•Self-Programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, it becomes possible to create an
application that can update itself in the field.
•Extended Instruction Set: The PIC18F45J10
family introduces an optional extension to the
PIC18 instruction set, which adds 8 new instruc-
tions and an Indexed Addressing mode. This
extension, enabled as a device configuration
option, has been specifically designed to optimize
re-entrant application code originally developed in
high-level languages, such as C.
•Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include Auto-Shutdown, for
disabling PWM outputs on interrupt or other select
conditions and Auto-Restart, to reactivate outputs
once the condition has cleared.
•Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the
LIN/J2602 protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution.
•10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
•Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 24.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Indi vidual Family
Members
Devices in the PIC18F45J10 family are available in
28-pin and 40/44-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in five
ways:
1. Flash program memory (16 Kbytes for
PIC18F24J10/44J10 devices and 32 Kbytes for
PIC18F25J10/45J10).
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectional ports on 28-pin devices,
5 bidirectional ports on 40/44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP mod-
ules, 40/44-pin devices have one standard CCP
module and one ECCP module).
5. Parallel Slave Port (present only on 40/44-pin
devices).
6. One MSSP module for PIC18F24J10/25J10
devices and 2 MSSP modules for
PIC18F44J10/45J10 devices
7. Parts designated with an “F” part number (i.e.,
PIC18F25J10) have a minimum VDD of 2.7 volts,
whereas parts designated with an “LF” part
number (i.e., PIC18LF25J10) can operate
between 2.0-3.6 volts on VDD; however,
VDDCORE should never exceed VDD.
All of the other features for devices in this family are
identical. These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
The PIC18F45J10 family of devices provides an on-chip
voltage regulator to supply the correct voltage levels to
the core. Parts designated with an “F” part number (such
as PIC18F25J10) have the voltage regulator enabled.
These parts can run from 2.7-3.6 volts on VDD but should
have the VDDCORE pin connected to VSS through a low-
ESR capacitor. Parts designated with an “LF” part
number (such as PIC18LF24J10) do not enable the
voltage regulator. An external supply of 2.0-2.7 Volts has
to be supplied to the VDDCORE pin while 2.0-3.6 Volts
can be supplied to VDD (VDDCORE should never exceed
VDD). See Section 21.3 “On-Chip Voltage Regulator”
for more details about the internal voltage regulator.
© 2009 Microchip Technology Inc. DS39682E-page 9
PIC18F45J10 FAMILY
TABLE 1-1: DEVICE FEATURES
Features PIC18F24J10 PIC18F25J10 PIC18F44J10 PIC18F45J10
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 16384 32768 16384 32768
Program Memory
(Instructions)
8192 16384 8192 16384
Data Memory (Bytes) 1024 1024 1024 1024
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 3 3 3 3
Capture/Compare/PWM Modules 2 2 1 1
Enhanced
Capture/Compare/PWM Modules
0011
Serial Communications MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Parallel Communications (PSP) No No Yes Yes
10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR(1),
RESET Instruction,
Stack Full, Stack
Underflow (PWRT,
OST),
MCLR, WDT
POR, BOR(1),
RESET Instruction,
Stack Full, Stack
Underflow (PWRT,
OST),
MCLR, WDT
POR, BOR(1),
RESET Instruction,
Stack Full, Stack
Underflow (PWRT,
OST),
MCLR, WDT
POR, BOR(1),
RESET Instruction,
Stack Full, Stack
Underflow (PWRT,
OST),
MCLR, WDT
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
Packages 28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin PDIP
44-pin QFN
44-pin TQFP
Note 1: BOR is not available in PIC18LF2XJ10/4XJ10 devices.
PIC18F45J10 FAMILY
DS39682E-page 10 © 2009 Microchip Technology Inc.
FIGURE 1-1: PIC18F 24 J10 /25 J1 0 (2 8- PI N) BL OCK DIA GRA M
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA5/AN4/SS1/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
Data Latch
Data Memory
(1 Kbyte)
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2(1)
PCLATU
PCU
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
RB4/KBI0/AN11
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSARTComparator MSSP
10-Bit
ADC
Timer2Timer1Timer0
CCP2CCP1
W
Instruct ion Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out(2)
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
Block
INTRC
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
BOR(2)
OSC1
OSC2
VDD,VSS
MCLR
T1OSI
T1OSO
VDDCORE
© 2009 Microchip Technology Inc. DS39682E-page 11
PIC18F45J10 FAMILY
FIGURE 1-2: PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
PORTE
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
OSC2
VDD,
Brown-out(2)
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR
Block
INTRC
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
PORTA
PORTB
PORTC
RA5/AN4/SS1/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSARTComparator MSSP
10-Bit
ADC
Timer2Timer1Timer0
CCP2ECCP1
BOR(2)
PORTD
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VDDCORE
PIC18F45J10 FAMILY
DS39682E-page 12 © 2009 Microchip Technology Inc.
TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS
Pin Name
Pin N um b e r Pin
Type Buffer
Type Description
SPDIP,
SOIC,
SSOP QFN
MCLR
MCLR
126
IST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
OSC1/CLKI
OSC1
CLKI
96
I
I
—
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. See related OSC2/CLKO pins.
OSC2/CLKO
OSC2
CLKO
10 7
O
O
—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39682E-page 13
PIC18F45J10 FAMILY
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
227
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
RA1/AN1
RA1
AN1
328
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
41
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA5/AN4/SS1/C2OUT
RA5
AN4
SS1
C2OUT
74
I/O
I
I
O
TTL
Analog
TTL
—
Digital I/O.
Analog Input 4.
SPI slave select input.
Comparator 2 output.
TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin N um b e r Pin
Type Buffer
Type Description
SPDIP,
SOIC,
SSOP QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F45J10 FAMILY
DS39682E-page 14 © 2009 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
21 18
I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O.
External Interrupt 0.
PWM Fault input for CCP1.
Analog input 12.
RB1/INT1/AN10
RB1
INT1
AN10
22 19
I/O
I
I
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
Analog input 10.
RB2/INT2/AN8
RB2
INT2
AN8
23 20
I/O
I
I
TTL
ST
Analog
Digital I/O.
External Interrupt 2.
Analog input 8.
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
24 21
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog Input 9.
Capture 2 input/Compare 2 output/PWM2 output.
RB4/KBI0/AN11
RB4
KBI0
AN11
25 22
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog Input 11.
RB5/KBI1/T0CKI/
C1OUT
RB5
KBI1
T0CKI
C1OUT
26 23
I/O
I
I
O
TTL
TTL
ST
—
Digital I/O.
Interrupt-on-change pin.
Timer0 external clock input.
Comparator 1 output.
RB6/KBI2/PGC
RB6
KBI2
PGC
27 24
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28 25
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2 : PI C18F24 J10 /25J 10 PINO UT I/O DES CRIPT IONS (CO NTINUED)
Pin Name
Pin N um b e r Pin
Type Buffer
Type Description
SPDIP,
SOIC,
SSOP QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39682E-page 15
PIC18F45J10 FAMILY
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 8
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
12 9
I/O
I
I/O
ST
Analog
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
RC2/CCP1
RC2
CCP1
13 10
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
14 11
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
15 12
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
16 13
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 14
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
18 15
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
VDD 20 17 P — Positive supply for logic and I/O pins.
VDDCORE/VCAP
VDDCORE
VCAP
63
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin N um b e r Pin
Type Buffer
Type Description
SPDIP,
SOIC,
SSOP QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F45J10 FAMILY
DS39682E-page 16 © 2009 Microchip Technology Inc.
TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
MCLR
MCLR
11818
IST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
OSC1/CLKI
OSC1
CLKI
13 32 30
I
I
—
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. See related OSC2/CLKO pins.
OSC2/CLKO
OSC2
CLKO
14 33 31
O
O
—
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39682E-page 17
PIC18F45J10 FAMILY
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
21919
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
RA1/AN1
RA1
AN1
32020
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
42121
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52222
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA5/AN4/SS1/C2OUT
RA5
AN4
SS1
C2OUT
72424
I/O
I
I
O
TTL
Analog
TTL
—
Digital I/O.
Analog Input 4.
SPI slave select input.
Comparator 2 output.
TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F45J10 FAMILY
DS39682E-page 18 © 2009 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
33 9 8
I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O.
External Interrupt 0.
PWM Fault input for Enhanced CCP1.
Analog input 12.
RB1/INT1/AN10
RB1
INT1
AN10
34 10 9
I/O
I
I
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
Analog input 10.
RB2/INT2/AN8
RB2
INT2
AN8
35 11 10
I/O
I
I
TTL
ST
Analog
Digital I/O.
External Interrupt 2.
Analog input 8.
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
36 12 11
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog Input 9.
Capture 2 input/Compare 2 output/PWM2 output.
RB4/KBI0/AN11
RB4
KBI0
AN11
37 14 14
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog Input 11.
RB5/KBI1/C1OUT
RB5
KBI1
C1OUT
38 15 15
I/O
I
O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Comparator 1 output.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming
clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
TABLE 1-3 : PI C18F44 J10 /45J 10 PINO UT I/O DES CRIPT IONS (CO NTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39682E-page 19
PIC18F45J10 FAMILY
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 34 32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
16 35 35
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 output.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
18 37 37
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
23 42 42
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
24 43 43
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 44 44
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
26 1 1
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F45J10 FAMILY
DS39682E-page 20 © 2009 Microchip Technology Inc.
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
RD0/PSP0/SCK2/
SCL2
RD0
PSP0
SCK2
SCL2
19 38 38
I/O
I/O
I/O
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Slave Port data.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C™ mode.
RD1/PSP1/SDI2/SDA2
RD1
PSP1
SDI2
SDA2
20 39 39
I/O
I/O
I
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Slave Port data.
SPI data in.
I2C data I/O.
RD2/PSP2/SDO2
RD2
PSP2
SDO2
21 40 40
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
SPI data out.
RD3/PSP3/SS2
RD3
PSP3
SS2
22 41 41
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
RD4/PSP4
RD4
PSP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD5/PSP5/P1B
RD5
PSP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD6/PSP6/P1C
RD6
PSP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD7/PSP7/P1D
RD7
PSP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
TABLE 1-3 : PI C18F44 J10 /45J 10 PINO UT I/O DES CRIPT IONS (CO NTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc. DS39682E-page 21
PIC18F45J10 FAMILY
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
82525
I/O
I
I
ST
TTL
Analog
Digital I/O.
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
92626
I/O
I
I
ST
TTL
Analog
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 27 27
I/O
I
I
ST
TTL
Analog
Digital I/O.
Chip Select control for Parallel Slave Port
(see related RD and WR pins).
Analog input 7.
VSS 12, 31 6, 30,
31
6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29
7, 28 P — Positive supply for logic and I/O pins.
VDDCORE/VCAP
VDDCORE
VCAP
62323
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
NC — 13 12, 13,
33, 34
— — No connect.
TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
PIC18F45J10 FAMILY
DS39682E-page 22 © 2009 Microchip Technology Inc.
NOTES: