IDT49C465AGB - Integrated Device Technology, Inc.

Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc. 11.7 DSC-9028/7

32-BIT FLOW-THRU

ERROR DETECTION

AND CORRECTION UNIT

IDT49C465

IDT49C465A

The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc.

FEATURES

• 32-bit wide Flow-thruEDC unit, cascadable to 64 bits

• Single-chip 64-bit Generate Mode

• Separate system and memory buses

• On-chip pipeline latch with external control

• Supports bidirectional and common I/O memories

• Corrects all single-bit errors

• Detects all double-bit errors, some multiple-bit errors

• Error Detection Time — 12ns

• Error Correction Time — 14ns

• On chip diagnostic registers.

• Parity generation and checking on system data bus

• Low power CMOS — 100mA typical at 20MHZ

• 144-pin PGA and PQFP packages

• Military product compliant to MIL-STD 883, Class B

DESCRIPTION

The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC

unit. The chip provides single-error correction and two and

three bit error detection of both hard and soft memory errors.

It can be expanded to 64-bit widths by cascading 2 units,

without the need for additional external logic. The Flow-

thruEDC has been optimized for speed and simplicity of

control.

The EDC unit has been designed to be used in either of two

configurations in an error correcting memory system. The

bidirectional configuration is most appropriate for systems

using bidirectional memory buses. A second system

configuration utilizes external octal buffers, and is well suited

for systems using memory with separate I/O buses.

The IDT49C465/A supports partial word writes, pipelining

and error diagnostics. It also provides parity protection for

data on the system side.

2552 drw 01

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

Latch Memory

Checkbit

Generator

Checkbit

Latch Mux

Byte

Mux System

Checkbit

Generator Mux

Detect

Logic

Correct

Logic

Expansion

Logic

Syndrome

Generator

Latch

Pipeline

Latch

MD0–31

MLE

CBI0–7

PCBI0–7

SD0–31

SLE

PLE CONTROL

CONTROL

CBO0–7

MERR

ERR

11.7 2

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

PQFP

TOP VIEW

2552 drw 02

49C465Y

PQ144-2

144109

108

72 37

GND

MOE

MLE

GND

SLE

PLE

SOE

GND

SD3

PCBI

CODE ID

GND

MODE

MERR

ERR

SYO

SY0

GND

SY0

SYO

VCC

CBI

GND

CBI

CLEAR

SCLKEN

SYNCLK

MODE 2

GND

PERR

PSEL

CBO

CBOE

CBO

11.7 3

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

2552 drw 03

PGA (CAVITY UP)

TOP VIEW

ABC DEFGHJ KLMNP R

VCC SD 2

SD 6SD 4

SD 5

SD 7

SD 10SD 12

SD 11

SD 9

SD 15

SD 13

SD 19SD 17

SD 18 SD 20

SD 25SD 22SD 21

SD 28SD 26

SD 23

SD 27 SD 29

SD 14

SD 16

PCBI 6PCBI 5

PCBI 4PCBI 7

BE 0SD 3SD 0

PCBI 3

PCBI 1

VCC

SD 8

BE 1GND

SLE

SOE PLE GND

BE 2

GND SD 24 BE 3

VCC

VCC SD 30

SD 31

CB0 1CB0 3

CB0 2

CB0 5

CB0 0CBOE

CB0 4

CB0 7

CB0 6

PERRPSEL

GND

MODE

SCLK

SYN-

CLK

GND

CB1 0

CB1 6

CB1 3

CB1 1

CB1 7

CB1 4

CB1 2

CLEAR CB1 5VCC

MD 31

MD 30

MD 29

MD 26

MD 24

MD 22

MD 19

MD 18

MD 16MD 17

MD 28

MD 25

MD 23

MD 21

VCC

MD 27

GND

MD 20

GND

MD 14MOE MLE

MD 15MD 13

MD 12

MD 11MD 10MD 7

MD 4MD 8GND

MD 9MD 6MD 3

VCC

VCCGNDGNDGND

CODE

ID 1CODE

ID 0

PCBI 0SD 1

PCBI 2

MODE

1MERR ERR

MODE

MD 1

MD 5

MD 2VCC

SYO 7

SYO 6SYO 4

SYO 5

SYO 2

SYO 0

SYO 3

MD 0

SYO 1

G144-2

NC*

*Tied to Vcc internally

11.7 4

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

2552 drw 04

DETAILED FUNCTIONAL BLOCK DIAGRAM

MUX

ERROR

DETECT

PIPE

LATCH

PARITY

GEN

PARITY

CHECK

CONTROL

LOGIC

MUX MUX

MUX

INTERNAL

FINAL

SYNDRO

SYNDROME

GENERATOR

MUX ERROR DATA LATCH

DIAGNOSTIC

LATCHES

BYTE MUX

CLEAR

INTERNAL SYNCLK

CHECKBIT

GENERATOR

MUX CHECK

BIT

LATCH MUX

LATCH

CHECKBIT

GENERATOR

CHECKBIT

GENERATOR

8 8

ERR

MERR

SYO0–7

PLE

SOE

BE0–3

SD0–31

SLE

PSEL

P0–3

PERR

SYNCLK

SCLKEN

CLEAR

MODE0–2

CODE ID 0,1

PCBI0–7

CBOE

CBO0–7

MOE

MD0–31

CBI0–7

MLE

PCBI 0–7

BE 0–3

INTERNAL SYNCLK

/ERR

Dashed Line = Diagnostic path

ERROR

CORRECT

1 OF 4

BYTES

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SYSTEM CONFIGURATIONS

The IDT49C465 EDC unit can be used in various

configurations in an EDC system. The basic configurations

are shown below.

Figure 1 illustrates a bidirectional configuration, which is

most appropriate for systems using bidirectional memory

buses. It is the simplest configuration to understand and use.

During a correction cycle, the corrected data word can be

simultaneously output on both the system bus and memory

bus. Logically, no other parts are required for the correction

function. During partial-word-write operations, the new bytes

are internally combined with the corrected old bytes for

checkbit generation and writing to memory.

Figure 1. Common I/O Configuration

Figure 2 illustrates a separate I/O configuration. This is

appropriate for systems using separate I/O memory buses.

This configuration allows separate input and output memory

buses to be used. Corrected data is output on the SD outputs

for the system and for re-write to memory. Partial word-write

bytes are combined externally for writing and checkbit

generation.

Figure 3 illustrates a third configuration which utilizes

external buffers and is also well suited for systems using

memory with separate I/O buses. Since data from memory

does not need to pass through the part on every cycle, the

EDC system may operate in “bus-watch” mode. As in the

separate I/O configuration, corrected data is output on the SD

outputs.

Figure 4 illustrates the single-chip generate-only mode for

very fast 64-bit checkbit generation in systems that use

separate checkbit-generate and detect-correct units. If this is

not desired, 64-bit checkbit generation and correction can be

done with just 2 EDC units. 64-bit correction is also straight-

forward, fast and requires no extra hardware for the

expansion.

Figure 2. Separate I/O Configuration

Figure 3. Bypassed Separate I/O Configuration

Figure 4. Separate Generate/Correction Units

with 64-Bit Checkbit Generation

BUFFER

MEMORY

OUTPUT BUS

MEMORY

INPUT BUS MEMORY

INPUT BUS

CHECK

BITS OUT CHECK

BITS IN

CBO

64-BIT

GEN.

ONLY

EDC

BUFFER BUFFER BUFFER

CBI

LOWER

DATA UPPER

DATA

EDC EDC

CPU BUS 2552 drw 08

CPU

I/O MEMORY

I/O

CHECKBITS

SD MD

CBI

CBO

EDC

2552 drw 05

EXT.BUFFER

MEMORY

INPUT BUS CHECKBIT

I/O MEMORY

OUTPUT BUS

EXT. BUFFER

CPU BUS

EDC

SD MD

CBICBO

2552 drw 07

CPU

MEMORY

INPUTS

MEMORY

OUTPUTS

CHECKBITS

CBO

CBI

EDC

EXT. BUFFER

2552 drw 06

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FUNCTIONAL DESCRIPTION

The error detection/correction codes consist of a modified

Hamming code; it is identical to that used in the IDT49C460.

32-BIT MODE (CODE ID 1,0=00)

Figure 5. 32-Bit Mode

VCC

CHECKBITS–IN

CHECKBITS–OUT

SYNDROME–OUT

CBO

SYO

PCBI

CBI0–6

CBI7

EDC

2552 drw 09

64-BIT MODE (CODE ID 1,0=10 & 11)

The expansion bus topology is shown in Figure 6. This

topology allows the syndrome bits used by the correction logic

to be generated simultaneously in both parts used in the

expansion. During a 64-bit detection or correction operation,

“Partial-Checkbit” data and “Partial-Syndrome” data is simul-

taneously exchanged between the two EDC units in opposite

directions on dedicated expansion buses. This results in very

short 64-bit detection and correction times.

8 8

8 FINAL

CHECKBITS–OUT

(DETECT AND CORRECT)

CBO

SYO

ERR

PCBI

CBI

UPPER EDC

PARTIAL–CHECKBITS–OUT (10)

(GENERATE ONLY)

PARTIAL–SYNDROME

(DETECT/CORRECT ONLY)

PARTIAL–CHECKBITS–OUT (10)

(GENERATE ONLY)

PARTIAL–CHECKBITS–OUT (11)

(CORRECTION ONLY)

CBO

SYO

PCBI

CBI

CHECKBITS–IN

LOWER EDC

(CODE ID 1,0 = 10) (CODE ID 1,0 = 11)

2552 drw 10

Figure 6. 64-Bit Mode — 2 Cascaded IDT49C465 Devices

64-BIT GENERATE-ONLY MODE (CODE ID 1,0=01)

If the Identity pins CODE ID 1,0 = 01, a single EDC is placed

in the 64-bit “Generate-only” mode. In this mode, the lower 32

bits of the 64-bit data word enter the device on the MD0-31

inputs and the upper 32-bits of the 64 bit data word enter the

Figure 7. 64-Bit "Generate-Only" Mode (Single Chip)

device on the SD0-31 inputs. This provides the device with the

full 64-bit word from memory. The resultant generated

checkbits are output on the CBO0-7 outputs. The generate

time is less than that resulting from using a 2-chip cascade.

CBOMD0–31

SD0–31

EDC

CHECKBITS–OUT

LOWER 32 BITS (0–31)

UPPER 32 BITS (32–63)

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PIN DESCRIPTIONS

Symbol I/O Name and Function

I/O Buses and Controls

SD0-7 I/O System Data Bus: Data from MD0-31 appears at these pins corrected if MODE 2-0 = x11, or uncor-

SD8-15 rected in the other modes. The BEn inputs must be high and the

SOE

pin must be low to enable the SD

SD16-23 output buffers during a read cycle. (Also, see diagnostic section.)

SD24-31 Separate I/O memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on

SDn to n+7 for re-writing to memory, if BE n is high and

SOE

is low. The new bytes to be written to memory

are input on the SDn pins, for writing checkbits to memory, if BEn is low.

Bi-directional memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed

to the MD I/O pins, if BEn is high, for checkbit generation and rewriting to memory via the MD I/O pins.

SOE

must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written

are input on the SDn pins for checkbit generation and writing to memory. BEn must be low to direct input

data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory.

SLE I System Latch Enable: SLE is an input used to latch data at the SD inputs. The latch is transparent when

SLE is high; the data is latched when SLE is low.

PLE

IPipeline Latch Enable:

PLE

is an input which controls a pipeline latch, which controls data to be output on

the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent when

PLE

is low; the data is latched when

PLE

is high.

SOE

ISystem Output Enable: When low, enables System output drivers and Parity output drivers if correspond-

ing Byte Enable inputs are high.

BE0-3 IByte Enables: In systems using separate I/O memory buses, BEn is used to enable the SD and Parity

outputs for byte n. The BEn pins also control the “Byte mux”. When BEn is high, the corrected or uncorrected

data from the Memory Data latch is directed to the MD I/O pins and used for checkbit generation for byte

n. This is used in partial-word-write operations or during correction cycles. When BEn is low, the data from

the System Data latch is directed to the MD I/O pins and used for checkbit generation for byte n.

BE0 controls SD0-7 BE2 controls SD16-23

BE1 controls SD8-15 BE3 controls SD24-31

MD0-31 I/O Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/

or correction. They also output corrected old data or new data to be written to main memory when the EDC

unit is used in a bi-directional configuration.

MLE I Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs.

The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper

slice in a 64-bit cascade, the checkbit latch is bypassed.

MOE

IMemory Output Enable:

MOE

enables Memory Data Bus output drivers when low.

P0-3 I/O Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when

that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating

the Parity ERRor (

PERR

) signal under certain conditions (see Byte Enable definition). The parity is odd or

even depending on the state of the Parity SELect pin (PSEL).

PSEL I Parity SELect: If the Parity SELect pin is low, the parity is even.

If the Parity SELect pin is high, the parity is odd.

Inputs

CBI0-7 ICheckBits-In (00) CheckBits-In-1 (10) Partial-Syndrome-In (11):

In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits

from the checkbit memory. In the upper slice in a cascaded EDC system, these inputs accept the “Partial-

Syndrome” from the lower slice (Detect/Correct path).

PCBI 0-7 IPartial-CheckBits-In (10) Partial-CheckBits-In (11):

In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC

system, the “Partial-Checkbits” used by the lower slice are accepted by these inputs (Correction path only).

In the upper slice of a cascaded EDC system, “Partial-Checkbits” generated by the lower slice are accepted

by these inputs (Generate path).

CODE ID1,0 ICODE IDentity: Inputs which identify the slice position/ functional mode of the IDT49C465.

(00) Single 32-bit EDC unit (10) Lower slice of a 64-bit cascade

(01) 64-bit “Checkbit-generate-only” unit (11) Upper slice of a 64-bit cascade

2552 tbl 01

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PIN DESCRIPTIONS (Con’t.)

Symbol I/O Name and Function

Inputs (Con’t.)

MODE 2-0 IMODE select: Selects one of four operating modes.

(x11) “Normal” Mode: Normal EDC operation (Flow-thru correction and generation).

(x10) “Generate-Detect” Mode: In this mode, error correction is disabled. Error generation and detection are

normal.

(000) “Error-Data-Output” Mode: Allows the uncorrected data captured from an error event by the Error-Data

CLEAR

low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data

from the first error that occurs after they are reset by the

CLEAR

pin. The Syndrome Register and Error-Data

ERR

= low),

and the Error Counter indicates zero.

All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of

all-zero-data for hardware initialization of memory, if this desired.

(x01) Diagnostic-Output Mode: In this mode, the contents of the Syndrome Register , Error Counter and Error-

Type Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read

by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated

when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates

zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred

after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling

CLEAR

low. The Error Counter lets the system tell if more than one error has occurred since the last time

the Syndrome Register or Error-Data Register was read.

(100) Checkbit-Injection Mode: In the “Checkbit-Injection” Mode, diagnostic checkbits may be input on System

Data Bus bits 0-7 (see Diagnostic Features - Detailed Description).

CLEAR

ICLEAR: When the

CLEAR

pin is taken low, the Error-Data Register, the Syndrome Register, the Error

Counter and the Error-Type Register are cleared.

SYNCLK I SYNdrome CLocK: If

ERR

is low, and the Error Counter indicates zero errors, syndrome bits are clocked

into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the

Error-Data Register on the low-to-high edge of SYNCLK. If

ERR

is low, the Error Counter will increment on

the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors.

SCLKEN

ISynCLK ENable: The

SCLKEN

enables the SYNCLK signal. SYNCLK is ignored if

SCLKEN

is high.

Outputs and Enables

CBO0-7 OCheckBits-Out (00, 01) Partial-CheckBits-Out (10) Checkbits-Out (11):

In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice

in a cascaded EDC system, the “Partial-checkbits” used by the upper slice are output by these outputs

(Generate path only). In the upper slice in a cascade, the “Final-Checkbits” appear at these outputs

(Generate path only).

CBOE

ICheckBits Out Enable: Enables CheckBit Output drivers when low.

SYO0-7 OSYndrome-Out (00) Partial-SYndrome-Out (10) Partial-Checkbits-Out (11):

In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded

system, the “Partial-Syndrome” bits appear at these outputs (Detect/ Correct path). In the upper slice in a

cascaded EDC system, the “Partial-Checkbits” appear at these outputs (Correct path only). In a 64-bit

cascaded system, the “Final-Syndrome” may be accessed in the “Diagnostic-Output” Mode from either the

lower or the upper slice since the final syndrome is contained in both.

ERR

OERROR: When in “Normal” and “Detect only” modes, a low on this pin indicates that one or more errors have

been detected.

ERR

is not gated or latched internally.

MERR

OMultiple ERRor: When in “Normal” and “Detect only” modes, a low on this pin indicates that two or more

errors have been detected.

MERR

is not gated or latched internally.

PERR

OParity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by

the 4 Byte Enable pins. Parity ERRor (

PERR

) is not gated or latched internally (see Byte Enable definition).

Power Supply Pins

Vcc 1- 10 P +5 Volts

GND1-12 P Ground

2552 tbl 02

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DIAGNOSTIC DATA FORMAT (SYSTEM BUS)

DIAGNOSTIC FEATURES — DETAILED DESCRIPTION

Mode 2-0

x11 “NORMAL” Mode

In this mode, operation is “Normal” or non-diagnostic.

x10 “GENERATE-DETECT” Mode

When the EDC unit is in the “Generate-Detect” Mode , data is not corrected or altered by the error correction network.

(Also referred to as the “Detect-only” Mode.)

000 “ERROR-DATA-OUTPUT” Mode

In this mode, the 32-bit data from the Error-Data Register is output on the SD bus.

Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register

if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when the

ERR

signal is

low. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was

cleared. This register is cleared by pulling the

CLEAR

input low. The register is read via the System Data bus by entering

the “Error-Data-Output” Mode and enabling the System Data bus output drivers.

All-Zero-Data: The Error-Data Register can be used as an “all-zero-data” data source for memory initialization in systems

where the initialization process is to be done entirely by hardware.

x01 “DIAGNOSTIC-OUTPUT” Mode

In this mode, data from the diagnostic registers, the PCBI bus and the CBI bus is output on the SD bus.

Direct Checkbit Readback: Internal data paths allow both the “Partial-CheckBit-Input” bus and the data in the “CheckBit-

Input” latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial

Checkbit Input Bus are read via the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System

Data bus output drivers. The checkbits are output on System Data bus bits 0-7; the Partial Checkbits are output on bits

8-15.

Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal

Syndrome Register if the error counter contents indicates “0” and there is a positive transition on the SYNCLK input when

the

ERR

signal is low. This register is cleared by pulling the

CLEAR

input low. The register is read via the System Data

bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus outputs. This data is output on SD

bits 16-23.

Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which

corresponds to a count of 15, and there is a positive transition on the SYNCLK input when the

ERR

signal is low. This

counter is cleared by pulling the

CLEAR

input low. The counter is read via the System Data bus by entering the

“Diagnostic-Output” Mode and enabling the System Data bus output drivers. This data is output on System Data bus

bits 24-27.

Test Register: These 2 bits are reserved for factory diagnostics only and must not be used by system software. This data

is output on System Data bus bits 28-29.

Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves 2 bits which indicate whether a

recorded error was a single or a multiple-bit error. This register holds only the first error type to occur after the last Clear

operation. This data is output on System Data bus bits 30-31.

100 Direct Read-Path Checkbit Injection: In the “Checkbit-Injection” Mode, bits 0-7 of the System Data input latch are

presented to the inputs of the Checkbit Input latch. If MLE is strobed, the checkbit latch will be loaded with this value in

place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC

can be verified “on-board”. Except for the “Checkbit-Injection” function, operation in this mode is identical to “Normal” Mode

operation.

2552 tbl 03

Byte 3 Byte 2 Byte 1 Byte 0

Checkbits

08 716 1524 2331

Partial Checkbits

76543210

S M - - 2 2 2 2

Syndrome bits

Error

Counter

Error

Type Re-

served

Latched Data Data Out (Unlatched)

7654321076543210

2552 drw 12

301

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OPERATING MODE CHARTS

SLICE IDENTIFICATION

CODE ID 1 CODE ID 0 Slice Definition

0 0 32-bit Flow-Thru EDC

0 1 64-bit GENERATE Only EDC

1 0 64-bit EDC- Lower 32 bits (0-31)

1 1 64-bit EDC- Upper 32 bits (32-63)

2552 tbl 04

SLICE POSITION CONTROL

Checkbit Buses

Slice Position/

CODE Functional Operation PCBI CBI CBO SYO P

SOE

SD Bus

MOE

MD Bus Bus Bus Bus Bus Bus

PERR

1 0 Width = 32 32 8 8 8 8 4 1

0 0 Single 32-bit EDC unit

Generate(1) 1 Sys. 0–31 0 Sys. Byte Mux — — CBs out — P in active

Detect/Correct(2) 0 Pipe. latch 1 MD 0–31 — CBs in — Syn. out P out —

0 1 “64-bit Generate-only” 1 Sys. 32–63 1 Sys. 0–31 — — CBs out — — —

1 0 Lower word, 64-bit bus

Generate(1) 1 Sys. 0–31 0 MD 0–31 — — PCBs out — P in active

Detect/Correct(2) 0 Pipe. latch 1 MD 0–31 U-SYOout CBs in — Par.Synd P out —

1 1 Upper word, 64-bit bus

Generate(1) 1 Sys. 32–63 0 MD 32–63 L-CBOout — F.CBs out — P in active

Detect/Correct(2) 0 Pipe. latch 1 MD 32–63 — L-SYOout — Par.Cbits P out —

NOTES: 2552 tbl 05

1. Checkbits generated from the data in the SD Latch.

2. Corrected data residing in the Pipe Latch.

PCBI CBI CBO SYO P

FUNCTIONAL MODE CONTROL

Checkbit Buses

Functional Mode

of SD Bus PCBI CBI CBO SYO P

MODE

SOE

SD Bus

MOE

MD Bus Bus Bus Bus Bus Bus

PERR

2 1 0 Width = 32 32 8 8 8 8 4 1

x11 “Normal”

Generate 1 CPU Data 0 Pipe. latch — — CB out — P in active

Correct 0 Pipe. latch 1 RAM Data — CB in — — P out —

x10 “Generate-Detect”

Generate 1 CPU Data 0 Pipe. latch — — CB out — P in active

Detect 0 Pipe. latch 1 RAM Data — CB in — — P out —

000 “Error-Data-Output” 0 Err. D. latch — — — — — — — —

x01 “Diagnostic-Output” 0 CBin latch — — PCBI in CB in — — — —

PCBIin bus

Syn. register

Err. counter

Er. type reg.

100 “Checkbit-Injection”

Generate 1 SDin latch 0 Pipe. latch — — CB out — P in active

Inject Checkbits 1 SD0–7 in 0 Pipe. latch — — — — — —

Correct 0 Pipe. latch 1 RAM Data — CB in — — P out —

2552 tbl 06

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PRIMARY DATA PATH vs. MEMORY CONFIGURATION

CPU

BUFFER

SD MD

PCBO

CBI

IDT49C465

OUT

MAIN

MEMORY

CHECKBIT

MEMORY

CPU SD MD

PCBO

CBI

IDT49C465

I/O

MAIN

MEMORY

CHECKBIT

MEMORY

1. Checkbit Generation

Write New Word to Memory 1. Checkbit Generation

Write New Word to Memory

CPU

BUFFER

SD MD

PCBO

CBI

IDT49C465

OUT

MAIN

MEMORY

CHECKBIT

MEMORY

CPU SD MD

PCBO

CBI

IDT49C465

I/O

MAIN

MEMORY

CHECKBIT

MEMORY

2. Data Correction

Read Memory Word 2. Data Correction

Read Memory Word

CPU

BUFFER

SD MD

PCBO

CBI

IDT49C465

OUT

MAIN

MEMORY

CHECKBIT

MEMORY

CPU SD MD

PCBO

CBI

IDT49C465

I/O

MAIN

MEMORY

CHECKBIT

MEMORY

3. Memory Generation

Re-write Corrected Word to Memory 3. Memory Generation

Re-write Corrected Word to Memory

CORRECTED CORRECTED

CORRECTED

SEPARATE I/O MEMORIES: COMMON I/O MEMORIES:

2552 drw 13

11.7 12

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

In order to perform a partial-word-write operation, the

complete word in question must be read from memory. This

must be done in order to correct any error which may have

occurred in the old word. Once the complete, corrected word

is available, with all the bytes verified, the new word may be

assembled in the byte mux and the new checkbits generated.

PARTIAL-WORD-WRITE OPERATIONS

FOR COMMON I/O MEMORIES:

The example shown above illustrates the case of combin-

ing 3 bytes from an old word with a new lower order byte to

form a new word. The new word, along with the new checkbits,

may now be written to memory.

In the separate I/O memory configuration, the situation is

similar except that the new word is output on the SD Bus

instead of the MD Bus (refer to previous page).

2552 drw 14

B3 = 1

B2 = 1

B1 = 1

B0 = 0

CORRECTION

BLOCK

MD LATCH

SD LATCHPIPE LATCH

SD BUS

BYTE 3

BYTE 2

BYTE 1

BYTE 0

BYTE 3

BYTE 2

BYTE 1

BYTE 0

MD BUS

MAIN

MEMORY

CHECKBIT

MEMORY

CHECKBIT

GENERATOR

CBO

CBI

BYTE

MUX

IDT49C465

11.7 13

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT DATA WORD CONFIGURATION

A single IDT49C465 EDC unit, connected as shown below,

provides all the logic needed for single-bit error correction,

and double-bit error detection, of a 32-bit data field. The

identification code (00) indicates 7 checkbits are required.

The CBI7 pin should be tied high.

The 39-bit data format for four bytes of data and 7 checkbits

is indicated below.

Syndrome bits are generated by an exclusive-OR of the

generated checkbits with the checkbits read from memory.

For example, Sn is the XOR of checkbits from those read with

those generated. During Data Correction, the syndrome bits

are used to complement (correct) single-bit errors in the data

bits.

32-BIT DATA FORMAT

32-BIT HARDWARE CONFIGURATION

BYTE 3 BYTE 2 BYTE 1 BYTE 0

DATA CHECKBITS

C0C1C2C3C4C5C6

08 716 1524 2331 2552 drw 15

PCBI0–7

CBI7

CBI0–6

CBO0–6

SYO0–6

ERR

MERR

MD0–31

P0–3

SD0–31

SYNDROME–OUT

MEMORY DATA I/O

CHECKBITS–OUT

CHECKBITS–IN

SYSTEM DATA I/O

CODE ID 1,0 = 00

VCC

32 32

IDT49C465 2552 drw 16

11.7 14

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

64-BIT DATA WORD CONFIGURATION

Two IDT49C465 EDC units, connected as shown below,

provide all the logic needed for single-bit error correction, and

double-bit error detection, of a 64-bit data field. The “Slice

Identification” Table gives the CODE ID1,0 values needed for

distinguishing the upper 32 bits from the lower 32 bits. Final

generated checkbits,

ERR

and

MERR

(indicates multiple

errors) signals come from the upper slice, the IC with CODE

ID1,0=11. Control signals not shown are connected to both

units in parallel.

Data-In bits 0 through 31 are connected to the same

numbered inputs of the EDC with CODE ID1,0=10, while

Data-In bits 32 through 63 are connected to data inputs 0 to

31, respectively, for the EDC unit with CODE ID1,0=11.

The 72-bit data format of data and checkbits is indicated

below.

Correction of single-bit errors in the 64-bit configuration

requires a simultaneous exchange of partial checkbits and

partial syndrome bits between the upper and lower units.

Syndrome bits are generated by an exclusive-OR of the

generated checkbits with the checkbits read from memory.

For example, Sn is the XOR of checkbits read and checkbits

generated. During data correction, the syndrome bits are

used to complement (correct) single-bit errors in the data bits.

For double or multiple-bit error detection, the data available as

output by the Pipeline Latch is not defined.

Critical AC performance data is provided in the Table “Key

AC Calculations”, which illustrates the delays that are critical

to 64-bit cascaded performance. As indicated, a summation

of propagation delays is required when cascading these units.

64-BIT DATA FORMAT

64-BIT HARDWARE CONFIGURATION

BYTE 2 BYTE 1 BYTE 0

DATA CHECKBITS

C0C1C2C3C4C5C6

08 716 1524 23

BYTE 4 BYTE 5BYTE 6BYTE 7

32 3148 47 40 3956 5563

BYTE 3

2552 drw 17

PCBI0–7 PARTIAL–CHECKBITS

(GENERATE ONLY)

CBI0–7

P0–3

SD0–31

SYO0–7

CBO0–7

IDT49C465

LOWER EDC

(CODE ID 1,0 = 10)

PCBI0–7

CBI0–7

P0–3

SD0–31 MD0–31

SYO0–7

CBO0–7

IDT49C465

UPPER EDC

(CODE ID 1,0 = 11)

CHECKBITS–IN

SYSTEM DATA 0–31

SYSTEM DATA 32–63

PARTIAL–SYNDROME

(DETECT/CORRECT)

PARTIAL–CHECKBITS (CORRECT ONLY)

FINAL CHECKBITS

(GENERATE ONLY)

(DETECT AND CORRECT)

MEMORY DATA 32–63

MEMORY DATA 0–31

8ERR

MERR

2552 drw 18

11.7 15

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEFINITIONS OF TERMS:

D0 – D31 = System Data and/or Memory Data Inputs

CBI0 – CBI7= Checkbit Inputs

PCBI0 – PCBI7= Partial Checkbit Inputs

FS0 – FS7= Final Internal Syndrome bits

FUNCTIONAL EQUATIONS:

The equations below describe the terms used in the

IDT49C465 to determine the values of the partial checkbits,

checkbits, partial syndromes and final internal syndromes.

NOTE: All “⊕” symbols below represent the “EXCLUSIVE-

OR” function.

PA = D0 ⊕ D1 ⊕ D2 ⊕ D4 ⊕ D6 ⊕ D8 ⊕ D10 ⊕ D12 ⊕ D16 ⊕ D17

⊕ D18 ⊕ D20 ⊕ D22 ⊕ D24 ⊕ D26 ⊕ D28

PB = D0 ⊕ D3 ⊕ D4 ⊕ D7 ⊕ D9 ⊕ D10 ⊕ D13 ⊕ D15 ⊕ D16 ⊕ D19

⊕ D20 ⊕ D23 ⊕ D25 ⊕ D26 ⊕ D29 ⊕ D31

PC = D0 ⊕ D1 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D16 ⊕ D17

⊕ D21 ⊕ D22 ⊕ D23 ⊕ D27 ⊕ D28 ⊕ D29

PD = D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D14 ⊕ D15 ⊕ D18 ⊕ D19

⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23 ⊕ D30 ⊕ D31

PE = D8 ⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D24

⊕ D25 ⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31

PF = D0 ⊕ D1 ⊕ D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D24 ⊕ D25

⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31

PG = D8 ⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D16

⊕ D17 ⊕ D18 ⊕ D19 ⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23

PH0 = D0 ⊕ D4 ⊕ D6 ⊕ D7 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18

⊕ D19 ⊕ D21 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31

PH1 = D1 ⊕ D2 ⊕ D3 ⊕ D5 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18

⊕ D19 ⊕ D21 ⊕ D24 ⊕ D25 ⊕ D27 ⊕ D30

PH2 = D0 ⊕ D4 ⊕ D6 ⊕ D7 ⊕ D10 ⊕ D12 ⊕ D13 ⊕ D15 ⊕ D16 ⊕

D20 ⊕ D22 ⊕ D23 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31

CMOS TESTING CONSIDERATIONS

Special test board considerations must be taken into

account when applying high-speed CMOS products to the

automatic test environment. Large output currents are being

switched in very short periods and proper testing demands

that test set-ups have minimized inductance and guaranteed

zero voltage grounds. The techniques listed below will assist

the user in obtaining accurate testing results:

1) All input pins should be connected to a voltage potential

during testing. If left floating, the device may oscillate,

causing improper device operation and possible latchup.

2) Placement and value of decoupling capacitors is critical.

Each physical set-up has different electrical

characteristics and it is recommended that various

decoupling capacitor sizes be experimented with.

Capacitors should be positioned using the minimum lead

lengths. They should also be distributed to decouple

power supply lines and be placed as close as possible to

the DUT power pins.

3) Device grounding is extremely critical for proper device

testing. The use of multi-layer performance boards with

radial decoupling between power and ground planes is

necessary. The ground plane must be sustained from the

performance board to the DUT interface board and wiring

unused interconnect pins to the ground plane is recom-

mended. Heavy gauge stranded wire should be used for

power wiring, with twisted pairs being recommended for

minimized inductance.

4) To guarantee data sheet compliance, the input thresholds

should be tested per input pin in a static environment. To

allow for testing and hardware-induced noise, IDT recom-

mends using VIL ≤ 0V and VIH ≥ 3V for AC tests.

11.7 16

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION — CHECKBIT AND

SYNDROME GENERATION vs. CODE ID

LOGIC EQUATIONS FOR THE CBO OUTPUTS

CODE ID 1,0

Checkbit 00 10 11

Generation Final Chkbits Partial Checkbits Final Checkbits

CBO0PH0PH1PH2 ⊕ PCBI0

CBO1PA PA PA ⊕ PCBI1

CBO2

PB PB

PB ⊕ PCBI2

CBO3

PC PC

PC ⊕ PCBI3

CBO4PD PD PD ⊕ PCBI4

CBO5PE PE PE ⊕ PCBI5

CBO6PF PF PF ⊕ PCBI6

CBO7— PF PG ⊕ PCBI7

2552 tbl 07

LOGIC EQUATIONS FOR THE SYO OUTPUTS

Checkbit/ CODE ID 1,0

Syndrome 00 10 11

Generation Final Syndrome Partial Syndrome Partial Checkbits

SYO0 PH0 ⊕ CBI0 PH1 ⊕ CBI0 PH2

SYO1 PA ⊕ CBI1 PA ⊕ CBI1 PA

SYO2

⊕ CBI2

⊕ CBI2 PB

SYO3

⊕ CBI3

⊕ CBI3 PC

SYO4 PD ⊕ CBI4 PD ⊕ CBI4 PD

SYO5 PE ⊕ CBI5 PE ⊕ CBI5 PE

SYO6 PF ⊕ CBI6 PF ⊕ CBI6 PF

SYO7 — PF ⊕ CBI7 PG

2552 tbl 08

32-BIT SYNDROME DECODE TO BIT-IN-ERROR (1)

HEX 01234567

S6 00001111

Syndrome S5 00110011

Bits S4 01010101

HEX S3 S2 S1 S0

0 0 0 0 0 * C4 C5 T C6 T T 30

10001 C0TT14TMMT

2 0 0 1 0 C1 T T M T 2 24 T

30011 T188TMTTM

4 0 1 0 0 C2T T15T 325T

5 0 1 0 1 T 19 9 T M T T 31

6 0 1 1 0 T 20 10 T M T T M

70111 MTTMT426T

8 1 0 0 0 C3 T T M T 5 27 T

9 1 0 0 1 T 21 11 T M T T M

A 1 0 1 0 T 22 12 T 1 T T M

B 1 0 1 1 17 T T M T 6 28 T

C 1 1 0 0 T 23 13 T M T T M

D1101 MTTMT729T

E 1110 16TTMTMMT

F 1111 TMMT0TTM

NOTES: 2552 tbl 12

1. The table indicates the decoding of the seven syndrome bits to identify the

bit-in-error for a single-bit error, or whether a double or triple-bit error was

detected. The all-zero case indicates no error detected.

* = No errors detected

# = The number of the single bit-in-error

T = Two errors detected

M = Three or more errors detected

LOGIC EQUATIONS FOR THE FINAL SYNDROME (FSn)

Final CODE ID 1,0

Syndrome 00 10, 11

Generation Final Syndrome Final Internal Syndrome

FS0PH0 ⊕ CBI0PH1 (L) ⊕ PH2 (U) ⊕ CBI0

FS1PA ⊕ CBI1PA (L) ⊕ PA (U) ⊕ CBI1

FS2

⊕ CBI2PB (L) ⊕ PB (U) ⊕ CBI2

FS3

⊕ CBI3PC (L) ⊕ PC (U) ⊕ CBI3

FS4PD ⊕ CBI4PD (L)⊕ PD (U) ⊕ CBI4

FS5PE ⊕ CBI5PE (L) ⊕ PE (U) ⊕ CBI5

FS6PF ⊕ CBI6PF (L) ⊕ PF (U) ⊕ CBI6

FS7— PF (L) ⊕ PG (U)⊕ CBI7

2552 tbl 09

11.7 17

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION — 32-BIT CONFIGURATION

32-BIT MODIFIED HAMMING CODE — CHECKBIT ENCODING CHART(1)

Generated Participating Data Bits

Checkbits Parity 0123456789101112131415

CB0 Even (XOR) X X XXXX X X

CB1 Even (XOR) X X XXXXXX

CB2 Odd (XNOR) X X X X X X X X

CB3 Odd (XNOR) X X X X X X X X

CB4 Even (XOR) XXXXXX XX

CB5 Even (XOR) X X X XXXXX

CB6 Even (XOR) XXXXXXXX

2552 tbl 10

Generated Participating Data Bits

Checkbits Parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CB0 Even (XOR) X X X X X X X X

CB1 Even (XOR) X X XXXXXX

CB2 Odd (XNOR) X X X X X X X X

CB3 Odd (XNOR) X X X X X X X X

CB4 Even (XOR) XXXXXX XX

CB5 Even (XOR) X X X XXXXX

CB6 Even (XOR) X X X XXXXX

NOTE: 2552 tbl 11

1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 16 data input bits

marked with an X.

11.7 18

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

Generated Participating Data Bits

Checkbits Parity 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

CB0 Even (XOR) X X X X X X X X

CB1 Even (XOR) X X X XXXXX

CB2 Odd (XNOR) X X X X X X X X

CB3 Odd (XNOR) X X X X X X X X

CB4 Even (XOR) X X XXXX XX

CB5 Even (XOR) XXXXXXXX

CB6 Even (XOR) XXXXXXXX

CB7 Even (XOR) XXXXXXXX

2552 tbl 15

Generated Participating Data Bits

Checkbits Parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CB0 Even (XOR) X X X X X X X X

CB1 Even (XOR) X X X XXXXX

CB2 Odd (XNOR) X X X X X X X X

CB3 Odd (XNOR) X X X X X X X X

CB4 Even (XOR) X X XXXX XX

CB5 Even (XOR) XXXXXXXX

CB6 Even (XOR) XXXXXXXX

CB7 Even (XOR) XXXXXXXX

2552 tbl 14

Generated Participating Data Bits

Checkbits Parity 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

CB0 Even (XOR) X X X X X X X X

CB1 Even (XOR) X X X XXXXX

CB2 Odd (XNOR) X X X X X X X X

CB3 Odd (XNOR) X X X X X X X X

CB4 Even (XOR) X X XXXX XX

CB5 Even (XOR) XXXXXXXX

CB6 Even (XOR) XXXXXXXX

CB7 Even (XOR) XXXXXXXX

NOTES: 2552 tbl 16

1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 64 data input bits

marked with an X.

2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an “X” in the table.

DETAILED DESCRIPTION — 64-BIT CONFIGURATION

64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART(1, 2)

Generated Participating Data Bits

Checkbits Parity 0123456789101112131415

CB0 Even (XOR) X X X X X X X X

CB1 Even (XOR) X X X XXXXX

CB2 Odd (XNOR) X X X X X X X X

CB3 Odd (XNOR) X X X X X X X X

CB4 Even (XOR) X X XXXX XX

CB5 Even (XOR) XXXXXXXX

CB6 Even (XOR) XXXXXXXX

CB7 Even (XOR) XXXXXXXX

2552 tbl 13

11.7 19

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION — 64-BIT CONFIGURATION (Con’t.)

64-BIT SYNDROME DECODE TO BIT-IN-ERROR(1)

HEX 0123456789ABCDEF

S7 0000000011111111

S6 0000111100001111

Syndrome S5 0011001100110011

Bits S4 0101010101010101

HEX S3 S2 S1 S0

00000 *C4C5TC6TT62C7TT46TMM

10001 C0TT14TMMTTMMTMTT

20010 C1TTMT3456TT5040TMTT

30011 T188TMTTMMTTMT224

40100 C2TT15T3557TT5141TMTT

50101 T199TMTT63MTT47T325

60110 T2010TMTTMMTTMT426

70111 MTTMT3658TT5242TMTT

81000 C3TTMT3759TT5343TMTT

91001 T2111TMTTMMTTMT527

A1010 T2212T33TTM49TTMT628

B1011 17TTMT3860TT5444T1TT

C1100 T2313TMTTMMTTMT729

D1101 MTTMT3961TT5545TMTT

E1110 16TTMTMMTTMMT0TT

F1111 TMMT32TTM48TTMTMM

NOTES: 2552 tbl 17

1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was

detected. The all-zero case indicates no error detected.

* = No errors detected

# = The number of the single bit-in-error

T = Two errors detected

M = Three or more detected

KEY AC CALCULATIONS — 64-BIT CASCADED CONFIGURATION

64-Bit Propagation Delay Total AC Delay for IDT49C465 in 64-bit Mode

(L) = Lower slice

Mode From To (U) = Upper slice

Generate SD Bus Checkbits out SD to CBO(L) + PCBI to CBO(U)

t SC(L) + t PCC(U)

Detect MD Bus

ERR

for 64-bits MD to SYO(L) + CBI to

ERR

(U)

t MSY(L) + t CE (U)

MD Bus

MERR

for 64-bits MD to SYO(L) + CBI to

M ERR

t MSY(L) + t CME (

)

Correct MD Bus Corrected data out MD to SYO(L) + CBI to SD(U)

t MSY(L) + t CS (U)

(or) → MD to SYO(U) + PCBI to SD(L)

t MSY(U) + t PCS(L)

NOTE: 2552 tbl 18

1. (or) = Whichever is worse.

11.7 20

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter(1) Conditions Pkg. Typ. Unit

CIN Input VIN = 0V PGA 10 pF

Capacitance PQFP 5

COUT Output VOUT = 0V PGA 12 pF

Capacitance PQFP 7

NOTE: 2552 tbl 20

1. This parameter is sampled and not 100% tested.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Rating Com’l. Mil. Unit

VCC Power Supply –0.5 to +7.0 –0.5 to +7.0 V

Voltage

VTERM Terminal Voltage –0.5 to –0.5 to V

with Respect VCC + 0.5 VCC + 0.5

to Ground

TAOperating 0 to +70 –55 to +125 °C

Temperature

TBIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

TSTG Storage –55 to +125 –65 to +150 °C

Temperature

IOUT DC Output 30 30 mA

Current

NOTE: 2552 tbl 19

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to Absolute Maximum Ratings for

extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

The following conditions apply unless otherwise specified:

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

VIH Input HIGH Level(4) Guaranteed Logic HIGH Normal Inputs 2.0 — — V

Hysteresis Inputs 3.0 — —

VIL Input LOW Level(4) Guaranteed Logic LOW — — 0.8 V

IIH Input HIGH Current VCC = Max., VIN = VCC — — 5.0 µA

IIL Input LOW Current VCC = Max., VIN = GND — — –5.0 µA

IOZ Off State (Hi-Z) V CC = Max. VO = 0V — — –10 µA

VO = 3V — — 10

IOS Short Circuit Current VCC = Max.(3) –20 — –150 mA

VOH Output HIGH Voltage VCC = Min. IOH = –6mA COM’L. 2.4 — — V

VIN = VIH or VIL IOH = –4mA MIL. 2.4 — —

VOL Output LOW Voltage VCC = Min. IOL = 12mA COM’L. — — 0.5 V

VIN = VIH or VIL IOL = 6mA MIL. — — 0.5

VHHysteresis

CLEAR

, MLE,

PLE

, SLE,

SYNCLK

SCLKEN

— 200 — mV

NOTES: 2552 tbl 21

1. For conditions shown as min. or max., use appropriate value specified above for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient temperature and maximum loading.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

11.7 21

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con’t.)

The following conditions apply unless otherwise specified:

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

ICCQ Quiescent Power Supply Current VIN = VCC or GND — — 5 mA

CMOS Input Levels VCC = Max. All Inputs

Outputs Disabled

ICCQT Quiescent Power Supply Current VIH = 3.4V, VIL = 0V — — 1 mA/

TTL Input Levels VCC = Max. All Inputs input

Outputs Disabled

ICCD1 Dynamic Power Supply Current fCP = 10MHz, 50% Duty Cycle COM'L. — — 100 mA

f = 10MHz VIH = VCC, VIL = GND

Read Mode, Outputs Disabled MIL. — — 115

ICCD2 Dynamic Power Supply Current fCP = 20MHz, 50% Duty Cycle COM'L. — — 200 mA

f = 20MHz VIH = VCC, VIL = GND

Read Mode, Outputs Disabled MIL. — — 230

NOTES: 2552 tbl 22

1. For conditions shown as Min. or Max., use appropriate value specified above for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient temperature, and maximum loading.

3. Total supply current is the sum of the Quiescent current and the dynamic current and is calculated as follows:

ICC = ICCQ + ICCQT (NT x DT) + ICCD (fOP)

where: NT = Total # of quiescent TTL inputs

DT = AC Duty cycle – % of time high (TTL)

fOP = Operating frequency

11.7 22

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC PARAMETERS - 49C465A

PROPAGATION DELAY TIMES

32-bit 64-bit 64-bit System

System “Generate

Standalone only” Lower Upper

Slice Slice Slice Slice

CODE ID=00 CODE ID=01 CODE ID=10 CODE ID=11

Parameter Description Com. Mil. Com. Mil. Com. Mil. Com. Mil. Refer to

Number Parameter From To Timing Diagram

Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit Figure

GENERATE (WRITE) PARAMETERS

01 t BC BENCBO 15 20 — — 15 20 15 20 ns —

02 t BM BENMDOUT 15 20 — — 15 20 15 20 ns —

03 t MC MDIN CBO ——15 18 ———— ns 10

04 t PCC PCBI CBO ——————12 18 ns 7

05 t PPE PXIN

PERR

12 18 — — 12 18 12 18 ns —

06 t SC CBO 14 18 14 18 14 18 14 18 ns 7

07 t SM SDIN MDOUT 12 18 — — 12 18 12 18 ns 7

08 tSPE

PERR

12 18 — — 12 18 12 18 ns —

DETECT (READ) PARAMETERS

09 t CE

ERR

Low 14 18 — — — — 12 18 ns 8,10

10 t CME CBI

MERR

= Low 15 20 — — — — 15 20 ns 8,10

11 t CSY SYO 12 18 — — 12 18 — — ns 8,10

12 t ME

ERR

12 18 — — — — 12 18 ns 8,10

13 t MME MDIN

MERR

16 20 — — — — 16 20 ns 8,10

14 t MSY SYO 16 20 — — 12 18 12 18 ns 8,10

CORRECT (READ) PARAMETERS

15 t CS CBI SDOUT 16 20 — — — — 16 20 ns 8,11

16 t MP Px 18 22 — — 18 22 18 22 ns 8,11

17 t MS MDIN SDOUT 14 18 — — — — — — ns 8,11

18 t MSY SYO 16 20 — — 12 18 1218 ns 8,11

19 t PCS PCBI SDOUT ————13 18 —— ns 11

DIAGNOSTIC PARAMETERS

20 t CLR CLEAR = Low SDOUT 15 20 — — 15 20 15 20 ns 15

21 t MIS MODE ID SDOUT 15 20 — — 15 20 15 20 ns 15

NOTES:

1. Where “edge” is not specified, both HIGH and LOW edges are implied.

2. BOLD indicates critical system parameters.

2552 tbl 24

11.7 23

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

PROPAGATION DELAY TIMES FROM LATCH ENABLES

Parameter Description Com.’l. Mil. Refer to

Parameter From To Timing Diagram

Number Name Input (edge) Output (edge) Max. Max. Unit Figure

22 t MLC CBO * 16 20 ns 13

23 t MLE

ERR

* 13 18 ns 8, 10, 11

24 t MLME MLE = HIGH

MERR

*16 20 ns 8

25 t MLP Px * 18 22 ns 8, 11

26 t MLS SDOUT * 18 22 ns 8, 10, 11

27 t MLSY SYO * 15 20 ns 8, 10

28 t PLS

PLE

= LOW SDOUT * 10 12 ns 8, 11

29 t PLP

PLE

= LOW Px * 13 18 ns 8, 11

30 t SLC SLE = HIGH CBO * 16 20 ns 7, 9

31 t SLM SLE = HIGH MDOUT * 12 18 ns 7, 9

NOTE: 2552 tbl 27

“*” = Both HIGH and LOW edges are implied.

AC PARAMETERS - 49C465A

ENABLE AND DISABLE TIMES

Parameter Description Com’l. Mil. Refer to

Parameter From To Timing Diagram

Number Name Input (edge) Output (edge) Min. Max. Min. Max. Unit Figure

32 t BESZx BEN = HIGH SDOUT * 2 13 2 16 ns 8, 10, 11

33 t BESxZ LOW Hi – Z 2 11 2 14 ns

34 t BEPZx BEN = HIGH POUT * 2 13 2 16 ns 8, 11

35 t BEPxZ LOW Hi – Z 2 11 2 14 ns

36 t CECZx

CBOE

= LOW CBO * 2 13 2 16 ns 7, 9

37 t CECxZ HIGH Hi – Z 2 11 2 14 ns

38 t MEMZx

MOE

= LOW MDOUT * 2 13 2 16 ns 7, 9

39 t MEMxZ HIGH Hi – Z 2 11 2 14 ns 8, 10

40 t SESZx

SOE

= LOW SDOUT * 2 13 2 16 ns 8, 10

41 t SESxZ HIGH Hi – Z 2 11 2 14 ns 7, 9

NOTE: 2552 tbl 28

“*” = Delay to both edges.

11.7 24

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

MINIMUM PULSE WIDTH

Refer to

Parameter Minimum Pulse Width Com’l. Mil. Timing Diagram

Number Name Input Conditions Min. Min. Unit Figure

59 t CLEAR Min.

CLEAR

LOW time to clear diag. registers Data = Valid 8 10 ns 14

60 t MLE Min. MLE HIGH time to strobe new data MD, CBI = Valid 5 6 ns —

61 t PLE Min.

PLE

LOW time to strobe new data SD = Valid 5 6 ns —

62 t SLE Min. SLE HIGH time to strobe new data SD = Valid 5 6 ns —

63 t SYNCLK Min. SYNCLK HIGH time to clock in new data SCKEN = LOW 5 6 ns 142552 tbl 33

SET-UP AND HOLD TIMES - 49C465A

Parameter Description Com.’l. Mil. Refer to

Parameter From To Timing Diagram

Number Name Input (edge) Output (edge) Min. Min. Unit Figure

42 t SSLS SDIN Set-up * before SLE = LOW 3 4 ns 7, 9

43 t SSLH SDIN Hold * after SLE = LOW 3 4 ns 7, 9

44 t MMLS MDIN Set-up * before MLE =LOW 3 4 ns 8, 10, 11

45 t MMLH MDIN Hold * after MLE = LOW 3 4 ns 8, 10, 11

46 t CMLS CBI Set-up * before MLE = LOW 3 4 ns 8, 10, 11

47 t CMLH CBI Hold * after MLE = LOW 3 4 ns 8, 10, 11

48 t MPLS MDIN Set-up * before

PLE

= HIGH 10 12 ns —

49 t MPLH MDIN Hold * after

PLE

= HIGH 0 0 ns —

50 t CPLS CBI Set-up * before

PLE

=HIGH 10 12 ns —

51 t CPLH CBI Hold * after

PLE

= HIGH 0 0 ns —

52 t PCPLS PCBI Set-up * before

PLE

= HIGH 10 12 ns —

53 t PCPLH PCBI Hold * after

PLE

= HIGH 0 0 ns —

DIAGNOSTIC SET-UP AND HOLD TIMES

54 t CSCS CBI Set-up * 10 12 ns 15

55 t MSCS MDIN Set-up * before SYNCLK=HIGH 10 12 ns 15

56 t MLSCS MLE Set-up =HIGH 10 12 ns 15

57 t SESCS SCLKEN Set-up =LOW 3 4 ns 15

58 t SESCH SCLKEN Hold =LOW after SYNCLK =HIGH 3 4 ns 15

NOTE: 2552 tbl 32

“*” = Where “edge” is not specified, both HIGH and LOW edges are implied.

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 1V/ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 18

2552 tbl 34

11.7 25

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC PARAMETERS - 49C465

PROPAGATION DELAY TIMES

32-bit 64-bit 64-bit System

System “Generate

Standalone only” Lower Upper

Slice Slice Slice Slice

CODE ID=00 CODE ID=01 CODE ID=10 CODE ID=11

Parameter Description Com. Mil. Com. Mil. Com. Mil. Com. Mil. Refer to

Number Parameter From To Timing Diagram

Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit Figure

GENERATE (WRITE) PARAMETERS

01 t BC BENCBO 20 25 — — 20 25 20 25 ns —

02 t BM BENMDOUT 20 25 — — 20 25 20 25 ns —

03 t MC MDIN CBO ——17 20 ———— ns 10

04 t PCC PCBI CBO ——————15 20 ns 7

05 t PPE PXIN

PERR

15 20 — — 15 20 15 20 ns —

06 t SC CBO 16 20 16 20 16 20 16 20 ns 7

07 t SM SDIN MDOUT 15 20 — — 15 20 15 20 ns 7

08 tSPE

PERR

15 20 — — 15 20 15 20 ns —

DETECT (READ) PARAMETERS

09 t CE

ERR

= LOW 16 20 — — — — 15 20 ns 8,10

10 t CME CBI

MERR

= LOW 20 24 — — — — 20 24 ns 8,10

11 t CSY SYO 15 20 — — 12 18 — — ns 8,10

12 t ME

ERR

= LOW 15 20 — — — — 15 20 ns 8,10

13 t MME MDIN

MERR

= LOW 20 24 — — — — 20 24 ns 8,10

14 t MSY SYO 18 22 — — 15 20 15 20 ns 8,10

CORRECT (READ) PARAMETERS

15 t CS CBI SDOUT 20 24 — — — — 20 24 ns 8,11

16 t MP Px 20 26 — — 20 26 20 26 ns 8,11

17 t MS MDIN SDOUT 16 20 — — — — — — ns 8,11

18 t MSY SYO 18 22 — — 15 20 15 20 ns 8,11

19 t PCS PCBI SDOUT ————15 20 —— ns 11

DIAGNOSTIC PARAMETERS

20 t CLR CLEAR = LOW SDOUT 20 24 — — 20 24 20 24 ns 15

21 t MIS MODE ID SDOUT 20 24 — — 20 24 20 24 ns 15

NOTES:

1. Where “edge” is not specified, both HIGH and LOW edges are implied.

2. BOLD indicates critical system parameters.

2552 tbl 23

11.7 26

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

ENABLE AND DISABLE TIMES

Parameter Description Com’l. Mil. Refer to

Parameter From To Timing Diagram

Number Name Input (edge) Output (edge) Min. Max. Min. Max. Unit Figure

32 t BESZx BEN = HIGH SDOUT * 2 15 2 18 ns 8, 10, 11

33 t BESxZ LOW Hi – Z 2 13 2 16 ns

34 t BEPZx BEN = HIGH POUT * 2 15 2 18 ns 8, 11

35 t BEPxZ LOW Hi – Z 2 13 2 16 ns

36 t CECZx

CBOE

= LOW CBO * 2 15 2 18 ns 7, 9

37 t CECxZ HIGH Hi – Z 2 13 2 16 ns

38 t MEMZx

MOE

= LOW MDOUT * 2 15 2 18 ns 7, 9

39 t MEMxZ HIGH Hi – Z 2 13 2 16 ns 8, 10

40 t SESZx

SOE

= LOW SDOUT * 2 15 2 18 ns 8, 10

41 t SESxZ HIGH Hi – Z 2 13 2 16 ns 7, 9

NOTE: 2552 tbl 26

“*” = Delay to both edges.

PROPAGATION DELAY TIMES FROM LATCH ENABLES

Parameter Description Com.’l. Mil. Refer to

Parameter From To Timing Diagram

Number Name Input (edge) Output (edge) Max. Max. Unit Figure

22 t MLC CBO * 20 24 ns 13

23 t MLE

ERR

* 15 20 ns 8, 10, 11

24 t MLME MLE = HIGH

MERR

*20 24 ns 8

25 t MLP Px * 20 25 ns 8, 11

26 t MLS SDOUT * 20 25 ns 8, 10, 11

27 t MLSY SYO * 18 22 ns 8, 10

28 t PLS

PLE

= LOW SDOUT * 12 16 ns 8, 11

29 t PLP

PLE

= LOW Px * 16 20 ns 8, 11

30 t SLC SLE = HIGH CBO * 20 24 ns 7, 9

31 t SLM SLE = HIGH MDOUT * 15 20 ns 7, 9

NOTE: 2552 tbl 25

“*” = Both HIGH and LOW edges are implied.

AC PARAMETERS - 49C465

11.7 27

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

MINIMUM PULSE WIDTH

Refer to

Parameter Minimum Pulse Width Com’l. Mil. Timing Diagram

Number Name Input Conditions Min. Min. Unit Figure

59 t CLEAR Min.

CLEAR

LOW time to clear diag. registers Data = Valid 8 10 ns 14

60 t MLE Min. MLE HIGH time to strobe new data MD, CBI = Valid 5 6 ns —

61 t PLE Min.

PLE

LOW time to strobe new data SD = Valid 5 6 ns —

62 t SLE Min. SLE HIGH time to strobe new data SD = Valid 5 6 ns —

63 t SYNCLK Min. SYNCLK HIGH time to clock in new data SCLKEN = LOW 5 6 ns 142552 tbl 30

SET-UP AND HOLD TIMES - 49C465

Parameter Description Com.’l. Mil. Refer to

Parameter From To Timing Diagram

Number Name Input (edge) Output (edge) Min. Min. Unit Figure

42 t SSLS SDIN Set-up * before SLE =LOW 4 5 ns 7, 9

43 t SSLH SDIN Hold * after SLE = LOW 4 5 ns 7, 9

44 t MMLS MDIN Set-up * before MLE =LOW 4 5 ns 8, 10, 11

45 t MMLH MDIN Hold * after MLE = LOW 4 5 ns 8, 10, 11

46 t CMLS CBI Set-up * before MLE =LOW 4 5 ns 8, 10, 11

47 t CMLH CBI Hold * after MLE = LOW 4 5 ns 8, 10, 11

48 t MPLS MDIN Set-up * before

PLE

=HIGH 12 15 ns —

49 t MPLH MDIN Hold * after

PLE

= HIGH 0 0 ns —

50 t CPLS CBI Set-up * before

PLE

=HIGH 12 15 ns —

51 t CPLH CBI Hold * after

PLE

= HIGH 0 0 ns —

52 t PCPLS PCBI Set-up * before

PLE

=HIGH 12 15 ns —

53 t PCPLH PCBI Hold * after

PLE

= HIGH 0 0 ns —

DIAGNOSTIC SET-UP AND HOLD TIMES

54 t CSCS CBI Set-up * 12 15 ns 15

55 t MSCS MDIN Set-up * before SYNCLK=HIGH 12 15 ns 15

56 t MLSCS MLE Set-up = HIGH 12 15 ns 15

57 t SESCS SCLKEN Set-up = LOW 4 5 ns 15

58 t SESCH SCLKEN Hold = LOW after SYNCLK =HIGH 4 5 ns 15

NOTE: 2552 tbl 29

“*” = Where “edge” is not specified, both HIGH and LOW edges are implied.

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 1V/ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 18

2552 tbl 31

11.7 28

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 32-BIT CONFIGURATION

NOTE: 2552 drw 19

1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH.

Figure 7. 32-Bit Generate Timing

BENt BESxZ

t BESxZ

t SESxZ

t SSLS

t SSLH

t SPE

t PPE

t SM

t SLM

t SC

t SLC

t CECZx

t BESxZ min.

t BESxZ max.

t SESxZ min.

t SESxZ max.

t SSLS

t SSLH

t SPE

t PPE

t SM

t SLM

t MEMZx

t SC

t SLC

t CECZx

SOE

SLE

SD0–31

PERR

MOE

MD0–31

CBOE

CBO

tMEMZx

BEN = Low to SDOUT Disabled

SOE = Low to SDOUT Disabled

SDIN Set-up to SLEIN = Low

SDIN Hold to SLEIN = Low

SDIN to PERROUT

Px to PERROUT

SDIN to MDOUT

SLE = High to MDOUT

MOE = Low to MDOUT Enabled

SDIN to CBO

SLE = High to CBO

CBOE = Low to CBO Enable max.

min.

max.

min.

max.

min.

max.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT) DATAIN

(INPUT) M DATAOUT = S DATAIN

to 1 2 3 4 5

(1)

11.7 29

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 32-BIT CONFIGURATION

NOTE: 2552 drw 20

1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil,) before MLE goes HIGH.

Figure 8. 32-Bit Detect Timing

t CMLH

MLE

MD 0–31

MOE

min.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT) Valid DATAIN

CBI Valid Checkbits In

t CMLS

t MMLH

t MMLS

t MEMxZ

t MSY

t CSY

t MLSY

t ME

t CE

t MLEx

t MME

t CME

t MLMEx

SYO

ERR

MERR

t CMLH

t CMLS

t MMLH

t MMLS

t MEMxZ

t MSY

t CSY

t MLSY

t ME

t CE

t MLEx

t MME

t CME

t MLEMx

Checkbit Hold to MLE = Low

Checkbit Set-up to MLE = Low

MDIN Hold to MLE = Low

MDIN Set-up to MLE = Low

MOE = High to MDOUT Disabled

MDIN to SYOOUT

Checkbits in to SYOOUT

MLE = High to SYOOUT

MDIN to ERR = Low

Checkbits in to ERR = Low

MLE = High to ERR = Low

MDIN to

MERR

= Low

Checkbits in to MERR = Low

MLE = High to MERR = Low

min.

max.

to 1 2 3 4 5

(1)

(1) (1)

(1)

11.7 30

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 32-BIT CONFIGURATION

NOTE: 2552 drw 21

1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil.) before MLE goes HIGH.

Figure 9. 32-Bit Correct Timing

t CMLH

MLE

MD 0–31

MOE

min.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT)

CBI Valid Checkbits In

t CMLS

t MMLH

t MMLS

t MEMxZ

t MLS

t CMLH

t CMLS

t MMLH

t MMLS

t MEMxZ

Checkbit Hold to MLE = Low

Checkbit Set-up to MLE = Low

MDIN Hold to MLE = Low

MDIN Set-up to MLE = Low

MOE = High to MDOUT Disabled

min.

max.

t PLS

t BESZx

t SESZx

t CS

t MS

t MP

t MLP

t PLP

t BEPZx

t SEP

Corrected DATAOUT

Parity Out

t MLS

t PLS

t BESZx

t SESZx

t CS

t MS

t MP

t MLP

t PLP

t BEPZx

t SEP

MLEIN = High to SDOUT

PLE = Low to SDOUT

BEN = High to SDOUT Enabled

SOE = Low to SDOUT Enabled

CBI to Corrected SDOUT

MDIN to Corrected SDOUT

MDIN to Parity Out

MLE = High to Parity Out

PLE = Low to Parity Out

BEN = High to Parity Out

SOE = Low to Parity Out

max.

PLE

BEN

SOE

P0–3

to12345

(1)

(1) (1)

(1)

Valid DATAIN

11.7 31

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 64-BIT CONFIGURATION

NOTE: 2552 drw 22

1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH.

Figure 10. 64-Bit Generate Timing — (64-Bit Cascading System)

BEN

t SESxZ

t SSLS t SSLH

t PPE

t SM

t SC

t SLC

t CECZx

t SESxZ min.

t SESxZ max.

t SSLS

t SSLH

t PPE

t SM

t MEMZx

t SC

t SLC

t CECZx

SOE

SLE

SD (L & U)

PERR

MOE

MD (L & U)

CBOE

CBO

t MEMZx

SOE = High to SDOUT Disabled

SDIN Set-up to SLEIN = Low

SDIN Hold to SLEIN = Low

Px to PERR

SDIN to MDOUT

MOE = Low to MDOUT Enabled

SD Lower In to CBO

SLEIN = High to CBO

CBOE = Low to CBO Enabled

min.

max.

min.

max.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT) DATAIN

(INPUT) MD DATAOUT = SD DATAIN

LOWER 465 Partial Checkbits Out

Partial Checkbits In

UPPER 465

Final Checkbits Out

t PCC t PCC PCBI to CBO max.

3Inter-chip delay (Design dependent)

PCBI

CBO

Parity In

t SLM t SLM SLE = High to MDOUT max.

t BEMt BEM BEN to MDOUT max.

max.

BOTH

465s to 1 2 3 4 5

to 1 2 3 4 5

(1)

(1) (1)

(1)

11.7 32

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 64-BIT CONFIGURATION

NOTE: 2552 drw 23

1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH.

Figure 11. 64-Bit Detect Timing

t CMLH

MLE

MD (L)

MOE

min.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT)

CBI Valid Checkbits In

t CMLS

t MMLH

t MMLS

t MEMxZ

t MLS

t CMLH

t CMLS

t MMLH

t MMLS

t MEMxZ

CBI Hold to MLE = Low

CBI Set-up to MLE = Low

MDIN Hold to MLE = Low

MDIN Set-up to MLE = Low

MOE = High to MDOUT

Disabled

min.

max.

t BESZx

t SESZx

Corrected DATAOUT

Partial Syndrome Out

t MLS

t BESZx

t SESZx

MLE = High to SDOUT

BEN = High to SDOUT Enabled

SOE = Low to SDOUT Enabled

max.

BEN

SOE

SD0–31

SYO

MD (U) (OUTPUT)

t MSY

t CSY

t MLSY

t CME

t MLME

t CE

t MLE

t MME

t ME

LOWER 465

UPPER 465 Partial Syndrome In

t MSY

t CSY

t MLSY

t CME

t MLME

t CE

t MLE

t MME

t ME

MD Lower In to SYOOUT

CBI to SYO

MLE = High to SYO

CBI to MERR

MLE = High to MERR

CBI to ERR

MLE = High to ERR

MDIN to MERR

MDIN to ERR

Inter-chip delay (Design dependent)

max.

CBI

MERR

ERR

BOTH

465s to12345

to12345

(1)

(1) (1)

(1)

Valid DATAIN

11.7 33

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 64-BIT CONFIGURATION

Figure 12. 64-Bit Correct Timing (Lower Slice)

NOTE: 2552 drw 24

1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH.

t CMLH

MLE

0–31

MOE

min.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT)

CBI

Valid Checkbits In

t CMLS

t MMLH

t MMLS

t MEMxZ

t MLS

t CMLH

t CMLS

t MMLH

t MMLS

t MEMxZ

CBI Hold to MLE = Low

CBI Set-up to MLE = Low

Hold to MLE = Low

Set-up to MLE = Low

MOE = High to MD

OUT

Disabled

min.

max.

t PLS

t BESZx

t SESZx

t CS

t MS

t CSY

t MLP

t PLP

t BEPZx

t SEP

Corrected DATA

OUT

Parity Out

t MLS

t PLS

t BESZx

t SESZx

t CS

t MS

t CSY

t MLP

t PLP

t BEPZx

t SEP

MLE

= High to SD

OUT

PLE = Low to SD

OUT

= High to SD

OUT

Enabled

SOE = Low to SD

OUT

Enabled

CBI to Corrected SD

OUT

to Corrected SD

OUT

CBI to Syndrome

MLE = High to Parity Out

PLE = Low to Parity Out

= High to Parity Out

SOE = Low to Parity Out

max.

PLE

SOE

0–31

0–3

Partial checkbits in from Upper

PCBI

t CSY t CSY

CBI to Syndrome

max.

t MSY t MSY

to Syndrome

max.

t MP t MP

to Parity Out

max.

Partial Syndrome Out

SYO

64-BIT

U/L Slice

to 1 2 3 4 5

(1)

(1) (1)

(1)

(1)(1)

Valid DATA

11.7 34

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 64-BIT CONFIGURATION

NOTE: 2552 drw 25

1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH.

Figure 13. 64-Bit Correct Timing (Upper Slice)

t CMLH

MLE

MD 0–31

MOE

min.

Parameter

Name Propagation Delay

From To Min./

Max.

(OUTPUT)

CBI Valid Checkbits In

t CMLS

t MMLH

t MMLS

t MEMxZ

t MLS

t CMLH

t CMLS

t MMLH

t MMLS

t MEMxZ

CBI Hold to MLE = Low

CBI Set-up to MLE = Low

MDIN Hold to MLE = Low

MDIN Set-up to MLE = Low

MOE = High to MDOUT

Disabled

min.

max.

t PLS

t BESZx

t SESZx

t CS

t MSY

t MLP

t PLP

t BEPZx

t SEP

Corrected DATAOUT

Parity Out

t MLS

t PLS

t BESZx

t SESZx

t CS

t MSY

t MLP

t PLP

t BEPZx

t SEP

MLEIN = High to SDOUT

PLE = Low to SDOUT

BEN = High to SDOUT Enabled

SOE = Low to SDOUT Enabled

CBI to Corrected SDOUT

MDIN to Corrected SDOUT

MLE = High to Parity Out

PLE = Low to Parity Out

BEN = High to Parity Out

SOE = Low to Parity Out

max.

PLE

BEN

SOE

SD0–31

P0–3

t MP t MP MDIN to Parity Out max.

Partial Checkbits/ Syndrome Out

SYO

t MS t MS MDIN to Corrected SDOUT max.

64-BIT

U/L Slice to12345

to12345

(1)

(1) (1)

(1)

Valid DATAIN

11.7 35

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — 64-BIT CONFIGURATION

NOTE: 2552 drw 26

1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH.

2. Assumes that Memory Data is valid at least 4ns (Com.) before MLE goes HIGH.

Figure 14. 64-Bit Single Chip "Generate Only" Timing

t SLC

MOE

SD Bus

SOE

max.

Parameter

Name Propagation Delay

From To Min./

Max.

SLE

t SSLH

t SSLS

t SLC

t SSLH

t SSLS

SLE = High to CBO

SDIN Hold to SLEIN = Low

SDIN Set-up to SLEIN = Low

min.

t MMLH

t MLC

t CECZx

Final Checkbits Out

t MMLH

t MLC

t CECZx

MDIN Hold to MLEIN = Low

MLEIN = High to CBO

CBOE = Low to CBO Enabled

min.

max.

MD Bus

MLE

CBOE

CBO

(SOE = Tied high)

SINGLE

465

t MC t MC Bits 0–31 to CBO max.

t SC t SC Bits 32–63 to CBO max.

t MMLS t MMLS MDIN Set-up to MLEIN = Low min.

(MOE = Tied high)

to 1 2 3 4 5

(1)

(2) (2) (2)

(1) (1)

Valid DATAIN

11.7 36

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TIMING DIAGRAMS — DIAGNOSTIC TIMING

2552 drw 27

Figure 15. 32-Bit Diagnostic Timing

CBI

Parameter

Name Propagation Delay

From To Min./

Max.

t CSCS

Checkbits In

465

MD Bus

MLE

SCLKEN

Memory DataIN

Valid DataOUT

t MSCS

t MLSCS

t SESCS t SESCH

t SYNCLK

t SCS

t CLEAR

t CLR

t CSCS

t MSCS

t MLSCS

t SESCS

t SESCH

t SYNCLK

t SCS

t CLEAR

t CLR

CBI Set-up to SYNCLK = High

MDIN Set-up to SYNCLK = High

MLE = High Set-up to SYNCLK = High

SCLKEN Set-up to SYNCLK = High

SCLKEN = Hold After SYNCLK = High

SCLKEN Pulse Width

SCLKEN = High to SDOUT

CLEAR Pulse Width

CLEAR = Low to SDOUT

min.

max.

min.

max.

SYNCLK

CLEAR

SD Bus

to12345

11.7 37

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCH POSITION

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

PROPAGATION DELAY ENABLE AND DISABLE TIMES

Pulse

Generator

D.U.T.

VCC

VIN

VOUT

50pF 500Ω

500Ω

7.0V

1.5V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

tSU tH

tREM

tSU tH

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

1.5V

SAME PHASE

INPUT TRANSITION

1.5V

VOH

tPLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

1.5V

tPLH tPHL

tPHL

VOL

CONTROL

INPUT

1.5V

3.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

VOL

0.3V

tPLZtPZL

tPZH tPHZ

3.5V

1.5V

ENABLE DISABLE

VOH

PRESET

CLEAR

CLOCK ENABLE

ETC.

Test Switch

Disable Low

Enable Low

Closed

All Other Tests Open

Open Drain

DEFINITIONS:

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

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NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

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2552 tbl 35

11.7 38

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT 49C465

Device Type XX

Package X

Process/

Temperature

Range

BLANK

PQF

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Plastic Quad Flatpack

Pin Grid Array

49C465 32-Bit Flow-thru EDC

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Speed

BLANK

AStandard Speed

High Speed

ORDERING INFORMATION