Audio, Dual-Matched
NPN Transistor
SSM2212
Rev. B
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FEATURES
Very low voltage noise: 1 nV/√Hz maximum @ 100 Hz
Excellent current gain match: 0.5%
Low offset voltage (VOS): 200 μV maximum
Outstanding offset voltage drift: 0.03 μV/°C
High gain bandwidth product: 200 MHz
PIN CONFIGURATION
C
11
B
12
E
13
NIC
4
C
2
8
B
2
7
E
2
6
NIC
5
SSM2212
NIC = NO INT ERNAL CONNECTION
09043-001
Figure 1. 8-Lead SOIC_N
GENERAL DESCRIPTION
The SSM2212 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow noise
audio systems.
With its extremely low input base spreading resistance (rbb' is
typically 28 Ω) and high current gain (hFE typically exceeds 600
at IC = 1 mA), the SSM2212 can achieve outstanding signal-to-
noise ratios. The high current gain results in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.
Excellent matching of the current gain (ΔhFE) to about 0.5% and
low VOS of less than 10 μV typical make the SSM2212 ideal for
symmetrically balanced designs, which reduce high-order
amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection
diodes across the base-emitter junction. These diodes prevent
degradation of beta and matching characteristics due to reverse
biasing of the base-emitter junction.
The SSM2212 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because a
current mirror’s accuracy degrades exponentially with mismatches
of VBE between transistor pairs, the low VOS of the SSM2212
does not need offset trimming in most circuit applications.
The SSM2212 performance and characteristics are guaranteed
over the extended temperature range of −40°C to +85°C.
SSM2212
Rev. B | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance.......................................................................4
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information.................................................................8
Fast Logarithmic Amplifier..........................................................8
Outline Dimensions ..........................................................................9
Ordering Guide .............................................................................9
REVISION HISTORY
7/10—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
6/10—Rev. 0 to Rev. A
Changes to Fast Logarithmic Amplifier Section .......................... 8
6/10—Revision 0: Initial Version
SSM2212
Rev. B | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCB = 15 V, IO = 10 μA, TA = 25°C, unless otherwise specified.
Table 1.
Parameter Symbol Text Conditions/Comments Min Typ Max Unit
DC AND AC CHARACTERISTICS
Current Gain1 h
FE
I
C = 1 mA 300 605
−40°C ≤ TA ≤ +85°C 300
I
C = 10 μA 200 550
−40°C ≤ TA ≤ +85°C 200
Current Gain Match2 ΔhFE 10 μA ≤ IC ≤ 1 mA 0.5 5 %
Noise Voltage Density3 e
N I
C = 1 mA, VCB = 0 V
f
O = 10 Hz 1.6 2 nV/√Hz
f
O = 100 Hz 0.9 1 nV/√Hz
f
O = 1 kHz 0.85 1 nV/√Hz
f
O = 10 kHz 0.85 1 nV/√Hz
Low Frequency Noise (0.1 Hz to 10 Hz) eN p-p IC = 1 mA 0.4 μV p-p
Offset Voltage VOS V
CB = 0 V, IC = 1 mA 10 200 μV
−40°C ≤ TA ≤ +85°C 220 μV
Offset Voltage Change vs. VCB ΔVOS/ΔVCB 0 V ≤ VCB ≤ VMAX 4,1 μA ≤ IC ≤ 1 mA5 10 50 μV
Offset Voltage Change vs. IC ΔVOS/ΔIC 1 μA ≤ IC ≤ 1 mA5, VCB = 0 V 5 70 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 0.08 1 μV/°C
−40°C ≤ TA ≤ +85°C, VOS trimmed to 0 V 0.03 0.3 μV/°C
Breakdown Voltage BVCEO 40 V
Gain Bandwidth Product fT I
C = 100 mA, VCE = 10 V 200 MHz
Collector-to-Base Leakage Current ICBO V
CB = VMAX 25 500 pA
−40°C ≤ TA ≤ +85°C 3 nA
Collector-to-Collector Leakage Current ICC V
CC = VMAX6, 7 35 500 pA
−40°C ≤ TA ≤ +85°C 4 nA
Collector-to-Emitter Leakage Current ICES V
CE = VMAX, VBE = 0 V6, 7 35 500 pA
−40°C ≤ TA ≤ +85°C 4 nA
Input Bias Current IB I
C = 10 μA 50 nA
−40°C ≤ TA ≤ +85°C 50 nA
Input Offset Current IOS I
C = 10 μA 6.2 nA
−40°C ≤ TA ≤ +85°C 13 nA
Input Offset Current Drift ΔIOS/ΔT IC = 10 μA6, −40°C ≤ TA ≤ +85°C 40 150 pA/°C
Collector Saturation Voltage VCE (SAT) I
C = 1 mA, IB = 100 μA 0.05 0.2 V
Output Capacitance COB V
CB = 15 V, IE = 0 μA 23 pF
Bulk Resistance RBE 10 μA ≤ IC ≤ 10 mA6 0.3 1.6 Ω
Collector-to-Collector Capacitance CCC V
CC = 0 V 35 pF
1 Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents.
2 Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC).
3 Noise voltage density is guaranteed, but not 100% tested.
4 This is the maximum change in VOS as VCB is swept from 0 V to 40 V.
5 Measured at IC = 10 μA and guaranteed by design over the specified range of IC.
6 Guaranteed by design.
7 ICC and ICES are verified by measurement of ICBO.
SSM2212
Rev. B | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Breakdown Voltage of
Collector-to-Base Voltage (BVCBO)
40 V
Breakdown Voltage of
Collector-to-Emitter Voltage (BVCEO)
40 V
Breakdown Voltage of
Collector-to-Collector Voltage (BVCC)
40 V
Breakdown Voltage of
Emitter-to-Emitter Voltage (BVEE)
40 V
Collector Current (IC) 20 mA
Emitter Current (IE) 20 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC (R-8) 120 45 °C/W
ESD CAUTION
SSM2212
Rev. B | Page 5 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCE = 5 V, unless otherwise specified.
CH1 2.00V M4.00s A CH1 15.8V
1
CH1 4.92V p -p
0
9043-002
Figure 2. Low Frequency Noise (0.1 Hz to 10 Hz), IC = 1 mA, Gain = 10,000,000
1k
0.1
1
10
100
0.1 1 10 100 1k 10k 100k
NOISE VOLTAGE DENSITY (nV/ Hz)
FREQUENCY (Hz )
I
C
= 1mA TEST
I
C
= 10µA TES T
I
C
= 1µA TEST
09043-003
Figure 3. Noise Voltage Density vs. Frequency
100
0
20
40
60
80
0.001 10.10.01
TOTAL NOISE (nV/ Hz)
COLLE CT OR CURRENT , I
C
(mA)
R
S
= 100kΩ
R
S
= 10kΩ
R
S
= 1kΩ
09043-004
Figure 4. Total Noise vs. Collector Current, f = 1 kHz
900
800
700
600
500
400
300
200
100
0.001 10.10.01
CURRENT G AIN (h
FE
)
COLLE CT OR CURRENT ( mA)
T
A
= +25°C
T
A
= –55°C
T
A
= +125°C
09043-005
Figure 5. Current Gain vs. Collector Current (VCB = 0 V)
900
800
700
600
500
400
300
200
0
100
–100 –50 0 50 100 150
CURRENT G AI N (h
FE
)
TE M P ERATURE ( °C)
1mA
1µA
09043-006
Figure 6. Current Gain vs. Temperature (Excludes ICBO)
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.001 0.01 0.1 1 10
BASE EMITTER VOLTAGE, V
BE
(V)
COL LECT OR CURRENT, I
C
(mA)
V
CE
= 5V
09043-008
Figure 7. Base Emitter Voltage vs. Collector Current
SSM2212
Rev. B | Page 6 of 12
100
10
1
0.1
0.01
0.001
0.001 0.01 0.1 1 10
INPUT RESISTANCE,
h
IE
(MΩ)
COL LECT OR CURRENT, I
C
(mA)
V
CE
= 5V
09043-009
Figure 8. Small Signal Input Resistance vs. Collector Current
1m
0.1m
0.01m
1µ
0.1µ
0.01µ
0.001 10001001010.10.01
CONDUCT ANCE, h
OE
(mho)
COLLE CTOR CURRE NT, I
C
(mA)
V
CE
= 5V
09043-010
Figure 9. Small Signal Output Conductance vs. Collector Current
0.01
0.1
1
10
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
COL LECT OR CURRENT, I
C
(mA)
SATURATION VO LTAGE, V
SAT
(V)
T
A
= –55° C T
A
= +125°C
T
A
= +25°C
09043-017
Figure 10. Collector Current vs. Saturation Voltage
1000
100
10
1
0.1
0.0125 50 75 100 125
CURRENT , I
CBO
(nA)
TE M P ERATURE ( °C)
09043-012
Figure 11. Collector-to-Base Leakage Current vs. Temperature
40
35
30
25
20
15
10
5
00 102030405
CAPACITANCE, C
CB
(pF)
REVERSE BIAS VO LT AGE (V) 0
09043-013
Figure 12. Collector-to-Base Capacitance vs. Reverse Bias Voltage
40
35
30
25
20
15
10
5
00 102030405
CAPACITANCE, C
CC
(pF)
COL LECTOR-TO-SUBSTRATE VOLT AGE (V) 0
09043-014
Figure 13. Collector-to-Collector Capacitance vs.
Collector-to-Substrate Voltage
SSM2212
Rev. B | Page 7 of 12
1000
100
10
1
0.1
0.0125 50 75 100 125
CURRENT, I
CC
(nA)
TE M P ERATURE ( °C)
09043-015
Figure 14. Collector-to-Collector Leakage Current vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00 102030405
CAPACITANCE, C
CC
(pF)
REVERSE BIAS VO LT AGE (V) 0
09043-016
Figure 15. Collector-to-Collector Capacitance vs. Reverse Bias Voltage
SSM2212
Rev. B | Page 8 of 12
APPLICATIONS INFORMATION
FAST LOGARITHMIC AMPLIFIER
The circuit of Figure 16 is a modification of a standard
logarithmic amplifier configuration. Running the SSM2212 at
2.5 mA per side (full-scale) allows for a fast response with a wide
dynamic range. The circuit has a 7 decade current range and a
5 decade voltage range, and it is capable of 2.5 μs settling time to
1% with a 1 V to 10 V step. The output follows the equation:
IN
REF
OV
V
q
kT
R
RR
Vln
2
23 +
=
To compensate for the temperature dependence of the kT/q term, a
resistor with a positive 0.35%/°C temperature coefficient is chosen
for R2. The output is inverted with respect to the input and is
nominally −1 V/decade using the component values indicated.
1
4
3
28
7
5
6
–15V
330pF
R3
7.5kΩ
R2
500Ω
R2 = T E L L ABS QB1E ( +0.35%/°C)
330pF
VO
+15
V
RS
4kΩ
R1
4kΩ
4kΩ
VIN
(0V TO 10V)
V
REF
10V
AD8512
SSM2212
1/2
AD8512
09043-018
Figure 16. Fast Logarithmic Amplifier
SSM2212
Rev. B | Page 9 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 17. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
SSM2212RZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2212RZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2212RZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
1 Z = RoHS Compliant Part.
SSM2212
Rev. B | Page 10 of 12
NOTES
SSM2212
Rev. B | Page 11 of 12
NOTES
SSM2212
Rev. B | Page 12 of 12
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09043-0-7/10(B)
