PTB48510BAH - Texas Instruments - Datasheet.Directory

1+VI

2 Sync In

3 Enable

4-VI

VO1

VOAdj 7

COM

*VO2

PTB4851x

COM

+VI

-VI

IO1

IO2

UDG-07040

*VO1 @| VO2 |

*VO2is the negative voltage.

Not Recommended for New Designs

PTB48510

PTB48511

www.ti.com

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

DUAL COMPLEMENTARY-OUTPUT DC/DC CONVERTER FOR DSL

Check for Samples: PTB48510,PTB48511

1FEATURES

• Dual Complementary Outputs

(±5 V, ±12 V, or ±15 V)

• Input Voltage Range: 36 V to 75 V

• On/Off Enable for Sequencing

• 1500 VDC Isolation

• Overcurrent Protection

• Overvoltage Protection (PTB48511 only)

• Over Temperature Shutdown DESCRIPTION

• Undervoltage Lockout The PTB4851x series of isolated DC/DC converter

• Temperature Range: –40°C to 85°C modules produce a complementary pair of regulated

• Industry Standard Outline supply voltages for powering line-driver devices in

• Fixed Frequency Operation xDSL telecom applications. The modules operate

from a standard telecom (–48 V) central office (CO)

• Synchronizes with PTB48500 supply and can provide up to a 72 W of power in a

• Powers Line Drivers for AC-7 and Other xDSL balanced load configuration.

Chipsets The A-suffix module (±5 V) is designed to power the

• Safety Approvals: line driver devices for the AC-7 ADSL chipset. Other

– EN 60950 voltage options powers other analog applications

– UL/cUL 60950 requiring a complementary supply with relatively

balanced loads.o

STAND-ALONE APPLICATION Both the PTB48510 and PTB48511 include an

“on/off” enable control, output current limit, over-

temperature protection, and input under-voltage

lockout (UVLO). The PTB48511 adds output

overvoltage protection (OVP).

The control inputs, Enable and Sync In, are

compatible with the EN Out and Sync Out signals of

the PTB48500 DC/DC converter. This allows the

power-up and switching frequency of the PTB4851x

modules to be directly controlled from a PTB48500.

Together the PTB48500 and PTB4851xA converters

meet all the system power and sequencing

requirements of the AC- ADSL chipset.

The PTB4851x uses double-sided surface mount

technology contruction. The package size is based on

the industry standard outline and does not require a

heatsink. Both through-hole and surface mount pin

configurations are available.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Not Recommended for New Designs

PTB48510

PTB48511

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

www.ti.com

ORDERING INFORMATION

BASE DEVICE NUMBER. (PTB4851xxx) OUTPUT VOLTAGE PACKAGE OPTIONS (PT4851xx)

(PTB4851xx)

ORDER VOLTAGE PACKAGE

DESCRIPTION CODE CODE DESCRIPTION

PREFIX (V) REFERENCE(1)

PTB48510xxx Basic model A ±5 AH Horizontal T/H ERK

Adds output overvoltage protection(2) B ±12 AS SMD, Standard(3) ERL

PTB48511xxx C ±15(4)

(1) Reference the applicable package reference drawing for the dimensions and PC board layout

(2) Output overvoltage protection

(3) Standard option specifies 63/37, Sn/Pb pin solder material

(4) ±15-V output is not available with the PTB48511

Environmental and General Specifications

(Unless otherwise stated, all voltages are with respect to VI2)VALUE UNIT

VIInput Voltage Range Over output load range 36 to 75 VDC

Isolation Voltage Input-output/input/case 1500 V

Capacitance Input to output 1500 pF

Resistance Input to output 10 mΩ

TAOperating Temperature Range Over VIRange –40 to 85

Shutdown threshold 115(1)

OTP Over-Temperature Protection Hysterisis 10 °C

Treflow Solder Reflow Temperature Surface temperature of module body or pins 235(2)

TsStorage Temperature –55 to 125

Per Mil-STD-883D, Method 2002.3 T/H 500

Mechanical Shock G

1 ms, 1/2 Sine, mounted SMD 250

T/H 10

Mil-STD-883D, Method 2007.2

Mechanical Vibration Mil-STD-883D G

20-2000 Hz SMD 5

Weight 28 grams

Flammability Meets UL 94V-O

(1) This parameter is assured by design.

(2) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated

maximum.

Not Recommended for New Designs

PTB48510

PTB48511

www.ti.com

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated, TA= 25°C, VI= 48 V, CI= 0 μF, CO= 0 μF, IO1 = IO2 = 3.25 A maximum) PTB4851xA

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POOutput Power Total output power from VO1 or VO2 0 65 (1) W

IO1, IO2 Output Current Over VIrange, IO1 ≤0.1 A or IO2 ≤0.1 A 0 6.5(2) A

IO1 - IO2 Output Load Imbalance IO1 ≤0.1 A or IO2 ≤0.1 A 0 1(3) A

Includes set point, line, load, IO1 ≤0.1 A or IO2 ≤0.1 A

VO1, VO2 Output Voltage 4.75(2) 5 5.25(2) V

–40°C ≤TA≤85°C VO1 ±1

–40°C ≤TA≤85°C, IO1 ≤0.1 A or IO2 ≤0.1

ΔRegtemp Temperature Variation %VO

AVO2 ±1

ΔRegline Line Regulation Over VIrange, balanced load VO1 or VO2 ±0.1 ±0.4 %VO

ΔRegload Load Regulation Over IO1, IO2range, balanced load VO1 or VO2 ±0.2 ±0.4 %VO

ηEfficiency 86%

VrVORipple (pk-pk) 20 MHz bandwidth, CO= 10-μF tantalum capacitor 20 30(4) mVpp

ttr 0.11 A/μs load step, 50% to 75% IO1 or IO2 maximum 30 μs

Transient Response

ΔVtr VO1 or VO2 overshoot/undershoot ±1.0 %VO

IOtrip Overcurrent Threshold VI= 36 V, reset followed by auto-recovery 6.8 7.5 10 A

PTB48510 NA NA

VO1(trip),Overvoltage Threshold Outputs latched off (5) V

VO2(trip) PTB48511 5.9 7

IO1(pk) IO2(pk) 12.5 A

Short Circuit Current Continuous overcurrent trip, IO1 = IO2 Duty 10%

VO1(adj), Output Voltage Adjust VO1 or VO2 adjust simultaneously 3.5 5.5 V

VO2(adj) Range

fSSwitching Frequency Over VIand IOranges 440 470(6) 500 kHz

VIon VIincreasing 33

Undervoltage lockout V

VIoff VIdecreasing 32

On/Off Enable (pin 3)

VIH High-level input voltage 3.6 75(7)

Referenced to VI(pin 4) V

VIL Low-level input voltage –0.2 0.8

IIL Low-level input current –1 mA

IIstandby Standby Input Current Pin 3 connected 2 mA

tON Start-up Time IO1 ≤0.1 A or IO2 ≤0.1 A, VO1 or VO2 rising 0 to 0.95 (typ) 6 10 22 ms

CIInternal Input Capacitance 3 μF

External Output 5000(8

COCapacitance from either output to COM (pin 6) 0 μF

Capacitance )

PTB48510A 2.7

Per Telcordia SR-332 50% stress,

MTBF Reliability 106hrs

TA= 40°C, ground benign PTB48511A 2.5

(1) See Safe Operating Area curves or contact the factory for the appropriate derating.

(2) Under balanced load conditions, load current flowing out of VO1 is balanced to within ±0.1 A of that flowing into VO2.

(3) A load imbalance is the difference in current flowing from VO1 to VO2. The module can operate with a higher imbalance but with reduced

specifications.

(4) Output voltage ripple is measured with a 10-μF tantalum capacitor connected from VO1 (pin 5) or VO2 (pin 8), to COM (pin 6).

(5) If the overvoltage threshold is exceeded by either regulated output the module will shut down, turning both outputs off. This is a latched

condition, which can only by reset by removing and then re-applying the module's input power.

(6) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together

in a system.

(7) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is

diode protected and may be connected to VI. The open-circuit voltage is 5 V maximum. If it is left open circuit the converter operates

when input power is applied.

(8) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the

factory before using capacitors with organic, or polymer-aluminum type electrolytes.

Not Recommended for New Designs

PTB48510

PTB48511

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

www.ti.com

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated, TA= 25°C, VI= 48 V, CI= 0 μF, CO= 0 μF, IO1 = IO2 = 3.25 A maximum)PTB4851xB

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POOutput Power Total output power from VO1or VO1 0 72(1) W

IO1 or IO2 Output Current Over VIrange, IO1 ≤0.1 A or IO2 ≤0.1 A ≤0.1 A 0 3(2) A

IO1 - IO2 Output Load Imbalance IO1 ≥0.1 A, IO2 ≥0.1 A 0 1(3) A

Includes set point, line, load, IO1 ≤0.1 A or IO2 ≤0.1 A ≤

VO1 or VO2 Output Voltage 0.1 A 11.6(2) 12 12.4(2) V

–40°C ≤TA≤85°C

–40°C ≤TA≤85°C, IO1 ≤0.1 A or IO2 ≤0.1 VO1 or VO2 ±1

ΔRegtemp Temperature Variation %VO

ΔRegline Line Regulation Over VIrange, balanced load VO1 or VO2 ±0.05 ±0.5 %VO

ΔRegload Load Regulation Over IO1 or IO2 range, balanced load VO1 or VO2 ±0.1 ±1 %VO

ηEfficiency 89%

VrVORipple (pk-pk) 20 MHz bandwidth, CO= 10 μF tantalum capacitor 20 80(4) mVpp

ttr 0.1 A/μs load step, 50% to 75% IO1 or IO2 maximum 30 μs

Transient Response

ΔVtr VO1 or VO2 overshoot/undershoot ±1 %VO

IOtrip Overcurrent Threshold VI= 36 V, reset followed by auto-recovery 3.3 3.8 5 A

PTB48510A NA NA

VO1(trip),Overvoltage Threshold Outputs latched off (5) V

VO2(trip) PTB48511A 14 15.8 17

IO1(pk) IO2(pk) 6 A

Short Circuit Current Continuous overcurrent trip, IO1 = IO2 Duty 10%

VO1(adj), Output Voltage Adjust VO1 and VO2 adjust simultaneously 6.5 13.4 V

VO2(adj) Range

fSSwitching Frequency Over VIand IOranges 440 480(6) 500 kHz

VIon VIincreasing 33

Under-Voltage Lockout V

VIoff VIdecreasing 32

On/Off Enable (pin 3) Referenced to VI(pin 4)

VIH High-level input voltage 3.6 75(7) V

VIL Low-level input voltage –0.2 0.8

IIL Low-level input current –1 mA

IIstandby Standby Input Current Pin 3 open circuit 2 mA

tON Start-up Time IO1 ≤1 A or IO2 ≤1 A, VO1 or VO2 rising 0 to 0.95 (typ) 6 12 18 ms

CIInternal Input Capacitance 3 μF

External Output 3000(8

COCapacitance from either output to COM (pin 6) 0 μF

Capacitance )

PTB48510B 2.8

Per Telcordia SR-332 50% stress,

MTBF Reliability 106Hrs

TA= 40°C, ground benign PTB48511B 2.5

(1) See Safe Operating Area curves or contact the factory for the appropriate derating.

(2) Under balanced load conditions, load current flowing out of VO1 is balanced to within ±0.1 A of that flowing into VO2.

(3) A load imbalance is the difference in current flowing from VO1 to VO2. The module can operate with a higher imbalance but with reduced

specifications.

(4) Output voltage ripple is measured with a 10 μF tantalum capacitor connected from VO1 (pin 5) or VO2 (pin 8), to COM (pin 6).

(5) If the overvoltage threshold is exceeded by either regulated output the module will shut down, turning both outputs off. This is a latched

condition, which can only by reset by removing and then re-applying the module's input power.

(6) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together

in a system.

(7) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is

diode protected and may be connected to VI. The open-circuit voltage is 5 V maximum. If it is left open circuit the converter operates

when input power is applied.

(8) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the

factory before using capacitors with organic, or polymer-aluminum type electrolytes.

Not Recommended for New Designs

PTB48510

PTB48511

www.ti.com

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated, TA= 25°C, VI= 48 V, CI= 0 μF, CO= 0 μF, IO1 = IO2 = 3.25 A maximum)PTB4851xC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POOutput Power Total output power from VO1 or VO2 0 66(1) W

IO1 or IO2 Output Current Over VIrange, IO1 ≤0.1 A or IO2 ≤0.1 A 0 2.2(2) A

IO1 - IO2 Output Load Imbalance IO1 ≤0.1 A or IO2 ≤0.1 A 0 1(3) A

Includes set point, line, load, IO1 - IO2 ≤0.1 A,

VO1 or VO2 Output Voltage 14.5(2) 15 15.5(2) V

–40°C ≤TA≤85°C

–40°C ≤TA≤85°C, IO1 ≤0.1 A or IO2 ≤0.1 VO1 or VO2 ±1

ΔRegtemp Temperature Variation %VO

ΔRegline Line Regulation Over VIrange, balanced load VO1 or VO2 ±0.05 ±0.5 %VO

ΔRegload Load Regulation Over IO1 or IO2 range, balanced load VO1 or VO2 ±0.1 ±1 %VO

ηEfficiency IO1 = IO2 90%

VrVORipple (pk-pk) 20 MHz bandwidth, CO= 10 μF tantalum capacitor 50 100(4) mVpp

ttr 0.1 A/μs load step, 50% to 75% IO1 or IO2 maximum 30 μs

Transient Response

ΔVtr VO1 or VO2 overshoot/undershoot ±1 %VO

IOtrip Over Current Threshold VI= 36 V, reset followed by auto-recovery 2.45 3 3.85 A

IO1(pk) IO2(pk) 4.5 A

Short Circuit Current Continuous overcurrent trip, IO1 = IO2 Duty 10%

VO1(adj) , Output Voltage Adjust VO1 and VO2 adjust simultaneously 7.2 16.7 V

VO2(adj) Range

fSSwitching Frequency Over VIand IOranges 440 480(5) 520 kHz

VIon VIincreasing 33

Under-Voltage Lockout V

VIoff VIdecreasing 32

On/Off Enable (pin 3) Referenced to –VI(pin 4)

VIH High-level input voltage 3.6 75(6) V

VIL Low-level input voltage –0.2 0.8

IIL Low-level input current –1 mA

IIstandby Standby Input Current Pin 3 open circuit 2 mA

tON Start-up Time IO1 ≤1 A or IO2 ≤1 A, VO1 or VO2 or rising 0 to 0.95 (typ) 6 12 18 ms

CIInternal Input Capacitance 3 μF

External Output 3000(7

COCapacitance from either output to COM (pin 6) 0 μF

Capacitance )

Per Telcordia SR-332 50% stress,

MTBF Reliability 2.8 106hrs

TA= 40°C, ground benign

(1) See Safe Operating Area curves or contact the factory for the appropriate derating.

(2) Under balanced load conditions, load current flowing out of VO1 is balanced to within ±0.1 A of that flowing into VO2.

(3) A load imbalance is the difference in current flowing from VO1 to VO2. The module can operate with a higher imbalance but with reduced

specifications.

(4) Output voltage ripple is measured with a 10-μF tantalum capacitor connected from VO1 (pin 5) or VO2 (pin 8), to COM (pin 6).

(5) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together

in a system.

(6) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is

diode protected and may be connected to VI. The open-circuit voltage is 5 V maximum. If it is left open circuit the converter operates

when input power is applied.

(7) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the

factory before using capacitors with organic, or polymer-aluminum type electrolytes.

Not Recommended for New Designs

PTB48510

PTB48511

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

www.ti.com

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL DESCRIPTION

NAME NO.

The positive input supply for the module with respect to VI(or ground return). When powering the module from

+VI(1) 1a –48 V telecom central office supply, this input is connected to the primary system ground.

This pin is used when the PTB4851x and PTB4850x DC/DC converter modules are used together. Connecting

Sync In 2 this pin to the Sync Out of the PTB4850x module allows the PTB4851x to be synchronized to the same switch

conversion frequency as the PTB4850x.

This is an open-collector (open-drain) negative logic input that enables the module output. This pin is

Enable (2) 3 referenced to –VI. A logic 0 at this pin enables the module's outputs, and a high impedance disables the

outputs. If this feature is not used the pin should be connected to –VI.

Note: Connecting this input directly to the EN Out pin of the PTB4850x enables the output voltages from both

converters (PTB4850x and PTB4851x) to power up in sequence.

The negative input supply for the module, and the 0 VDC reference for the Enable, and Sync In signals. When

-VI4the module is powered from a +48-V supply, this input is connected to the 48-V Return.

The positive output supply voltage, which is referenced to the COM node. The voltage at VO1 has the same

VO1 5magnitude, but is the complement to that at VO2 .

The negative output supply voltage, which is referenced to the COM node. The voltage at VO2 has the same

VO2 8magnitude, but is the complement to that at VO1 .

The secondary return reference for the module's regulated output voltages. This node is dc isolated from the

COM 6 input supply pins.

Using a single resistor, this pin allows the magnitude of both VO1 and VO2 to be adjusted together, either higher

VOAdj 7 or lower than their preset value. If not used, this pin should be left open circuit.

(1) Shaded functions indicate signals that are referenced to -VI

(2) Denotes negative logic: Open = Output Off, –VI= Normal operation.

0 1 2 43 65

TA- Ambient Temperature - °C

VI= 48 VDC

Natural

Convection

100 LFM

200 LFM

400 LFM

(IO1 = IO2) - Load Current - A

-300

-200

-100

100

200

300

0 1 2 43 65

IO1 - Load Current - A

Cross Regulation - mV

DVO2 with IO2 = 1 A

0 1 2 43

5 6

PD- Power Dissipation - W

(IO1 = IO2) - Load Current - A

2 43

100

5 6

(IO1 = IO2) - Load Current - A

h- Efficiency - %

-300

-200

-100

100

200

300

0 1 2 43 65

IO2 - Load Current - A

Cross Regulation - mV

DVO1 with IO1 = 1 A

Not Recommended for New Designs

PTB48510

PTB48511

www.ti.com

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

TYPICAL CHARACTERISTICS

PTB4851xA CHARACTERISTIC DATA at VI= 48 V (1) (2)

Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the

converter.

EFFICIENCY POWER DISSIPATION

vs vs

LOAD CURRENT LOAD CURRENT CROSS REGULATION

Figure 3.

Figure 1. (1) Figure 2. (1)

CROSS REGULATION SAFE OPERATING AREA

Figure 4. Figure 5. (1) (2)

(1) Under a balanced load, current flowing out of VO1 is equal to that flowing into VO2.

(2) SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating

temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper.

TA- Ambient Temperature - °C

(IO1 = IO2) - Load Current - A

0 0.5 1.0 1.5 2.0 3.02.5

VI= 48 VDC

Natural

Convection

100 LFM

200 LFM

400 LFM

IO1 - Load Current - A

DVO2 with IO2 = 1 A

-400

-200

200

400

Cross Regulation - mV

0 0.5 1.0 1.5 2.0 3.02.5

PD- Power Dissipation - W

(IO1 = IO2) - Load Current - A

0 0.5 1.0 1.5 2.0 3.02.5

0.5

1.0 1.5

100

2.0 3.0

(IO1 = IO2) - Load Current - A

h- Efficiency - %

2.5

-400

-200

200

400

IO2 - Load Current - A

Cross Regulation - mV

DVO1 with IO1 = 1 A

0 0.5 1.0 1.5 2.0 3.02.5

Not Recommended for New Designs

PTB48510

PTB48511

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

www.ti.com

TYPICAL CHARACTERISTICS (Continued)

PTB4851xB CHARACTERISTIC DATA at VI= 48 V (1) (2)

Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the

converter.

EFFICIENCY POWER DISSIPATION

vs vs

LOAD CURRENT LOAD CURRENT CROSS REGULATION

Figure 8.

Figure 6. (1) Figure 7. (1)

CROSS REGULATION SAFE OPERATING AREA

Figure 9. Figure 10. (1) (2)

(1) Under a balanced load, current flowing out of VO1 is equal to that flowing into VO2.

(2) SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating

temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper.

TA- Ambient Temperature - °C

0 0.5 1.0 1.5 2.0 3.02.5

VI= 48 VDC

Natural

Convection

100 LFM

200 LFM

400 LFM

(IO1 = IO2) - Load Current - A

-300

-200

-100

100

200

300

Cross Regulation - mV

0 0.3 0.6 0.9 1.2 1.81.5 2.1

IO1 - Load Current - A

DVO2 with IO2 = 1 A

0.3

0.6 0.9

100

1.2 1.8

h- Efficiency - %

1.5 2.1

(IO1 = IO2) - Load Current - A

-300

-200

-100

100

200

300

Cross Regulation - mV

0 0.3 0.6 0.9 1.2 1.81.5 2.1

IO2 - Load Current - A

DVO1 with IO1 = 1 A

PD- Power Dissipation - W

0 0.3 0.6 0.9 1.2 1.81.5 2.1

(IO1 = IO2) - Load Current - A

Not Recommended for New Designs

PTB48510

PTB48511

www.ti.com

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

TYPICAL CHARACTERISTICS (Continued)

PTB4851xC CHARACTERISTIC DATA at VI= 48 V (1) (2)

Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the

converter.

EFFICIENCY POWER DISSIPATION

vs vs

LOAD CURRENT LOAD CURRENT CROSS REGULATION

Figure 13.

Figure 11. (1) Figure 12. (1)

CROSS REGULATION SAFE OPERATING AREA

Figure 14. Figure 15. (1) (2)

(1) Under a balanced load, current flowing out of VO1 is equal to that flowing into VO2.

(2) SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating

temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper.

ǒR2Ǔ[Adjust Down] +Roǒ2 Va*VrǓ

2ǒVo*VaǓ*RskW

R1[Adjust Up] +VrRo

2ǒVa*VoǓ*RskW

VO1

VOAdj 7

COM

VO2

PTB48510

VO2

UDG-07041

VO1

Adjust Up

VO1

VOAdj 7

COM

VO2

PTB48510

VO2

UDG-07042

VO1

Adjust Down

Not Recommended for New Designs

PTB48510

PTB48511

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

www.ti.com

APPLICATION INFORMATION

ADJUSTING THE OUTPUT VOLTAGE OF THE PTB4851x SERIES OF DC/DC CONVERTERS

The PTB48510 and PTB48511 DC/DC converters produce a balanced pair of complimentary output voltages.

They are identified VO1 and VO2, respectively. The magnitude of both output voltages can be adjusted together as

a pair, higher or lower, by up to ±10% of their nominal. The adjustment method uses a single external resistor.1

The value of the resistor determines the adjustment magnitude, and its placement determines whether the

magnitude is increased or decreased. The resistor values can be calculated using the appropriate formula (see

below). The formula constants are given in Table 1. The placement of each resistor is as follows.

Adjust Up: To increase the magnitude of both output voltages, place a resistor R1between VO 1Adj (pin 7) and

the VO2 (pin 8) voltage rail; see Figure 16.

Adjust Down: To decrease the magnitude of both output voltages, add a resistor (R2), between VOAdj (pin 7)

and the VO1 (pin 5) voltage rail; see Figure 17.

Figure 16. Adjust Up Resistor Placement Figure 17. Adjust Down Resistor Placement

ADJUST RESISTOR CALCULATION

The value of the adjust resistor is calculated using one of the following equations. Use the equation for R1to

adjust up, or (R2) to adjust down.

(1)

(2)

Where:

VO= Magitude of the original VO1 or VO2

Va= Magnitude of the adjusted voltage

Vr= The reference voltage from Table 1

RO= The resistance value in Table 1

RS= The series resistance from Table 1

Not Recommended for New Designs

PTB48510

PTB48511

www.ti.com

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

Table 1. Adjustment Range and Formula Parameters

PARAMETERS PTB4851xA PTB4851xB PTB48510C

VO(nom) (V) 5 12 15

Va(min) (V) 3.5 6.5 7.2

Va(max) (V) 5.5 13.4 16.7

Vr (V) 2.495 2.495 2.495

Rn(kΩ) 7.5 18.2 22.1

Rs(kΩ) 9.09 16.9 16.9

NOTES:

1. A 0.05 W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100

ppm/°C or better. Place the resistor in either the R1or (R2) location, as close to the converter as possible.

2. Never connect capacitors to the Vo Adj pin. Capacitance added to this pin can affect the stability of the

regulated output.

3. The overvoltage protection (PTB48511x) is nominally set to 25% above the original output voltage set-

point. Increasing the magnitude of the output voltages reduces the margin between the output voltage and

the overvoltage (OV) protection threshold. This could make the module more sensitive to OV faults, as a

result of random noise and load transients.

Note: An OV fault is a latched condition that shuts down the converter's outputs. The fault can be cleared by

cycling the Enable pin, or by momentarily removing input power to the module.

CONFIGURING THE PTB4850x and PTB4851x DC/DC CONVERTERS FOR DSL APPLICATIONS

When operated as a pair, the PTB4850x and PTB4851x converters are specifically designed to provide all the

required supply voltages for powering xDSL chipsets. The PTB4850x produces two logic voltages. They include

a 3.3-V source for logic and I/O, and a low-voltage for powering a digital signal processor core. The PTB4851x

produces a balanced pair of complementary supply voltages that is required for the xDSL transceiver ICs. When

used together in these types of applications, the PTB4850x and PTB4851x may be configured for power-up

sequencing, and also synchronized to a common switch conversion frequency. Figure 19 shows the required

cross-connects between the two converters to enable these two features.

SWITCHING FREQUENCY SYNCHRONIZATION

Unsynchronized, the difference in switch frequency introduces a beat frequency into the input and output AC

ripple components from the converters. The beat frequency can vary considerably with any slight variation in

either converter’s switch frequency. This results in a variable and undefined frequency spectrum for the ripple

waveforms, which would normally require separate filters at the input of each converter. When the switch

frequency of the converters are synchronized, the ripple components are constrained to the fundamental and

higher. This simplifies the design of the output filters, and allows a common filter to be specified for the treatment

of input ripple.

POWER-UP SEQUENCING

The desired power-up sequence for the AC7 supply voltages requires that the two logic-level voltages from the

PTB4850x converter rise to regulation prior to the two complementary voltages that power the transceiver ICs.

This sequence cannot be assured if the PTB4850x and PTB4851x are allowed to power up independently,

especially if the 48-V input voltage rises relatively slowly. To ensure the desired power-up sequence, the EN Out

pin of the PTB4850x is directly connected to the activelow Enable input of the PTB4851x (see Figure 19). This

allows the PTB4850x to momentarily hold off the outputs from the PTB4851x until the logic-level voltages have

risen first. Figure 19 shows the power-up waveforms of all four supply voltages from the schematic of Figure 19.

1+VI

Sync In

3 Enable

4-VI

VO1

VOAdj

COM

VO2

PTB48510A

UDG-07043

1+VI

3 Enable

5-VI

VO1

VOAdj

COM

VO2

PTB48500A

Sync Out

EN Out

Input

Filter

+VCCIO

VCORE

POR

+VTCVR

-VTCVR

-48 VRTN

-48 V

VCORE

(1 V/div)

VCCIO

(1 V/div)

+VTCVR

(5 V/div)

+VTCVR

(5 V/div)

T - Time - 10 ms/div

Not Recommended for New Designs

PTB48510

PTB48511

SLTS219F –FEBRUARY 2004–REVISED MARCH 2007

www.ti.com

Figure 18. Power-Up Sequencing Waveforms

Figure 19. Example of PTB4850x and PTB4851x Modules Configured for DSL Applications

PACKAGE OPTION ADDENDUM

www.ti.com 1-Sep-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

PTB48510AAH NRND Through-

Hole Module ERK 8 9 Pb-Free (RoHS) SN N / A for Pkg Type

PTB48510BAH NRND Through-

Hole Module ERK 8 9 Pb-Free (RoHS) SN N / A for Pkg Type

PTB48510BAS NRND Surface

Mount Module ERL 8 9 TBD SNPB Level-1-235C-UNLIM/

Level-3-260C-168HRS

PTB48510BAZ NRND Surface

Mount Module ERL 8 9 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR

PTB48510CAH NRND Through-

Hole Module ERK 8 9 Pb-Free (RoHS) SN N / A for Pkg Type

PTB48510CAS NRND Surface

Mount Module ERL 8 9 TBD SNPB Level-1-235C-UNLIM/

Level-3-260C-168HRS

PTB48510CAZ NRND Surface

Mount Module ERL 8 9 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR

PTB48511AAH NRND Through-

Hole Module ERK 8 9 Pb-Free (RoHS) SN N / A for Pkg Type

PTB48511AAS OBSOLETE Surface

Mount Module ERL 8 TBD Call TI Call TI

PTB48511BAH NRND Through-

Hole Module ERK 8 9 Pb-Free (RoHS) SN N / A for Pkg Type

PTB48511BAZ NRND Surface

Mount Module ERL 8 9 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

PACKAGE OPTION ADDENDUM

www.ti.com 1-Sep-2012

Addendum-Page 2

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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