Februar y 2015
DocID025457 Rev 3
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This is information on a product in full production.
www.st.com
STL42P6LLF6
P-channel 60 V, 0.023 Ω typ., 42 A STripFET™ F6
Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet - product ion data
Figure 1: Internal schematic diagram
Features
Order code VDS RDS(on) max. ID
STL42P6LLF6 60 V 0.026 Ω @ 10 V 42 A
• Ve ry low on-resistance
• Very low gate charge
• High avalanche ruggedness
• Low gate drive power los s
Applications
• Switching applications
Description
This device is a P-c ha nne l Po wer MOSFET
developed using the STripFET™ F6 technology,
with a new trench gate structure. The resulting
Power MOSFET exhibits very low RDS(on) in all
packages.
For the P-channel Power MOSFET, current
polarity of voltages and current have to be
reversed.
Table 1: Device summary
Order code Marking Package Packaging
STL42P6LLF6 42P6LLF6 PowerFLAT™ 5x6 Tape and reel
1
2
3
4
PowerFLAT™ 5x6
AM01475v4
D(5, 6, 7, 8)
G(4)
S(1, 2, 3)
Contents
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Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.2 Electrical characteristics (curves) ...................................................... 6
3 Test cir c uit s ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 PowerFLAT™ 5x6 package information ............................................ 9
4.2 PowerFLAT™ 5x6 packing information ........................................... 11
5 Revision history ............................................................................ 13
STL42P6LLF6
Electrical ratings
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1 Electrical ratings
Table 2: A bsolut e maximum r ating s
Symbol Parameter Value Unit
VDS Drain-source voltage 60 V
VGS Gate-source voltage ± 20 V
ID(1) Drain current (continuous) at TC = 25 °C 42 A
ID(1) Drain current (continuous) at TC = 100 °C 30 A
ID(1)(3) Drain current (pulsed) 168 A
ID(2) Drain current (continuous) at Tpcb= 25 °C 9 A
ID(2) Drain current (continuous) at Tpcb= 100 °C 6.6 A
IDM(2)(3) Drain current (pulsed) 36 A
PTOT(1) Total dissipation at TC = 25 °C 100 W
PTOT(2) Total dissipation at Tpcb= 25 °C 4.8 W
Tstg Storage temperat ur e -55 to 175 °C
Tj Maximum junction temperature 175 °C
Notes:
(1)The value is limited by Rthj-case.
(2)The value is limited by Rthj-pcb.
(3)Pulse width is limited by safe operating area.
Table 3: Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case max 1.5 °C/W
Rthj-pcb(1) T hermal resi stan ce jun cti on-pcb max 31.3 °C/W
Notes:
(1)When mounted on FR-4 board of 1 inch², 2 Oz C u, t < 10 s.
For the P-channel Power MOSFET, current polarity of voltages and current have
to be reversed.
Electrical characteristics
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2 Electrical characteristics
(TC= 25 °C unless otherwise specified)
Table 4: Static
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown
voltage VGS = 0 V, ID = 250 µA 60
V
IDSS Zero gate voltage Drain
current
VGS = 0 V, VDS = 60 V
1 µA
VGS = 0 V, VDS = 60 V,
TC = 125 °C
10 µA
IGSS Gate-body leakage
current VDS = 0 V, VGS = ± 20 V
±100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1
2.5 V
RDS(on) Static drain-source on-
resistance VGS = 10 V, ID = 4.5 A
0.023 0.026 Ω
VGS = 4.5 V, ID= 4.5 A
0.028 0.034
Table 5: Dy namic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capac itan ce
VDS = 25 V, f = 1 MHz,
VGS = 0 V
- 3780 - pF
Coss Output capacitance - 262 - pF
Crss Reverse transfer
capacitance - 170 - pF
Qg Total gate charge VDD = 30 V, ID = 9 A,
VGS = 4.5 V (see Figure 14:
"Gate charge test circuit" )
- 30 - nC
Qgs Gate-source charge - 10.8 - nC
Qgd Gate-drain charge - 10.5 - nC
RG Gate input resistance ID = 0 A, gate DC bia s = 0 V,
f = 1 MHz, magnitude of
alternativ e sig nal = 20 mV - 1.7 - Ω
Table 6: Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 30 V, ID = 4.5 A
RG = 4.7 Ω, VGS = 10 V (see
Figure 13: "Switching times
test circuit for resi sti ve load " )
- 51.4 - ns
tr Rise time - 39 - ns
td(off) Turn-off-delay time - 171 - ns
tf Fall time - 21 - ns
For the P-channel Power MOSFET, current polarity of voltages and current have
to be reversed.
STL42P6LLF6
Electrical characteristics
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Table 7: Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSD (1) Forward on voltage VGS = 0 V, ISD = 9 A -
1.1 V
trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs,
VDD = 4.8 V, Tj = 150 °C (see
Figure 15: "Test circ uit for
inductive load switching and diode
recovery times" )
- 34
ns
Qrr Reverse recovery
charge - 48 nC
IRRM Reverse recovery
current - 2.8
A
Notes:
(1)Puls e test: pulse durati on = 300 µs, duty cycle 1.5%
For the P-channel Power MOSFET, current polarity of voltages and current have
to be reversed.
Electrical characteristics
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2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer char a cter i st ics
Figure 6: Normalized gate threshold voltage vs
temperature
Figure 7: Normalized V(BR)DSS vs
temperature
STL42P6LLF6
Electrical characteristics
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Figure 8: Static drain-source on-resistance
Figure 9: Normalized on-resistance vs.
temperature
Figure 10: Gate charge vs gate-source
voltage
Figure 11: Capacitance variations voltage
Figure 12: Source-drain diode forward characteristics
Test circuits
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3 Test circuits
Figure 13: Switching times test circuit for
resistive load
Figure 14: Gate charge test circuit
Figure 15: Test circuit for inductive load switching and diode recovery times
STL42P6LLF6
Package information
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4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1 PowerFLAT™ 5x6 package information
Figure 16: PowerFLAT™ 5x6 type R package outline
Package information
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Table 8: PowerFLAT™ 5x6 type R mechanical data
Dim. mm
Min. Typ. Max.
A 0.80
1.00
A1 0.02
0.05
A2
0.25
b 0.30
0.50
D 5.00 5.20 5.40
E 5.95 6.15 6.35
D2 4.11
4.31
e
1.27
L 0.60
0.80
K 1.275
1.575
E3 2.35
2.55
E4 0.40
0.60
E5 0.08
0.28
Figure 17: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
STL42P6LLF6
Package information
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4.2 PowerFLAT™ 5x6 packing inform ation
Figure 18: PowerFLAT™ 5x6 tape (dimensions are in mm)
Figure 19: PowerFLAT™ 5x6 package orientation in carrier tape
Measur ed f r om c ent er line of spr ock et hole
to center line of pocket .
Cumulative toler ance of 10 s pr ocket
holes is ± 0.20 .
Measur ed f r om c ent er line of spr ock et
hole to cent er line of pocket .
(I)
(II)
(III)
2
2.0±0. 1 ( I )
Bo (5.30±0. 1)
Ko (1.20±0. 1)
±0.05)
Ø1.5 MIN.
Ø1.55±0.05
P
Ao(6.30±0.1)
F(5.50±0.1)(III)
W(12.00±0.3)
1.75±0.1
4.0±0.1 (II)
P0
Y
Y
SECTION Y-Y
C
L
P1(8.00±0.1)
Do
D1
E1
(0.30
T
REF.R0.50
REF 0.20
Base and bulk quantity 3000 pcs
8234350_Tape_rev_C
Package information
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Figure 20: PowerFLAT™ 5x6 reel
STL42P6LLF6
Revision history
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5 Revision history
Table 9: Document rev ision history
Date Revision Changes
28-Oct-2013 1 First release.
25-Aug-2014 2 Modified: Figure 1: "Internal schematic diagram"
Updated: Section 10: "Package mechanical data"
Minor text changes
24-Feb-2015 3
In title description on cover page, changed 0.02 Ω to 0.023 Ω
In features table on cover page, changed 0.028 Ω to 0.026 Ω
Updated Table 2: Absolute ma ximum ratings
Updated Table 4: Static – renamed table and updated Static drain-
source on-resistance values
Updated Table 5: Dynamic – tes t conditions and all typical values
Updated Table 6: Switching tim es – test conditions and all typical
values
Updated Table 7: Source-drain diode – test conditions and all typical
values
Added Secti on 2.2: Electrical characteristics (curves)
Updated Section 4: Package mechanical data
Minor text changes
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