843441AM-100 - Integrated Device Technology

DATA SHEET

FemtoClock® SAS/SATA Clock Generator ICS843441

General Description

The ICS843441 is a low jitter, high performance clock generator. The

ICS843441 is designed for use in applications using the SAS and

SATA interconnect. The ICS843441 uses an external, 25MHz,

parallel resonant crystal to generate four selectable output

frequencies: 75MHz, 100MHz, 150MHz, and 300MHz. This silicon

based approach provides excellent frequency stability and reliability.

The ICS843441 features down and center spread spectrum (SSC)

clocking techniques.

Additional Ordering Information

Features

•Designed for use in SAS, SAS-2, and SATA systems

•Center (±0.33%) Spread Spectrum Clocking (SSC)

•Down (-0.30% or -0.60%) SSC

•Better frequency stability than SAW oscillators

•One differential 3.3V LVPECL output

•Crystal oscillator interface designed for 25MHz

(CL = 18pF) frequency

•External fundamental crystal frequency ensures high reliability

and low aging

•Selectable output frequencies: 75MHz, 100MHz, 150MHz,

300MHz

•Output frequency is tunable with external capacitors

•RMS phase jitter: 1.33ps (typical)

•3.3V operating supply

•0°C to 70°C ambient operating temperature

•Industrial temperature available upon request

•Available in lead-free (RoHS 6) package

Part/Order Number Package Output Frequency

(MHz)

843441AG 16 TSSOP 75, 100, 150, 300

843441AM-75 8 SOIC 75

843441AM-100 8 SOIC 100

843441AM-150 8 SOIC 150

843441AM-300 8 SOIC 300

Block Diagrams

FemtoClock

PLL

OSC

nPLL_SEL

25MHz

XTAL

XTAL_IN

XTAL_OUT

00 = 75MHz

01 = 100MHz

10 = 150MHz

(default)

11 = 300MHz

SSC_SEL(1:0)

F_ S E L( 1: 0)

SSC Output

Control Logic

16- Lead TSSOP

FemtoClock

PLL

OSC

25MHz

XTAL

XTAL_IN

XTAL_OUT

SSC_SEL(1:0) SSC Output

Control Logic

8 - Lead SOIC

Pulldown

Pullup : Pulldown

Pulldown:Pulldown

Pin Assignments

SSC_SEL0

XTAL_IN

XTAL_OUT

VEE F_SEL1

nPLL_SEL

VCC

F_SEL0

SSC_SEL1

VEE

ICS843441

16-Lead TSSOP

4.4mm x 5.0mm x 0.925mm package body

G Package

Top View

ICS843441

8-Lead SOIC, 150 Mil

3.90mm x 4.90mm x 1.375mm package body

M Package

Top View

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Table 1A. Pin Descriptions (SOIC Package)

NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 1B. Pin Descriptions (TSSOP Package)

NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

XTAL_OUT,

XTAL_IN Input Pullup Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

SSC_SEL0,

SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.

CC Power Power supply pin.

6, 7 Q, nQ Output Differential clock outputs. LVPECL interface levels.

EE Power Negative supply pin.

Number Name Type Description

1, 15 VEE Power Negative supply pins.

XTAL_OUT,

XTAL_IN Input Pullup Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

SSC_SEL0,

SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.

5, 6, 7 nc Unused No connect pins.

9, 11 VCC Power Power supply pins.

10 F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.

12, 13 Q, nQ Output Differential clock outputs. LVPECL interface levels.

14 nPLL_SEL Input Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels.

16 F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLDOWN Input Pulldown Resistor 51 kΩ

RPULLUP Input Pullup Resistor 51 kΩ

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Function Tables

Table 3A. SSC_SEL[1:0] Function Table

Table 3B. F_SEL[1:0] Function Table

Table 3B applicable only for 16 Lead TSSOP package.

Inputs

ModeSSC_SEL1 SSC_SEL0

0 (default) 0 (default) SSC Off

0 1 0.60% Down-spread

1 0 0.30% Down-spread

1 1 0.33% Center-spread

Inputs

Output Frequency (MHz)F_SEL1 F_SEL0

00 75

01 100

1 (default) 0 (default) 150

11 300

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C

Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C

Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C

NOTE 1: Output termination with 50Ω to VCC – 2V.

Item Rating

Supply Voltage, VCC 4.6V

Inputs, VI, (LVCMOS)

XTAL_IN

Other Inputs

0V to VCC

-0.5V to VCC + 0.5V

Outputs, IO

Continuos Current

Surge Current

50mA

100mA

Package Thermal Impedance, θJA

16 Lead TSSOP

8 Lead SOIC

81.2°C/W (0 mps)

96.0°C/W (0 lfpm)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Power Supply Voltage 3.135 3.3 3.465 V

IEE Power Supply Current 66 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIH

Input

High Current

F_SEL1 VCC = VIN = 3.465V 5 µA

SSC_SEL[0:1],

F_SEL0, nPLL_SEL VCC = VIN = 3.465V 150 µA

IIL

Input

Low Current

F_SEL1 VCC = 3.465V, VIN = 0V -150 µA

SSC_SEL[0:1],

F_SEL0, nPLL_SEL VCC = 3.465V, VIN = 0V -5 µA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V

VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V

VSWING Peak-to-Peak Output Voltage Swing 0.6 0.9 V

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

AC Electrical Characteristics

Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C

NOTE: Using a 25MHz, 18pF quartz crystal.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Please refer to the Phase Noise plots.

NOTE 2: Refer to Application Section for peak-to-peak jitter calculations.

NOTE 3: Tested per JEDEC 65B.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency

F_SEL(1:0) = 00 75 MHz

F_SEL(1:0) = 01 100 MHz

F_SEL(1:0) = 10 150 MHz

F_SEL(1:0) = 11 300 MHz

tjit(Ø) RMS Phase Jitter

(Random); NOTE 1

75MHz,

Integration Range: 12kHz – 20 MHz 1.33 ps

100MHz,

Integration Range: 12kHz – 20MHz 1.39 ps

150MHz,

Integration Range: 12kHz – 20MHz 1.36 ps

300MHz,

Integration Range: 12kHz – 20MHz 1.37 ps

tjit(per) Period Jitter, RMS;

NOTE 2, 3

75MHz, SSC Off 4.15 ps

100MHz, SSC Off 4.05 ps

150MHz, SSC Off 4.15 ps

300MHz, SSC Off 4.25 ps

tjit(cc) Cycle-to-Cycle Jitter:

NOTE 3

75MHz, SSC Off 31 ps

100MHz, SSC Off 31 ps

150MHz, SSC Off 31 ps

300MHz, SSC Off 31 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 700 ps

odc Output Duty Cycle 45 55 %

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Typical Phase Noise at 100MHz

NOTE: Measured on Aeroflex PN9000

Noise Power dBc

Offset Frequency (Hz)

100MHz

RMS Phase Jitter (Random)

12kHz to 20MHz = 1.39ps (typical)

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Parameter Measurement Information

3.3V LVPECL Output Load AC Test Circuit

Output Rise/Fall Time

Cycle-to-Cycle Jitter

RMS Phase Jitter

Output Duty Cycle/Pulse Width/Period

RMS Period Jitter, Peak-to-Peak

SCOPE

nQx

LVPECL

VEE

VCC

-1.3V ± 0.165V

20%

80% 80%

20%

tRtF

VSWING

➤

tcycle n tcycle n+1

tjit(cc) =

tcycle n – tcycle n+1

1000 Cycles

Offset Frequency

f1f2

Phase Noise Plot

RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers

Noise Power

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

VOH

VREF

VOL

Mean Period

(First edge after trigger)

10,000 cycles

Reference Point

(Trigger Edge)

Histogram

t jit (pk-pk)

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Applications Information

Recommendations for Unused Input Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullups and pulldowns; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

Overdriving the XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 1A. The XTAL_OUT pin can be left floating. The

maximum amplitude of the input signal should not exceed 2V and the

input edge rate can be as slow as 10ns. This configuration requires

that the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the crystal input will attenuate the signal in

half. This can be done in one of two ways. First, R1 and R2 in parallel

should equal the transmission line impedance. For most 50Ω

applications, R1 and R2 can be 100Ω. This can also be

accomplished by removing R1 and making R2 50Ω. By overdriving

the crystal oscillator, the device will be functional, but note, the device

performance is guaranteed by using a quartz crystal.

Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface

VCC XTAL_OUT

XTAL_IN

100

Zo = 50 ohmsRs

Zo = Ro + Rs

.1uf

LVCMOS Driver

XTA L _ O U T

XTA L _ I N

Zo = 50 ohms C2

.1uf

LVPECL Driver

Zo = 50 ohms

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50Ω

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 2A and 2B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination

3.3V

VCC - 2V

50Ω

RTT

Zo = 50Ω

RTT = * Zo

((VOH + VOL) / (VCC – 2)) – 2

3.3V

LVPECL Input

84Ω

3.3V

125Ω

Zo = 50Ω

LVPECL Input

3.3V

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Schematic Example

Figure 3 shows an example of ICS843441 application schematic. In

this example, the device is operated at VCC = 3.3V. An 18pF parallel

resonant 25MHz crystal is used. The load capacitance C1 = 27pF

and C2 = 27pF are recommended for frequency accuracy.

Depending on the parasitics of the printed circuit board layout, these

values might require a slight adjustment to optimize the frequency

accuracy. Crystals with other load capacitance specifications can be

used. This will required adjusting C1 and C2.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS843441 provides separate

power supplies to isolate noise from coupling into the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1µF capacitor in each power pin filter should be placed on the

device side of the PCB and the other components can be placed on

the opposite side.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supply frequencies, it is recommended that component values

be adjusted and if required, additional filtering be added. Additionally,

good general design practices for power plane voltage stability

suggests adding bulk capacitances in the local area of all devices.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure the logic control inputs are properly

set.

Figure 3. ICS843441 Schematic Example

Optional

Y-Termination

Set Logic

Input to

'1'

10uF

27pF

Zo = 50 Ohm

Logic Control Input Examples

SSC_SEL1

8 9

VEE

XTAL_OUT

XTAL_IN

SSC_SEL0

SSC_SEL1 VCC

F_SEL0

VCC

nPLL_SEL

VEE

F_SEL1

XTAL_IN

BLM18BB221SN1

Ferrite Bead

1 2

RU1

3.3V

XTAL_OUT

VCC

LVPECL Termination

F_SEL0

RD2

nPLL_SEL

133

0.1uF

To Logic

Input

pins

SSC_SEL0

27pF

82.5

F_SEL1

RD1

Not Install

82.5

RU2

Not Install

Set Logic

Input to

'0'

0.1uF

18pF

VCC

Zo = 50 Ohm

3.3V

133

25MHz

To Logic

Input

pins

0.1uF

Zo = 50 Ohm

VCC

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Peak-to-Peak Jitter Calculations

A standard deviation of a statistical population or data set is the

square root of its variance. A standard deviation is used to calculate

the probability of an anomaly or to predict a failure. Many times, the

term "root mean square" (RMS) is used synonymously for standard

deviation. This is accurate when referring to the square root of the

mean squared deviation of a signal from a given baseline and the

data set contains a Gaussian distribution with no deterministic

components. A low standard deviation indicates that the data set

tends to be close to the mean with little variation. A large standard

deviation indicates that the data set is spread out and has a large

variation from the mean.

A standard deviation is required when calculating peak-to-peak jitter.

Since true peak-to-peak jitter is random and unbounded, it is

important to always associate a bit error ratio (BER) when specifying

a peak-to-peak jitter limit. Without it, the specification is meaningless.

Given that a BER is application specific, many frequency timing

devices specify jitter as an RMS. This allows the peak-to-peak jitter

to be calculated for the specific application and BER requirement.

Because a standard deviation is the variation from the mean of the

data set, it is important to always calculate the peak-to-peak jitter

using the typical RMS value.

The table shows the BER with its appropriate RMS Multiplier. Once

the BER is chosen, the peak to peak jitter can be calculated by simply

multiplying the RMS multiplier with the typical RMS datasheet

specification. For example, if a 10-12 BER is required, multiply 14.260

times the typical jitter specification.

Jitter (peak-to-peak) = RMS Multiplier x RMS (typical)

This calculation is not specific to one type of Jitter classification. It

can be used to calculate BER on various types of RMS jitter. It is

important that the user understands their jitter requirement to ensure

they are calculating the correct BER for their jitter requirement.

BER RMS Multiplier

10-3 6.582

10-4 7.782

10-5 8.834

10-6 9.784

10-7 10.654

10-8 11.462

10-9 12.218

10-10 12.934

10-11 13.614

10-12 14.260

10-13 14.882

10-14 15.478

10-15 16.028

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS843441.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS843441 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 66mA = 228.69mW

• Power (outputs)MAX = 30mW/Loaded Output pair

Total Power_MAX (3.465V, with all outputs switching) = 228.69mW + 30mW = 258.69mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 96°C/W per Table 6B below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.259W * 96°C/W = 94.864°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6A. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection

Table 6B. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W

θJA vs. Air Flow

Linear Feet per Second 0200500

Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 4.

Figure 4. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of

VCC – 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCC_MAX – VOH_MAX) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V

(VCC_MAX – VOL_MAX) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =

[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =

[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

VOUT

VCC

VCC - 2V

50Ω

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Reliability Information

Table 7A. θJA vs. Air Flow Table for a 16 Lead TSSOP

Table 7B. θJA vs. Air Flow Table for a 8 Lead SOIC

Transistor Count

The transistor count for ICS843441 is: 6303

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W

θJA vs. Air Flow

Linear Feet per Second 0200500

Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Package Outline and Package Dimensions

Package Outline - G Suffix for 16-Lead TSSOP

Table 8A. Package Dimensions for 16 Lead TSSOP

Reference Document: JEDEC Publication 95, MO-153

Package Outline - M Suffix for 8 Lead SOIC

Table 8B. Package Dimensions for 8 Lead SOIC

Reference Document: JEDEC Publication 95, MS-012

All Dimensions in Millimeters

Symbol Minimum Maximum

N16

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D4.90 5.10

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

All Dimensions in Millimeters

Symbol Minimum Maximum

A1.35 1.75

A1 0.10 0.25

B0.33 0.51

C0.19 0.25

D4.80 5.00

E3.80 4.00

e1.27 Basic

H5.80 6.20

h0.25 0.50

L0.40 1.27

α0° 8°

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Ordering Information

Table 9. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

843441AGLF 843441AL 16 Lead “Lead-Free” TSSOP Tube 0°C to 70°C

843441AGLFT 843441AL 16 Lead “Lead-Free” TSSOP 2500 Tape & Reel 0°C to 70°C

843441AM-75LF 3441A75L 8 Lead “Lead-Free” SOIC Tube 0°C to 70°C

843441AM-75LFT 3441A75L 8 Lead “Lead-Free” SOIC 2500 Tape & Reel 0°C to 70°C

843441AM-100LF 441A100L 8 Lead “Lead-Free” SOIC Tube 0°C to 70°C

843441AM-100LFT 441A100L 8 Lead “Lead-Free” SOIC 2500 Tape & Reel 0°C to 70°C

843441AM-150LF 441A150L 8 Lead “Lead-Free” SOIC Tube 0°C to 70°C

843441AM-150LFT 441A150L 8 Lead “Lead-Free” SOIC 2500 Tape & Reel 0°C to 70°C

843441AM-300LF 441A300L 8 Lead “Lead-Free” SOIC Tube 0°C to 70°C

843441AM-300LFT 441A300L 8 Lead “Lead-Free” SOIC 2500 Tape & Reel 0°C to 70°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product

for use in life support devices or critical medical instruments.

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

Revision History Sheet

Rev Table Page Description of Change Date

A T3A 3 SSC_SEL Function Table - updated Mode column. 5/18/11

ICS843441 Data Sheet FEMTOCLOCK® SAS/SATA CLOCK GENERATOR

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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

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