Rev: 1.03a 5/2003 1/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8160Z18/36AT-300/250/200/150
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Functional Description
The GS8160Z18/36AT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8160Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-300 -250 -200 -150 Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tCycle
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Curr (x18)
Curr (x32/x36)
335
390
280
330
230
270
185
210
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr (x18)
Curr (x32/x36)
230
270
210
240
185
205
170
190
mA
mA
Rev: 1.03a 5/2003 2/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
GS8160Z18AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
VDD
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
VSS
VDDQ
VDDQ
VSS
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
A
E1
E2
NC
NC
BB
BA
E3
CK
W
CKE
VDD
VSS
G
ADV
A
A
A
A
A
1M x 18
Top View
DQPA
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03a 5/2003 3/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
GS8160Z36AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
VDD
VSS
DQD
DQD2
VDDQ
VSS
DQD
DQD
DQD
VSS
VDDQ
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
A
E1
E2
BD
BC
BB
BA
E3
CK
W
CKE
VDD
VSS
G
ADV
A
A
A
A
A
512K x 36
Top View
DQB
DQPB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQPA
DQC
DQC
DQC
DQD
DQD
DQD
DQPD
DQC
DQPC
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03a 5/2003 4/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
100-Pin TQFP Pin Descriptions
Symbol Type Description
A0, A1In Burst Address Inputs; Preload the burst counter
A In Address Inputs
CK In Clock Input Signal
BAIn Byte Write signal for data inputs DQA1-DQA9; active low
BBIn Byte Write signal for data inputs DQB1-DQB9; active low
BCIn Byte Write signal for data inputs DQC1-DQC9; active low
BDIn Byte Write signal for data inputs DQD1-DQD9; active low
WIn Write Enable; active low
E1In Chip Enable; active low
E2In Chip Enable; Active High. For self decoded depth expansion
E3In Chip Enable; Active Low. For self decoded depth expansion
GIn Output Enable; active low
ADV In Advance/Load; Burst address counter control pin
CKE In Clock Input Buffer Enable; active low
NC —No Connect
DQAI/O Byte A Data Input and Output pins
DQBI/O Byte B Data Input and Output pins
DQCI/O Byte C Data Input and Output pins
DQDI/O Byte D Data Input and Output pins
ZZ In Power down control; active high
FT In Pipeline/Flow Through Mode Control; active low
LBO In Linear Burst Order; active low
VDD In Core power supply
VSS In Ground
VDDQ In Output driver power supply
Rev: 1.03a 5/2003 5/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
GS8160Z18/36A NBT SRAM Functional Block Diagram
K
SA1
SA0 Burst
Counter
LBO
ADV
Memory
Array
E3
E2
E1
G
W
BD
BC
BB
BA
CK
CKE
D Q
FT
DQa–DQn
K
SA1’
SA0’
D Q
Match
Write Address
Register 2
Write Address
Register 1
Write Data
Register 2
Write Data
Register 1
KK
KK
K
K
Sense Amps
Write Drivers
Read, Write and
Data Coherency
Control Logic
FT
A0–An
Rev: 1.03a 5/2003 6/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function W BABBBCBD
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Rev: 1.03a 5/2003 7/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Synchronous Truth Table
Operation Type Address E1E2E3ZZ ADV W Bx GCKE CK DQ Notes
Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03a 5/2003 8/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Deselect
New Read New Write
Burst Read Burst Write
W
R
B
R
B
W
DD
B
B
W
R
DB
W
R
DD
Pipeline and Flow Through Read Write Control State Diagram
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
WR
Rev: 1.03a 5/2003 9/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Intermediate Intermediate
Intermediate
Intermediate Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
BWB
R
B
D
R
W
R
W
DD
Pipeline Mode Data I/O State Diagram
Current State (n) Next State (n+2)
Transition
ƒ
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State Intermediate
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Next State
State
Rev: 1.03a 5/2003 10/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
High Z
(Data In)
Data Out
(Q Valid)
High Z
BWB
R
B
D
R
W
R
W
DD
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Flow Through Mode Data I/O State Diagram
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.03a 5/2003 11/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO L Linear Burst
H Interleaved Burst
Output Register Control FT L Flow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Linear Burst Sequence
N
ote: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.03a 5/2003 12/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
CK
ZZ tZZR
tZZH
tZZS
~
~
~
~
Sleep
~
~
~
~~
~
Rev: 1.03a 5/2003 13/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Rev: 1.03a 5/2003 14/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 2.0 —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.8 V 1
VDDQ I/O Input High Voltage VIHQ 2.0 —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.8 V 1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.03a 5/2003 15/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions) TA02570°C2
Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 45pF
Input/Output Capacitance CI/O VOUT = 0 V 67pF
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2
Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2
Junction to Case (TOP) —RΘJC 9°C/W 3
20% tKC
V
SS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Rev: 1.03a 5/2003 16/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA
ZZ Input Current IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 8 mA —0.4 V
DQ
VDDQ/2
50Ω30pF*
Output Load 1
* Distributed Test Jig Capacitance
Rev: 1.03a 5/2003 17/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Operating Currents
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Parameter Test Conditions Mode Symbol
-300 -250 -200 -150
Unit
0
to 70°C
–40
to 85°C
0
to 70°C
–40
to 85°C
0
to 70°C
–40
to 85°C
0
to 70°C
–40
to 85°C
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x32/
x36)
Pipeline IDD
IDDQ
345
45
355
45
290
40
300
40
240
30
250
30
190
20
200
20 mA
Flow Through IDD
IDDQ
240
30
250
30
220
20
230
20
190
15
200
15
175
15
185
15 mA
(x18)
Pipeline IDD
IDDQ
310
25
320
25
260
20
270
20
215
15
225
15
170
15
180
15 mA
Flow Through IDD
IDDQ
215
15
225
15
200
10
210
10
175
10
185
10
160
10
170
10 mA
Standby
Current ZZ ≥ VDD – 0.2 V —
Pipeline ISB 40 50 40 50 40 50 40 50 mA
Flow Through ISB 40 50 40 50 40 50 40 50 mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—
Pipeline IDD 85 90 85 90 75 80 60 65 mA
Flow Through IDD 60 65 60 65 50 55 50 55 mA
Rev: 1.03a 5/2003 18/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter Symbol -300 -250 -200 -150 Unit
Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 3.3 —4.0 —5.0 —6.7 —ns
Clock to Output Valid tKQ —2.5 —2.5 —3.0 —3.8 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —ns
Setup time tS 1.0 —1.2 —1.4 —1.5 —ns
Hold time tH 0.1 —0.2 —0.4 —0.5 —ns
Flow Through
Clock Cycle Time tKC 5.0 —5.5 —6.5 —7.5 —ns
Clock to Output Valid tKQ —5.0 —5.5 —6.5 —7.5 ns
Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —ns
Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —ns
Setup time tS 1.4 —1.5 —1.5 —1.5 —ns
Hold time tH 0.4 —0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.3 —1.3 —1.3 —1.5 —ns
Clock LOW Time tKL 1.5 —1.5 —1.5 —1.7 —ns
Clock to Output in
High-Z tHZ11.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0 ns
G to Output Valid tOE —2.5 —2.5 —3.0 —3.8 ns
G to output in Low-Z tOLZ10—0—0—0—ns
G to output in High-Z tOHZ1—2.5 —2.5 —3.0 —3.8 ns
ZZ setup time tZZS25—5—5—5—ns
ZZ hold time tZZH21—1—1—1—ns
ZZ recovery tZZR 20 —20 —20 —20 —ns
Rev: 1.03a 5/2003 19/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Pipeline Mode Timing (NBT)
Write A Read B Suspend Read C Write D Suspend1 Write Read E Deselect
tHZ
tKQX
tKQ
tLZ
tS
tKQXtKQ
tKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
AB CD
D(A) Q(B) Q(C) D(D) Q(E)
E
CK
CKE
E
ADV
W
Bn
A0–An
DQ
Rev: 1.03a 5/2003 20/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Flow Through Mode Timing (NBT)
Write A Read B Suspend Read C Write D1 Suspend1 Write Read E Deselect
tHZ
tKQXtLZ
tHZ
tKQXtKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
AB CD E
D(A) Q(B) Q(C) D(D) Q(E)
CK
CKE
E
ADV
W
Bn
A0–An
DQ
Rev: 1.03a 5/2003 21/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
TQFP Package Drawing
BPR 1999.05.18
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 —0.20
D Terminal Dimension 21.9 22.0 20.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch —0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length —1.00 —
Y Coplanarity ——0.10
θLead Angle 0°—7°
Rev: 1.03a 5/2003 22/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
Ordering Information—GSI NBT Synchronous SRAM
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
1M x 18 GS8160Z18AT-300 NBT Pipeline/Flow Through TQFP 300/5 C
1M x 18 GS8160Z18AT-250 NBT Pipeline/Flow Through TQFP 250/5.5 C
1M x 18 GS8160Z18AT-200 NBT Pipeline/Flow Through TQFP 200/6.5 C
1M x 18 GS8160Z18AT-150 NBT Pipeline/Flow Through TQFP 150/7.5 C
512K x 36 GS8160Z36AT-300 NBT Pipeline/Flow Through TQFP 300/5 C
512K x 36 GS8160Z36AT-250 NBT Pipeline/Flow Through TQFP 250/5.5 C
512K x 36 GS8160Z36AT-200 NBT Pipeline/Flow Through TQFP 200/6.5 C
512K x 36 GS8160Z36AT-150 NBT Pipeline/Flow Through TQFP 150/7.5 C
1M x 18 GS8160Z18AT-300I NBT Pipeline/Flow Through TQFP 300/5 I
1M x 18 GS8160Z18AT-250I NBT Pipeline/Flow Through TQFP 250/5.5 I
1M x 18 GS8160Z18AT-200I NBT Pipeline/Flow Through TQFP 200/6.5 I
1M x 18 GS8160Z18AT-150I NBT Pipeline/Flow Through TQFP 150/7.5 I
512K x 36 GS8160Z36AT-300I NBT Pipeline/Flow Through TQFP 300/5 I
512K x 36 GS8160Z36AT-250I NBT Pipeline/Flow Through TQFP 250/5.5 I
512K x 36 GS8160Z36AT-200I NBT Pipeline/Flow Through TQFP 200/6.5 I
512K x 36 GS8160Z36AT-150I NBT Pipeline/Flow Through TQFP 150/7.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160Z36AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03a 5/2003 23/23 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36AT-300/250/200/150
Preliminary
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content Page;Revisions;Reason
8160Z18A_r1 • Creation of new datasheet
8160Z18A_r1;
8160Z18A_r1_01 Content
• Updated FT power numbers
• Updated AC Characteristics table
• Updated ZZ recovery time diagram
• Updated AC Test Conditions table and removed Output Load
2 diagram
8160Z18A_r1_01;
8160Z18A_r1_02 Content
• Removed extraneous VDDQ1 table on page 13 and changed
VDDQ2 table to VDDQ
• Removed pin locations from pin description table
GS8160ZxxA_r1_02;
GS8160ZxxA_r1_03 Content • Entire datasheet rewritten due to design changes
