MC27C160-120XM1TR - STMicroelectronics

1/18July 2001

M27C160

16 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM

■5V ±10% SUPPLY VOLTAGE in READ

OPERATION

■ACCESS TIME: 70ns

■BYTE-WIDE or WORD-WIDE

CONFIGURABLE

■16 Mbit MASK ROM REPLACEMENT

■LOW POWER CONSUMPTION

– Active Current 70mA at 8MHz

– Standby Current 100µA

■PROGRAMMING VOLTAGE: 12.5V ±0.25V

■PROGRAMMING TIME: 100µs/word

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: B1h

DESCRIPTION

The M27C160 is a 16 Mbit EPROM offered in the

two ranges UV (ultra violet erase) and OTP (one

time programmable). It is ideally suited for micro-

processor systemsrequiring large data or program

storage and is organised as either 2 Mbit words of

8 bit or 1 Mbit words of 16 bit. The pin-out is com-

patible with a 16 Mbit Mask ROM.

The FDIP42W (window ceramic frit-seal package)

has a transparent lid which allows the user to ex-

pose the chipto ultravioletlight to erasethe bit pat-

tern. A new pattern can then be written rapidly to

the device by following the programming proce-

dure.

For applications where the content isprogrammed

only one time and erasure is not required, the

M27C160 is offered in PDIP42, SDIP42, PLCC44

and SO44 packages.

FDIP42W (F)

SO44 (M)

PDIP42 (B)

PLCC44 (K)

SDIP42 (S)

Figure 1. Logic Diagram

AI00739B

A0-A19

BYTEVPP

Q0-Q14

VCC

M27C160

VSS

Q15A–1

M27C160

2/18

Figure 2B. PLCC Connections

AI03012

A11

A14

Q12

VSS

A10

A16

BYTEVPP

A13

VSS

M27C160

A12

Q13

VSS

Q14

Q10

A1 A15

Q15A–1G

Q11

VCC

A18

A17

A19

Figure 2A. DIP Connections

VSS

A13

VSS

A14

A15

A12

A16

BYTEVPP

Q15A-1

Q5Q2

Q3 VCC

Q11 Q4

Q14

A8A17

A18 A19

AI00740

M27C160

Q13

A11

A10

Q10

Q12

Figure 2C. SO Connections

VSS

A13

VSS

A14

A15

A12

A16

BYTEVPP

Q15A-1

Q5Q2

Q3 VCC

Q11 Q4

Q14

A19A18

NC NC

AI01264

M27C160

2322

17Q1

Q13

A11

A10

Q10 21 Q12

A17 A8

Table 1. Signal Names

A0-A19 Address Inputs

Q0-Q7 Data Outputs

Q8-Q14 Data Outputs

Q15A–1 Data Output / Address Input

E Chip Enable

GOutput Enable

BYTEVPP Byte Mode / Program Supply

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

3/18

M27C160

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions forextended periods may affect device reliability. Referalso to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = VIH or VIL,V

ID = 12V ±0.5V.

Table 4. Electronic Signature

Note: Outputs Q15-Q8 are set to ’0’.

Symbol Parameter Value Unit

TAAmbient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO(2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Mode E G BYTEVPP A9 Q15A–1 Q8-Q14 Q7-Q0

Read Word-wide VIL VIL VIH X Data Out Data Out Data Out

Read Byte-wide Upper VIL VIL VIL XVIH Hi-Z Data Out

Read Byte-wide Lower VIL VIL VIL XVIL Hi-Z Data Out

Output Disable VIL VIH X X Hi-Z Hi-Z Hi-Z

Program VIL Pulse VIH VPP X Data In Data In Data In

Verify VIH VIL VPP X Data Out Data Out Data Out

Program Inhibit VIH VIH VPP X Hi-Z Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z Hi-Z

Electronic Signature VIL VIL VIH VID Code Codes Codes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 00100000 20h

Device Code VIH 10110001 B1h

M27C160

4/18

DEVICE OPERATION

The operating modes of the M27C160are listed in

the OperatingModes Table. A single power supply

is required in the read mode. All inputs are TTL

compatible except for VPP and 12V on A9 for the

Electronic Signature.

Read Mode

The M27C160 has two organisations, Word-wide

and Byte-wide. The organisation is selected by the

signal level on the BYTEVPP pin. When BYTEVPP

is at VIH the Word-wide organisation is selected

and the Q15A–1 pin is used for Q15 Data Output.

When the BYTEVPP pin is at VIL the Byte-wide or-

ganisation is selected and the Q15A–1 pin is used

for the Address Input A–1. When the memory is

logically regarded as 16 bit wide, but read in the

Byte-wide organisation, then with A–1 at VIL the

lower 8bits of the 16bit data are selected andwith

A–1 at VIH the upper 8 bits of the 16 bit data are

selected.

The M27C160 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. In addition the Word-wide or

Byte- wide organisation must be selected.

Chip Enable(E) is the power control and should be

used for device selection. Output Enable (G)is the

output control and should be used to gate data to

the output pins independent of device selection.

Assuming that the addresses are stable, the ad-

dress access time (tAVQV) is equal to the delay

from E to output (tELQV). Data is available at the

output after a delay of tGLQV from the falling edge

of G, assuming that E has been low and the ad-

dresses have beenstable forat least tAVQV-tGLQV.

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤10ns ≤20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL= 30pF for High Speed

CL= 100pF for Standard

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance (1) (TA=25°C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance (except BYTEVPP)V

IN =0V 10 pF

Input Capacitance (BYTEVPP)V

IN =0V 120 pF

COUT Output Capacitance VOUT =0V 12 pF

5/18

M27C160

Table 7. Read Mode DC Characteristics (1)

(TA= 0 to 70 °C or –40 to 85 °C; VCC =5V±5% or 5V ±10%; VPP =V

CC)

Note: 1. VCC must be applied simultaneously withor before VPP and removed simultaneously or after VPP.

2. Maximum DC voltage on Output is VCC +0.5V.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO Output Leakage Current 0V ≤VOUT ≤VCC ±10 µA

ICC Supply Current

E=V

IL,G=V

IL,

IOUT = 0mA, f = 8MHz 70 mA

E=V

IL,G=V

IL,

IOUT = 0mA, f = 5MHz 50 mA

ICC1 Supply Current (Standby) TTL E = VIH 1mA

CC2 Supply Current (Standby) CMOS E>V

CC – 0.2V 100 µA

IPP Program Current VPP =V

CC 10 µA

VIL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC +1 V

OL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA2.4 V

Standby Mode

The M27C160 has a standby mode which reduces

the active current from 50mA to 100µA. The

M27C160 is placed in thestandby mode by apply-

ing aCMOS highsignal to the Einput. When inthe

standby mode, the outputs are in a high imped-

ance state, independent of the G input.

Two Line Output Control

Because EPROMs are usually used in larger

memory arrays, this product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control

lines, E should bedecoded and used as theprima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system controlbus. This ensures that all deselect-

ed memory devices are in their low powerstandby

mode and that the output pins are only active

when data is required from a particular memory

device.

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

supplies to the devices. The supply current ICC

has three segments of importance to the system

designer: the standby current, the active current

and the transient peaks that are produced by the

falling and rising edges of E.

The magnitude of the transient current peaks is

dependent on the capacitiveand inductive loading

of the device outputs. The associated transient

voltage peaks can be suppressed by complying

with the two line output control and by properly se-

lected decoupling capacitors. It is recommended

that a 0.1µF ceramic capacitor is used on every

device between VCC and VSS. This should be a

high frequency type of low inherent inductance

and should be placed as close as possible to the

device. In addition, a 4.7µF electrolytic capacitor

should be used between VCC and VSS for every

eight devices.

This capacitor should be mounted near the power

supply connection point. The purpose of this ca-

pacitor isto overcome the voltage drop caused by

the inductive effects of PCB traces.

M27C160

6/18

Figure 5. Word-Wide Read Mode AC Waveforms

Note: BYTEVPP =V

IH.

AI00741B

tAXQX

tEHQZ

A0-A19

Q0-Q15

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

VALID

Table 8. Read Mode AC Characteristics (1)

(TA= 0 to 70 °C or –40 to 85 °C; VCC =5V±5% or 5V ±10%; VPP =V

CC)

Note: 1. VCC must be applied simultaneously withor before VPP and removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Symbol Alt Parameter Test Condition

M27C160

Unit

-70 (3) -90 -100 -120/-150

Min Max Min Max Min Max Min Max

tAVQV tACC Address Validto

Output Valid E=V

IL,G=V

IL 70 90 100 120 ns

tBHQV tST BYTE High to

Output Valid E=V

IL,G=V

IL 70 90 100 120 ns

tELQV tCE Chip Enable Low to

Output Valid G=V

IL 70 90 100 120 ns

tGLQV tOE Output Enable Low

to Output Valid E=V

IL 35 45 50 60 ns

tBLQZ (2) tSTD BYTE Lowto Output

Hi-Z E=V

IL,G=V

IL 30 30 40 50 ns

tEHQZ (2) tDF Chip Enable High to

Output Hi-Z G=V

IL 025030040050ns

GHQZ (2) tDF Output Enable High

to OutputHi-Z E=V

IL 025030040050ns

AXQX tOH Address Transition

to Output Transition E=V

IL,G=V

IL 5555ns

BLQX tOH BYTE Low to

Output Transition E=V

IL,G=V

IL 5555ns

7/18

M27C160

Figure 6. Byte-Wide Read Mode AC Waveforms

Note: BYTEVPP =V

IL.

Figure 7. BYTE Transition AC Waveforms

Note: Chip Enable (E) and Output Enable (G) = VIL.

AI00742B

tAXQX

tEHQZ

A–1,A0-A19

Q0-Q7

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

VALID

AI00743C

tAXQX

tBHQV

A0-A19

BYTEVPP

tAVQV

tBLQX

tBLQZ

VALID

Hi-Z

A–1

DATA OUT

VALID

Q0-Q7

Q8-Q15

M27C160

8/18

Table 9. Programming Mode DC Characteristics (1)

(TA=25°C; VCC = 6.25V ±0.25V; VPP = 12.5V ±0.25V)

Note: 1. VCC must be applied simultaneously withor before VPP and removed simultaneously or after VPP.

Table 10. Programming Mode AC Characteristics (1)

(TA=25°C; VCC = 6.25V ±0.25V; VPP = 12.5V ±0.25V)

Note: 1. VCC must be applied simultaneously withor before VPP and removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0≤VIN ≤VCC ±1µA

ICC Supply Current 50 mA

IPP Program Current E =VIL 50 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.4 VCC +0.5 V

OL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –2.5mA 3.5 V

VID A9 Voltage 11.5 12.5 V

Symbol Alt Parameter Test Condition Min Max Unit

tAVEL tAS Address Valid to Chip Enable Low 2 µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

tVPHAV tVPS VPP High to Address Valid 2µs

tVCHAV tVCS VCC High to Address Valid 2 µs

tELEH tPW Chip Enable Program Pulse Width 45 55 µs

tEHQX tDH Chip Enable High to Input Transition 2 µs

tQXGL tOES Input Transition to Output Enable Low 2 µs

tGLQV tOE Output Enable Low to Output Valid 120 ns

tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns

tGHAX tAH Output Enable High to Address

Transition 0ns

Programming

When delivered (and after each erasure for UV

EPROM), all bits of the M27C160 are in the ’1’

state. Data is introduced by selectively program-

ming ’0’s into the desired bit locations. Although

only ’0’s will beprogrammed, both ’1’s and ’0’s can

be present in the data word. The only way to

change a’0’to a ’1’is by die exposure to ultraviolet

light (UV EPROM). The M27C160 is in the pro-

gramming mode when VPP input is at 12.5V, G is

at VIH and E is pulsed to VIL. The data to be pro-

grammed isapplied to 16bits in parallel to thedata

output pins. The levels required for the address

and data inputs are TTL. VCC is specified to be

6.25V ±0.25V.

9/18

M27C160

PRESTO III Programming Algorithm

The PRESTO III Programming Algorithm allows

the whole array to be programed with a guaran-

teed margin in a typicaltime of 52.5 seconds. Pro-

gramming with PRESTO III consists of applying a

sequence of 50µs program pulses to each word

until a correct verify occurs (see Figure 9). During

programing and verify operation a MARGIN

MODE circuitis automatically activated to guaran-

tee that each cell is programed with enough mar-

gin. No overprogram pulse is applied since the

verify in MARGIN MODE provides the necessary

margin to each programmed cell.

Program Inhibit

Programming of multiple M27C160s in parallel

with different datais also easily accomplished. Ex-

cept for E, all like inputs including G of the parallel

M27C160 may be common. A TTL low level pulse

applied to a M27C160’s E input and VPP at 12.5V,

will program that M27C160. A high level E input in-

hibits the other M27C160s from being pro-

grammed.

Program Verify

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with E

at VIH and G at VIL,V

PP at 12.5V and VCC at

6.25V.

Figure 8. Programming and Verify Modes AC Waveforms

tAVEL

VALID

AI00744

A0-A19

Q0-Q15

BYTEVPP

VCC

DATA IN DATA OUT

tQVEL

tVPHAV

tVCHAV

tEHQX

tELEH

tGLQV

tQXGL

tGHQZ

tGHAX

PROGRAM VERIFY

Figure 9. Programming Flowchart

AI01044B

n=0

Last

Addr

VERIFY

E=50µs Pulse

++n

=25 ++ Addr

VCC = 6.25V, VPP = 12.5V

FAIL

CHECK ALL WORDS

BYTEVPP =VIH

1st: VCC =6V

2nd: VCC = 4.2V

YES

M27C160

10/18

Electronic Signature

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode

is intended for use by programming equipment to

automatically matchthe device tobe programmed

with its corresponding programming algorithm.

The ES mode is functional in the 25°C±5°C am-

bient temperaturerange that is required when pro-

gramming the M27C160. To activate the ES

mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the

M27C160, with VPP =V

CC = 5V. Two identifier

bytes maythen be sequencedfrom the device out-

puts bytoggling addressline A0 fromVIL toVIH. All

other address lines must be held at VIL during

Electronic Signature mode. Byte 0 (A0 = VIL) rep-

resents the manufacturer code and byte 1

(A0=V

IH) the device identifier code. For the ST-

Microelectronics M27C160, these two identifier

bytes are given in Table 4 and can be read-out on

outputs Q7 to Q0.

ERASURE OPERATION (applies to UV EPROM)

The erasure characteristics of the M27C160 is

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that

sunlight and some type of fluorescent lamps have

wavelengths in the 3000-4000 Å range. Research

shows that constant exposure to room level fluo-

rescent lighting could erase a typical M27C160 in

about 3 years, while it would take approximately 1

week to cause erasure when exposed to direct

sunlight. If the M27C160 is to be exposed to these

types of lighting conditions for extended periodsof

time, itis suggested that opaque labels beput over

the M27C160window to preventunintentional era-

sure. The recommended erasure procedure for

M27C160 is exposure to short wave ultraviolet

light which has a wavelength of 2537 Å. The inte-

grated dose (i.e. UV intensity x exposure time) for

erasure should be a minimum of 30 W-sec/cm2.

The erasure time with this dosage is approximate-

ly 30 to 40 minutes using an ultraviolet lamp with

12000 µW/cm2power rating. The M27C160

should be placed within 2.5cm (1 inch) of the lamp

tubes during theerasure. Some lamps have a filter

on their tubes which should be removed before

erasure.

11/18

M27C160

Table 11. OrderingInformation Scheme

Note: 1. High Speed, see AC Characteristics section for further information.

2. This speed is guaranteed at VCC =5V±5%.

3. The M27C160 product PLCC44 package version is offered in theTemperature Range 0 to 70 °C only.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

Example: M27C160 -70 X M 1 TR

Device Type

M27

Supply Voltage

C=5V

Device Function

160 = 16 Mbit (2mb x 8 or 1Mb x 16)

Speed

-70(1,2) =70ns

-90 = 90 ns

-100 = 100 ns

-120 = 120 ns

-150 = 150 ns

VCC Tolerance

blank = ±10%

X=±5%

Package

F = FDIP42W

B = PDIP42

S = SDIP42

K = PLCC44(3)

M = SO44

Temperature Range

1=0to70°C

6=–40to85°C

Options

TR = Tape & Reel Packing

M27C160

12/18

Table 12. Revision History

Date Revision Details

January 1999 First Issue

09/20/00 AN620 Reference removed

19-Jul-2001 SDIP42 package added

13/18

M27C160

Table 13. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 5.72 0.225

A1 0.51 1.40 0.020 0.055

A2 3.91 4.57 0.154 0.180

A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022

B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012

D 54.41 54.86 2.142 2.160

D2 50.80 – – 2.000 – –

E 15.24 – – 0.600 – –

E1 14.50 14.90 0.571 0.587

e 2.54 – – 0.100 – –

eA 14.99 – – 0.590 – –

eB 16.18 18.03 0.637 0.710

L 3.18 0.125

S 1.52 2.49 0.060 0.098

K 9.40 – – 0.370 – –

K1 11.43 – – 0.450 – –

α4°11°4°11°

N42 42

Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline

Drawing is not to scale.

FDIPW-b

B1 B e1

E1 E

M27C160

14/18

Table 14. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A – 5.08 – 0.200

A1 0.25 – 0.010 –

A2 3.56 4.06 0.140 0.160

B 0.38 0.53 0.015 0.021

B1 1.27 1.65 0.050 0.065

C 0.20 0.36 0.008 0.014

D 52.20 52.71 2.055 2.075

D2 50.80 – – 2.000 – –

E 15.24 – – 0.600 – –

E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –

eA 14.99 – – 0.590 – –

eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135

S 0.86 1.37 0.034 0.054

α0°10°0°10°

N42 42

Figure 11. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Outline

Drawing is not to scale.

PDIP

B1 B e1

E1 E

15/18

M27C160

Table 15. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 5.08 0.200

A1 0.51 0.020

A2 3.81 3.05 4.57 0.150 0.120 0.180

b 0.46 0.38 0.56 0.018 0.015 0.022

b2 1.02 0.89 1.14 0.040 0.035 0.045

c 0.25 0.23 0.38 0.010 0.009 0.015

D 36.83 36.58 37.08 1.450 1.440 1.460

e 1.78 – – 0.070 – –

E 15.24 16.00 0.600 0.630

E1 13.72 12.70 14.48 0.540 0.500 0.570

eA 15.24 – – 0.600 – –

eB 18.54 0.730

L 3.30 2.54 3.56 0.130 0.100 0.140

S 0.64 0.025

N42 42

Figure 12. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Outline

Drawing is not to scale.

SDIP

b2 b e

E1 E

M27C160

16/18

Table 16. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 4.20 4.70 0.165 0.185

A1 2.29 3.04 0.090 0.120

A2 – 0.51 – 0.020

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

D 17.40 17.65 0.685 0.695

D1 16.51 16.66 0.650 0.656

D2 14.99 16.00 0.590 0.630

E 17.40 17.65 0.685 0.695

E1 16.51 16.66 0.650 0.656

E2 14.99 16.00 0.590 0.630

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010

R 0.89 – – 0.035 – –

N44 44

CP 0.10 0.004

Figure 13. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline

Drawing is not to scale.

PLCC

Ne E1 E

D2/E2 e

0.51 (.020)

1.14 (.045)

17/18

M27C160

Table 17. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010

A2 2.25 2.35 0.089 0.093

B 0.50 0.020

C 0.10 0.25 0.004 0.010

D 28.10 28.30 1.106 1.114

E 13.20 13.40 0.520 0.528

e 1.27 – – 0.050 – –

H 15.90 16.10 0.626 0.634

L 0.80 – – 0.031 – –

α3°––3°––

N44 44

CP 0.10 0.004

Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Drawing is not to scale.

SO-b

LA1 α

M27C160

18/18

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor for any infringement of patents or other rights ofthird parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

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