LTC4224IMS-1#TRPBF - Linear Technology Corporation

LTC4224-1/LTC4224-2

422412fa

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Compact Dual Low

Voltage Hot Swap Controller

The LTC

4224 Dual Low Voltage Hot Swap™ controller

allows a board to be safely inserted and removed from a

live backplane. It controls two supplies with external N-

channel MOSFETs and operates with one supply as low

as 1V provided the other supply is 2.7V or greater. The

LTC4224 can ramp up the supplies in any order and at

adjustable ramp rates. To minimize the number of external

components and PCB area, the gate capacitor is optional,

all timing delays are generated internally, and the ON pins

have integrated pull-up currents.

Protection against overcurrent faults is provided by a fast-

acting current limit and timed circuit breakers. A FAULT pin

signals overcurrent faults. The LTC4224-1 remains off after

a fault, while the LTC4224-2 automatically tries to apply

power again after a four second cool-down period.

Normal Power-Up Waveform

n Allows Safe Board Insertion and Removal from a

Live Backplane

n Controls Load Voltages from 1V to 6V

n No Gate Components Required

n Adjustable Current Limit with Circuit Breaker

n Limits Peak Fault Current in ≤1μs

n No External Timing Capacitor Required

n Adjustable Supply Voltage Power-Up Rate

n Gate Drive for External N-channel MOSFET

n LTC4224-1: Latchoff After Fault

n LTC4224-2: Automatic Retry After Fault

n 10-Lead MSOP and 3mm × 2mm DFN Packages

n Optical Networking

n Low Voltage Hot Swap

n Electronic Circuit Breakers L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

422412 TA01a

LTC4224

VCC1

FAULT

SENSE1 SENSE2 GATE1 GATE2

ON1

ON2

GND GND

VCC2

3.3V

0.015Ω

0.010Ω

FDS6911

3.3V

LTC4224

CONNECTOR PLUG-IN

CARD

VOUT1

5V/DIV

VOUT2

5V/DIV

0.5ms/DIV 422412 TA01b

IIN1

2A/DIV

IIN2

2A/DIV

CLOAD = 150µF

LTC4224-1/LTC4224-2

422412fa

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCCn) .................................. –0.3V to 9V

Input Voltages

SENSEn, ONn ........................................... –0.3V to 9V

Output Voltages

GATEn – VCC (Note 4) .............................. –0.3V to 5V

FAULT ....................................................... –0.3V to 9V

(Notes 1, 2)

TOP VIEW

DDB PACKAGE

10-LEAD

(

3mm × 2mm

)

PLASTIC DFN

SENSE1

VCC1

GATE1

FAULT

ON1

SENSE2

VCC2

GATE2

GND

ON2

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 11) PCB GND CONNECTION OPTIONAL

SENSE1

VCC1

GATE1

FAULT

ON1

SENSE2

VCC2

GATE2

GND

ON2

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 160°C/W

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4224CDDB-1#PBF LTC4224CDDB-1#TRPBF LDTT 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C

LTC4224CDDB-2#PBF LTC4224CDDB-2#TRPBF LDNV 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C

LTC4224IDDB-1#PBF LTC4224IDDB-1#TRPBF LDTT 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C

LTC4224IDDB-2#PBF LTC4224IDDB-2#TRPBF LDNV 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C

LTC4224CMS-1#PBF LTC4224CMS-1#TRPBF LTDTV 10-Lead Plastic MSOP 0°C to 70°C

LTC4224CMS-2#PBF LTC4224CMS-2#TRPBF LTDNW 10-Lead Plastic MSOP 0°C to 70°C

LTC4224IMS-1#PBF LTC4224IMS-1#TRPBF LTDTV 10-Lead Plastic MSOP –40°C to 85°C

LTC4224IMS-2#PBF LTC4224IMS-2#TRPBF LTDNW 10-Lead Plastic MSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

Operating Temperature Range

LTC4224C ................................................ 0°C to 70°C

LTC4224I.............................................. –40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature Range (Soldering, 10 sec)

MSOP Package ................................................. 300°C

LTC4224-1/LTC4224-2

422412fa

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to GND unless otherwise

speciﬁ ed.

The l denotes the speciﬁ cations which apply over the full operating

temperature range. TA = 25°C, VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VCC VCC Supply Range VCC = Max (VCC1, VCC2)l2.7 6 V

ICC VCC Supply Current l1.4 3 mA

VCC(UVL) VCC Undervoltage Lockout VCC Rising l2.2 2.4 2.65 V

VCCLO VCCLO Supply Range VCCLO = Min (VCC1, VCC2),

VCC ≥ 2.7V

l16V

ICCLO VCCLO Supply Current l40 100 A

VCCLO(UVL) VCCLO Undervoltage Lockout VCCLO Falling l0.76 0.8 0.84 V

External Gate Drive

ΔVGATE Gate Drive

(VGATEn – VCC)

IGATEn = 0µA, –1µA l4.5 5.5 7 V

IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATEn = 1V l–7 –10 –13 A

IGATE(DN) Gate Pull-Down Current VONn = 1V, VGATEn = 10V l0.5 1.5 3 mA

IGATE(FPD) Gate Fast Pull-Down Current Fast Turn-Off, VGATEn = 10V l50 125 200 mA

Current Limit

ΔVSENSE(CB) Circuit Breaker Trip Sense Voltage

(VCCn – SENSEn)

l22.5 25 27.5 mV

ISENSE SENSE Input Current VSENSE1 = 5V, VSENSE2 = 3.3V l40 100 A

Inputs and Outputs

VON(TH) ONn Threshold Voltage VONn Rising l0.76 0.8 0.84 V

ΔVON(HYST) ONn Hysteresis l15 30 50 mV

ION(IN) ONn Pull-Up Current VONn = 1V l–5 –10 –15 A

VOL Output Low Voltage (FAULT)I

FAULT = 3mA l0.2 0.4 V

Delay

tCB Circuit Breaker Delay l2.5 5 7.5 ms

tPHL(SENSE) Sense Voltage, (VCCn – SENSEn) High to

GATE Low

ΔVSENSE = 200mV, CGATE = 10nF l0.4 1 s

tPLH(GATE) ONn Low or Input Supply High to GATEn

High Prop Delay

l51015 ms

tPLH(UVL) VCCn Low to GATEn Low Prop Delay l816 s

tD(UV) UV Turn-On Delay VCC Out of UV l80 160 240 ms

tD(COOL) Auto-Retry Cooling Delay Note 3 l246 s

tBLANK Start-Up Circuit Breaker Blanking Delay l2.5 5 7.5 ms

Note 3: LTC4224-2 only.

Note 4: The greater of VCC1 and VCC2 is the internal supply voltage (VCC).

An internal clamp limits the GATE pin to a minimum 5V above VCC. Driving

this pin beyond the clamp may damage the device.

LTC4224-1/LTC4224-2

422412fa

TYPICAL PERFORMANCE CHARACTERISTICS

ICC vs VCC

Circuit Breaker Trip Voltage

vs VCC Circuit Breaker Delay vs VCC

Gate Drive vs Temperature

Gate Pull-Down Current

vs Gate Voltage

Gate Fast Pull-Down Current

vs Gate Voltage

Gate Drive vs IGATE

Active Current Limit Delay

vs Sense Voltage

FAULT Voltage

vs FAULT Sink Current

Speciﬁ cations are TA = 25°C, VCC1 = 5V, VCC2 = 3.3V, unless otherwise speciﬁ ed.

VCC (V)

2.5

ICC (mA)

1.5

1.4

1.2

1.3

1.1

1.0 4.53.5 5.5

422412 G01

6435

VCC (V)

VCB (mV)

26.0

25.5

24.5

24.0

25.0

23.5

23.0 3

422412 G02

6425

VCC (V)

2.5

tCB (ms)

5.5

5.4

5.2

5.3

5.1

5.0 3.5

422412 G03

653 4.54 5.5

TEMPERATURE (°C)

–50

ΔVGATE (V)

5.65

5.60

5.50

5.55

5.45

5.40

5.35 –25

422412 G05

1005025075

VGATE (V)

GATE NORMAL PULL-DOWN CURRENT (mA)

2.0

1.8

1.6

1.4

1.2

1.0

422412 G06

131110912

VGATE (V)

GATE FAST PULL-DOWN CURRENT (mA)

150

140

130

120

110

100

422412 G07

131110912

IGATE (µA)

ΔVGATE (V)

422412 G04

–12–8–6–4–2 –10

SENSE VOLTAGE (mV)

ACTIVE CURRENT LIMIT DELAY (µs)

1.5

1.2

0.9

0.6

0.3

0.0

422412 G08

1501251007550

IFAULT (mA)

VOL (mV)

500

400

300

100

200

422412 G09

54321

T = 25°C

T = –60°C

T = 90°C

LTC4224-1/LTC4224-2

422412fa

PIN FUNCTIONS

SENSE1, SENSE2 (Pins 1,10): Current Sense Input. Con-

nect this pin to an external sense resistor. The current limit

circuit controls GATEn to limit the voltage between VCCn

and SENSEn to 25mV. An Electronic Circuit Breaker (ECB)

is active during current limiting and trips after 5ms. To

disable current limit, connect this pin to VCCn.

VCC1, VCC2 (Pins 2, 9): Supply Voltage and Current Sense

Input. An undervoltage lockout circuit disables the part

until VCC, the higher of VCC1 and VCC2, exceeds 2.4V. The

lower supply is disabled until it exceeds 0.8V.

GATE1, GATE2 (Pins 3, 8): Gate Drive for External N-channel

MOSFET. A charge pump sources 10µA from GATE to turn

on the external MOSFET. An internal clamp limits the gate

voltage to 5.5V above the higher of VCC1 and VCC2. During

turn-off, a 1.5mA pulldown current discharges GATE to

ground. During short-circuits, a 125mA pulldown current

is activated to discharge GATE to ground.

FAULT (Pin 4): Fault Status Output. Open-drain output

that is normally pulled high to VCC1 or VCC2 by an exter-

nal resistor. It is pulled low when the ECB trips due to an

overcurrent condition at either supply. This pin may be

left open if unused.

ON1, ON2 (Pins 5, 6): On Control Input. A falling edge

turns on the external N-channel MOSFET and a rising edge

turns it off. A low to high transition on this pin resets an

ECB fault for the corresponding channel. Internally pulled

up to VCC by a 10µA current source.

GND (Pin 7): Device Ground.

Exposed Pad (DFN Package Only): Exposed Pad may be

left open or connected to device ground.

FUNCTIONAL DIAGRAM

CHARGE

PUMP

422412 FD

0.8V

2.4V

VCC

–

CHARGE

PUMP

–

GATE

PULLDOWN

LOGIC

CONTROL

GATE

PULLDOWN

0.8V

–

0.8V

VCC1

VCC2

10µA

GATE1

GATE2

ON1

FAULT

ON2

SENSE2

SENSE1

GND

ACL1

ACL2

10µA

5.5V

ON2

ON1

ECB1

ECB2

VCC1 UV

VCC2 UV

25mV

VCC

LTC4224-1/LTC4224-2

422412fa

OPERATION

The LTC4224 is designed to control power on a live back-

plane, allowing boards to be safely inserted and removed. It

controls two supplies (VCC1, VCC2) with operating voltages

between 1V and 6V via two external N-channel MOSFETs.

For applications where the total load current is 5A or less,

dual MOSFETs such as the FDS6911 can be used to save

board area. The two supplies can be turned on and off

independently using the active low ON1 and ON2 pins.

Internal 10µA current sources pull these pins to VCC.

Pulling the ON pin low turns on a charge pump which

sources 10µA at the GATE pin thereby ramping up the gate

of the external MOSFET. When the MOSFET turns on, the

inrush current is limited at a level set by an external sense

resistor. Inrush current can be further reduced, if desired,

by adding a capacitor from GATE to GND. To protect the

external MOSFET, the GATE pins are clamped to about

5.5V above the higher of the two supplies.

Each supply is continuously monitored for undervoltage

and overcurrent conditions. The undervoltage monitor

shuts off the external MOSFET when the corresponding

supply is too low.

Current is monitored by an active current limit ampliﬁ er

(ACL) and a timed electronic circuit breaker (ECB). Like

all timing delays in the LTC4224, the ECB delay of 5ms is

generated internally without requiring any external timing

capacitors. The ECB threshold is slightly below the ACL

threshold and shuts off the external MOSFET after 5ms.

FAULT is latched low to indicate an overcurrent fault.

The LTC4224-1 remains latched off until reset by either

turning off and then on the affected supply or its ON pin.

The LTC4224-2 automatically restarts after four seconds

to allow time for the MOSFET to cool down.

The typical LTC4224 application is in a high availability

system where two positive supply voltages are distributed

to power individual cards. The LTC4224 detects board

presence during insertion and removal, allowing power

to be delivered in a controlled manner without damaging

the connector. It reports overcurrent faults to the system

controller through its FAULT pin, which can light an LED

or can be monitored by a system controller.

Figure 1. Typical Application

LTC4224

VCC1 SENSE1 SENSE2 GATE1 GATE2

GND

ON1

ON2FAULT

VCC2

FDS6911

0.010Ω

0.015Ω

390

BULK SUPPLY

BYPASS CAPACITOR

BULK SUPPLY

BYPASS CAPACITOR

3.3V

RMOD_DET

GND

3.3V

CONNECTOR PLUG-IN CARD

MOD DETECT

APPLICATIONS INFORMATION

The basic LTC4224 application circuit is shown in Figure 1.

The following sections cover VCC selection, the normal

turn-on and turn-off sequence, various fault conditions

and recovery from fault situations. External component

selection is discussed in detail in the Design Example

section.

LTC4224-1/LTC4224-2

422412fa

APPLICATIONS INFORMATION

VCC Selection

The LTC4224 is powered from the higher of its two supply

pins, VCC1 and VCC2.This allows the part to control a sup-

ply voltage as low as 1V, while the other supply is 2.7V or

greater. If both supplies are tied together, the part derives

its power from both equally. The Functional Diagram shows

the VCC selection circuit in an ideal diode OR-ing arrange-

ment. It is designed to ensure swift and smooth internal

power switchover from one supply to the other.

Turn-On Sequence

Separate ON1 and ON2 pins allow the VCC1 and VCC2

supplies to be turned on in any order. The power supplies

delivered to a plug-in card are controlled by external N-

channel MOSFETs, Q1 and Q2. For X2/XENPAK deﬁ ned

optical transceiver modules, it has been speciﬁ ed that the

MOD DETECT pin pulls low inside the module through a

1k resistor (RMOD_DET), as shown in Figure 1. Several

conditions must be satisﬁ ed to turn on the MOSFETs.

First, VCC1 or VCC2 must exceed the 2.4V VCC undervoltage

lockout level for longer than an internal UV turn-on delay

of 160ms. Next, if VCCn is greater than 0.8V and ONn is

low (<0.8V), a debounce delay of 10ms is started. If VCCn

drops below 0.8V or ONn goes high before the end of the

10ms debounce delay, the debounce delay is restarted the

next time these pins are properly conditioned.

When the 10ms debounce delay expires, the external

MOSFET is turned on by charging up the GATE with a

Figure 2. Normal Power-Up Sequence

VOUT1

5V/DIV

VOUT2

5V/DIV

5ms/DIV 422412 F02

ON1/2

2V/DIV

GATE1

5V/DIV

GATE2

5V/DIV

10µA charge pump generated current source. When the

GATE voltage reaches the MOSFET threshold voltage, the

inrush current can build up quickly as the GATE continues

to rise. The ACL ampliﬁ er actively controls the gate volt-

age to maintain 25mV across the sense resistor. In this

condition, the inrush current is given by:

IINRUSH =25mV

RSENSE

As the inrush current charges up the load capacitor, the

output rises with a corresponding increase in gate voltage.

When the supply is no longer in current limit, an internal

charge pump pulls the gate to 5.5V above the higher of VCC1

or VCC2 to achieve a low resistance power path. Figure 2

shows a typical start-up sequence with CLOAD1 = CLOAD2

= 150µF, RLOAD1 = 4.7Ω and RLOAD2 = 2Ω.

The inrush current can be reduced to below the current

limit level by adding an external gate capacitor as shown

in Figure 3.

GATE capacitor CGATE provides gate slew rate control to limit

the inrush current. However, CGATE could cause parasitic

high frequency self oscillation in Q1. A 10Ω resistor, RG, as

shown in Figure 3 can be used to prevent the oscillation.

To be effective, RG needs to be laid out close to Q1.

The voltage at the GATE pin rises with a slope equal to IGATE/

CGATE. For a given supply inrush current IINRUSH and load

capacitor CLOAD, CGATE can be calculated according to:

CGATE =IGATE

IINRUSH

•C

LOAD

Figure 3. Inrush Current Control by Gate Capacitor

422412 F03

LTC4224

VCC1 SENSE1

GATE1

0.015Ω

IGATE

CGATE

10Ω

CLOAD

LTC4224-1/LTC4224-2

422412fa

APPLICATIONS INFORMATION

If the voltage across the sense resistor R1 becomes too

high, the inrush current is limited by the internal current

limit circuitry.

Turn-Off Sequence

The MOSFETs can be turned off by the conditions sum-

marized in Table 1.

Table 1. Turn-Off Conditions

CONDITION

RESULT

CHANNEL 1 CHANNEL 2 CLEARED BY

ON1 Goes High Turns Off No Effect ON1 Low

ON2 Goes High No Effect Turns Off ON2 Low

UVLO on VCC Turns Off Turns Off VCC > UVLO

UVLO on VCC1 Turns Off No Effect VCC1 > UVLO

UVLO on VCC2 No Effect Turns Off VCC2 > UVLO

CH1 Overcurrent Fault Turns Off No Effect ON1 High,

UVLO on VCC1

CH2 Overcurrent Fault No Effect Turns Off ON2 High,

UVLO on VCC2

When ON1 or ON2 is pulled high, the corresponding GATE

pin is pulled to ground by 1.5mA. With the MOSFET off,

the load current discharges the load capacitor. Figure 4

shows VCC1 supply turning off by pulling ON1 high with

RLOAD1 = 4.7Ω discharging CLOAD1 = 150µF.

Overcurrent Fault

The LTC4224 features an adjustable current limit with circuit

breaker function that protects external MOSFETs against

short circuits or excessive load current. The voltage across

the external sense resistor is monitored by the active cur-

rent limit (ACL) ampliﬁ er and the electronic circuit breaker

(ECB) comparator. An overcurrent condition results in the

current being limited by the ACL ampliﬁ er. During current

limiting, the ECB is activated and initiates a chain of logic

and timing events to handle the fault.

Figure 5 illustrates the LTC4224’s response to an overcurrent

condition on one supply output. Start-up and overcurrent

control for the two supplies are independent. Before time

point t1, the ON pin is high and the part is in reset. When

the ON pin goes low, a 10ms debounce delay is started.

After 10ms (time point t2), the external MOSFET is turned

on by charging GATE with 10µA. The load capacitor starts

to charge up and the output voltage increases. At the same

Figure 4. Normal Power-Down Sequence

Figure 5. Fault Handling Sequence

0.2ms/DIV

ON1

2V/DIV

VOUT1

5V/DIV

GATE1

5V/DIV

422412 F04

422412 F05

5ms ECB Arm

RESET

t1t6

IDLE

OVERCURRENT 5ms

ECB BLANKING DELAY

5ms START-UP

BLANKING DELAY

10ms DEBOUNCE DELAY

FAULT

VOUT

IOUT

ILIMIT ILIMIT

LTC4224-1/LTC4224-2

422412fa

APPLICATIONS INFORMATION

time, a 5ms start-up blanking delay begins during which

the circuit breaker is not allowed to latchoff the MOSFET.

If the ECB is tripped at the end of 5ms (time point t3), the

MOSFET is latched off by pulling GATE down with 1.5mA

and FAULT is latched low. The waveform in Figure 6 shows

an unsuccessful start-up due to a short circuit at the output.

To ensure start-up, the load capacitor must be charged

up sufﬁ ciently to exit current limit before the end of the

5ms blanking delay. For large load capacitors, it may be

necessary to connect an external capacitor from GATE to

GND as described in the Turn-On Sequence section.

After start-up, any transient overcurrent faults lasting

less than 100µs are ignored. Any overcurrent condition

lasting more than 100µs will initiate the 5ms ECB blank-

ing delay (time point t4). After the ECB blanking delay,

the ECB is armed for the following 5ms (time point t5 to

t6). Any 100µs overcurrent pulse during this time latches

off the MOSFET. In summary, for 5ms to 10ms after a

100µs or greater overcurrent fault is detected, a second

100µs fault condition causes the MOSFET to latchoff. If

no overcurrent condition is detected during this time, the

part re-enters the IDLE state and another blanking delay

following an overcurrent condition is again required before

the MOSFET latches off. Figure 7 shows how the output

latches off following an overcurrent fault.

During a severe short-circuit (see Figure 8), the output load

current can brieﬂ y surge to tens of amperes. The LTC4224

rapidly brings the current under control by discharging

the MOSFET’s gate with 125mA towards ground. After a

short delay, the ACL ampliﬁ er regulates the gate voltage

until the ECB trips at the end of 5ms.

Undervoltage Fault

An undervoltage fault occurs if either VCC1 or VCC2 falls

below 0.8V for longer than 8s. This turns off the affected

supply’s switch by discharging GATE with 1.5mA and

clears its fault latch. An undervoltage fault on one supply

does not affect the operation of the other supply. If VCC,

the higher of VCC1 and VCC2, falls below 2.4V for more

than 12s, all supply switches are turned off and all fault

latches are cleared.

Figure 6. Start-Up with Short at Output

5ms/DIV

ON1

2V/DIV

FAULT

5V/DIV

IOUT1

1A/DIV

GATE1

5V/DIV

422412 F06

Figure 8. Severe Short-Circuit on Output

0.5µs/DIV

IOUT2

8A/DIV

VOUT2

5V/DIV

GATE2

5V/DIV

422412 F08

Figure 7. Overcurrent Fault on Output

2ms/DIV

IOUT1

1A/DIV

VOUT1

5V/DIV

GATE1

5V/DIV

422412 F07

LTC4224-1/LTC4224-2

422412fa

APPLICATIONS INFORMATION

If there is signiﬁ cant supply lead inductance, a severe

output short may collapse the input to ground before the

LTC4224 can bring the current under control. In this case,

the undervoltage lockout activates after an 8µs ﬁ lter delay,

and the GATE is pulled down by 1.5mA.

Resetting Faults

Following an overcurrent fault, the LTC4224-1 latches

off while the LTC4224-2 automatically restarts after a

four second cool down period. An overcurrent fault on

either supply causes the ECB for that supply to turn off

the MOSFET and pull the FAULT pin low. Faults are reset

by pulling the ON pin high for at least 20µs, after which

the FAULT pin releases and the turn-on sequence begins.

Taking the lower supply below VCCLO(UVL) clears only that

supply’s fault and the turn-on sequence commences im-

mediately. Pulling the higher supply below VCC(UVL) clears

both supplies’ faults and the turn-on sequence begins after

a 160ms UV turn-on delay. When both supplies are above

2.5V, either supply going low only resets its own fault.

For the auto-retry version (LTC4224-2), if the fault is not

cleared within four seconds, the latched fault will be cleared

automatically. FAULT will go high and the turn-on sequence

will begin. A persistent fault results in an auto-retry duty

cycle of about 0.1%. Figure 9 shows an auto-retry sequence

as a result of an overcurrent fault.

Gate Pin Voltage

The gate drive is compatible with logic level MOSFETs, but

caution is required if one supply is low. The guaranteed

range of gate drive is 4.5V to 7V, with a typical value of

5.5V. Each GATE pin is clamped with respect to VCC, the

higher of the two input supplies. When VCC is at 5V, both

GATE pins can be as high as 12V above ground. If the

lower supply is at 0V, the gate-to-source voltage of its

MOSFET can be 12V. In such applications, MOSFETs with

gate-to-source breakdown ratings of 12V or greater are

recommended.

Active Current Loop Compensation

The active current loop is compensated by the parasitic

capacitance of the external MOSFET. No further compensa-

tion components are normally required. In the case where a

MOSFET with less than 600pF of gate capacitance is chosen,

a 600pF compensation capacitor connected between the

GATE pin and ground may be required.

Supply Transient Protection

In applications where the supply inputs are fed directly

from the regulated output of the backplane supply, bulk

bypassing assures a spike-free operating environment.

In other applications where bulk bypassing is located far

from the LTC4224, spikes generated during output short-

circuit events could exceed the absolute maximum ratings

for VCC. To minimize such spikes, use wider traces or

heavier trace plating to reduce the power trace inductance.

Figure 10. Input Supply Transient Protection

Network for Applications without Input Capacitance

422412 F10

LTC4224

VCC2

GND

SENSE2 GATE2

0.010Ω

VCC2 VOUT

CLOAD2

FDS6911

RSNUB

10Ω

CSNUB

0.1µF

SMAJ5.0A

Figure 9. Auto-Retry After Overcurrent Fault

1s/DIV

IOUT

1A/DIV

GATE

2V/DIV

FAULT

5V/DIV

422412 F09

LTC4224-1/LTC4224-2

422412fa

APPLICATIONS INFORMATION

Figure 11. Recommended Layout for Input

Supply Transient Protection Network

422412 F11

RSNUB

CSNUB

LTC4224

VCC2

GATE2

GND

SENSE2

VCC2

SNUBBER

NETWORK

VIAS TO

GND PLANE

PCB layout for the sense resistors and the power MOSFETs

should include good thermal management techniques for

optimal device power dissipation. A recommended PCB

layout for the sense resistors and the power MOSFET

around the LTC4224 is illustrated in Figure 12. Note that

it is important to keep the trace from the LTC4224’s GATE

pin to the FDS6911’s gate short.

In Hot Swap applications where load currents can be 10A,

wide PCB traces are recommended to minimize resistance

and temperature rise. The suggested trace width for 1oz

copper foil is 0.03" for each ampere of DC current to keep

PCB trace resistance, voltage drop and temperature rise to

a minimum. Note that the sheet resistance of 1oz copper

foil is approximately 0.5m/square and voltage drops

due to trace resistances add up quickly in high current

applications.

In most applications, it is necessary to use plated-through

vias to make circuit connections from component layers to

power and ground layers internal to the PCB. For 1oz cop-

per foil plating, a general rule is 1A of DC current per via.

Consult your PCB fabrication facility for design rules

pertaining to other plating thicknesses.

Design Example

As a design example, consider the following speciﬁ cations:

VCC1 = 5V, VCC2 = 3.3V, ILOAD1(MAX) = 1A, ILOAD2(MAX) = 2A,

CLOAD1 = CLOAD2 = 150F (see Figure 1).

First, select the sense resistor for each supply. Calculate

the R1 and R2 values based on the maximum load cur-

rent and the minimum circuit breaker threshold limit,

ΔVSENSE(CB)(MIN).

If a 1% tolerance is assumed for the sense resistors, then

the following values of resistance should sufﬁ ce:

Table 2. Sense Resistor Values

SUPPLY VOLTAGE RSENSE (1%) ITRIP(MIN) ITRIP(MAX)

5V 15m 1.49A 1.85A

3.3V 10m 2.23A 2.78A

For proper operation, ITRIP(MIN) must exceed the maxi-

mum load current with margin, so RSENSE1 = 15mΩ and

RSENSE2 = 10mΩ should sufﬁ ce for the VCC1 and VCC2

supplies respectively.

Figure 12. Recommended Layout for

Power MOSFET and Sense Resistors

422412 F12

TOP SIDE

FDS6911

BOTTOM SIDE

LTC4224

5V3.3V

R2 R1

Also, bypass locally with a 10F electrolytic and 100nF

ceramic, or alternatively clamp the input with a transient

voltage suppressor (Z1) as shown in Figure 10. A 10,

100nF snubber damps the response and eliminates ring-

ing. A recommended layout of the transient protection

devices Z1, RSNUB and CSNUB around the LTC4224 is

shown in Figure 11.

PCB Layout Considerations

For proper operation of the LTC4224’s electronic circuit

breaker, Kelvin connections to the sense resistors are

strongly recommended. The PCB layout should be balanced

and symmetrical to minimize wiring errors. In addition, the

LTC4224-1/LTC4224-2

422412fa

APPLICATIONS INFORMATION

Next, assume that there is no load current at start-up,

and calculate the inrush current required to charge the

load capacitor. As there is no gate capacitor, the supplies

start-up in current limit. Compute the time, tSU, it takes

to fully charge the load capacitor:

tSU =VCC •C

LOAD

ITRIP

Table 3 lists the worst-case tSU values assuming 30%

tolerance for load capacitances.

Table 3. Worst-Case tSU

VOLTAGE SUPPLY tSU(MIN) tSU(MAX)

5V 0.53ms 0.65ms

3.3V 0.23ms 0.29ms

The start-up ECB blanking delay is guaranteed to be at least

2.5ms, which is longer than the tSU tabulated in Table 3.

Hence, both supplies can start up successfully.

Next, verify that the thermal ratings of the selected external

MOSFETs are not exceeded during power-up or an output

short-circuit. Assuming the MOSFET dissipates power only

due to inrush current charging the load capacitor, the energy

dissipated in the MOSFET during power-up is the same

as that stored in the load capacitor after power-up. The

average power dissipated in the MOSFET is given by:

PAVG =CLOAD •V

OUT2

2•tSU

The worst-case PAVG is calculated to be 4.6W for both the 5V

supply and the 3.3V supply. In this example, the FDS6911

MOSFET offers a good solution. Since this MOSFET is a dual

N-channel in a single SO8 package, it must be able to tolerate

the combined power dissipation of both supplies during

the tSU start-up time. The increase in steady-state junction

temperature due to power dissipated in the MOSFET is

ΔT = PAVG•ZTH where ZTH is the thermal impedance.

Under this condition, the FDS6911 datasheet’s Transient

Thermal Impedance plot indicates that the junction tem-

perature will increase by 6.4°C using ZTHJC = 0.7°C/W

(single pulse). The FDS6911’s on-resistance is 17m at

VGS = 4.5V, 25°C.

The magnitude of the power pulse that results during a

severe overload is calculated to be 9.25W for the 5V sup-

ply and 9.2W for the 3.3V supply under the worst case

conditions. Assuming a worst-case circuit breaker timeout

period of 7.5ms, the junction temperature will increase by

25°C, with one supply short-circuited. If both supplies are

short-circuited, the junction temperature will increase by

50°C in the worst-case. During auto-retry (LTC4224-2), in

the event of persistent faults at both supplies, the ample

four second cooling delay limits the increase in junction

temperature to 50°C. The SOA curves of the FDS6911

indicate that the above conditions are safe.

LTC4224-1/LTC4224-2

422412fa

TYPICAL APPLICATION

Hot Swap Application for Two Add-In Cards

5V and 3.3V Card Resident Application

422412 TA02

LTC4224

VCC1 SENSE1 SENSE2 GATE1 GATE2

GNDGND

ON1PWREN

ON2

FAULTPWRFLT

VCC2

0.004Ω

0.004Ω 5V

3.3V

10k

RSNUB2

10Ω

CSNUB2

100nF

RSNUB1

10Ω

CSNUB1

100nF Q2

Si7336ADP

BACKPLANE

CONNECTOR

CARD

CONNECTOR

Z1: SMAJ6.5A

Z2: SMAJ5.0A

3.3V

422412 TA03

LTC4224

VCC1 SENSE1

SENSE2

GATE1

GATE2

GND

ON1

ON2

FAULT

VCC2

0.004Ω

10k

Si7336ADP

BACKPLANE

CONNECTOR1

CARD

CONNECTOR1

PRSNT1

PRSNT2

BACKPLANE

CONNECTOR2

CARD

CONNECTOR2

LTC4224-1/LTC4224-2

422412fa

DDB Package

10-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1722)

PACKAGE DESCRIPTION

2.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

0.64 ± 0.05

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

2.39 ±0.05

(2 SIDES)

3.00 ±0.10

(2 SIDES)

106

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0 – 0.05

(DDB10) DFN 0905 REV Ø

0.25 ± 0.05

2.39 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.64 ±0.05

(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

PIN 1

R = 0.20 OR

0.25 × 45°

CHAMFER

0.50 BSC

LTC4224-1/LTC4224-2

422412fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

MSOP (MS) 0307 REV E

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

12345

4.90 ± 0.152

(.193 ± .006)

0.497 ± 0.076

(.0196 ± .003)

REF

8910 76

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

0.50

(.0197)

BSC

0.1016 ± 0.0508

(.004 ± .002)

LTC4224-1/LTC4224-2

422412fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1108 REV A • PRINTED IN USA

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PART NUMBER DESCRIPTION COMMENTS

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X2/XENPAK Hot Swap Application

422412 TA04

LTC4224

VCC1 SENSE1 SENSE2 GATE1 GATE2

GND

ON1

ON2FAULT

VCC2

FDS6911

0.010Ω

390

APS

APS: 1V TO 1.8V

BULK SUPPLY

BYPASS CAPACITOR

BULK SUPPLY

BYPASS CAPACITOR

3.3V

GND

APS

3.3V

CONNECTOR PLUG-IN

CARD