DX-DI-PCI32-SL - Xilinx, Inc. - Datasheet.Directory

DS206 July 15, 2004 www.xilinx.com 1

Product Specification v3.0.129

registered trademarks are the property of their respective owners. All specificati ons a re subject to cha ng e wi thout notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application,

or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen-

tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple-

mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

Features

• Fully PC I 2.3 -co mpliant core, 32-bit, 66/33 MHz

interface

• Customiz able, programmable, single-chip solution

• Predefined implementation for predictable timing

• Incorporates X ilinx Smart-IP™ tech nology

• 3.3V operation at 0-66 MHz

• 5.0V operation at 0-33 MHz

• Fully verified design tested with Xilin x proprietary

test bench and hardware

• Available on the web:

- Configuration and downlo ad tool

- User constraints file ge ne rator tool

• CardBus compliant

• Supported initi ato r fu nctions:

- Configuration read, configuration write

- Memory read, memory write, MRM, MRL

- Interrupt acknowledge, special cycles

- I/O read, I/O write

• Supported target functions:

- Type 0 configuration space header

- Up to three base address registers (MEM or I/O

with adjustable block size from 16 bytes to 2 GB)

- Medium decode speed

- Parity generation, parity error detection

- Configuration read, configuration write

- Memory read, memory write, MRM, MRL

- Interrupt acknowledge

- I/O read, I/O write

- Target abort, target retry, target disconnect

LogiCORE PCI32 Interface

v3.0

DS206 July 15, 2004 00 Product Specification v3.0.129

LogiCORE Facts

PCI32 Resource Utilization (1)

Slice Four Input LUTs 553

Slice Flip-Flops 566

IOB Flip-Flops 97

IOBs 50

TBUFs 288 (10)

GCLKs 1 (2)

Provided with Core

Documentation

PCI Design Guide

PCI Implementation Guide

Design File Formats Verilog/VHDL Simulation Model

NGO Netlist

Constraints Files User Constraints File (UCF)

Guide File (NCD)

Example Design Verilog/VHDL Example Design

Design Tool Requirements

Xilinx Tools v6.2i SP3

Tested Entry and

Verification Tools (3)

Synplicity Synplify

Xilinx XST (4)

Model Technology ModelSim

Xilinx provides technical support for this LogiCORE

product when used as described in the Design Guide and

the Implementation Guide. Xilinx cannot guarantee timing,

functionality, or support of product if implemented in

devices not listed, or if customized beyond that allowed in

the product documentation.

LogiCORE PCI32 Interface v3.0

2www.xilinx.com DS206 July 15, 2004

Product Specification v3.0.129

Notes:

1. The resource utilization depends on configuration of the interface and the user design. Unused resources are

trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a

maximum configuration.

2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB and two GCLKs.

3. See the implementation guide or product release notes for current supported versions.

4. XST is command line option only. See Implementation Guide for details.

5. Universal card implementations require two bitstreams.

6. Virtex-E and Spartan-IIE recommended for CardBus.

7. Commercial devices; 0oC < Tj < 85oC.

8. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge.

9. XC2V1000 is supported over Military Temp. range

10. The Spart an-3 device does not conta in TBUFs. The Xilinx tools aut omatically tra nslate TBUF s to LUTs, and they

are included in the worst case LUT count listed.

11. Virtex-II Pro devices are supported over commercial and industrial temperature ranges.

Note:

1. Spartan-3 PCI Solution pending production speed files.

Table 1:

Core Implementation

Supported Device Power Supply

PCI32/66

Virtex™ XCV200FG256-6C 3.3V only

Virtex-E XCV200EFG256-6C 3.3V only

Virtex-E XCV400EFG676-6C 3.3V only

PCI32/33

Virtex XCV300BG432-5C 3.3V, 5.0V only

Virtex XCV1000FG680-5C 3.3V, 5.0V only

Virtex-E XCV100EBG352-6C 3.3V only

Virtex-E XCV300EBG432-6C 3.3V only

Virtex-E XCV1000EFG680-6C 3.3V only

Virtex-II™ XC2V1000FG456-4C/I/M 3.3V only

Virtex-II Pro™ XC2VP7FF672-5C/I 3.3V only

Spartan-II XC2S30PQ208-5C 3.3V, 5.0V only

Spartan-II XC2S50PQ208-5C 3.3V, 5.0V only

Spartan-II XC2S100PQ208-5C 3.3V, 5.0V only

Spartan-II XC2S150PQ208-5C 3.3V, 5.0V only

Spartan-II XC2S200PQ208-5C 3.3V, 5.0V only

Spartan-IIE 2S50EPQ208-6C 3.3V only

Spartan-IIE XC2S100EPQ208-6C 3.3V only

Spartan-IIE XC2S150EPQ208-6C 3.3V only

Spartan-IIE XC2S200EPQ208-6C 3.3V only

Spartan-IIE XC2S300EPQ208-6C 3.3V only

Spartan-3™ XC3S1000FG456-4C/I (1) 3.3V only

LogiCORE PCI32 Interface v3.0

DS206 July 15, 2004 www.xilinx.com 3

Product Specification v3.0.129

Applications

• Embedded applications in networking, industrial,

and telecommunication systems

• PCI add-in boards such as frame buffers, network adapters, and data acquisition boards

• Hot swap CompactPCI boards

• CardBus compliant

• Any applications that need a PCI interface

General Description

The Xilinx LogiCORE PCI Interface is a pre-implemented and fully tested module for Xilinx FPGAs.

The pinout for each device and the relative placement of the internal logic ar e predefined. Critical paths

are controlled by constraints and guide files to ensure predictable timing. This significantly reduces

engineering time required to implement the PCI portion of your design. Resources can instead be

focused on your unique user application logic in the FPGA and on the system-level design. As a result,

Xilinx PCI products minimize your product development tim e .

The core meets the setup, hold, and clock-to-timing requirements as specified in the PCI-X specifica-

tion. The interface is verified through extensive simulation.

Other features that enable efficient implementation of a PCI system include:

• Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write and

dual-port RA M capabilities. Used in PCI de signs to implement FIFOs.

• SelectRAM memory. Distributed on-chip ultra-fast RAM with syn chronous wr ite option and

dual-port RA M capabilities. Used in PCI de signs to implement FIFOs.

• Internal three-state bus capability for data m ultiplexing.

The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA

devices.

Smart-IP Technology

Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the

highest perfor mance, predictability, repeatability, and flexibility in P CI de signs. Th e Smart- IP techno l-

ogy is incorpo r ated in every LogiCORE PCI interface.

Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and

segmented routing, as well as floorplanning information, such as logic mapping and location con-

straints. This technology provides the best physical layout, predictability, and performance. In addi-

tion, these features allow for significantly reduced compile time s over competing architectures.

To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the

PCI interface is delivered with Smart-IP constraint files that are unique for a device an d package com-

bination. These constraint files guide the implementation tools so that the critical paths always are

within specification.

Xilinx provides Sm art-IP constraint files for m any device and packa ge combinations. Constraint files

for unsupported device and package combin ations may be generated using the web-based constraint

file generator.

LogiCORE PCI32 Interface v3.0

4www.xilinx.com DS206 July 15, 2004

Product Specification v3.0.129

Functional Description

The LogiCORE PCI In terface is pa rtitioned into five major blocks a nd a us er application as shown in

Figure 1.

PCI I/O Interface Block

The I/O interface blo ck handles the physi cal connection to the PCI bus incl uding all signalin g, input

and output synchronization, output three-state controls, and all request-grant handshaking for bus

mastering.

User Application

The LogiCORE PCI Interface provides a simple, general-purpose interface for a wide range of applica-

tions.

PCI Configuration Space

This block provides the first 64 bytes of Type 0, version 2.3 Configuration Space Header, as shown in

Table 2, to support software-driven “Plug-and-Play” initialization and configuration. This includes

information for Comm and, Status, a nd three Base Address Registe rs (BARs).

The capability for extending configuration space has been built into the user application interface. This

capability, including the abil ity to implement a capabilities pointer in configura tion space, allows the

user to implement functions such as power management and m essage signaled interrupts in the user

application.

Parity Generator/Checker

This block generates and checks even parity across the AD bus, the CBE# li nes, and the parity signals.

It also reports data parity errors via PERR# and address parity errors via SERR#.

Figure Top x-ref 1

Figure 1:

LogiCORE PCI Interface Block Diagram

Parity

Generator/

Checker

PCI Configuration Space

Initiator

State

Machine

Interrupt

Pin and

Line

Latency

Timer

Vendor ID,

Rev ID,

Other User

Data

Ta r g e t

State

Machine

PCI I/O INTERFACE

USER APPLICATION

ADIO[63:0]

AD[63:0]

PA R

GNT-

PERR-

SERR-

FRAME-

IRDY-

REQ-

TRDY-

DEVSEL-

STOP-

Base

Address

Base

Address

Command/

Status

Base

Address

REQ64-

ACK64-

PAR64

ADIO[63:0]

LogiCORE PCI32 Interface v3.0

DS206 July 15, 2004 www.xilinx.com 5

Product Specification v3.0.129

Initiator State Machine

This block controls the PCI interface initiator functions. The states implemented are a subset of those

defined in Appendix B of the PCI Local Bus Specification. The initiator control logic uses one-hot encod-

ing for maximum perf ormance.

Target State Machine

This block controls the PCI interface target functions. The states implemented are a subset of those

defined in Appendi x B o f the P CI Local Bus Specification. The targ et contr o l logic uses one-hot encoding

for maximum perfor mance.

Table 2:

PCI Configuration Space Header

31 16 15 0

Device ID Vendor ID 00h

Status Command 04h

Class Code Rev ID 08h

BIST

Header

Type

Latency

Timer

Cache Line

Size

0Ch

Base Address Register 0 (BAR0) 10h

Base Address Register 1 (BAR1) 14h

Base Address Register 2 (BAR2) 18h

Base Address Register 3 (BAR3)

1Ch

Base Address Register 4 (BAR4)

20h

Base Address Register 5 (BAR5)

24h

Cardbus CIS Pointer 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address

30h

Reserved CapPtr 34h

Reserved 38h

Max Lat Min Gnt Int Pin Int Line 3Ch

Reserved 40h-FFh

Notes:

1. Shaded areas are not implemented and return zero.

LogiCORE PCI32 Interface v3.0

6www.xilinx.com DS206 July 15, 2004

Product Specification v3.0.129

Interface Configuration

The LogiCORE PCI Interface can be easily configured to fit unique system requirements by using the

Xilinx Configuration and Download tool or by changing the HDL configuration file. The following cus-

tomization options, among many others, are supported by the interface and are described in the prod-

uct design guide.

• Base Add ress R eg iste r s (number, siz e , and type)

• Configuration Space Header ROM

Burst Transfer

The PCI bus derives its performance from its ability to support burst transfers. The performance of any

PCI application depends largely on the size of the burst transfer. Buffers to su pport P CI burs t transfer

can efficiently be implemented using on-chip RAM resources.

Supported PCI Commands

Table 3 illustrates the PCI bus commands supported by the PCI Interface.

Bandwidth

The PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and

receiving data. This interface supports a sustained bandwidth of up to 264 MBytes/sec. The design can

be configured to take advantage of the ability of the PCI Interface to do very long bursts.

The flexible user applica tion interface, combined with support for many different PCI features, gives

users a solu tio n that lend s itsel f t o use in many hig h-performan ce appl ication s. The user is no t locked

into one DMA engine; hence, an optimized design that fits a specific applicatio n can be designed.

Recommended Design Experience

The LogiCORE PCI Interface is pre implemented, allowing engineering focus on the unique user appli-

cation functions of a PCI design. Regardless, PCI is a high-performance design that is challenging to

implement in any technology. Therefore, previous experience with building high-performance, pipe-

lined FPGA designs using Xilinx implementation software, constraint files, and guide files is recom-

mended. The challenge to implement a complete PCI design including user application functions

varies depending on configuration and functionality of your application. Contact your local Xilinx r ep-

resentative for a closer review and estimation for your specific requirements.

Timing Specifications

The maximum speed at which your user design is capable of running can be affected by the size and

quality of the design. The following tables show the key timing parameters for the PCI Interface.

Table 4 lists the T iming Parameters in the 66 MHz Implementations and Table 5 li sts T i ming Para meters

in the 33 MHz Implementations.

LogiCORE PCI32 Interface v3.0

DS206 July 15, 2004 www.xilinx.com 7

Product Specification v3.0.129

Table 3:

PCI Bus Commands

CBE [3:0] Command PCI

Initiator

PCI

Target

0000 Interrupt Acknowledge Yes Yes

0001 Special Cycle Yes Ignore

0010 I/O Read Yes Yes

0011 I/O Write Yes Yes

0100 Reserved Ignore Ignore

0101 Reserved Ignore Ignore

0110 Memory Read Yes Yes

0111 Memory Write Yes Yes

1000 Reserved Ignore Ignore

1001 Reserved Ignore Ignore

1010 Configuration Read Yes Yes

1011 Configuration Write Yes Yes

1100 Memory Read Multiple Yes Yes

1101 Dual Address Cycle No Ignore

1110 Memory Read Line Yes Yes

1111 Memory Write Invalidate No Yes

Table 4:

Timing Parameters, 66 MHz Implementations

Symbol Parameter Min Max

Tcyc CLK Cycle Time 15130

Thigh CLK High Time 6 -

Tlow CLK Low Time 6 -

Tval

CLK to Signal Valid Delay

(bussed signals) 2262

Tval

CLK to Signal Valid Delay

(point to point signals) 2262

Ton Float to Active Delay 22-

Toff Active to Float Delay - 141

Tsu

Input Setup Time to CLK

(bussed signals) 32,3 -

Tsu

Input Setup Time to CLK

(point to point signals) 52,3 -

ThInput Hold Time from CLK 02,3 -

Trstoff Reset Active to Output Float - 40

Notes:

1. Controlled by timespec co nstraints, included in product.

2. Controlled by SelectIO configured for PCI66_3.

3. Controlled by guid e fi le, included in p rodu ct .

LogiCORE PCI32 Interface v3.0

8www.xilinx.com DS206 July 15, 2004

Product Specification v3.0.129

Ordering Information

This core may be downloaded from the Xilinx IP Center ; or a license may be downloaded from the Xil-

inx IP Center for use with the Xilinx CORE Generator™ system v6.2i and later. The Xilinx CORE Gen-

erator system is bundl ed wit h all Allia nce and Foundatio n Series Sof tware packages, at no a dditional

charge.

To order the Xilinx PCI core, please contact your local Xilinx sales representative.

Part Numbers

• DO-DI-PCI32-IP

- Access to the v3.0 PCI32 33 MHz Spartan and 66 MHz Virtex Families

• DX-DI-PCI32-SL

- Upgrade from PCI32 33 MHz Spartan only to v3.0 PCI32 33 MHz Spartan and 66 MHz Vi rtex

families

• DO-DI-PCI32-SP

- Access to the v3.0 PCI32 S p artan family project license

Table 5:

Timing Parameters, 33 MHz Implementations

Symbol Parameter Min Max

Tcyc CLK Cycle Time 301-

Thigh CLK High Time 11 -

Tlow CLK Low Time 11 -

Tval

CLK to Signal Valid Delay

(bussed signals) 22112

Tval

CLK to Signal Valid Delay

(point to point signals) 22112

Ton Float to Active Delay 22-

Toff Active to Float Delay - 281

Tsu

Input Setup Time to CLK

(bussed signals) 72-

Tsu

Input Setup Time to CLK

(point to point signals) 102-

ThInput Hold Time from CLK 02-

Trstoff Reset Active to Output Float - 40

Notes:

1. Controlled by timespec co nstraints, included in product.

2. Controlled b y Sel ect IO configured for PCI 33_3 or PCI33_5.

LogiCORE PCI32 Interface v3.0

DS206 July 15, 2004 www.xilinx.com 9

Product Specification v3.0.129

Revision History

The following table shows the revision history for this document.

Date Version Revision

07/30/02 1.2 Style updates

12/18/02 1.3 Updated to build v3.0.103; v5.Ii, 1st feature: 32-bit was 64/32-bit

3/7/03 1.4 Updated to build v3.0.105; v5.2i

4/14/03 1.5 Updated to build v3.0.106; in LogiCORE Facts table, updated PC32/33 product

listings to include Spartan-3 device support.

5/8/03 1.6 Updated Xilinx tools to 5.2i SP2; added Note 10.

9/17/03 1.7 Updated to build v3.0.113; in LogiCORE Facts table, Xilinx Tools v6.1i SP1 was v5.2i

SP2; date was May 8, 2003.

10/28/03 1.8 Updated to build v3.0.116, in Supported Devices table, added XC prefix to device

names.

1/30/04 1.9 Updated to build v3.0.122, updated copyright information to 2004.

4/9/04 1.10 Updated to build v3.0.126; updated Xilinx tools to 6.2i SP1; in supported devices

table, added notes 11 and 12; added suffix /I to all Virtex-II Pro devices.

4/26/04 1.11 Updated to build v3.0.128, updated Xilinx tools to 6.2i SP2, changed date to April 26,

2004.

7/15/04 1.12 Updated to build v3.0.129 and to support Xilinx tools v6.2i SP3. The data sheet is

updated to the new template.