0 Virtex-II ProTM Platform FPGAs: Introduction and Overview R DS083-1 (v1.0) January 31, 2002 0 Advance Product Specification 0 Summary of Virtex-II Pro Features * * High-performance Platform FPGA solution including - Up to sixteen Rocket I/OTM embedded multi-gigabit transceiver blocks (based on Mindspeed's SkyRailTM technology) - Up to four IBM(R) PowerPC (R) RISC processor blocks Based on VirtexTM-II Platform FPGA technology - Flexible logic resources - SRAM-based in-system configuration - Active InterconnectTM technology - SelectRAMTM memory hierarchy - Dedicated 18-bit x 18-bit multiplier blocks - High-performance clock management circuitry - SelectI/OTM-Ultra technology - Digitally Controlled Impedance (DCI) I/O The members and resources of the Virtex-II Pro family are shown in Table 1. Rocket I/O Features * * * * * Full-duplex serial transceiver (SERDES) capable of baud rates from 622 Mb/s to 3.125 Gb/s 80 Gb/s duplex data rate (16 channels) Monolithic clock synthesis and clock recovery (CDR) Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and Infiniband-compliant transceivers 8-, 16-, or 32-bit selectable internal FPGA interface * * * * * * * * * 8B /10B encoder and decoder 50 /75 on-chip selectable transmit and receive terminations Programmable comma detection Channel bonding support (two to sixteen channels) Rate matching via insertion/deletion characters Four levels of selectable pre-emphasis Five levels of output differential voltage Per-channel internal loopback modes 2.5V transceiver supply voltage PowerPC RISC Core Features * * * * * * * * * * * * Embedded 300+ MHz Harvard architecture core Low power consumption: 0.9 mW/MHz Five-stage data path pipeline Hardware multiply/divide unit Thirty-two 32-bit general purpose registers 16 KB two-way set-associative instruction cache 16 KB two-way set-associative data cache Memory Management Unit (MMU) - 64-entry unified Translation Look-aside Buffers (TLB) - Variable page sizes (1 KB to 16 MB) Dedicated on-chip memory (OCM) interface Supports IBM CoreConnectTM bus architecture Debug and trace support Timer facilities Table 1: Virtex-II Pro FPGA Family Members CLB (1 CLB = 4 slices = Max 128 bits) Device Rocket I/O Transceiver Blocks PowerPC Processor Array Blocks Row x Col Slices Block SelectRAM Maximum 18 X 18 Bit Distributed Multiplier RAM (Kb) Blocks 18 Kb Blocks Max Block RAM (Kb) DCMs Max I/O Pads XC2VP2 4 0 16 x 22 1,408 44 12 12 216 4 204 XC2VP4 4 1 40 x 22 3,008 94 28 28 504 4 348 XC2VP7 8 1 40 x 34 4,928 154 44 44 792 4 396 XC2VP20 8 2 56 x 46 9,280 290 88 88 1,584 8 564 XC2VP50 16 4 88 x 70 22,592 706 216 216 3,888 8 852 (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-1 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R General Description Virtex-II Pro Platform FPGA Technology * * * * * * * SelectRAM memory hierarchy - Up to 4 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources - Up to 706 Kb of distributed SelectRAM resources - High-performance interfaces to external memory Arithmetic functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible logic resources - Up to 45,184 internal registers/latches with Clock Enable - Up to 45,184 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state busing High-performance clock management circuitry - Up to eight Digital Clock Manager (DCM) modules * Precise clock de-skew * Flexible frequency synthesis * High-resolution phase shifting - 16 global clock multiplexer buffers in all parts Active Interconnect technology - Fourth-generation segmented routing structure - Fast, predictable routing delay, independent of fanout - Deep sub-micron noise immunity benefits SelectI/O-Ultra technology - Up to 852 user I/Os - Twenty two single-ended standards and five differential standards - Programmable LVTTL and LVCMOS sink/source current (2 mA to 24 mA) per I/O - Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI support(1) - Differential signaling * 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers * Bus LVDS I/O * HyperTransport (LDT) I/O with current driver buffers * Built-in DDR input and output registers - Proprietary high-performance SelectLink technology for communications between Xilinx devices * High-bandwidth data path * Double Data Rate (DDR) link * Web-based HDL generation methodology * * * * * * SRAM-based in-system configuration - Fast SelectMAPTM configuration - Triple Data Encryption Standard (DES) security option (bitstream encryption) - IEEE1532 support - Partial reconfiguration - Unlimited reprogrammability - Readback capability Supported by Xilinx FoundationTM and AllianceTM series development systems - Integrated VHDL and Verilog design flows - ChipScopeTM Integrated Logic Analyzer 0.13-m, nine-layer copper process with 90 nm high-speed transistors 1.5V (VCCINT) core power supply, dedicated 2.5V VCCAUX auxiliary and VCCO I/O power supplies IEEE 1149.1 compatible boundary-scan logic support Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in standard 1.00 mm pitch Each device 100% factory tested General Description The Virtex-II Pro family is a platform FPGA for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU cores in Virtex-II Pro Series FPGA architecture. It empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The leading-edge 0.13m CMOS nine-layer copper process and the Virtex-II Pro architecture are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the Virtex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gate arrays. 1. PCI supported in some banks only. 2 www.xilinx.com 1-800-255-7778 DS083-1 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Introduction and Overview Architecture channel can be operated at a maximum data transfer rate of 3.125 Gb/s. Virtex-II Pro Array Overview Each Rocket I/O core implements the following functionality: Virtex-II Pro devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-II Pro devices implement the following functionality: * * * * * * * Embedded high-speed serial transceivers enable data bit rate up to 3.125 Gb/s per channel. Embedded IBM PowerPC 405 RISC CPU cores provide performance of 300+ MHz. SelectI/O-Ultra blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by the programmable IOBs. Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources. Block SelectRAM memory modules provide large 18 Kb storage elements of True Dual-Port RAM. Embedded multiplier blocks are 18-bit x 18-bit dedicated multipliers. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, and coarse- and fine-grained clock phase shifting. A new generation of programmable routing resources called Active Interconnect Technology interconnects all of these elements. The general routing matrix (GRM) is an array of routing switches. Each programmable element is tied to a switch matrix, allowing multiple connections to the general routing matrix. The overall programmable interconnection is hierarchical and designed to support high-speed designs. * * * * * * * * * * * * * * * PowerPC 405 Processor Block The PPC405 RISC CPU can execute instructions at a sustained rate of one instruction per cycle. On-chip instruction and data cache reduce design complexity and improve system throughput. The PPC405 features include: * All programmable elements, including the routing resources, are controlled by values stored in static memory cells. These values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements. Virtex-II Pro Features This section briefly describes Virtex-II Pro features. Rocket I/O Multi-Gigabit Transceiver Cores The Rocket I/O Multi-Gigabit Transceiver core, based on Mindspeed's SkyRail technology, is a flexible parallel-to-serial and serial-to-parallel transceiver embedded core used for high-bandwidth interconnection between buses, backplanes, or other subsystems. Multiple user instantiations in an FPGA are possible, providing up to 80 Gb/s of full-duplex raw data transfer. Each DS083-1 (v1.0) January 31, 2002 Advance Product Specification Serializer and deserializer (SERDES) Monolithic clock synthesis and clock recovery (CDR) Fibre Channel, Gigabit Ethernet, XAUI, and Infiniband compliant transceivers 8-, 16-, or 32-bit selectable FPGA interface 8B/10B encoder and decoder with bypassing option on each channel Channel bonding support (two to sixteen channels) - Elastic buffers for inter-chip deskewing and channel-to-channel alignment Receiver clock recovery tolerance of up to 75 non-transitioning bits 50 /75 on-chip selectable TX and RX terminations Programmable comma detection Rate matching via insertion/deletion characters Automatic lock-to-reference function Optional TX and RX data inversion Four levels of pre-emphasis support Per-channel serial and parallel transmitter-to-receiver internal loopback modes Cyclic Redundancy Check (CRC) support * PowerPC RISC CPU - Implements the PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications - Thirty-two 32-bit general purpose registers (GPRs) - Static branch prediction - Five-stage pipeline with single-cycle execution of most instructions, including loads/stores - Unaligned and aligned load/store support to cache, main memory, and on-chip memory - Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide) - Enhanced string and multiple-word handling - Big/little endian operation support Storage Control - Separate instruction and data cache units, both two-way set-associative and non-blocking - Eight words (32 bytes) per cache line - 16 KB array Instruction Cache Unit (ICU), 16 KB array Data Cache Unit (DCU) www.xilinx.com 1-800-255-7778 3 R Architecture * * * * * * Operand forwarding during instruction cache line fill Copy-back or write-through DCU strategy Doubleword instruction fetch from cache improves branch latency Virtual mode memory management unit (MMU) - Translation of the 4 GB logical address space into physical addresses - Software control of page replacement strategy - Supports multiple simultaneous page sizes ranging from 1 KB to 16 MB OCM controllers provide dedicated interfaces between Block SelectRAM memory and processor core instruction and data paths for high-speed access PowerPC timer facilities - 64-bit time base - Programmable interval timer (PIT) - Fixed interval timer (FIT) - Watchdog timer (WDT) Debug Support - Internal debug mode - External debug mode - Debug Wait mode - Real Time Trace debug mode - Enhanced debug support with logical operators - Instruction trace and trace-back support - Forward or backward trace Two hardware interrupt levels support Advanced power management support Input/Output Blocks (IOBs) IOBs are programmable and can be categorized as follows: * * * Input block with an optional single data rate (SDR) or double data rate (DDR) register Output block with an optional SDR or DDR register and an optional 3-state buffer to be driven directly or through an SDR or DDR register Bidirectional block (any combination of input and output configurations) These registers are either edge-triggered D-type flip-flops or level-sensitive latches. IOBs support the following single-ended I/O standards: * * * * * * LVDS and Extended LVDS (2.5V only) BLVDS (Bus LVDS) ULVDS LDT Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the routing resources. Configurable Logic Blocks (CLBs) CLB resources include four slices and two 3-state buffers. Each slice is equivalent and contains: * * * * * * * Two function generators (F & G) Two storage elements Arithmetic logic gates Large multiplexers Wide function capability Fast carry look-ahead chain Horizontal cascade chain (OR gate) The function generators F & G are configurable as 4-input look-up tables (LUTs), as 16-bit shift registers, or as 16-bit distributed SelectRAM memory. In addition, the two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches. Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources. Block SelectRAM Memory The block SelectRAM memory resources are 18 Kb of True Dual-Port RAM, programmable from 16K x 1 bit to 512 x 36 bit, in various depth and width configurations. Each port is totally synchronous and independent, offering three "read-during-write" modes. Block SelectRAM memory is cascadable to implement large embedded storage blocks. Supported memory configurations for dual-port and single-port modes are shown in Table 2. Table 2: Dual-Port and Single-Port Configurations 16K x 1 bit 4K x 4 bits 1K x 18 bits 8K x 2 bits 2K x 9 bits 512 x 36 bits 18 X 18 Bit Multipliers A multiplier block is associated with each SelectRAM memory block. The multiplier block is a dedicated 18 x 18-bit 2s complement signed multiplier, and is optimized for operations based on the block SelectRAM content on one port. The 18 x 18 multiplier can be used independently of the block SelectRAM resource. Read/multiply/accumulate operations and DSP filter structures are extremely efficient. LVTTL LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) PCI (33 and 66 MHz) GTL and GTLP HSTL 1.5V and 1.8V (Class I, II, III, and IV) SSTL (3.3V and 2.5V, Class I and II) The DCI I/O feature automatically provides on-chip termination for each single-ended I/O standard. The IOB elements also support the following differential signaling I/O standards: 4 * * * * Both the SelectRAM memory and the multiplier resource are connected to four switch matrices to access the general routing resources. www.xilinx.com 1-800-255-7778 DS083-1 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Introduction and Overview Global Clocking The DCM and global clock multiplexer buffers provide a complete solution for designing high-speed clock schemes. Up to eight DCM blocks are available. To generate deskewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also provides 90-, 180-, and 270-degree phase-shifted versions of its output clocks. Fine-grained phase shifting offers high-resolution phase adjustments in increments of 1/256 of the clock period. Very flexible frequency synthesis provides a clock output frequency equal to a fractional or integer multiple of the input clock frequency. For exact timing parameters, see Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics (Module 3). Virtex-II Pro devices have 16 global clock MUX buffers, with up to eight clock nets per quadrant. Each clock MUX buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. Each DCM can send up to four of its clock outputs to global clock buffers on the same edge. Any global clock pin can drive any DCM on the same edge. Routing Resources The IOB, CLB, block SelectRAM, multiplier, and DCM elements all use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the performance of high-speed designs. There are a total of 16 global clock lines, with eight available per quadrant. In addition, 24 vertical and horizontal long lines per row or column, as well as massive secondary and local routing resources, provide fast interconnect. Virtex-II Pro buffered interconnects are relatively unaffected by net fanout, and the interconnect layout is designed to minimize crosstalk. Horizontal and vertical routing resources for each row or column include: * * * * 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions) uring Virtex-II Pro devices, complying with IEEE standards 1149.1 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II Pro device will continue to function while executing non-test boundary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Virtex-II Pro Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE, and USERCODE non-test instructions. The EXTEST, INTEST, and HIGHZ test instructions are also supported. Configuration Virtex-II Pro devices are configured by loading the bitstream into internal configuration memory using one of the following modes: * * * * * Slave-serial mode Master-serial mode Slave SelectMAP mode Master SelectMAP mode Boundary-Scan mode (IEEE 1532) A Data Encryption Standard (DES) decryptor is available on-chip to secure the bitstreams. One or two triple-DES key sets can be used to optionally encrypt the configuration data. The Xilinx System Advanced Configuration Enviornment (System ACE) family offers high-capacity and flexible solution for FPGA configuration as well as program/data storage for the processor. See DS080, System ACE CompactFlash Solution for more information. Readback and Integrated Logic Analyzer Configuration data stored in Virtex-II Pro configuration memory can be read back for verification. Along with the configuration data, the contents of all flip-flops/latches, distributed SelectRAM, and block SelectRAM memory resources can be read back. This capability is useful for real-time debugging. The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores and Integrated Bus Analyzer (IBA) cores, along with the ChipScope Pro Analyzer software, provide a complete solution for accessing and verifying user designs within Virtex-II Pro devices. Boundary Scan Boundary-scan instructions and associated data registers support a standard methodology for accessing and config- DS083-1 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R IP Core and Reference Support IP Core and Reference Support Intellectual Property is part of the Platform FPGA solution. In addition to the existing FPGA fabric cores, the list below shows some of the currently available hardware and software intellectual properties specially developed for Virtex-II Pro by Xilinx. Each IP core is modular, portable, Real-Time Operating System (RTOS) independent, and CoreConnect compatible for ease of design migration. Refer to www.xilinx.com for the latest and most complete list of cores. Hardware Cores * Bus Infrastructure cores (arbiters, bridges, and more) * * * Memory cores (Flash, SRAM, and more) Peripheral cores (UART, IIC, and more) Networking cores (ATM, Ethernet, and more) Software Cores * * * * * * Boot code Test code Device drivers Protocol stacks RTOS integration Customized board support package Virtex-II Pro Device/Package Combinations and Maximum I/Os Offerings include ball grid array (BGA) packages with 1.0 mm pitch. In addition to traditional wire-bond interconnects, flip-chip interconnect is used in some of the BGA offerings. The use of flip-chip interconnect offers more I/Os than are possible in wire-bond versions of the similar packages. Flip-chip construction offers the combination of high pin count and excellent power dissipation. The Virtex-II Pro device/package combination table (Table 3) details the maximum number of I/Os for each device and package using wire-bond or flip-chip technology. * * * FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). BF denotes flip-chip fine-ptich BGA (1.27 mm pitch). Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os (Advance Information) User Available I/Os 6 Package Pitch (mm) Size (mm) XC2VP2 XC2VP4 XC2VP7 FG256 1.00 17 x 17 140 140 FG456 1.00 23 x 23 156 248 248 FF672 1.00 27 x 27 204 348 396 FF896 1.00 31 x 31 FF1152 1.00 35 x 35 FF1517 1.00 40 x 40 BF957 1.27 40 x 40 396 XC2VP20 XC2VP50 556 564 692 852 564 www.xilinx.com 1-800-255-7778 584 DS083-1 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Introduction and Overview Virtex-II Pro Ordering Information Virtex-II Pro ordering information is shown in Figure 1. Example: XC2VP7-7FG456C Device Type Speed Grade (-6, -7, -8) Temperature Range: C = Commercial (Tj = 0C to +85C) I = Industrial (Tj = -40C to +100C) Number of Pins Package Type DS083_02_102301 Figure 1: Virtex-II Pro Ordering Information NOTE: Maximum serial transceiver baud rates for flipchip and wirebond packages are 3.125 Gb/s and 2.5 Gb/s respectively. Revision History This section records the change history for this module of the data sheet. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II Pro Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II ProTM Platform FPGAs: Functional Description (Module 2) * Virtex-II ProTM Platform FPGAs: Pinout Information (Module 4) DS083-1 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 7 R Virtex-II Pro Data Sheet Modules 8 www.xilinx.com 1-800-255-7778 DS083-1 (v1.0) January 31, 2002 Advance Product Specification 0 Virtex-II ProTM Platform FPGAs: Functional Description R DS083-2 (v1.0) January 31, 2002 0 0 Virtex-II Pro Array Functional Description CLB For detailed Rocket I/O digital and analog design considerations, refer to the Rocket I/O User Guide. All of the documents above, as well as a complete listing and description of Xilinx-developed Intellectual Property cores for Virtex-II Pro, are available on the Xilinx website at www.xilinx.com/virtex2pro. Virtex-II Pro Compared to Virtex-II Devices Virtex-II Pro is built on the Virtex-II FPGA architecture. Most FPGA features are identical to Virtex-II. The differences are described below: CLB * CLB Configurable Logic SelectI/OTM-Ultra * DS083-1_01_010802 Figure 1: Virtex-II Pro Generic Architecture Overview * This module describes the following Virtex-II Pro functional components, as shown in Figure 1: * * FPGA fabric based on Virtex-II architecture. For a detailed description of the PPC405 core programming models and internal core operations, refer to the PowerPC 405 User Manual and the Processor Block Manual. Rocket I/OTM Multi-Gigabit Transceiver CLB Multipliers and Block SelectRAM * Processor Block DCM Advance Product Specification Embedded Rocket I/OTM Multi-Gigabit Transceivers (MGTs) Processor Blocks containing embedded IBM(R) PowerPC (R) 405 RISC CPU (PPC405) cores and integration circuitry. Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) * Virtex-II Pro is the first FPGA family incorporating embedded PPC405 cores and Rocket I/O MGTs. VCCAUX, the auxiliary supply voltage, is 2.5V instead of 3.3V as for Virtex-II devices. Advanced processing at 0.13 m has resulted in a smaller die, faster speed, and lower power consumption. The Virtex-II Pro family is neither bitstream-compatible nor pin-compatible with the Virtex-II family. However, Virtex-II designs can be compiled into Virtex-II Pro devices. All banks support 2.5V (and below) I/O standards. 3.3V I/O standards including PCI are supported in certain banks only. (See Table 4 in Module 4.) LVPECL, LVDS_33, LVDSEXT_33, LVDCI_DV2_33, and AGP-2X are not supported. 622 Mb/s to 3.125 Gb/s per channel. This includes specific baud rates used by various standards as listed in Table 1. . This section summarizes the features of the Rocket I/O multi-gigabit transceiver. For an in-depth discussion of the Rocket I/O MGT, refer to the Rocket I/O User Guide. Table 1: Standards Supported by the Rocket I/O MGT Internal Clock Rate (REFCLK) (MHz) 1.06 53 2.12 106 Mode Fibre Channel 1 Gbit Ethernet 1 1.25 62.5 XAUI 4 3.125 156.25 Overview The embedded Rocket I/O multi-gigabit transceiver core is based on Mindspeed's SkyRailTM technology. Up to sixteen transceiver cores are available. The transceiver core is designed to operate at any baud rate in the range of I/O Baud Rate (Gb/s) Channels (Lanes) (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 9 Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) Table 1: Standards Supported by the Rocket I/O MGT Channels (Lanes) I/O Baud Rate (Gb/s) Internal Clock Rate (REFCLK) (MHz) 1, 4, 12 2.5 125 Aurora (Xilinx) 1, 2, 3, 4, ... 0.840 - 3.125 42.00-156.25 Custom mode 1, 2, 3, 4, ... up to 3.125 up to 156.25 Mode Infiniband The serial bit rate need not be configured in the transceiver, as the operating frequency is implied by the received data and reference clock applied. 10 R The Rocket I/O transceiver core consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the serializer and deserializer. The PCS contains the bypassable 8B/10B encoder/ decoder, elastic buffers, and Cyclic Redundancy Check (CRC) units. The encoder and decoder handle the 8B/10B coding scheme. The elastic buffers support the clock correction (rate matching) and channel bonding features. The CRC units perform CRC generation and checking. Figure 2 shows the Rocket I/O high-level block diagram and FPGA interface signals. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description PACKAGE PINS AVCCAUXRX VTRX MULTI-GIGABIT TRANSCEIVER CORE FPGA FABRIC Power Down 2.5V RX POWERDOWN RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN Termination Supply RX CRC Check RXCHECKINGCRC RXCRCERR RXDATA[15:0] RXDATA[31:16] RXP Comma Detect Realign RXN Clock Manager 8B/10B Decoder RXNOTINTABLE[3:0] RXDISPERR[3:0] RXCHARISK[3:0] RXCHARISCOMMA[3:0] RXRUNDISP[3:0] RXBUFSTATUS[1:0] ENCHANSYNC CHBONDDONE CHBONDI[3:0] CHBONDO[3:0] Channel Bonding and Clock Correction Parallel Loopback Path Serial Loopback Path Deserializer RX Elastic Buffer RXLOSSOFSYNC RXCLKCORCNT TXBUFERR TXFORCECRCERR TXDATA[15:0] TXDATA[31:16] TX FIFO TXP TXN Serializer 8B/10B Encoder Output Polarity CRC TXBYPASS8B10B[3:0] TXCHARISK[3:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXKERR[3:0] TXRUNDISP[3:0] TXPOLARITY TXINHIBIT GNDA AVCCAUXTX VTTX LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 TX/RX GND 2.5V TX Termination Supply TX DS083-2_04_010202 Figure 2: Rocket I/O Block Diagram DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 11 R Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) Clock Synthesizer Synchronous serial data reception is facilitated by a clock/data recovery circuit. This circuit uses a fully monolithic Phase Lock Loop (PLL), which does not require any external components. The clock/data recovery circuit extracts both phase and frequency from the incoming data stream. The recovered clock is presented on output RXRECCLK at 1/20 of the serial received data rate. The gigabit transceiver multiplies the reference frequency provided on the reference clock input (REFCLK) by 20. The multiplication of the clock is achieved by using a fully monolithic PLL that does not require any external components. No fixed phase relationship is assumed between REFCLK, RXRECCLK, and/or any other clock that is not tied to either of these clocks. When the 4-byte or 1-byte receiver data path is used, RXUSRCLK and RXUSRCLK2 have different frequencies, and each edge of the slower clock is aligned to a falling edge of the faster clock. The same relationships apply to TXUSRCLK and TXUSRCLK2. as standard data. If the K-character input is High, and a user applies other than one of the twelve possible combinations, TXKERR indicates the error. Disparity Control The 8B/10B encoder is initialized with a negative running disparity. Unique control allows forcing the current running disparity state. TXRUNDISP signals its current running disparity. This may be useful in those cases where there is a need to manipulate the initial running disparity value. Bits TXCHARDISPMODE and TXCHARDISPVAL control the generation of running disparity before each byte. For example, the transceiver can generate the sequence K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+ by specifying inverted running disparity for the second and fourth bytes. Clock and Data Recovery Transmit FIFO The clock/data recovery (CDR) circuits will lock to the reference clock automatically if the data is not present. For proper operation, the frequency of the reference clock must be within 100 ppm of the nominal frequency. Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-locked to the reference clock (REFCLK). Phase variations up to one clock cycle are allowable. The FIFO has a depth of four. Overflow or underflow conditions are detected and signaled at the interface. Bypassing of this FIFO is programmable. It is critical to keep power supply noise low in order to minimize common and differential noise modes into the clock/data recovery circuitry. Refer to the Rocket I/O User Guide for more details. Transmitter FPGA Transmit Interface The FPGA can send either one, two, or four characters of data to the transmitter. Each character can be either 8 bits or 10 bits wide. If 8-bit data is applied, the additional inputs become control signals for the 8B/10B encoder. When the 8B/10B encoder is bypassed, the 10-bit character order is generated as follows: TXCHARDISPMODE[0] (first bit transmitted) TXCHARDISPVAL[0] TXDATA[7:0] (last bit transmitted is TXDATA[0]) 8B/10B Encoder A bypassable 8B/10B encoder is included. The encoder uses the same 256 data characters and 12 control characters that are used for Gigabit Ethernet, Fibre Channel, and InfiniBand. The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per character applied, and generates a 10 bit character for transmission. If the K-character signal is High, the data is encoded into one of the twelve possible K-characters available in the 8B/10B code. If the K-character input is Low, the 8 bits are encoded 12 Serializer The multi-gigabit transceiver multiplies the reference frequency provided on the reference clock input (REFCLK) by 20. Clock multiplication is achieved by using a fully monolithic PLL requiring no external components. Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs. Bit 0 is transmitted first and bit 19 is transmitted last. The electrical connection of TXP and TXN can be interchanged through configuration. This option can be controlled by an input (TXPOLARITY) at the FPGA transmitter interface. This facilitates recovery from situations where printed circuit board traces have been reversed. Transmit Termination On-chip termination is provided at the transmitter, eliminating the need for external termination. Programmable options exist for 50 (default) and 75 termination. Pre-Emphasis Circuit and Swing Control Four selectable levels of pre-emphasis (10% [default], 20%, 25%, and 33%) are available. Optimizing this setting allows the transceiver to drive up to 20 inches of FR4 at the maximum baud rate. The programmable output swing control can adjust the differential output level between 400 mV and 800 mV in four increments of 100 mV. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Receiver Deserializer The Rocket I/O transceiver core accepts serial differential data on its RXP and RXN inputs. The clock/data recovery circuit extracts the clock and retimes incoming data to this clock. It uses a fully monolithic PLL requiring no external components. The clock/data recovery circuitry extracts both phase and frequency from the incoming data stream. The recovered clock is presented on output RXRECCLK at 1/20 of the received serial data rate. The receiver is capable of handling either transition-rich 8B/10B streams or scrambled streams, and can withstand a string of up to 75 non-transitioning bits without an error. Word alignment is dependent on the state of comma detect bits. If comma detect is enabled, the transceiver will recognize up to two 10-bit preprogrammed characters. Upon detection of the character or characters, the comma detect output is driven high and the data is synchronously aligned. If a comma is detected and the data is aligned, no further alignment alteration will take place. If a comma is received and realignment is necessary, the data is realigned and an indication is given at the receiver interface. The realignment indicator is a distinct output. The transceiver will continuously monitor the data for the presence of the 10-bit character(s). Upon each occurrence of the 10-bit character, the data is checked for word alignment. If comma detect is disabled, the data will not be aligned to any particular pattern. The programmable option allows a user to align data on comma+, comma-, both, or a unique user-defined and programmed sequence. The receiver can be configured to reverse the RXP and RXN inputs. This can be useful in the event that printed circuit board traces have been reversed. Receiver Termination On-chip termination is provided at the receiver, eliminating the need for external termination. The receiver includes programmable on-chip termination circuitry for 50 (default) or 75 impedance. 8B/10B Decoder An optional 8B/10B decoder is included. A programmable option allows the decoder to be bypassed. When the 8B/10B decoder is bypassed, the 10-bit character order is, for example, RXCHARISK[0] RXRUNDISP[0] RXDATA[7:0] (first bit received) (last bit received is RXDATA[0]) The decoder uses the same table that is used for Gigabit Ethernet, Fibre Channel, and InfiniBand. In addition to decoding all data and K-characters, the decoder has several extra features. The decoder separately detects both "disparity errors" and "out-of-band" errors. A disparity error is the reception of 10-bit character that exists within the DS083-2 (v1.0) January 31, 2002 Advance Product Specification 8B/10B table but has an incorrect disparity. An out-of-band error is the reception of a 10-bit character that does not exist within the 8B/10B table. It is possible to obtain an out-of-band error without having a disparity error. The proper disparity is always computed for both legal and illegal characters. The current running disparity is available at the RXRUNDISP signal. The 8B/10B decoder performs a unique operation if out-of-band data is detected. If out-of-band data is detected, the decoder signals the error and passes the illegal 10-bits through and places them on the outputs. This can be used for debugging purposes if desired. The decoder also signals the reception of one of the 12 valid K-characters. In addition, a programmable comma detect is included. The comma detect signal registers a comma on the receipt of any comma+, comma-, or both. Since the comma is defined as a 7-bit character, this includes several out-of-band characters. Another option allows the decoder to detect only the three defined commas (K28.1, K28.5, and K28.7) as comma+, comma-, or both. In total, there are six possible options, three for valid commas and three for "any comma." It should be noted that all bytes (1, 2, or 4) at the RX FPGA interface will each have their own individual 8B/10B indicators (K-character, disparity error, out-of-band error, current running disparity, and comma detect). Loopback In order to facilitate testing without having the need to either apply patterns or measure data at GHz rates, two programmable loop-back features are available. One option, serial loopback, places the gigabit transceiver into a state where transmit data is directly fed back to the receiver. An important point to note is that the feedback path is at the output pads of the transmitter. This tests the entirety of the transmitter and receiver. The second loopback path is a parallel path that checks the digital circuitry. When the parallel option is enabled, the serial loopback path is disabled. However, the transmitter outputs remain active and data is transmitted over a link. If TXINHIBIT is asserted, TXP is forced to 0 until TXINHIBIT is de-asserted. Elastic and Transmitter Buffers Both the transmitter and the receiver include buffers (FIFOs) in the datapath. This section gives the reasons for including the buffers and outlines their operation. Receiver Buffer The receiver buffer is required for two reasons: * * Clock corection to accommodate the slight difference in frequency between the recovered clock RXRECCLK and the internal FPGA user clock RXUSRCLK Channel bonding to allow realignment of the input www.xilinx.com 1-800-255-7778 13 R Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) stream to ensure proper alignment of data being read through multiple transceivers The receiver uses an elastic buffer, where "elastic" refers to the ability to modify the read pointer for clock correction and channel bonding. Clock Correction Clock RXRECCLK (the recovered clock) reflects the data rate of the incoming data. Clock RXUSRCLK defines the rate at which the FPGA fabric consumes the data. Ideally, these rates are identical. However, since the clocks typically have different sources, one of the clocks will be faster than the other. The receiver buffer accommodates this difference between the clock rates. See Figure 3. Read RXUSRCLK Write RXRECCLK "Nominal" condition: buffer half-full Read Write Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer will fill up over time. The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA fabric byte stream. This is shown in the bottom buffer, Figure 3, where the solid read pointer increments to the value represented by the dashed pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design will skip a single byte sequence when necessary to partially empty a buffer. If attribute CLK_COR_REPEAT_WAIT is 0, the transceiver may also skip two consecutive removable byte sequences in one step to further empty the buffer when necessary. These operations require the clock correction logic to recognize a byte sequence that can be freely repeated or omitted in the incoming data stream. This sequence is generally an IDLE sequence, or other sequence comprised of special values that occur in the gaps separating packets of meaningful data. These gaps are required to occur sufficiently often to facilitate the timely execution of clock correction. Channel Bonding Read Buffer less than half -full (emptying) Repeatable sequence Write Some gigabit I/O standards such as Infiniband specify the use of multiple transceivers in parallel for even higher data rates. Words of data are split into bytes, with each byte sent over a separate channel (transceiver). See Figure 4. Buffer more than half-full (filling up) Removable sequence DS083-2_15_100901 In Transmitters: Full word SSSS sent over four channels, one byte per channel Figure 3: Clock Correction in Receiver Nominally, the buffer is always half full. This is shown in the top buffer, Figure 3, where the shaded area represents buffered data not yet read. Received data is inserted via the write pointer under control of RXRECCLK. The FPGA fabric reads data via the read pointer under control of RXUSRCLK. The half full/half empty condition of the buffer gives a cushion for the differing clock rates. This operation continues indefinitely, regardless of whether or not "meaningful" data is being received. When there is no meaningful data to be received, the incoming data will consist of IDLE characters or other padding. If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The clock correction logic corrects for this by decrementing the read pointer to reread a repeatable byte sequence. This is shown in the middle buffer, Figure 3, where the solid read pointer decrements to the value represented by the dashed pointer. By decrementing the read pointer instead of incrementing it in the usual fashion, the buffer is partially refilled. The transceiver design will repeat a single repeatable byte sequence when necessary to refill a buffer. If the byte sequence length is greater than one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver may repeat the same sequence multiple times until the buffer is refilled to the desired extent. 14 PQRS T Channel (lane) 0 PQRS T Channel (lane) 1 PQRS T Channel (lane) 2 PQRS T Channel (lane) 3 Read RXUSRCLK PQRS T PQRS T In Receivers: Read RXUSRCLK PQRS T PQRS T PQRS T PQRS T PQRS T PQRS T Before channel bonding After channel bonding DS083-2_16_010202 Figure 4: Channel Bonding (Alignment) The top half of the figure shows the transmission of words split across four transceivers (channels or lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the four channels. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description The bottom-left portion of the figure shows the initial situation in the FPGA's receivers at the other end of the four channels. Due to variations in transmission delay--especially if the channels are routed through repeaters--the FPGA fabric may not correctly assemble the bytes into complete words. The bottom-left illustration shows the incorrect assembly of data words PQPP, QRQQ, RSRR, etc. To support correction of this misalignment, the data stream will include special byte sequences that define corresponding points in the several channels. In the bottom half of Figure 4, the shaded "P" bytes represent these special characters. Each receiver recognizes the "P" channel bonding character, and remembers its location in the buffer. At some point, one transceiver designated as the master instructs all the transceivers to align to the channel bonding character "P" (or to some location relative to the channel bonding character). After this operation, the words transmitted to the FPGA fabric will be properly aligned: RRRR, SSSS, TTTT, etc., as shown in the bottom-right portion of Figure 4. To ensure that the channels remain properly aligned following the channel bonding operation, the master transceiver must also control the clock correction operations described in the previous section for all channel-bonded transceivers. Transmitter Buffer The transmitter's buffer write pointer (TXUSRCLK) is frequency-locked to its read pointer (REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of the transmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK. A simple FIFO suffices for this purpose. A FIFO depth of four will permit reliable operation with simple detection of overflow or underflow, which could occur if the clocks are not frequency-locked. CRC The Rocket I/O transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, FibreChannel, and Gigabit Ethernet. On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC. For Gigabit Ethernet and FibreChannel, transmitter CRC may adjust certain trailing bytes to generate the required running disparity at the end of the packet. On the receiver side, the CRC logic verifies the received CRC value, supporting the same standards as above. The CRC logic also supports a user mode, with a simple data packet stucture beginning and ending with user-defined SOP and EOP characters. trolled by configuration. Xilinx implementation software supports 16 transceiver primitives, as shown in Table 2. Table 2: Supported Rocket I/O Transceiver Primitives GT_CUSTOM Fully customizable by user GT_FIBRE_CHAN_1 Fibre Channel, 1-byte data path GT_FIBRE_CHAN_2 Fibre Channel, 2-byte data path GT_FIBRE_CHAN_4 Fibre Channel, 4-byte data path GT_ETHERNET_1 Gigabit Ethernet, 1-byte data path GT_ETHERNET_2 Gigabit Ethernet, 2-byte data path GT_ETHERNET_4 Gigabit Ethernet, 4-byte data path GT_XAUI_1 10-gigabit Ethernet, 1-byte data path GT_XAUI_2 10-gigabit Ethernet, 2-byte data path GT_XAUI_4 10-gigabit Ethernet, 4-byte data path GT_INFINIBAND_1 Infiniband, 1-byte data path GT_INFINIBAND_2 Infiniband, 2-byte data path GT_INFINIBAND_4 Infiniband, 4-byte data path GT_AURORA_1 Xilinx protocol, 1-byte data path GT_AURORA_2 Xilinx protocol, 2-byte data path GT_AURORA_4 Xilinx protocol, 4-byte data path Each of the above primitives defines default values for the configuration attributes, allowing some number of them to be modified by the user. Refer to the Rocket I/O User Guide for more details. Reset / Power Down The receiver and transmitter have their own synchronous reset inputs. The transmitter reset recenters the transmission FIFO, and resets all transmitter registers and the 8B/10B decoder. The receiver reset recenters the receiver elastic buffer, and resets all receiver registers and the 8B/10B encoder. Neither reset signal has any effect on the PLLs. The Power Down module is controlled by the POWERDOWN input pin on the transceiver core. The Power down pin on the FPGA package has no effect on the transceiver core. Power Sequencing Although applying power in a random order does not damage the device, it is recommended to apply power in the following sequence to minimize power-on current: 1. Apply FPGA fabric power supplies (VCCINT and VCCAUX) in any order. Configuration 2. Apply AVCCAUXRX. This section outlines functions that may be selected or con- 3. Apply AVCCAUXTX, VTTX, and VTRX in any order. DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 15 R Functional Description: Processor Block Functional Description: Processor Block consumption. Specially designed interface logic integrates the core with the surrounding CLBs, block RAMs, and general routing resources. Up to four Processor Blocks can be available in a single Virtex-II Pro device. CPU-FPGA Interfaces BRAM The PPC405 core implements the PowerPC User Instruction Set Architecture (UISA), user-level registers, programming model, data types, and addressing modes for 32-bit fixed-point operations. 64-bit operations, auxiliary processor operations, and floating-point operations are trapped and can be emulated in software. BRAM Most of the PPC405 core features are compatible with the specifications for the PowerPC Virtual Environment Architecture (VEA) and Operating Environment Architecture (OEA). They also provide a number of optimizations and extensions to the lower layers of the PowerPC Architecture. The full architecture of the PPC405 is defined by the PowerPC Embedded Environment and the PowerPC UISA. FPGA CLB Array PPC 405 Core OCM Controller OCM Controller Control On-Chip Memory (OCM) Controllers Introduction BRAM BRAM Interface Logic Processor Block = CPU Core + Interface Logic + CPU-FPGA Interface DS083-2_03a_060701 Figure 5: Processor Block Architecture This section briefly describes the interfaces and components of the Processor Block. The subsequent section, Functional Description: PowerPC 405 Core beginning on page 19, offers a summary of major PPC405 core features. For an in-depth discussion on both Processor Block and PPC405, refer to the Processor Block Manual and the PPC405 User Manual. Processor Block Overview Figure 5 shows the internal architecture of the Processor Block. Within the Virtex-II Pro Processor Block, there are four components: * * * * Embedded IBM PowerPC 405-D5 RISC CPU core On-Chip Memory (OCM) controllers and interfaces Clock/control interface logic CPU-FPGA Interfaces * * * * The PowerPC 405D5 core is a 0.13 m implementation of the IBM PowerPC 405D4 core. The advanced process technology enables the embedded PowerPC 405 (PPC405) core to operate at 300+ MHz while maintaining low power ISBRAM only DSBRAM only Both ISBRAM and DSBRAM No ISBRAM and no DSBRAM One of OCM's primary advantages is that it guarantees a fixed latency of execution for a higher level of determinism. Additionally, it reduces cache pollution and thrashing, since the cache remains available for caching code from other memory resources. Typical applications for DSOCM include scratch-pad memory, as well as use of the dual-port feature of block RAM to enable bidirectional data transfer between processor and FPGA. Typical applications for ISOCM include storage of interrupt service routines. Functional Features Common Features * Embedded PowerPC 405 RISC Core 16 The OCM controllers serve as dedicated interfaces between the block RAMs in the FPGA fabric (see 18 Kb Block SelectRAM Resources, page 39) and OCM signals available on the embedded PPC405 core. The OCM signals on the PPC405 core are designed to provide very quick access to a fixed amount of instruction and data memory space. The OCM controller provides an interface to both the 64-bit Instruction-Side Block RAM (ISBRAM) and the 32-bit Data-Side Block RAM (DSBRAM). The designer can choose to implement: * * Separate Instruction and Data memory interface between Processor core and BRAMs in FPGA Dedicated interface to Device Control Register (DCR) bus for ISOCM and DSOCM Single-cycle and multi-cycle mode option for I-side and D-side interfaces www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R * * * * Virtex-II ProTM Platform FPGAs: Functional Description Single cycle = one clock cycle; multi-cycle = minimum of two and maximum of eight clock cycles FPGA configurable DCR addresses within DSOCM and ISOCM Independent 16 MB logical memory space available within PPC405 memory map for each of the DSOCM and ISOCM. The number of block RAMs in the device may limit the maximum amount of OCM supported. Maximum of 64K and 128K bytes addressable from DSOCM and ISOCM interfaces, respectively, using address outputs from OCM directly without additional decoding logic Data-Side OCM (DSOCM) * * * * * * 32-bit Data Read bus and 32-bit Data Write bus Byte write access to DSBRAM support Second port of dual port DSBRAM is available to read/write from an FPGA interface 22-bit address to DSBRAM port 8-bit DCR Registers: DSCNTL, DSARC Three alternatives to write into DSBRAM: BRAM initialization, CPU, FPGA H/W using second port fore processor signals have the same routability as other non-Processor Block user signals. Longlines and hex lines travel across the Processor Block both vertically and horizontally, allowing signals to route through the Processor Block. Processor Local Bus (PLB) Interfaces The PPC405 core accesses high-speed system resources through PLB interfaces on the instruction and data cache controllers. The PLB interfaces provide separate 32-bit address/64-bit data buses for the instruction and data sides. The cache controllers are both PLB masters. PLB arbiters can be implemented on FPGA fabric and are available as soft IP cores. Device Control Register (DCR) Bus Interface The device control register (DCR) bus has 10 bits of address space for components external to the PPC405 core. Using the DCR bus to manage status and configuration registers reduces PLB traffic and improves system integrity. System resources on the DCR bus are protected or isolated from wayward code since the DCR bus is not part of the system memory map. Instruction-Side OCM (ISOCM) On-Chip Memory (OCM) Interfaces The ISOCM interface contains a 64-bit read only port, for instruction fetches, and a 32-bit write only port, to initialize or test the ISBRAM. When implementing the read only port, the user must deassert the write port inputs. The preferred method of initializing the ISBRAM is through the configuration bitstream. Access to optional, user-configurable direct-mapped memory is through the OCM interfaces. The OCM interfaces can have the same access time as a cache hit, depending on the clock frequency and block RAM size. OCM may be attached to the PPC405 core through the instruction OCM interface and/or the data OCM interface. * * * * * * Instruction side OCM is often used to hold critical code such as an interrupt handler that requires guaranteed low-latency deterministic access. Data side OCM offers the same fixed low-latency access and is used to hold critical data such as filter coefficients for a DSP application or packets for fast processing. Refer to On-Chip Memory (OCM) Controllers, page 16, for more information. 64-bit Data Read Only bus (two instructions per cycle) 32-bit Data Write Only bus (through DCR) Separate 21-bit address to ISBRAM 8-bit DCR Registers: ISCNTL, ISARC 32-bit DCR Registers: ISINIT, ISFILL Two alternatives to write into ISBRAM: BRAM initialization, DCR and write instruction Clock/Control Interface Logic The clock/control interface logic provides proper initialization and connections for PPC405 clock/power management, resets, PLB cycle control, and OCM interfaces. It also couples user signals between the FPGA fabric and the PPC405 CPU core. The processor clock connectivity is similar to CLB clock pins. It can connect either to global clock nets or general routing resources. Therefore the processor clock source can come from DCM, CLB, or user package pin. External Interrupt Controller (EIC) Interface Two level-sensitive user interrupt pins (critical and non-critical) are available. They can be either driven by user defined logic or Xilinx soft interrupt controller IP core outside the Processor Block. Clock/Power Management (CPM) Interface The CPM interface supports several methods of clock distribution and power management.Three modes of operation that reduce power consumption below the normal operational level are available. Reset Interface CPU-FPGA Interfaces All Processor Block user pins link up with the general FPGA routing resources through the CPU-FPGA interface. There- DS083-2 (v1.0) January 31, 2002 Advance Product Specification There are three user reset input pins (core, chip, and system) and three user reset output pins for different levels of reset, if required. www.xilinx.com 1-800-255-7778 17 R Functional Description: Processor Block CoreConnectTM Bus Architecture The JTAG port complies with IEEE Std 1149.1, which defines a test access port (TAP) and boundary scan architecture. Extensions to the JTAG interface provide debuggers with processor control that includes stopping, starting, and stepping the PPC405 core. These extensions are compliant with the IEEE 1149.1 specifications for vendor-specific extensions. The Trace port provides instruction execution trace information to an external trace tool. The PPC405 core is capable of back trace and forward trace. Back trace is the tracing of instructions prior to a debug event while forward trace is the tracing of instructions after a debug event. The processor JTAG port can be accessed independently from the FPGA JTAG port, or the two can be programmatically linked together and accessed via the FPGA's dedicated JTAG pins. System Core Arbiter System Core System Core DCR Bus Peripheral Core Bus Bridge Processor Local Bus Peripheral Core On-Chip Peripheral Bus Arbiter Debugging interfaces on the PPC405 core, consisting of the JTAG and Trace ports, offer access to resources internal to the core and assist in software development. The JTAG port provides basic JTAG chip testing functionality as well as the ability for external debug tools to gain control of the processor for debug purposes. The Trace port furnishes programmers with a mechanism for acquiring instruction execution traces. DCR Bus Debug Interface CoreConnect Bus Architecture Instruction Data Processor Block DCR Bus DS083-2_02a_010202 Figure 6: CoreConnect Block Diagram The Processor Block is compatible with the CoreConnectTM bus architecture. Any CoreConnect compliant cores including Xilinx soft IP can integrate with the Processor Block through this high-performance bus architecture implemented on FPGA fabric. The CoreConnect architecture provides three buses for interconnecting Processor Blocks, Xilinx soft IP, third party IP, and custom logic, as shown in Figure 6: * * * Processor Local Bus (PLB) On-Chip Peripheral Bus (OPB) Device Control Register (DCR) bus High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance. For more information, refer to: http://www-3.ibm.com/chips/techlib/techlib.nfs /productfamilies/CoreConnect_Bus_Architecture/ 18 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description PLB Master Interface Instruction OCM MMU I-Cache Array I-Cache Controller Instruction Cache Unit Cache Units Data Cache Unit D-Cache Array D-Cache Controller Instruction Shadow TLB (4 Entry) Fetch & Decode 3-Element Fetch Fetch and Queue Decode (PFB1, Logic PFB0, DCD) (FIT, PIT, Watchdog) Timers & Debug Unified TLB (64 Entry) Data Shadow TLB (8 Entry) Timers Execution Unit (EXU) 32 x 32 GPR ALU Debug Logic MAC Execution Unit PLB Master Interface Data OCM JTAG Instruction Trace DS083-2_01_062001 Figure 7: PPC405 Core Block Diagram Functional Description: PowerPC 405 Core This section offers a brief overview of the various functional blocks shown in Figure 7. PPC405 Core The PPC405 core is a 32-bit Harvard architecture processor. It consists of the following functional blocks as shown in Figure 7: * * * * * * The PPC405 core accesses external memory through the instruction (ICU) and data cache units (DCU). The cache units each include a 64-bit PLB master interface, cache arrays, and a cache controller. The ICU and DCU handle cache misses as requests over the PLB to another PLB device such as an external bus interface unit. Cache hits are handled as single cycle memory accesses to the instruction and data caches. Instruction Cache Unit (ICU) The ICU provides one or two instructions per cycle to the instruction queue over a 64-bit bus. A line buffer (built into the output of the array for manufacturing test) enables the ICU to be accessed only once for every four instructions, to reduce power consumption by the array. Cache units Memory Management unit Fetch Decode unit Execution unit Timers Debug logic unit It operates on instructions in a five stage pipeline consisting of a fetch, decode, execute, write-back, and load write-back stage. Most instructions execute in a single cycle, including loads and stores. The ICU can forward any or all of the four or eight words of a line fill to the EXU to minimize pipeline stalls caused by cache misses. The ICU aborts speculative fetches abandoned by the EXU, eliminating unnecessary line fills and enabling the ICU to handle the next EXU fetch. Aborting abandoned requests also eliminates unnecessary external bus activity, thereby increasing external bus utilization. Instruction and Data Cache Data Cache Unit (DCU) The PPC405 core provides an instruction cache unit (ICU) and a data cache unit (DCU) that allow concurrent accesses and minimize pipeline stalls. The instruction and data cache array are 16 KB each. Both cache units are two-way set associative. Each way is organized into 256 lines of 32 bytes (eight words). The instruction set provides a rich assortment of cache control instructions, including instructions to read tag information and data arrays. The DCU transfers one, two, three, four, or eight bytes per cycle, depending on the number of byte enables presented by the CPU. The DCU contains a single-element command and store data queue to reduce pipeline stalls; this queue enables the DCU to independently process load/store and cache control instructions. Dynamic PLB request prioritization reduces pipeline stalls even further. When the DCU is busy with a low-priority request while a subsequent storage DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 19 R Functional Description: PowerPC 405 Core operation requested by the CPU is stalled; the DCU automatically increases the priority of the current request to the PLB. The DCU provides additional features that allow the programmer to tailor its performance for a given application. The DCU can function in write-back or write-through mode, as controlled by the Data Cache Write-through Register (DCWR) or the Translation Look-aside Buffer (TLB); the cache controller can be tuned for a balance of performance and memory coherency. Write-on-allocate, controlled by the store word on allocate (SWOA) field of the Core Configuration Register 0 (CCR0), can inhibit line fills caused by store misses, to further reduce potential pipeline stalls and unwanted external bus traffic. Fetch and Decode Logic The PPC405 core has a 4 GB address space, which is presented as a flat address space. The MMU provides address translation, protection functions, and storage attribute control for embedded applications. The MMU supports demand-paged virtual memory and other management schemes that require precise control of logical-to-physical address mapping and flexible memory protection. Working with appropriate system-level software, the MMU provides the following functions: * * * The fetch and decode logic maintains a steady flow of instructions to the execution unit by placing up to two instructions in the fetch queue. The fetch queue consists of three buffers: pre-fetch buffer 1 (PFB1), pre-fetch buffer 0 (PFB0) and decode (DCD). The fetch logic ensures that instructions proceed directly to decode when the queue is empty. Static branch prediction as implemented on the PPC405 core takes advantage of some standard statistical properties of code. Branches with negative address displacement are by default assumed taken. Branches that do not test the condition or count registers are also predicted as taken. The PPC405 core bases branch prediction upon these default conditions when a branch is not resolved and speculatively fetches along the predicted path. The default prediction can be overridden by software at assembly or compile time. Branches are examined in the decode and pre-fetch buffer 0 fetch queue stages. Two branch instructions can be handled simultaneously. If the branch in decode is not taken, the fetch logic fetches along the predicted path of the branch instruction in pre-fetch buffer 0. If the branch in decode is taken, the fetch logic ignores the branch instruction in pre-fetch buffer 0. Execution Unit The PPC405 core has a single issue execution unit (EXU), which contains the register file, arithmetic logic unit (ALU), and the multiply-accumulate (MAC) unit. The execution unit performs all 32-bit PowerPC integer instructions in hardware. The register file is comprised of thirty-two 32-bit general purpose registers (GPR), which are accessed with three read ports and two write ports. During the decode stage, data is read out of the GPRs and fed to the execution unit. Likewise, during the write-back stage, results are written to the GPR. The use of the five ports on the register file enables either a load or a store operation to execute in parallel with an ALU operation. 20 Memory Management Unit (MMU) * * * Translation of the 4 GB effective address space into physical addresses Independent enabling of instruction and data translation/protection Page-level access control using the translation mechanism Software control of page replacement strategy Additional control over protection using zones Storage attributes for cache policy and speculative memory access control The MMU can be disabled under software control. If the MMU is not used, the PPC405 core provides other storage control mechanisms. Translation Look-Aside Buffer (TLB) The Translation Look-Aside Buffer (TLB) is the hardware resource that controls translation and protection. It consists of 64 entries, each specifying a page to be translated. The TLB is fully associative; a given page entry can be placed anywhere in the TLB. The translation function of the MMU occurs pre-cache. Cache tags and indexing use physical addresses. Software manages the establishment and replacement of TLB entries. This gives system software significant flexibility in implementing a custom page replacement strategy. For example, to reduce TLB thrashing or translation delays, software can reserve several TLB entries in the TLB for globally accessible static mappings. The instruction set provides several instructions used to manage TLB entries. These instructions are privileged and require the software to be executing in supervisor state. Additional TLB instructions are provided to move TLB entry fields to and from GPRs. The MMU divides logical storage into pages. Eight page sizes (1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, and 16 MB) are simultaneously supported, such that, at any given time, the TLB can contain entries for any combination of page sizes. In order for a logical to physical translation to exist, a valid entry for the page containing the logical address must be in the TLB. Addresses for which no TLB entry exists cause TLB-Miss exceptions. To improve performance, four instruction-side and eight data-side TLB entries are kept in shadow arrays. The www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description shadow arrays allow single-cycle address translation and also help to avoid TLB contention between load/store and instruction fetch operations. Hardware manages the replacement and invalidation of shadow-TLB entries; no system software action is required. Memory Protection for system error recovery in the event of software or system lockups. Users may select one of four time periods for the interval and the type of reset generated if the WDT expires twice without an intervening clear from software. If enabled, the watchdog timer generates a reset unless an exception handler updates the WDT status bit before the timer has completed two of the selected timer intervals. When address translation is enabled, the translation mechanism provides a basic level of protection. The Zone Protection Register (ZPR) enables the system software to override the TLB access controls. For example, the ZPR provides a way to deny read access to application programs. The ZPR can be used to classify storage by type; access by type can be changed without manipulating individual TLB entries. Time Base (Incrementer) TBL (32 bits) External Clock Source 0 The PowerPC Architecture provides WIU0GE (write-back / write-through, cacheability, user-defined 0, guarded, endian) storage attributes that control memory accesses, using bits in the TLB or, when address translation is disabled, storage attribute control registers. TBU (32 bits) 31 0 Bit 3 (229 clocks) Bit 7 (225 clocks) Bit 11 (221 clocks) Bit 11 (221 clocks) Bit 15 (217 clocks) Bit 19 (213 clocks) FIT Events Bit 23 (2 9 clocks) PIT (Decrementer) (32 bits) 0 31 Zero Detect Timers PIT Events DS083-2_06_062001 The PPC405 core contains a 64-bit time base and three timers, as shown in Figure 8: Figure 8: Relationship of Timer Facilities to Base Clock Interrupts Programmable Interval Timer (PIT) Fixed Interval Timer (FIT) Watchdog Timer (WDT) The time base counter increments either by an internal signal equal to the CPU clock rate or by a separate external timer clock signal. No interrupts are generated when the time base rolls over. The three timers are synchronous with the time base. The PIT is a 32-bit register that decrements at the same rate as the time base is incremented. The user loads the PIT register with a value to create the desired delay. When the register reaches zero, the timer stops decrementing and generates a PIT interrupt. Optionally, the PIT can be programmed to auto-reload the last value written to the PIT register, after which the PIT continues to decrement. The FIT generates periodic interrupts based on one of four selectable bits in the time base. When the selected bit changes from 0 to 1, the PPC405 core generates a FIT interrupt. The WDT provides a periodic critical-class interrupt based on a selected bit in the time base. This interrupt can be used DS083-2 (v1.0) January 31, 2002 Advance Product Specification WDT Events Bit 15 (217 clocks) When address translation is enabled, storage attribute control bits in the TLB control the storage attributes associated with the current page. When address translation is disabled, bits in each storage attribute control register control the storage attributes associated with storage regions. Each storage attribute control register contains 32 fields. Each field sets the associated storage attribute for a 128 MB memory region. * * * 31 The PPC405 provides an interface to an interrupt controller that is logically outside the PPC405 core. This controller combines the asynchronous interrupt inputs and presents them to the core as a single interrupt signal. The sources of asynchronous interrupts are external signals, the JTAG/debug unit, and any implemented peripherals. Debug Logic All architected resources on the PPC405 core can be accessed through the debug logic. Upon a debug event, the PPC405 core provides debug information to an external debug tool. Three different types of tools are supported depending on the debug mode: ROM monitors, JTAG debuggers, and instruction trace tools. In internal (intrusive) debug mode, a debug event enables exception-handling software at a dedicated interrupt vector to take over the CPU core and communicate with a debug tool. The debug tool has read-write access to all registers and can set hardware or software breakpoints. ROM monitors typically use the internal debug mode. www.xilinx.com 1-800-255-7778 21 R Functional Description: FPGA In external (non-intrusive) debug mode, the CPU core enters stop state (stops instruction execution) when a debug event occurs. This mode offers a debug tool non-intrusive read-write access to all registers in the PPC405 core. Once the CPU core is in stop state, the debug tool can start the CPU core, step an instruction, freeze the timers, or set hardware or software break points. In addition to CPU core control, the debug logic is capable of writing instructions into the instruction cache, eliminating the need for external memory during initial board bring up. Communication to a debug tool using external debug mode is through the JTAG port. Real-time trace debug mode is always enabled. The debug logic continuously broadcasts instruction trace information to the trace port. When a debug event occurs, the debug logic signals an external debug tool to save instruction trace information before and after the event. The number of instructions traced depends on the trace tool. Debug wait mode offers the same functionality as external debug mode with one exception. In debug wait mode, the CPU core goes into wait state instead of stop state after a debug event. Wait state is identical to stop state until an interrupt occurs. In wait state, the PPC405 core can vector to an exception handler, service an interrupt and return to wait state. This mode is particularly useful when debugging real time control systems. The PPC405 core supports big endian or little endian byte ordering for instructions stored in external memory. Since the PowerPC architecture is big endian internally, the ICU rearranges the instructions stored as little endian into the big endian format. Therefore, the instruction cache always contains instructions in big endian format so that the byte ordering is correct for the execution unit. This feature allows the 405 core to be used in systems designed to function in a little endian environment. Functional Description: FPGA standard used. For exact supply voltage absolute maximum ratings, see Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics (Module 3). Input/Output Blocks (IOBs) Virtex-II Pro I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as input and/or output for single-ended I/Os. Two IOBs can be used as a differential pair. A differential pair is always connected to the same switch matrix, as shown in Figure 9. Debug events signal the debug logic to stop the CPU core, put the CPU core in debug wait state, cause a debug exception or save instruction trace information. Big Endian and Little Endian Support Table 3: Supported Single-Ended I/O Standards Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS33 3.3 3.3 N/A N/A IOB PAD3 LVCMOS25 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A IOB PAD2 LVCMOS15 1.5 1.5 N/A N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A GTL Note (1) Note (1) 0.8 1.2 GTLP Note (1) Note (1) 1.0 1.5 IOB PAD4 I/O Standard Differential Pair Switch Matrix Differential Pair IOB PAD1 DS083-2_30_010202 Figure 9: Virtex-II Pro Input/Output Tile IOB blocks are designed for high-performance I/Os, supporting 22 single-ended standards, as well as differential signaling with LVDS, LDT, and bus LVDS. HSTL_I 1.5 N/A 0.75 0.75 HSTL_II 1.5 N/A 0.75 0.75 HSTL_III 1.5 N/A 0.9 1.5 Supported I/O Standards HSTL_IV 1.5 N/A 0.9 1.5 Virtex-II Pro IOB blocks feature SelectI/O inputs and outputs that support a wide variety of I/O signaling standards. In addition to the internal supply voltage (VCCINT = 1.5V), output driver supply voltage (VCCO) is dependent on the I/O standard (see Table 3 and Table 4). An auxiliary supply voltage (VCCAUX = 2.5V) is required, regardless of the I/O HSTL_I_18 1.8 N/A 0.9 0.9 HSTL_II_18 1.8 N/A 0.9 0.9 HSTL_III _18 1.8 N/A 1.08 1.8 HSTL_IV_18 1.8 N/A 1.08 1.8 22 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Table 3: Supported Single-Ended I/O Standards Table 5: Supported DCI I/O Standards (Continued) Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) SSTL2_I 2.5 N/A 1.25 1.25 SSTL2_II 2.5 N/A 1.25 1.25 SSTL3_I 3.3 N/A 1.5 1.5 SSTL3_II 3.3 N/A 1.5 1.5 I/O Standard Notes: 1. VCCO of GTL or GTLP should not be lower than the termination voltage or the voltage seen at the I/O pad. Table 4: Supported Differential Signal I/O Standards I/O Standard Output VCCO Input VCCO Input VREF Output VOD LDT_25 2.5 N/A N/A 0.500 - 0.740 LVDS_25 2.5 N/A N/A 0.250 - 0.400 LVDSEXT_25 2.5 N/A N/A 0.330 - 0.700 BLVDS_25 2.5 N/A N/A 0.250 - 0.450 ULVDS_25 2.5 N/A N/A I/O Standard Output VCCO Input VCCO Input VREF Termination Type HSTL_I_DCI_18 1.8 1.8 0.9 Split HSTL_II_DCI_18 1.8 1.8 0.9 Split HSTL_III_DCI_18 1.8 1.8 1.08 Single HSTL_IV_DCI_18 1.8 1.8 1.08 Single SSTL2_I_DCI (2) 2.5 2.5 1.25 Split SSTL2_II_DCI (2) 2.5 2.5 1.25 Split SSTL3_I_DCI (2) 3.3 3.3 1.5 Split SSTL3_II_DCI (2) 3.3 3.3 1.5 Split Notes: 1. LVDCI_XX is LVCMOS controlled impedance buffers, matching the reference resistors or half of the reference resistors. 2. These are SSTL compatible. IOB DDR mux Input Reg 0.500 - 0.740 OCK1 All of the user IOBs have fixed-clamp diodes to VCCO and to ground. The IOBs are not compatible or compliant with 5V I/O standards (not 5V tolerant). Reg ICK1 Reg OCK2 Table 5 lists supported I/O standards with Digitally Controlled Impedance. See Digitally Controlled Impedance (DCI), page 27. 3-State Reg ICK2 DDR mux Reg Table 5: Supported DCI I/O Standards I/O Standard OCK1 PAD Output VCCO Input VCCO Input VREF Termination Type LVDCI_33 (1) 3.3 3.3 N/A Series LVDCI_25 2.5 2.5 N/A Series LVDCI_DV2_25 2.5 2.5 N/A Series LVDCI_18 1.8 1.8 N/A Series LVDCI_DV2_18 1.8 1.8 N/A Series Logic Resources LVDCI_15 1.5 1.5 N/A Series LVDCI_DV2_15 1.5 1.5 N/A Series IOB blocks include six storage elements, as shown in Figure 10. GTL_DCI 1.2 1.2 0.8 Single GTLP_DCI 1.5 1.5 1.0 Single HSTL_I_DCI 1.5 1.5 0.75 Split HSTL_II_DCI 1.5 1.5 0.75 Split HSTL_III_DCI 1.5 1.5 0.9 Single HSTL_IV_DCI 1.5 1.5 0.9 Single DS083-2 (v1.0) January 31, 2002 Advance Product Specification Reg OCK2 Output DS031_29_100900 Figure 10: Virtex-II Pro IOB Block Each storage element can be configured either as an edge-triggered D-type flip-flop or as a level-sensitive latch. On the input, output, and 3-state path, one or two DDR registers can be used. Double data rate is directly accomplished by the two registers on each path, clocked by the rising edges (or falling edges) from two different clock nets. The two clock signals are generated by the DCM and must be 180 degrees out of phase, as shown in Figure 11. There are two input, output, and 3-state data signals, each being alternately clocked out. www.xilinx.com 1-800-255-7778 23 R Functional Description: FPGA This DDR mechanism can be used to mirror a copy of the clock on the output. This is useful for propagating a clock along the data that has an identical delay. It is also useful for multiple clock generation, where there is a unique clock driver for every clock load. Virtex-II Pro devices can produce many copies of a clock with very little skew. DCM DCM 0 180 0 FDDR FDDR D1 D1 Q1 Q1 CLK1 CLK1 DDR MUX Q DDR MUX D2 Q D2 Q2 Q2 CLK2 CLK2 DS083-2_26_122001 Figure 11: Double Data Rate Registers Each group of two registers has a clock enable signal (ICE for the input registers, OCE for the output registers, and TCE for the 3-state registers). The clock enable signals are active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. For each storage element, the SRHIGH, SRLOW, INIT0, and INIT1 attributes are independent. Synchronous or asynchronous set / reset is consistent in an IOB block. Each IOB block has common synchronous or asynchronous set and reset (SR and REV signals). Each register or latch, independent of all other registers or latches, can be configured as follows: SR forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic 1. SRLOW forces a logic "0". When SR is used, a second input (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition. The initial state after configuration or global initialization state is defined by a separate INIT0 and INIT1 attribute. By default, the SRLOW attribute forces INIT0, and the SRHIGH attribute forces INIT1. * * * * * * * All the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed. No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear) The synchronous reset overrides a set, and an asynchronous clear overrides a preset. Refer to Figure 12. 24 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description (O/T) 1 FF LATCH D1 (O/T) CE Q1 Attribute INIT1 INIT0 SRHIGH SRLOW CE CK1 SR REV (O/T) CLK1 SR Shared by all registers REV FF1 DDR MUX FF2 (OQ or TQ) FF LATCH D2 Q2 CE CK2 SR REV (O/T) CLK2 Attribute INIT1 INIT0 SRHIGH SRLOW (O/T) 2 Reset Type SYNC ASYNC DS031_25_110300 Figure 12: Register / Latch Configuration in an IOB Block Input/Output Individual Options VCCO Each device pad has optional pull-up/pull-down resistors and weak-keeper circuit in the LVCMOS SelectI/O configuration, as illustrated in Figure 13. Values of the optional pull-up and pull-down resistors fall within a range of 40 K to 120 K when VCCO = 2.5V (from 2.38V to 2.63V only). The clamp diode is always present, even when power is not. Clamp Diode OBUF VCCO Program Current Weak Keeper 40K - 120K PAD VCCO 40K - 120K VCCAUX = 2.5V VCCINT = 1.5V Program Delay IBUF The optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low. If the pin is connected to a multiple-source signal, the weak-keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. An enabled pull-up or pull-down overrides the weak-keeper circuit. DS083-2_07_101801 Figure 13: LVCMOS SelectI/O Standard DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 25 R Functional Description: FPGA LVTTL sinks and sources current up to 24 mA. The current is programmable for LVTTL and LVCMOS SelectI/O standards (see Table 6). Drive strength and slew rate controls for each output driver minimize bus transients. For LVDCI and LVDCI_DV2 standards, drive strength and slew rate controls are not available. Table 6: LVTTL and LVCMOS Programmable Currents (Sink and Source) SelectI/O Programmable Current (Worst-Case Guaranteed Minimum) LVTTL 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS33 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS25 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS18 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a LVCMOS15 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a Figure 14 shows the SSTL2 and HSTL configurations. HSTL can sink current up to 48 mA. (HSTL IV) VCCO Clamp Diode OBUF Input Path The Virtex-II Pro IOB input path routes input signals directly to internal logic and / or through an optional input flip-flop or latch, or through the DDR input registers. An optional delay element at the D-input of the storage element eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the Virtex-II Pro device, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signaling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in the same bank. See I/O banking description. PAD Output Path VREF VCCAUX = 2.5V VCCINT = 1.5V DS031_24_100900 Figure 14: SSTL or HSTL SelectI/O Standards All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. Virtex-II Pro uses two memory cells to control the configuration of an I/O as an input. This is to reduce the probability of an I/O configured as an input from flipping to an output when subjected to a single event upset (SEU) in space applications. Prior to configuration, all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive. The dedicated pin HSWAP_EN controls the pull-up resistors prior to configuration. By default, HSWAP_EN is set High, which disables the pull-up resistors on user I/O pins. When HSWAP_EN is set Low, the pull-up resistors are activated on user I/O pins. All Virtex-II Pro IOBs (except Rocket I/O pins) support IEEE 1149.1 and IEEE 1532 compatible boundary scan testing. 26 The output path includes a 3-state output buffer that drives the output signal onto the pad. The output and / or the 3-state signal can be routed to the buffer directly from the internal logic or through an output / 3-state flip-flop or latch, or through the DDR output / 3-state registers. Each output driver can be individually programmed for a wide range of low-voltage signaling standards. In most signaling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in the same bank. See I/O banking description. I/O Banking Some of the I/O standards described above require VCCO and VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOB blocks, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from dividing each edge of the FPGA into two banks, as shown in Figure 15 and Figure 16. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Table 7: Compatible Output Standards Bank 5 Figure 15: Virtex-II Pro I/O Banks: Top View for Wire-Bond Packages (CS, FG, and BG) Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 7. GTL and GTLP appear under all voltages because their open-drain outputs do not depend on VCCO. Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this role. 2.5V SSTL2 (I & II), LVCMOS25, GTL, GTLP, LVDS_25, LVDSEXT_25, LVDCI_25, LVDCI_DV2_25, SSTL2_DCI (I & II), LDT, ULVDS, BLVDS 1.8V HSTL (I, II, III, & IV), HSTL_DCI (I,II, III & IV), LVCMOS18, GTL, GTLP, LVDCI_18, LVDCI_DV2_18 1.5V HSTL (I, II, III, & IV), HSTL_DCI (I,II, III & IV), LVCMOS15, GTL, GTLP, LVDCI_15, LVDCI_DV2_15, GTLP_DCI 1.2V GTL_DCI Bank 2 Bank 7 Bank 6 Notes: 1. LVPECL, LVDS_33, LVDSEXT_33, and AGP-2X are not supported. 2. Perfect impedance matching is required for 3.3V standards. 3. For optimum performance, it is recommended that PCI be used in conjunction with LVDCI_33. Contact Xilinx for more details. Digitally Controlled Impedance (DCI) Today's chip output signals with fast edge rates require termination to prevent reflections and maintain signal integrity. High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Bank 5 ds031_66_112900 Figure 16: Virtex-II Pro I/O Banks: Top View for Flip-Chip Packages (FF and BF) VREF pins within a bank are interconnected internally, and consequently only one VREF voltage can be used within each bank. However, for correct operation, all VREF pins in the bank must be connected to the external reference voltage source. The VCCO and the VREF pins for each bank appear in the device pinout tables. Within a given package, the number of VREF and VCCO pins can vary depending on the size of DS083-2 (v1.0) January 31, 2002 Advance Product Specification PCI (3), LVTTL, SSTL3 (I & II), LVCMOS33, LVDCI_33, SSTL3_DCI (I & II) (1) All VREF pins for the largest device anticipated must be connected to the VREF voltage and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or, if necessary, they can be connected to the VCCO voltage to permit migration to a larger device. Bank 0 Bank 3 Bank 4 3.3V (2) Bank 4 ug002_c2_014_112900 Bank 1 Compatible Standards (1) VCCO Bank 3 Bank 6 Bank 2 Bank 1 Bank 7 Bank 0 device. In larger devices, more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. Virtex-II Pro DCI provides controlled impedance drivers and on-chip termination for single-ended I/Os. This eliminates the need for external resistors, and improves signal integrity. The DCI feature can be used on any IOB by selecting one of the DCI I/O standards. When applied to inputs, DCI provides input parallel termination. When applied to outputs, DCI provides controlled impedance drivers (series termination) or output parallel termination. DCI operates independently on each I/O bank. When a DCI I/O standard is used in a particular I/O bank, external reference resistors must be connected to two dual-function pins www.xilinx.com 1-800-255-7778 27 R Functional Description: FPGA on the bank. These resistors, voltage reference of N transistor (VRN) and the voltage reference of P transistor (VRP) are shown in Figure 17. Table 8: SelectI/O Controlled Impedance Buffers VCCO DCI DCI Half Impedance 3.3V LVDCI_33 N/A DCI 2.5V LVDCI_25 LVDCI_DV2_25 DCI 1.8V LVDCI_18 LVDCI_DV2_18 1.5V LVDCI_15 LVDCI_DV2_15 1 Bank DCI Controlled Impedance Terminations (Parallel Termination) DCI VCCO DCI also provides on-chip termination for SSTL3, SSTL2, HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or transmitters on bidirectional lines. RREF (1%) VRN Table 9 lists the on-chip parallel terminations available in Virtex-II Pro devices. VCCO must be set according to Table 5. Note that there is a VCCO requirement for GTL_DCI and GTLP_DCI, due to the on-chip termination resistor. VRP RREF (1%) GND Table 9: SelectI/O Buffers With On-Chip Parallel Termination DS031_50_101200 Figure 17: DCI in a Virtex-II Pro Bank When used with a terminated I/O standard, the value of the resistors are specified by the standard (typically 50). When used with a controlled impedance driver, the resistors set the output impedance of the driver within the specified range (20 to 100). For all series and parallel terminations listed in Table 8 and Table 9, the reference resistors must have the same value for any given bank. One percent resistors are recommended. The DCI system adjusts the I/O impedance to match the two external reference resistors, or half of the reference resistors, and compensates for impedance changes due to voltage and/or temperature fluctuations. The adjustment is done by turning parallel transistors in the IOB on or off. Controlled Impedance Drivers (Series Termination) External Termination On-Chip Termination SSTL3 Class I SSTL3_I SSTL3_I_DCI (1) SSTL3 Class II SSTL3_II SSTL3_II_DCI (1) SSTL2 Class I SSTL2_I SSTL2_I_DCI (1) SSTL2 Class II SSTL2_II SSTL2_II_DCI (1) HSTL_I HSTL_I_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II HSTL_II_DCI HSTL_II_18 HSTL_II_DCI_18 HSTL_III HSTL_III_DCI HSTL_III_18 HSTL_III_DCI_18 HSTL_IV HSTL_IV_DCI HSTL_IV_18 HSTL_IV_DCI_18 GTL GTL GTL_DCI GTLP GTLP GTLP_DCI HSTL Class I HSTL Class II HSTL Class III DCI can be used to provide a buffer with a controlled output impedance. It is desirable for this output impedance to match the transmission line impedance (Z0). Virtex-II Pro input buffers also support LVDCI and LVDCI_DV2 I/O standards. HSTL Class IV Notes: 1. SSTL Compatible IOB Z I/O Standard Z Virtex-II Pro DCI VCCO = 3.3V, 2.5 V, 1.8 V, or 1.5 V DS083-2_09_122001 Figure 18: Internal Series Termination 28 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Figure 19 provides examples illustrating the use of the HSTL_IV_DCI, HSTL_II_DCI, and SSTL2_DCI I/O standards. HSTL_IV VCCO HSTL_II VCCO/2 VCCO R R R SSTL2_I VCCO/2 VCCO/2 R R Z0 Z0 Z0 HSTL_IV_DCI Transmitter HSTL_II_DCI Transmitter VCCO VCCO VCCO R R VCCO/2 VCCO/2 2R R R Z0 Z0 Z0 2R Virtex-II Pro DCI Virtex-II Pro DCI Virtex-II Pro DCI VCCO VCCO/2 VCCO 2R 2R Z0 Z0 Z0 HSTL_IV_DCI Transmitter and Receiver HSTL_II_DCI Transmitter and Receiver VCCO R R 2R Virtex-II Pro DCI 2R Virtex-II Pro DCI Virtex-II Pro DCI VCCO VCCO VCCO R R R SSTL2_I_DCI Receiver HSTL_II_DCI Receiver HSTL_IV_DCI Receiver SSTL2_I_DCI Transmitter and Receiver VCCO VCCO VCCO 2R 2R 2R Z0 Z0 Z0 2R Virtex-II Pro DCI SSTL2_I_DCI Transmitter Virtex-II Pro DCI 2R Virtex-II Pro DCI Virtex-II Pro DCI Virtex-II Pro DCI 2R Virtex-II Pro DCI DS083-2_08_122001 Figure 19: DCI Usage Examples DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 29 R Functional Description: FPGA Configurable Logic Blocks (CLBs) Slice Description The Virtex-II Pro configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the general routing matrix, as shown in Figure 20. A CLB element comprises 4 similar slices, with fast local feedback within the CLB. The four slices are split in two columns of two slices with two independent carry logic chains and one common shift chain. Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. As shown in Figure 21, each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM memory, or a 16-bit variable-tap shift register element. ORCY RAM16 COUT TBUF TBUF Switch Matrix MUXFx Slice X1Y1 COUT SRL16 LUT G Slice X1Y0 Slice X0Y0 Register/ Latch RAM16 MUXF5 SHIFT Slice X0Y1 CY CIN SRL16 Fast Connects to neighbors LUT F CY Register/ Latch Arithmetic Logic CIN DS083-2_32_122001 DS083-2_31_122001 Figure 20: Virtex-II Pro CLB Element 30 Figure 21: Virtex-II Pro Slice Configuration www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description The output from the function generator in each slice drives both the slice output and the D input of the storage element. Figure 22 shows a more detailed view of a single slice. COUT SHIFTIN ORCY SOPIN SOPOUT 0 Dual-Port Shift-Reg G4 G3 G2 G1 WG4 WG3 WG2 WG1 A4 LUT A3 RAM A2 ROM A1 D WG4 G WG3 WG2 MC15 WG1 WS DI YBMUX I YB MUXCY O I GYMUX Y DY XORG FF LATCH ALTDIG MULTAND 1 0 DYMUX G2 PROD G1 CYOG BY CE CLK D Q Q Y CE CK SR REV BY SLICEWE[2:0] WSG WE[2:0] WE CLK SR SHIFTOUT DIG MUXCY I O WSF CE CLK Shared between x & y Registers SR CIN DS031_01_110600 Figure 22: Virtex-II Pro Slice (Top Half) Configurations input of the storage element, or go to the MUXF5 (not shown in Figure 22). Look-Up Table Virtex-II Pro function generators are implemented as 4-input look-up tables (LUTs). Four independent inputs are provided to each of the two function generators in a slice (F and G). These function generators are each capable of implementing any arbitrarily defined boolean function of four inputs. The propagation delay is therefore independent of the function implemented. Signals from the function generators can exit the slice (X or Y output), can input the XOR dedicated gate (see arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the D DS083-2 (v1.0) January 31, 2002 Advance Product Specification In addition to the basic LUTs, the Virtex-II Pro slice contains logic (MUXF5 and MUXFX multiplexers) that combines function generators to provide any function of five, six, seven, or eight inputs. The MUXFX is either MUXF6, MUXF7, or MUXF8 according to the slice considered in the CLB. Selected functions up to nine inputs (MUXF5 multiplexer) can be implemented in one slice. The MUXFX can also be a MUXF6, MUXF7, or MUXF8 multiplexer to map any function of six, seven, or eight inputs and selected wide logic functions. www.xilinx.com 1-800-255-7778 31 R Functional Description: FPGA Register/Latch The storage elements in a Virtex-II Pro slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D input can be directly driven by the X or Y output via the DX or DY input, or by the slice inputs bypassing the function generators via the BX or BY input. The clock enable signal (CE) is active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. In addition to clock (CK) and clock enable (CE) signals, each slice has set and reset signals (SR and BY slice inputs). SR forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic 1 when SR is asserted. SRLOW forces a logic 0. When SR is used, an optional second input (BY) forces the storage element into the opposite state via the REV pin. The reset condition is predominant over the set condition. (See Figure 23.) The initial state after configuration or global initial state is defined by a separate INIT0 and INIT1 attribute. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. For each slice, set and reset can be set to be synchronous or asynchronous. Virtex-II Pro devices also have the ability to set INIT0 and INIT1 independent of SRHIGH and SRLOW. The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both storage elements in one slice. All of the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed. FFY FF LATCH DY D Q CE CK SR REV BY DX CE CLK SR BX D YQ Attribute INIT1 INIT0 SRHIGH SRLOW The set and reset functionality of a register or a latch can be configured as follows: * * * * * * * No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear) The synchronous reset has precedence over a set, and an asynchronous clear has precedence over a preset. Distributed SelectRAM Memory Each function generator (LUT) can implement a 16 x 1-bit synchronous RAM resource called a distributed SelectRAM element. The SelectRAM elements are configurable within a CLB to implement the following: * * * * * * * Single-Port 16 x 8-bit RAM Single-Port 32 x 4-bit RAM Single-Port 64 x 2-bit RAM Single-Port 128 x 1-bit RAM Dual-Port 16 x 4-bit RAM Dual-Port 32 x 2-bit RAM Dual-Port 64 x 1-bit RAM Distributed SelectRAM memory modules are synchronous (write) resources. The combinatorial read access time is extremely fast, while the synchronous write simplifies high-speed designs. A synchronous read can be implemented with a storage element in the same slice. The distributed SelectRAM memory and the storage element share the same clock input. A Write Enable (WE) input is active High, and is driven by the SR input. Table 10 shows the number of LUTs (2 per slice) occupied by each distributed SelectRAM configuration. Table 10: Distributed SelectRAM Configurations RAM Number of LUTs 16 x 1S 1 FFX 16 x 1D 2 FF LATCH 32 x 1S 2 32 x 1D 4 64 x 1S 4 64 x 1D 8 128 x 1S 8 Q CE CK SR REV XQ Attribute INIT1 INIT0 SRHIGH SRLOW Reset Type SYNC ASYNC Notes: 1. S = single-port configuration; D = dual-port configuration DS083-2_22_122001 Figure 23: Register / Latch Configuration in a Slice 32 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description For single-port configurations, distributed SelectRAM memory has one address port for synchronous writes and asynchronous reads. For dual-port configurations, distributed SelectRAM memory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads. The function generator (LUT) has separated read address inputs (A1, A2, A3, A4) and write address inputs (WG1/WF1, WG2/WF2, WG3/WF3, WG4/WF4). RAM 16x1D 4 DPRA[3:0] 4 A[3:0] dual_port RAM G[4:1] D DPO WG[4:1] WS DI (BY) D In single-port mode, read and write addresses share the same address bus. In dual-port mode, one function generator (R/W port) is connected with shared read and write addresses. The second function generator has the A inputs (read) connected to the second read-only port address and the W inputs (write) shared with the first read/write port address. WSG WE CK Figure 24, Figure 25, and Figure 26 illustrate various example configurations. 4 A[3:0] dual_port RAM G[4:1] D SPO WG[4:1] WS DI RAM 16x1S A[3:0] 4 D (SR) WE CK Registered Output Q DI (BY) DS031_04_110100 Figure 26: Dual-Port Distributed SelectRAM (RAM16x1D) (optional) WSG WE WCLK WE WCLK Output D WG[4:1] WS D WSG RAM A[4:1] 4 (SR) WE CK DS031_02_100900 Figure 24: Distributed SelectRAM (RAM16x1S) Similar to the RAM configuration, each function generator (LUT) can implement a 16 x 1-bit ROM. Five configurations are available: ROM16x1, ROM32x1, ROM64x1, ROM128x1, and ROM256x1. The ROM elements are cascadable to implement wider or/and deeper ROM. ROM contents are loaded at configuration. Table 11 shows the number of LUTs occupied by each configuration. RAM 32x1S A[4] Table 11: ROM Configuration (BX) 4 A[3:0] RAM G[4:1] D WG[4:1] WS D WE WCLK WSG WE0 WE CK WSF 4 Number of LUTs 16 x 1 1 32 x 1 2 64 x 1 4 128 x 1 8 (1 CLB) 256 x 1 16 (2 CLBs) DI (BY) (SR) ROM WS DI RAM D Output F5MUX D Registered Output Q (optional) F[4:1] Shift Registers WF[4:1] DS083-2_10_050901 Figure 25: Single-Port Distributed SelectRAM (RAM32x1S) DS083-2 (v1.0) January 31, 2002 Advance Product Specification Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 27. A dynamic read access is performed through the 4-bit address bus, A[3:0]. The configurable 16-bit shift regis- www.xilinx.com 1-800-255-7778 33 R Functional Description: FPGA ter cannot be set or reset. The read is asynchronous; however, the storage element or flip-flop is available to implement a synchronous read. Any of the 16 bits can be read out asynchronously by varying the address. The storage element should always be used with a constant address. For example, when building an 8-bit shift register and configuring the addresses to point to the 7th bit, the 8th bit can be the flip-flop. The overall system performance is improved by using the superior clock-to-out of the flip-flops. 1 Shift Chain in CLB DI D SRLC16 MC15 IN DI D SRLC16 MC15 FF FF SLICE S3 SRLC16 SHIFTIN SHIFTOUT SHIFT-REG A[3:0] 4 A[4:1] SHIFTIN Output D MC15 D WS Q DI Registered Output DI D SRLC16 MC15 FF DI D SRLC16 MC15 FF D(BY) WSG CE (SR) CLK (optional) WE CK SLICE S2 SHIFTOUT SHIFTOUT DS031_05_110600 SHIFTIN Figure 27: Shift Register Configurations An additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary LUT output. (See Figure 28.) Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the MUXF5, MUXF6, and MUXF7 multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one CLB. DI D SRLC16 MC15 FF DI D SRLC16 MC15 FF SLICE S1 SHIFTOUT SHIFTIN DI D SRLC16 MC15 FF DI D SRLC16 MC15 FF SLICE S0 CLB OUT CASCADABLE OUT DS031_06_110200 Figure 28: Cascadable Shift Register 34 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Multiplexers Virtex-II Pro function generators and associated multiplexers can implement the following: 4:1 multiplexer in one slice 8:1 multiplexer in two slices 16:1 multiplexer in one CLB element (4 slices) 32:1 multiplexer in two CLB elements (8 slices) F8 * * * * Each Virtex-II Pro slice has one MUXF5 multiplexer and one MUXFX multiplexer. The MUXFX multiplexer implements the MUXF6, MUXF7, or MUXF8, as shown in Figure 29. Each CLB element has two MUXF6 multiplexers, one MUXF7 multiplexer and one MUXF8 multiplexer. Examples of multiplexers are shown in the Virtex-II Pro User Guide. Any LUT can implement a 2:1 multiplexer. G F5 Slice S3 MUXF8 combines the two MUXF7 outputs (Two CLBs) F6 F G F5 Slice S2 MUXF6 combines the two MUXF5 outputs from slices S2 and S3 F7 F F5 G Slice S1 MUXF7 combines the two MUXF6 outputs from slices S0 and S2 Slice S0 MUXF6 combines the two MUXF6 outputs from slices S0 and S1 F6 F F5 G F CLB DS031_08_110200 Figure 29: MUXF5 and MUXFX multiplexers Fast Lookahead Carry Logic Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-II Pro CLB has two separate carry chains, as shown in the Figure 30. DS083-2 (v1.0) January 31, 2002 Advance Product Specification The height of the carry chains is two bits per slice. The carry chain in the Virtex-II Pro device is running upward. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions. www.xilinx.com 1-800-255-7778 35 R Functional Description: FPGA COUT to S0 of the next CLB COUT to CIN of S2 of the next CLB O I MUXCY FF LUT (First Carry Chain) SLICE S3 O I MUXCY FF LUT CIN COUT O I MUXCY FF LUT SLICE S2 O I O I MUXCY MUXCY FF LUT FF LUT O I SLICE S1 MUXCY FF LUT CIN COUT O I (Second Carry Chain) MUXCY FF LUT O I SLICE S0 MUXCY FF LUT CIN CIN CLB DS031_07_110200 Figure 30: Fast Carry Logic Path Arithmetic Logic The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, 36 a dedicated AND (MULT_AND) gate (shown in Figure 22) improves the efficiency of multiplier implementation. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description implementing large, flexible SOP chains. One input of each ORCY is connected through the fast SOP chain to the output of the previous ORCY in the same slice row. The second input is connected to the output of the top MUXCY in the same slice, as shown in Figure 31. Sum of Products Each Virtex-II Pro slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain are designed for ORCY ORCY ORCY ORCY SOP 4 LUT MUXCY 4 LUT Slice 1 4 LUT MUXCY 4 LUT MUXCY LUT MUXCY MUXCY LUT Slice 3 4 LUT MUXCY 4 LUT MUXCY Slice 0 4 4 LUT VCC LUT MUXCY Slice 1 4 LUT MUXCY 4 LUT MUXCY Slice 2 4 MUXCY 4 Slice 3 4 LUT MUXCY 4 LUT MUXCY Slice 0 4 MUXCY LUT VCC MUXCY Slice 2 4 LUT MUXCY VCC VCC CLB CLB ds031_64_110300 Figure 31: Horizontal Cascade Chain LUTs and MUXCYs can implement large AND gates or other combinatorial logic functions. Figure 32 illustrates LUT and MUXCY resources configured as a 16-input AND gate. OUT 4 MUXCY 0 1 LUT "0" 4 Slice MUXCY LUT 0 1 "0" 16 4 AND OUT MUXCY 0 1 LUT "0" 4 Slice MUXCY LUT 0 1 VCC DS031_41_110600 Figure 32: Wide-Input AND Gate (16 Inputs) DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 37 R Functional Description: FPGA 3-State Buffers The 3-state buffer logic is implemented using AND-OR logic rather than 3-state drivers, so that timing is more predictable and less load dependant especially with larger devices. Introduction Each Virtex-II Pro CLB contains two 3-state drivers (TBUFs) that can drive on-chip buses. Each 3-state buffer has its own 3-state control pin and its own input pin. Each of the four slices have access to the two 3-state buffers through the switch matrix, as shown in Figure 33. TBUFs in neighboring CLBs can access slice outputs by direct connects. The outputs of the 3-state buffers drive horizontal routing resources used to implement 3-state buses. Locations / Organization Four horizontal routing resources per CLB are provided for on-chip 3-state buses. Each 3-state buffer has access alternately to two horizontal lines, which can be partitioned as shown in Figure 34. The switch matrices corresponding to SelectRAM memory and multiplier or I/O blocks are skipped. Number of 3-State Buffers Table 12 shows the number of 3-state buffers available in each Virtex-II Pro device. The number of 3-state buffers is twice the number of CLB elements. TBUF TBUF Slice S3 Switch Matrix Table 12: Virtex-II Pro 3-State Buffers 3-State Buffers per Row Total Number of 3-State Buffers XC2VP2 44 704 XC2VP4 44 1,760 XC2VP7 68 2,720 Slice S2 Device Slice S1 Slice S0 DS031_37_060700 XC2VP20 92 5,152 XC2VP50 140 12,320 Figure 33: Virtex-II Pro 3-State Buffers 3 - state lines Programmable connection Switch matrix CLB-II Switch matrix CLB-II DS031_09_032700 Figure 34: 3-State Buffer Connection to Horizontal Lines CLB/Slice Configurations Table 13 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be imple- mented in one of the configurations listed. Table 14 shows the available resources in all CLBs. Table 13: Logic Resources in One CLB 38 Slices LUTs Flip-Flops MULT_ANDs Arithmetic & Carry-Chains SOP Chains Distributed SelectRAM Shift Registers TBUF 4 8 8 8 2 2 128 bits 128 bits 2 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Table 14: Virtex-II Pro Logic Resources Available in All CLBs Number of LUTs Max Distributed SelectRAM or Shift Register (bits) Number of Flip-Flops Number of Carry Chains (1) Number of SOP Chains (1) 1,408 2,816 45,056 2,816 44 32 40 x 22 3,008 6,016 96,256 6,016 44 80 XC2VP7 40 x 34 4,928 9,856 157,696 9,856 68 80 XC2VP20 56 x 46 9,280 18,560 296,960 18,560 92 112 XC2VP50 88 x 70 22,592 45,184 722,944 45,184 140 176 CLB Array: Row x Column Number of Slices XC2VP2 16 x 22 XC2VP4 Device Notes: 1. The carry-chains and SOP chains can be split or cascaded. 18 Kb Block SelectRAM Resources Introduction Virtex-II Pro devices incorporate large amounts of 18 Kb block SelectRAM. These complement the distributed SelectRAM resources that provide shallow RAM structures implemented in CLBs. Each Virtex-II Pro block SelectRAM is an 18 Kb true dual-port RAM with two independently clocked and independently controlled synchronous ports that access a common storage area. Both ports are functionally identical. CLK, EN, WE, and SSR polarities are defined through configuration. Each port has the following types of inputs: Clock and Clock Enable, Write Enable, Set/Reset, and Address, as well as separate Data/parity data inputs (for write) and Data/parity data outputs (for read). 1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb memory locations in any of the 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations. The advantage of the 9-bit, 18-bit and 36-bit widths is the ability to store a parity bit for each eight bits. Parity bits must be generated or checked externally in user logic. In such cases, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored and behave exactly as the other bits, including the timing parameters. Video applications can use the 9-bit ratio of Virtex-II Pro block SelectRAM memory to advantage. Each block SelectRAM cell is a fully synchronous memory as illustrated in Figure 35. Input data bus and output data bus widths are identical. 18-Kbit Block SelectRAM DI DIP ADDR Operation is synchronous; the block SelectRAM behaves like a register. Control, address and data inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a configuration option) clock edge. Data outputs change as a result of the same clock edge. WE EN SSR CLK Configuration The Virtex-II Pro block SelectRAM supports various configurations, including single- and dual-port RAM and various data/address aspect ratios. Supported memory configurations for single- and dual-port modes are shown in Table 15. 2K x 9 bits 8K x 2 bits 1K x 18 bits 4K x 4 bits 512 x 36 bits DS031_10_102000 Figure 35: 18 Kb Block SelectRAM Memory in Single-Port Mode Dual-Port Configuration Table 15: Dual- and Single-Port Configurations 16K x 1 bit DO DOP As a dual-port RAM, each port of block SelectRAM has access to a common 18 Kb memory resource. These are fully synchronous ports with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. Table 16 illustrates the different configurations available on ports A and B. Single-Port Configuration As a single-port RAM, the block SelectRAM has access to the 18 Kb memory locations in any of the 2K x 9-bit, DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 39 R Functional Description: FPGA Table 16: Dual-Port Mode Configurations Port A 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 Port B 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Port A 8K x 2 8K x 2 8K x 2 8K x 2 8K x 2 Port B 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Port A 4K x 4 4K x 4 4K x 4 4K x 4 Port B 4K x 4 2K x 9 1K x 18 512 x 36 Port A 2K x 9 2K x 9 2K x 9 Port B 2K x 9 1K x 18 512 x 36 Port A 1K x 18 1K x 18 Port B 1K x 18 512 x 36 Port A 512 x 36 Port B 512 x 36 If both ports are configured in either 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations, the 18 Kb block is accessible from port A or B. If both ports are configured in either 16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit block is accessible from Port A or Port B. All other configurations result in one port having access to an 18 Kb memory block and the other port having access to a 16 K-bit subset of the memory block equal to 16 Kbs. 18-Kbit Block SelectRAM DIA DIPA ADDRA WEA ENA SSRA CLKA CLKB Width Depth Address Bus Data Bus Parity Bus 1 16,384 ADDR[13:0] DATA[0] N/A 2 8,192 ADDR[12:0] DATA[1:0] N/A 4 4,096 ADDR[11:0] DATA[3:0] N/A 9 2,048 ADDR[10:0] DATA[7:0] Parity[0] 18 1,024 ADDR[9:0] DATA[15:0] Parity[1:0] 36 512 ADDR[8:0] DATA[31:0] Parity[3:0] The Virtex-II Pro block SelectRAM read operation is fully synchronous. An address is presented, and the read operation is enabled by control signal ENA or ENB. Then, depending on clock polarity, a rising or falling clock edge causes the stored data to be loaded into output registers. DOB DOPB DS031_11_102000 Figure 36: 18 Kb Block SelectRAM in Dual-Port Mode Each block SelectRAM cell is a fully synchronous memory, as illustrated in Figure 36. The two ports have independent inputs and outputs and are independently clocked. Port Aspect Ratios Table 17 shows the depth and the width aspect ratios for the 18 Kb block SelectRAM. Virtex-II Pro block SelectRAM also 40 Table 17: 18 Kb Block SelectRAM Port Aspect Ratio Read/Write Operations DOA DOPA DIB DIPB ADDRB WEB ENB SSRB includes dedicated routing resources to provide an efficient interface with CLBs, block SelectRAM, and multipliers. The write operation is also fully synchronous. Data and address are presented, and the write operation is enabled by control signals WEA and WEB in addition to ENA or ENB. Then, again depending on the clock input mode, a rising or falling clock edge causes the data to be loaded into the memory cell addressed. A write operation performs a simultaneous read operation. Three different options are available, selected by configuration: 1. WRITE_FIRST The WRITE_FIRST option is a transparent mode. The same clock edge that writes the data input (DI) into the www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description memory also transfers DI into the output registers DO, as shown in Figure 37. Data_in DI Internal Memory NO_CHANGE, only a read operation loads a new value in the output register DO, as shown in Figure 39. Data_in DO DI Data_out = Data_in Internal Memory DO No change during write CLK CLK WE WE Data_in New Address aa RAM Contents Old Data_in New Address aa RAM Contents Old New New Data_out Last Read Cycle Content (no change) New Data_out DS083-2_12_050901 DS083-2_14_050901 Figure 39: NO_CHANGE Mode Figure 37: WRITE_FIRST Mode Control Pins and Attributes 2. READ_FIRST The READ_FIRST option is a read-before-write mode. The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell addressed into the data output registers DO, as shown in Figure 38. Data_in DI Internal Memory DO Virtex-II Pro SelectRAM memory has two independent ports with the control signals described in Table 18. All control inputs including the clock have an optional inversion. Table 18: Control Functions Control Signal Prior stored data CLK WE Data_in New Address aa RAM Contents Old Data_out Function CLK Read and Write Clock EN Enable affects Read, Write, Set, Reset WE Write Enable SSR Set DO register to SRVAL (attribute) Initial memory content is determined by the INIT_xx attributes. Separate attributes determine the output register value after device configuration (INIT) and SSR is asserted (SRVAL). Both attributes (INIT_B and SRVAL) are available for each port when a block SelectRAM resource is configured as dual-port RAM. New Old Total Amount of SelectRAM Memory DS083-2_13_050901 Virtex-II Pro SelectRAM memory blocks are organized in multiple columns. The number of blocks per column depends on the row size, the number of Processor Blocks, and the number of Rocket I/O transceivers. Figure 38: READ_FIRST Mode 3. NO_CHANGE The NO_CHANGE option maintains the content of the output registers, regardless of the write operation. The clock edge during the write mode has no effect on the content of the data output register DO. When the port is configured as DS083-2 (v1.0) January 31, 2002 Advance Product Specification Table 19 shows the number of columns as well as the total amount of block SelectRAM memory available for each Virtex-II Pro device. The 18 Kb SelectRAM blocks are cascadable to implement deeper or wider single- or dual-port memory resources. www.xilinx.com 1-800-255-7778 41 R Functional Description: FPGA Total SelectRAM Memory Device Columns Blocks in Kb in Bits XC2VP2 4 12 216 221,184 XC2VP4 4 28 504 516,096 XC2VP7 6 44 792 811,008 XC2VP20 8 88 1,584 1,622,016 XC2VP50 12 216 3,888 3,981,312 Each SelectRAM memory and multiplier block is tied to four switch matrices, as shown in Figure 41. Switch Matrix Switch Matrix 18-Kbit block SelectRAM Switch Matrix Figure 40 shows the layout of the block RAM columns in the XC2VP4 device. DCM Rocket I/O TM Serial Transceivers BRAM Multiplier Blocks 18 x 18 Multiplier Table 19: Virtex-II Pro SelectRAM Memory Available Switch Matrix DCM DS031_33_101000 CLBs CLBs Figure 41: SelectRAM and Multiplier Blocks Association With Block SelectRAM Memory CLBs DCM CLBs CLBs The interconnect is designed to allow SelectRAM memory and multiplier blocks to be used at the same time, but some interconnect is shared between the SelectRAM and the multiplier. Thus, SelectRAM memory can be used only up to 18 bits wide when the multiplier is used, because the multiplier shares inputs with the upper data bits of the SelectRAM memory. PPC405 CPU Rocket I/OTM Serial Transceivers DCM DS083-2_11_010802 Figure 40: XC2VP4 Block RAM Column Layout This sharing of the interconnect is optimized for an 18-bit-wide block SelectRAM resource feeding the multiplier. The use of SelectRAM memory and the multiplier with an accumulator in LUTs allows for implementation of a digital signal processor (DSP) multiplier-accumulator (MAC) function, which is commonly used in finite and infinite impulse response (FIR and IIR) digital filters. Configuration 18-Bit x 18-Bit Multipliers Introduction A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2's complement signed multiplier. Virtex-II Pro devices incorporate many embedded multiplier blocks. These multipliers can be associated with an 18 Kb block SelectRAM resource or can be used independently. They are optimized for high-speed operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices. The multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). Both A and B are 18-bit-wide inputs, and the output is 36 bits. Figure 42 shows a multiplier block. Multiplier Block A[17:0] MULT 18 x 18 P[35:0] B[17:0] DS031_40_100400 Figure 42: Multiplier Block 42 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Locations / Organization Multiplier organization is identical to the 18 Kb SelectRAM organization, because each multiplier is associated with an 18 Kb block SelectRAM resource. Table 20: Multiplier Resources Device Columns Total Multipliers XC2VP2 4 12 XC2VP4 4 28 XC2VP7 6 44 XC2VP20 8 88 XC2VP50 12 216 Each global clock multiplexer buffer can be driven either by the clock pad to distribute a clock directly to the device, or by the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM), page 45. Each global clock multiplexer buffer can also be driven by local interconnects. The DCM has clock output(s) that can be connected to global clock multiplexer buffer inputs, as shown in Figure 44. Clock Pad Clock Pad CLKIN DCM Local Interconnect CLKOUT In addition to the built-in multiplier blocks, the CLB elements have dedicated logic to implement efficient multipliers in logic. (Refer to Configurable Logic Blocks (CLBs), page 30). Clock Multiplexer I Global Clock Multiplexer Buffers Clock Buffer Virtex-II Pro devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads center on both the top edge and the bottom edge of the device, as illustrated in Figure 43. The global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in Virtex-II Pro devices. Like the clock pads, eight global clock multiplexer buffers are on the top edge of the device and eight are on the bottom edge. O Clock Distribution DS083-2_43_122001 Figure 44: Virtex-II Pro Clock Multiplexer Buffer Configuration Global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in CLBs and IOBs, and SelectRAM blocks. Eight global clocks can be used in each quadrant of the Virtex-II Pro device. Designers should consider the clock distribution detail of the device prior to pin-locking and floorplanning. (See the Virtex-II Pro User Guide.) 8 clock pads Virtex-II Pro Device 8 clock pads DS083-2_42_061401 Figure 43: Virtex-II Pro Clock Pads DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 43 R Functional Description: FPGA Figure 45 shows clock distribution in Virtex-II Pro devices. 8 BUFGMUX NE NW NW 8 BUFGMUX NE 8 8 8 max 16 Clocks 16 Clocks 8 SW 8 BUFGMUX SE 8 SE SW 8 BUFGMUX DS083-2_45_122001 Figure 45: Virtex-II Pro Clock Distribution In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB rows (eight up and eight down). To reduce power consumption, any unused clock branches remain static. Global clocks are driven by dedicated clock buffers (BUFG), which can also be used to gate the clock (BUFGCE) or to multiplex between two independent clock inputs (BUFGMUX). itives. The falling clock edge option uses the BUFGCE_1 and BUFGMUX_1 primitives. BUFGCE If the CE input is active (High) prior to the incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through the clock buffer. Any level change of CE during the incoming clock High time has no effect. BUFGCE The most common configuration option of this element is as a buffer. A BUFG function in this (global buffer) mode, is shown in Figure 46. I CE BUFG I DS031_62_101200 Figure 47: Virtex-II Pro BUFGCE Function O DS031_61_101200 Figure 46: Virtex-II Pro BUFG Function The Virtex-II Pro global clock buffer BUFG can also be configured as a clock enable/disable circuit (Figure 47), as well as a two-input clock multiplexer (Figure 48). A functional description of these two options is provided below. Each of them can be used in either of two modes, selected by configuration: rising clock edge or falling clock edge. This section describes the rising clock edge option. For the opposite option, falling clock edge, just change all "rising" references to "falling" and all "High" references to "Low", except for the description of the CE and S levels. The rising clock edge option uses the BUFGCE and BUFGMUX prim- 44 O If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High time has no effect. CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output. BUFGMUX BUFGMUX can switch between two unrelated, even asynchronous clocks. Basically, a Low on S selects the I0 input, a High on S selects the I1 input. Switching from one clock to the other is done in such a way that the output High and Low time is never shorter than the shortest High or Low time of www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description either input clock. As long as the presently selected clock is High, any level change of S has no effect . BUFGMUX I0 I1 Digital Clock Manager (DCM) The Virtex-II Pro DCM offers a wide range of powerful clock management features. * Clock De-skew: The DCM generates new system clocks (either internally or externally to the FPGA), which are phase-aligned to the input clock, thus eliminating clock distribution delays. * Frequency Synthesis: The DCM generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. * Phase Shifting: The DCM provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control. O S DS083-2_63_121701 Figure 48: Virtex-II Pro BUFGMUX Function If the presently selected clock is Low while S changes, or if it goes Low after S has changed, the output is kept Low until the other ("to-be-selected") clock has made a transition from High to Low. At that instant, the new clock starts driving the output. The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock; that is, prior to the rising edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output. All Virtex-II Pro devices have 16 global clock multiplexer buffers. The DCM utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. It also utilizes fully digital feedback systems, operating dynamically to compensate for temperature and voltage variations during operation. Up to four of the nine DCM clock outputs can drive inputs to global clock buffers or global clock multiplexer buffers simultaneously (see Figure 50). All DCM clock outputs can simultaneously drive general routing resources, including routes to output buffers. DCM Figure 49 shows a switchover from CLK0 to CLK1. CLKIN CLKFB Wait for Low S RST CLK0 DSSEN Switch CLK1 CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV PSINCDEC CLKFX PSEN CLKFX180 PSCLK LOCKED Out STATUS[7:0] DS083-2_46_121701 clock signal Figure 49: Clock Multiplexer Waveform Diagram PSDONE control signal * * * * * * The current clock is CLK0. S is activated High. If CLK0 is currently High, the multiplexer waits for CLK0 to go Low. Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to Low. When CLK1 transitions from High to Low, the output switches to CLK1. No glitches or short pulses can appear on the output. DS083-2 (v1.0) January 31, 2002 Advance Product Specification DS031_67_112900 Figure 50: Digital Clock Manager The DCM can be configured to delay the completion of the Virtex-II Pro configuration process until after the DCM has achieved lock. This guarantees that the chip does not begin operating until after the system clocks generated by the DCM have stabilized. The DCM has the following general control signals: * RST input pin: resets the entire DCM * LOCKED output pin: asserted High when all enabled DCM circuits have locked. * STATUS output pins (active High): shown in Table 21. www.xilinx.com 1-800-255-7778 45 R Functional Description: FPGA Table 21: DCM Status Pins Status Pin Function 0 Phase Shift Overflow 1 CLKIN Stopped 2 CLKFX Stopped 3 N/A 4 N/A 5 N/A 6 N/A 7 N/A All frequency synthesis outputs automatically have 50/50 duty cycles, with the exception of the CLKDV output when performing a non-integer divide in high-frequency mode. See Table 22 for more details. Note that CLK2X and CLK2X180 are not available in high-frequency mode. Table 22: CLKDV Duty Cycle for Non-integer Divides CLKDV_DIVIDE Duty Cycle 1.5 1/ 3 2.5 2/5 3.5 3/ 7 4.5 4/9 5.5 5 / 11 6.5 6 / 13 7.5 7 / 15 Clock De-skew The DCM de-skews the output clocks relative to the input clock by automatically adjusting a digital delay line. Additional delay is introduced so that clock edges arrive at internal registers and block RAMs simultaneously with the clock edges arriving at the input clock pad. Alternatively, external clocks, which are also de-skewed relative to the input clock, can be generated for board-level routing. All DCM output clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock. To achieve clock de-skew, the CLKFB input must be connected, and its source must be either CLK0 or CLK2X. Note that CLKFB must always be connected, unless only the CLKFX or CLKFX180 outputs are used and de-skew is not required. Frequency Synthesis The DCM provides flexible methods for generating new clock frequencies. Each method has a different operating frequency range and different AC characteristics. The CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output creates divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. The CLKFX and CLKFX180 outputs can be used to produce clocks at the following frequency: The DCM provides additional control over clock skew through either coarse or fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by 1/4 of the input clock period relative to each other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode. Fine-phase adjustment affects all nine DCM output clocks. When activated, the phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the input clock period. In variable mode, the PHASE_SHIFT value can also be dynamically incremented or decremented as determined by PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 51 illustrates the effects of fine-phase shifting. For more information on DCM features, see the Virtex-II Pro User Guide. Table 23 lists fine-phase shifting control pins, when used in variable mode. Table 23: Fine Phase Shifting Control Pins FREQ CLKFX = ( M D ) * FREQ CLKIN Control Pin where M and D are two integers. Specifications for M and D are provided under DCM Timing Parameters. By default, M = 4 and D = 1, which results in a clock output frequency four times faster than the clock input frequency (CLKIN). CLK2X180 is phase shifted 180 degrees relative to CLK2X. CLKFX180 is phase shifted 180 degrees relative to CLKFX. 46 Phase Shifting Direction Function PSINCDEC In Increment or decrement PSEN In Enable phase shift PSCLK In Clock for phase shift PSDONE www.xilinx.com 1-800-255-7778 Out Active when completed DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description CLKIN CLKOUT_PHASE_SHIFT CLKFB = NONE CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED (PS/256) x PERIODCLKIN (PS/256) x PERIODCLKIN (PS negative) (PS positive) CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB (PS/256) x PERIODCLKIN (PS/256) x PERIODCLKIN (PS positive) (PS negative) DS031_48_110300 Figure 51: Fine-Phase Shifting Effects Two separate components of the phase shift range must be understood: * * PHASE_SHIFT attribute range FINE_SHIFT_RANGE DCM timing parameter range The PHASE_SHIFT attribute is the numerator in the following equation: Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN The full range of this attribute is always -255 to +255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE component, which represents the total delay achievable by the phase shift delay line. Total delay is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be as specified under DCM Timing Parameters. thus dividing the total delay line range in half. In fixed mode, since the PHASE_SHIFT value never changes after configuration, the entire delay line is available for insertion into either the CLKIN or CLKFB path (to create either positive or negative skew). Taking both of these components into consideration, the following are some usage examples: * If PERIODCLKIN = 2 * FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 128, and in variable mode it is limited to 64. * If PERIODCLKIN = FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 255, and in variable mode it is limited to 128. * If PERIODCLKIN 0.5 * FINE_SHIFT_RANGE, then PHASE_SHIFT is limited to 255 in either mode. Absolute range (fixed mode) = FINE_SHIFT_RANGE Operating Modes Absolute range (variable mode) = FINE_SHIFT_RANGE/2 The frequency ranges of DCM input and output clocks depend on the operating mode specified, either low-frequency mode or high-frequency mode, according to Table 24. For actual values, see Virtex-II Pro Switching Characteristics (Module 3). The CLK2X, CLK2X180, The reason for the difference between fixed and variable modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the delay line, Table 24: DCM Frequency Ranges Low-Frequency Mode Output Clock High-Frequency Mode CLKIN Input CLK Output CLKIN Input CLK Output CLK0, CLK180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF CLK90, CLK270 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF NA NA CLK2X, CLK2X180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF NA NA CLKDV CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF CLKFX, CLKFX180 CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 47 R Functional Description: FPGA CLK90, and CLK270 outputs are not available in high-frequency mode. * High or low-frequency mode is selected by an attribute. * Routing DCM and MGT Locations/Organization Virtex-II Pro DCMs and serial transceivers (MGTs) are placed on the top and bottom of each block RAM and multiplier column in some combination, as shown in Table 25. The number of DCMs and Rocket I/O transceiver cores total to twice the number of columns in the device. Refer to Figure 40, page 42 for an illustration of this in the XC2VP4 device. Table 25: DCM Organization Device * * The long lines are bidirectional wires that distribute signals across the device. Vertical and horizontal long lines span the full height and width of the device. The hex lines route signals to every third or sixth block away in all four directions. Organized in a staggered pattern, hex lines can only be driven from one end. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). The double lines route signals to every first or second block away in all four directions. Organized in a staggered pattern, double lines can be driven only at their endpoints. Double-line signals can be accessed either at the endpoints or at the midpoint (one block from the source). The direct connect lines route signals to neighboring blocks: vertically, horizontally, and diagonally. The fast connect lines are the internal CLB local interconnections from LUT outputs to LUT inputs. Columns DCMs MGTs XC2VP2 4 4 4 XC2VP4 4 4 4 XC2VP7 6 4 8 XC2VP20 8 8 8 In addition to the global and local routing resources, dedicated signals are available. XC2VP50 12 8 16 * * Dedicated Routing Place-and-route software takes advantage of this regular array to deliver optimum system performance and fast compile times. The segmented routing resources are essential to guarantee IP cores portability and to efficiently handle an incremental design flow that is based on modular implementations. Total design time is reduced due to fewer and shorter design iterations. Hierarchical Routing Resources * * Most Virtex-II Pro signals are routed using the global routing resources, which are located in horizontal and vertical routing channels between each switch matrix. As shown in Figure 52, page 49, Virtex-II Pro has fully buffered programmable interconnections, with a number of resources counted between any two adjacent switch matrix rows or columns. Fanout has minimal impact on the performance of each net. 48 * * There are eight global clock nets per quadrant. (See Global Clock Multiplexer Buffers, page 43.) Horizontal routing resources are provided for on-chip 3-state buses. Four partitionable bus lines are provided per CLB row, permitting multiple buses within a row. (See 3-State Buffers, page 38.) Two dedicated carry-chain resources per slice column (two per CLB column) propagate carry-chain MUXCY output signals vertically to the adjacent slice. (See CLB/Slice Configurations, page 38.) One dedicated SOP chain per slice row (two per CLB row) propagate ORCY output logic signals horizontally to the adjacent slice. (See Sum of Products, page 37.) One dedicated shift-chain per CLB connects the output of LUTs in shift-register mode to the input of the next LUT in shift-register mode (vertically) inside the CLB. (See Shift Registers, page 33.) www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description * 24 Horizontal Long Lines 24 Vertical Long Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 40 Horizontal Double Lines 40 Vertical Double Lines 16 Direct Connections (total in all four directions) 8 Fast Connects DS031_60_110200 Figure 52: Hierarchical Routing Resources Configuration Virtex-II Pro devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as general purpose inputs and outputs once configuration is complete. Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M2, M1 and M0 are dedicated pins. An additional pin, HSWAP_EN is used in conjunction with the mode pins to select whether user I/O pins have pull-ups during configuration. By default, HSWAP_EN is tied High (internal pull-up) which shuts off the pull-ups on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. Other dedicated pins are CCLK (the configuration clock pin), DONE, PROG_B, and the boundary-scan pins: TDI, TDO, TMS, and TCK. Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or an input accepting an externally generated clock. The configuration pins and boundary scan pins are independent of the VCCO. The auxiliary power supply (VCCAUX) of 2.5V is used for these pins. See Virtex-II Pro Switching Characteristics (Module 3). A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is DS083-2 (v1.0) January 31, 2002 Advance Product Specification not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications which employ partial reconfiguration or reconfiguration on the fly. Virtex-II Pro supports the following five configuration modes: * * * * * Slave-Serial Mode Master-Serial Mode Slave SelectMAP Mode Master SelectMAP Mode Boundary-Scan (JTAG, IEEE 1532) Mode Refer to Table 26, page 50. A detailed description of configuration modes is provided in the Virtex-II Pro User Guide. Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of configuration data. The CCLK pin on the FPGA is an input in this mode. The serial bitstream must be setup at the DIN input pin a short time before each rising edge of the externally generated CCLK. Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been config- www.xilinx.com 1-800-255-7778 49 R Functional Description: FPGA ured, the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the rising edge of CCLK. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback using the persist option. Slave-serial mode is selected by applying [111] to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. Multiple Virtex-II Pro FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by deasserting the CS_B pin of each device in turn and writing the appropriate data. Master-Serial Mode In master-serial mode, the CCLK pin is an output pin. It is the Virtex-II Pro FPGA device that drives the configuration clock on the CCLK pin to a Xilinx Serial PROM which in turn feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. Master SelectMAP Mode This mode is a master version of the SelectMAP mode. The device is configured byte-wide on a CCLK supplied by the Virtex-II Pro FPGA device. Timing is similar to the Slave SerialMAP mode except that CCLK is supplied by the Virtex-II Pro FPGA. The interface is identical to slave serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Boundary-Scan (JTAG, IEEE 1532) Mode In boundary-scan mode, dedicated pins are used for configuring the Virtex-II Pro device. The configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP). Virtex-II Pro device configuration using Boundary scan is compliant with IEEE 1149.1-1993 standard and the new IEEE 1532 standard for In-System Configurable (ISC) devices. The IEEE 1532 standard is backward compliant with the IEEE 1149.1-1993 TAP and state machine. The IEEE Standard 1532 for In-System Configurable (ISC) devices is intended to be programmed, reprogrammed, or tested on the board via a physical and logical protocol. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. Slave SelectMAP Mode The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the Virtex-II Pro FPGA device with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, an active Low Chip Select (CS_B) signal and a Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If RDWR_B is asserted, configuration data is read out of the FPGA as part of a readback operation. Table 26: Virtex-II Pro Configuration Mode Pin Settings M2 M1 M0 CCLK Direction Data Width Serial DOUT (2) Master Serial 0 0 0 Out 1 Yes Slave Serial 1 1 1 In 1 Yes Master SelectMAP 0 1 1 Out 8 No Slave SelectMAP 1 1 0 In 8 No Boundary Scan 1 0 1 N/A 1 No Configuration Mode (1) Notes: 1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pullups are used. 2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT support daisy chaining of downstream devices. 50 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Functional Description Table 27 lists the total number of bits required to configure each device. Table 27: Virtex-II Pro Bitstream Lengths Device Number of Configuration Bits XC2VP2 1,305,440 XC2VP4 3,006,560 XC2VP7 4,485,472 XC2VP20 8,214,624 XC2VP50 19,021,408 Readback In this mode, configuration data from the Virtex-II Pro FPGA device can be read back. Readback is supported only in the SelectMAP (master and slave) and Boundary Scan mode. Configuration Sequence The configuration of Virtex-II Pro devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user. The INIT_B pin can be held Low using an open-drain driver. An open-drain is required since INIT_B is a bidirectional open-drain pin that is held Low by a Virtex-II Pro FPGA device while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded. The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is signaled by the INIT_B pin going High, and the completion of the entire process is signaled by the DONE pin going High. The Global Set/Reset (GSR) signal is pulsed after the last frame of configuration data is written but before the start-up sequence. The GSR signal resets all flip-flops on the device. The default start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Write Enable (GWE) signal is released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. DS083-2 (v1.0) January 31, 2002 Advance Product Specification The relative timing of these events can be changed via configuration options in software. In addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start synchronously. The sequence can also be paused at any stage, until lock has been achieved on any or all DCMs, as well as DCI. Along with the configuration data, it is possible to read back the contents of all registers, distributed SelectRAM, and block RAM resources. This capability is used for real-time debugging. For more detailed configuration information, see the Virtex-II Pro User Guide. Bitstream Encryption Virtex-II Pro devices have an on-chip decryptor using one or two sets of three keys for triple-key Data Encryption Standard (DES) operation. Xilinx software tools offer an optional encryption of the configuration data (bitstream) with a triple-key DES determined by the designer. The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin, when the device is not powered. Virtex-II Pro devices can be configured with the corresponding encrypted bitstream, using any of the configuration modes described previously. A detailed description of how to use bitstream encryption is provided in the Virtex-II Pro User Guide. Your local FAE can also provide specific information on this feature. Partial Reconfiguration Partial reconfiguration of Virtex-II Pro devices can be accomplished in either Slave SelectMAP mode or Boundary-Scan mode. Instead of resetting the chip and doing a full configuration, new data is loaded into a specified area of the chip, while the rest of the chip remains in operation. Data is loaded on a column basis, with the smallest load unit being a configuration "frame" of the bitstream (device size dependent). Partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, or that require the ability to change portions of a design without having to reset or reconfigure the entire chip. www.xilinx.com 1-800-255-7778 51 R Revision History Revision History This section records the change history for this module of the data sheet. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II ProTM Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II Pro Platform FPGAs: Functional Description (Module 2) * Virtex-II ProTM Platform FPGAs: Pinout Information (Module 4) 52 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification 6 0 Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics R DS083-3 (v1.0) January 31, 2002 0 0 Advance Product Specification Virtex-II Pro Electrical Characteristics Virtex-II Pro devices are provided in -8, -7, and -6 speed grades, with -8 having the highest performance. commercial device). However, only selected speed grades and/or devices might be available in the industrial range. Virtex-II Pro DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -6 speed grade industrial device are the same as for a -6 speed grade All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Contact Xilinx for design considerations requiring more detailed information. All specifications are subject to change without notice. Virtex-II Pro DC Characteristics Table 1: Absolute Maximum Ratings Symbol Description Units VCCINT Internal supply voltage relative to GND -0.5 to 1.65 V VCCAUX Auxiliary supply voltage relative to GND -0.5 to 3.45 V VCCO Output drivers supply voltage relative to GND -0.5 to 3.45 V VBATT Key memory battery backup supply -0.5 to 3.45 V VREF Input reference voltage -0.5 to 3.45 V VIN Input voltage relative to GND (user and dedicated I/Os) -0.5 (2) to 3.45 (4) V VTS Voltage applied to 3-state output (user and dedicated I/Os) -0.5 (3) to 3.45 (5) V VCCAUXRX Auxilliary supply voltage relative to analog ground, GNDA (Rocket I/O pins) -0.5 to 3.45 V VCCAUXTX Auxilliary supply voltage relative to analog ground, GNDA (Rocket I/O pins) -0.5 to 3.45 V VTTX Terminal transmit supply voltage relative to GND (Rocket I/O pins) -0.5 to 3.45 V VTRX Terminal receive supply voltage relative to GND (Rocket I/O pins) -0.5 to 3.45 V TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature +220 C TJ Operating junction temperature +125 C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For 3.3V I/O standards only, I/O input pin voltage, including negative undershoot, must not fall below 0.0V, either on a continuous or transient basis (i.e., no negative undershoot is allowed). See Table 6, page 56. 3. For 3.3V I/O standards only, I/O output pin voltage while in 3-state mode must not fall below 0.0V, either on a continuous or transient basis. See Table 6, page 56. 4. I/O input pin voltage, including overshoot, must not exceed 3.45V, either on a continuous or transient basis. 5. I/O output pin voltage while in 3-state mode must not exceed 3.45V, either on a continuous or transient basis. (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 53 R Virtex-II Pro Electrical Characteristics Table 2: Recommended Operating Conditions Symbol VCCINT VCCAUX(1) VCCO(2) VBATT(3) VCCAUXRX, VCCAUXTX VTTX, VTRX Description Min Max Units Commercial 1.425 1.575 V Industrial 1.425 1.575 V Commercial 2.375 2.625 V Industrial 2.375 2.625 V Commercial 1.2 3.45 (4) V Industrial 1.2 3.45 (4) V Commercial 1.0 2.63 V Industrial 1.0 2.63 V Auxilliary supply voltage relative to GNDA Commercial 2.375 2.625 V Auxilliary supply voltage relative to GNDA Industrial 2.375 2.625 V Terminal supply voltage relative to GND Commercial 1.8 2.625 V Terminal supply voltage relative to GND Industrial 1.8 2.625 V Internal supply voltage relative to GND, TJ = 0 C to +85C Internal supply voltage relative to GND, TJ = -40C to +100C Auxiliary supply voltage relative to GND, TJ = 0 C to +85C Auxiliary supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Battery voltage relative to GND, TJ = 0 C to +85C Battery voltage relative to GND, TJ = -40C to +100C Notes: 1. For LVDS operation, VCCAUX min is 2.37V and max is 2.63V. 2. Configuration data is retained even if VCCO drops to 0V. 3. If battery is not used, do not connect VBATT. 4. For 3.3V operation, see Table 4 in Module 4 for banking information. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Device Min 1.2 Typ Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) All VDRI Data retention VCCAUX voltage (below which configuration data might be lost) All V IREF VREF current per bank All A Input or output leakage current per pin All A CIN Input capacitance (sample tested) All pF IRPU Pad pull-up (when selected) @ Vin = 0V, VCCO = 3.3V (sample tested) All Note (1) mA IRPD Pad pull-down (when selected) @ Vin = 3.6V (sample tested) All Note (1) mA IL V I CCAUXTX Operating VCCAUXTX supply current 60 mA I CCAUXRX Operating VCCAUXRX supply current 35 mA Operating ITTX supply current when transmitter is AC coupled 30 mA Operating ITTX supply current when transmitter is DC coupled 15 mA Operating ITRX supply current when receiver is AC coupled TBD mA Operating ITRX supply current when receiver is DC coupled 15 mA ITTX ITRX 54 Description www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions (Continued) Symbol PCPU PRXTX Description Device Min Typ Max Units mW / MHz Power dissipation of PowerPC (R) 405 processor block Power dissipation of Rocket I/O @ 3.125 Gb/s per channel 350 mW Power dissipation of Rocket I/O @ 2.5 Gb/s per channel 310 mW Power dissipation of Rocket I/O @ 1.25 Gb/s per channel 230 mW Notes: 1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. Table 4: Quiescent Supply Current Symbol ICCINTQ ICCOQ ICCAUXQ Description Device Quiescent VCCINT supply current Quiescent VCCO supply current Quiescent VCCAUX supply current Min Typ Max Units XC2VP2 mA XC2VP4 mA XC2VP7 mA XC2VP20 mA XC2VP50 mA XC2VP2 mA XC2VP4 mA XC2VP7 mA XC2VP20 mA XC2VP50 mA XC2VP2 mA XC2VP4 mA XC2VP7 mA XC2VP20 mA XC2VP50 mA Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 2. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWERTM. Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. The VCCINT, VCCAUX , and VCCO power supplies must ramp on no faster than 100 s and no slower than 50 ms. Ramp on is defined as: 0 VDC to minimum supply voltages (see Table 2, page 54). VCCAUX and VCCO for bank 4 must be connected together (2.5 VDC) to meet the following specification. DS083-3 (v1.0) January 31, 2002 Advance Product Specification Table 5, page 56, shows the minimum current required by Virtex-II Pro devices for proper power on and configuration. Power supplies can be turned on in any sequence, as long as VCCAUX and VCCO are connected together for bank 4. If any VCCO bank powers up before VCCAUX , then each bank draws up to 600 mA, worst case, until the VCCAUX powers on. This does not harm the device. (Note that the 600 mA is peak transient current, which eventually dissipates even if VCCAUX does not power on.) www.xilinx.com 1-800-255-7778 55 R Virtex-II Pro Electrical Characteristics If the currents minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. Once initialized and configured, use the power calculator to estimate current drain on these supplies. Table 5: Power-On Current for Virtex-II Pro Devices Device Symbol XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP50 Units ICCINTMIN 250 250 250 250 500 mA ICCAUXMIN 250 250 250 250 250 mA ICCOMIN 10 10 10 10 10 mA SelectI/O DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are cho- sen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 6: DC Input and Output Levels VIH VOL VOH IOL IOH V, max V, Max V, Min mA mA 2.0 VCCO 0.4 2.4 24 -24 0.8 2.0 VCCO 0.4 VCCO - 0.4 24 -24 -0.5 0.7 1.7 VCCO + 0.4 0.4 VCCO - 0.4 24 -24 LVCMOS18 -0.5 20% VCCO 70% VCCO VCCO + 0.4 0.4 VCCO - 0.45 16 -16 LVCMOS15 -0.5 20% VCCO 70% VCCO VCCO + 0.4 0.4 VCCO - 0.45 16 -16 PCI33_3 (2) 0.0 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO PCI66_3 (2) 0.0 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO GTLP -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.6 n/a 36 n/a GTL -0.5 VREF - 0.05 VREF + 0.05 VCCO + 0.4 0.4 n/a 40 n/a HSTL I -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 8(3) -8(3) HSTL II -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 16(3) -16(3) HSTL III -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 24(3) -8(3) HSTL IV -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 48(3) -8(3) SSTL3 I 0.0 VREF - 0.2 VREF + 0.2 VCCO VREF - 0.6 VREF + 0.6 8 -8 SSTL3 II 0.0 VREF - 0.2 VREF + 0.2 VCCO VREF - 0.8 VREF + 0.8 16 -16 SSTL2 I -0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.4 VREF - 0.61 VREF + 0.65 7.6 -7.6 SSTL2 II -0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.4 VREF - 0.80 VREF + 0.80 15.2 -15.2 VIL Input/Output Standard V, min V, max V, min LVTTL(1) 0.0 0.8 LVCMOS33 0.0 LVCMOS25 Notes: 1. VOL and VOH for lower drive currents are sample tested. The DONE pin is always CMOS 2.5 12 mA. 2. For optimum performance, it is recommended that PCI be used in conjunction with LVDCI_33. Contact Xilinx for more details. 3. This applies to 1.5V and 1.8V HSTL. 56 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics LDT DC Specifications (LDT_25) Table 7: LDT DC Specifications DC Parameter Supply Voltage Symbol Conditions VCCO Differential Output Voltage VOD Change in VOD Magnitude VOD Output Common Mode Voltage VOCM RT = 100 ohm across Q and Q signals Min Typ Max Units 2.38 2.5 2.63 V 500 600 700 mV 15 mV 640 mV 15 mV 1000 mV 15 mV 700 mV 15 mV -15 RT = 100 ohm across Q and Q signals 560 VOCM -15 Input Differential Voltage VID 200 Change in VID Magnitude VID -15 Input Common Mode Voltage VICM 500 VICM -15 Change in VOS Magnitude Change in VICM Magnitude 600 600 600 LVDS DC Specifications (LVDS_25) Table 8: LVDS DC Specifications DC Parameter Supply Voltage Symbol Conditions VCCO Min Typ Max Units 2.38 2.5 2.63 V 1.475 V Output High Voltage for Q and Q VOH RT = 100 across Q and Q signals Output Low Voltage for Q and Q VOL RT = 100 across Q and Q signals 0.925 Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High VODIFF RT = 100 across Q and Q signals 250 350 400 mV Output Common-Mode Voltage VOCM RT = 100 across Q and Q signals 1.125 1.2 1.275 V Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High VIDIFF Common-mode input voltage = 1.25V 100 350 600 mV Input Common-Mode Voltage VICM Differential input voltage = 350 mV 0.3 1.2 2.2 V Min Typ Max Units 2.38 2.5 2.63 V 1.70 V V Extended LVDS DC Specifications (LVDSEXT_25) Table 9: Extended LVDS DC Specifications DC Parameter Supply Voltage Symbol Conditions VCCO Output High Voltage for Q and Q VOH RT = 100 across Q and Q signals Output Low Voltage for Q and Q VOL RT = 100 across Q and Q signals 0.705 Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High VODIFF RT = 100 across Q and Q signals 440 Output Common-Mode Voltage VOCM RT = 100 across Q and Q signals 1.125 Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High VIDIFF Common-mode input voltage = 1.25V 100 Input Common-Mode Voltage VICM Differential input voltage = 350 mV 0.3 DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 V 1.200 1.2 820 mV 1.275 V 1000 mV 2.2 V 57 R Virtex-II Pro Electrical Characteristics Rocket I/O DC Input and Output Levels Table 10: Rocket I/O DC Specifications DC Parameter Peak-to-Peak Differential Input Voltage Peak-to-Peak Differential Output Voltage (1,2) Symbol Conditions DVIN DVOUT Min Typ Max Units 175 mV 800 mV 1000 mV 1200 mV 1400 mV 1600 mV Notes: 1. Output swing levels are selectable using TX_DIFF_CTRL attribute. Refer to the Rocket I/O User Guide or Chapter 2 in the Virtex-II Pro Platform FPGA Handbook for details. 2. Output preemphasis levels are selectable at 10% (default), 20%, 25%, and 33% using the TX_PREEMPHASIS attribute. Refer to the Rocket I/O User Guide or Chapter 2 in the Virtex-II Pro Platform FPGA Handbook for details. 58 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-II Pro devices. The numbers reported here are fully characterized worst-case values. Note that these values are subject to the same guidelines as Virtex-II Pro Switching Characteristics, page 61 (speed files). Table 11 provides pin-to-pin values (in nanoseconds) including IOB delays; that is, delay through the device from input pin to output pin. In the case of multiple inputs and outputs, the worst delay is reported. Table 11: Pin-to-Pin Performance Description Pin-to-Pin (w/ I/O delays) Device Used & Speed Grade Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Combinatorial (pad to LUT to pad) Memory: Block RAM Pad to setup Clock to Pad Distributed RAM Pad to setup Clock to Pad Table 12 shows internal (register-to-register) performance. Values are reported in MHz. Table 12: Register-to-Register Performance Description Register-to-Register Performance Device Used & Speed Grade Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register to LUT to Register 8-bit Adder 16-bit Adder DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 59 R Virtex-II Pro Performance Characteristics Table 12: Register-to-Register Performance (Continued) Description Register-to-Register Performance Device Used & Speed Grade 64-bit Adder 64-bit Counter 64-bit Accumulator Multiplier 18x18 (with Block RAM inputs) Multiplier 18x18 (with Register inputs) Memory: Block RAM Single-Port 4096 x 4 bits Single-Port 2048 x 9 bits Single-Port 1024 x 18 bits Single-Port 512 x 36 bits Dual-Port A:4096 x 4 bits & B:1024 x 18 bits Dual-Port A:1024 x 18 bits & B:1024 x 18 bits Dual-Port A:2048 x 9 bits & B: 512 x 36 bits Distributed RAM Single-Port 32 x 8-bit Single-Port 64 x 8-bit Single-Port 128 x 8-bit Dual-Port 16 x 8 Dual-Port 32 x 8 Dual-Port 64 x 8 Dual-Port 128 x 8 Shift Registers 128-bit SRL 256-bit SRL FIFOs (Async. in Block RAM) 1024 x 18-bit 1024 x 18-bit FIFOs (Sync. in SRL) 128 x 8-bit 128 x 16-bit CAMs in Block RAM 32 x 9-bit 64 x 9-bit 128 x 9-bit 256 x 9-bit 60 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 12: Register-to-Register Performance (Continued) Description Register-to-Register Performance Device Used & Speed Grade CAMs in SRL 32 x 16-bit 64 x 32-bit 128 x 40-bit 256 x 48-bit 1024 x 16-bit 1024 x 72-bit Virtex-II Pro Switching Characteristics Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Note that Virtex-II Pro Performance Characteristics, page 59 are subject to these guidelines, as well. Each designation is defined as follows: Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each DS083-3 (v1.0) January 31, 2002 Advance Product Specification device. Table 13 correlates the current status of each Virtex-II Pro device with a corresponding speed file designation. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Table 13: Virtex-II Pro Device Speed Grade Designations Speed Grade Designations Device Advance XC2VP2 -8, -7, -6 XC2VP4 -8, -7, -6 XC2VP7 -8, -7, -6 XC2VP20 -8, -7, -6 XC2VP50 -8, -7, -6 Preliminary Production Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-II Pro devices. www.xilinx.com 1-800-255-7778 61 R Virtex-II Pro Switching Characteristics PowerPC Switching Characteristics Table 14: Processor Clocks Absolute AC Characteristics Speed Grade -8 Description Min -7 Max Min -6 Max Min Max Units CPMC405CLOCK frequency MHz JTAGC405TCK frequency (1) MHz Notes: 1. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is dependent on the system, and will be much less Table 15: Processor Block Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (CPMC405CLOCK) Device Control Register Bus control inputs TPCCK_DCR/TPCKC_DCR ns, min Device Control Register Bus data inputs TPDCK_DCR/TPCKD_DCR ns, min Clock and Power Management control inputs TPCCK_CPM/TPCKC_CPM ns, min Reset control inputs TPCCK_RST/TPCKC_RST ns, min Debug control inputs TPCCK_DBG/TPCKC_DBG ns, min Trace control inputs TPCCK_TRC/TPCKC_TRC ns, min TPCCK_EIC/TPCKC_EIC ns, min Device Control Register Bus control outputs TPCKCO_DCR ns, max Device Control Register Bus address outputs TPCKAO_DCR ns, max Device Control Register Bus data outputs TPCKDO_DCR ns, max Clock and Power Management control outputs TPCKCO_CPM ns, max Reset control outputs TPCKCO_RST ns, max Debug control outputs TPCKCO_DBG ns, max Trace control outputs TPCKCO_TRC ns, max External Interrupt Controller control inputs Clock to Out 62 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 15: Processor Block Switching Characteristics (Continued) Speed Grade Description Symbol -8 -7 -6 Units CPMC405CLOCK minimum pulse width, high TCPWH ns, min CPMC405CLOCK minimum pulse width, low TCPWL ns, min Clock Table 16: Processor Block PLB Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (PLBCLK) Processor Local Bus(ICU/DCU) control inputs TPCCK_PLB/TPCKC_PLB ns, min Processor Local Bus (ICU/DCU) data inputs TPDCK_PLB/TPCKD_PLB ns, min Processor Local Bus(ICU/DCU) control outputs TPCKCO_PLB ns, max Processor Local Bus(ICU/DCU) address bus outputs TPCKAO_PLB ns, max Processor Local Bus(ICU/DCU) data bus outputs TPCKDO_PLB ns, max PLBCLK minimum pulse width, high TPPWH ns, min PLBCLK minimum pulse width, low TPPWL ns, min Clock to Out Clock Table 17: Processor Block JTAG Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (JTAGC405TCK) JTAG control inputs JTAG reset input TPCCK_JTAG/TPCKC_JTAG ns, min TPCCK_JTAGRST/ TPCKC_JTAGRST ns, min TPCKCO_JTAG ns, max Clock to Out JTAG control outputs DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 63 R Virtex-II Pro Switching Characteristics Table 17: Processor Block JTAG Switching Characteristics (Continued) Speed Grade Description Symbol -8 -7 -6 Units Clock JTAGC405TCK minimum pulse width, high TJPWH ns, min JTAGC405TCK minimum pulse width, low TJPWL ns, min Table 18: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (BRAMDSOCMCLK) Data-Side On-Chip Memory data bus inputs TPDCK_DSOCM/TPCKD_DSOCM ns, min Data-Side On-Chip Memory control outputs TPCKCO_DSOCM ns, max Data-Side On-Chip Memory address bus outputs TPCKAO_DSOCM ns, max Data-Side On-Chip Memory data bus outputs TPCKDO_DSOCM ns, max BRAMDSOCMCLK minimum pulse width, high TDPWH ns, min BRAMDSOCMCLK minimum pulse width, low TDPWL ns, min Clock to Out Clock Table 19: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (BRAMISOCMCLK) Instruction-Side On-Chip Memory data bus inputs TPDCK_ISOCM/TPCKD_ISOCM ns, min Instruction-Side On-Chip Memory control outputs TPCKCO_ISOCM ns, max Instruction-Side On-Chip Memory address bus outputs TPCKAO_ISOCM ns, max Instruction-Side On-Chip Memory data bus outputs TPCKDO_ISOCM ns, max Clock to Out 64 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 19: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics (Continued) Speed Grade Description Symbol -8 -7 -6 Units BRAMISOCMCLK minimum pulse width, high TIPWH ns, min BRAMISOCMCLK minimum pulse width, low TIPWL ns, min Clock Rocket I/O Switching Characteristics Table 20: Rocket I/O Reference Clock Switching Characteristics All Speed Grades Description Symbol Conditions Min Typ Max Units 40 Note(1) 156.25 MHz 100 ppm REFCLK frequency range (1) FGCLK REFCLK frequency tolerance FGTOL REFCLK rise time TRCLK 20% - 80% ns REFCLK fall time TFCLK 20% - 80% ns REFCLK duty cycle TDCREF REFCLK total jitter TGJTT Clock recovery frequency acquisition time TLOCK 10 s Clock recovery phase acquisition time TPHASE 960 bits Bit error rate 45 50 peak-to-peak 55 % 40 ps 10 -12 BER Notes: 1. REFCLK frequency is typically 1/20 of serial data rate. TRCLK 80% REFCLK 20% TFCLK DS083-3_01_101801 Figure 1: Reference Clock (REFCLK) Timing Parameters DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 65 R Virtex-II Pro Switching Characteristics Table 21: Rocket I/O Receiver Switching Characteristics Description Symbol Conditions Min Typ Max Units Receive total jitter tolerance TJTOL 0.65 UI (1) Receive deterministic jitter tolerance TDJTOL 0.41 UI Receive latency (2) TRXLAT 25 42 RXUSR CLK cycles RXUSRCLK duty cycle TRXDC 45 50 55 % RXUSRCLK2 duty cycle TRX2DC 45 50 55 % Bit error rate 10 -12 BER Notes: 1. UI = Unit Interval 2. Receive latency delay from RXP/RXN to RXDATA DATA ORIGINATES . . . . . 1 2 20 21 22 . . . . . 820 821 822 . . . . . 840 841 842 . . . . RXP/RXN TRXLAT DATA ARRIVES RXDATA[16:0] 0 1 41 42 RXUSRCLK2 DS083-3_02_082301 Figure 2: Receive Latency (Maximum) 66 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 22: Rocket I/O Transmitter Switching Characteristics Description Symbol Serial data rate, full-speed clock FGTX Serial data rate, half-speed clock Conditions Min Flipchip packages Typ Max Units 0.800 3.125 Gb/s Wirebond packages 0.800 2.5 Gb/s Flipchip packages 0.600 1.0 Gb/s Wirebond packages 0.600 1.0 Gb/s Serial data output deterministic jitter TDJ 0.18 UI (1) Serial data output random jitter TRJ 0.17 UI TX rise time TRTX TX fall time TFTX Transmit latency (2) TTXLAT TXUSRCLK duty cycle TTXDC TXUSRCLK2 duty cycle TTX2DC 20% - 80% 120 ps 120 ps Including CRC 14 17 Excluding CRC 8 11 TXUSR CLK cycles 45 50 55 % 45 50 55 % Notes: 1. UI = Unit Interval 2. Transmit latency delay from TXDATA to TXP/TXN 1 2 . . . . . 20 21 22 . . . . . 320 321 322 . . . . . 340 341 342 . . . . TXP/TXN TTXLAT DATA ARRIVES DATA ORIGINATES TXDATA[16:0] 0 1 16 17 TXUSRCLK2 DS083-3_03_082301 Figure 3: Transmit Latency (Maximum, Including CRC) DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 67 R Virtex-II Pro Switching Characteristics Table 23: Rocket I/O RXUSRCLK Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (RXUSRCLK) CHBONDI control inputs TGCCK_CHBI/TGCKC_CHBI ns, min TGCKCO_CHBO ns, max RXUSRCLK minimum pulse width, High TGPWH_RX ns, min RXUSRCLK minimum pulse width, Low TGPWL_RX ns, min Clock to Out CHBONDO control outputs Clock Table 24: Rocket I/O RXUSRCLK2 Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (RXUSRCLK2) RXRESET control input TGCCK_RRST/TGCKC_RRST ns, min RXPOLARITY control input TGCCK_RPOL/TGCKC_RPOL ns, min ENCHANSYNC control input TGCCK_ECSY/TGCKC_ECSY ns, min TGCKST_RNIT ns, max RXDISPERR status outputs TGCKST_RDERR ns, max RXCHARISCOMMA status outputs TGCKST_RCMCH ns, max RXREALIGN status output TGCKST_ALIGN ns, max RXCOMMADET status output TGCKST_CMDT ns, max RXLOSSOFSYNC status outputs TGCKST_RLOS ns, max RXCLKCORCNT status outputs TGCKST_RCCCNT ns, max RXBUFSTATUS status outputs TGCKST_RBSTA ns, max RXCHECKINGCRC status output TGCKST_RCCRC ns, max RXCRCERR status output TGCKST_RCRCE ns, max CHBONDDONE status output TGCKST_CHBD ns, max RXCHARISK status outputs TGCKST_RKCH ns, max RXRUNDISP status outputs TGCKST_RRDIS ns, max RXDATA data outputs TGCKDO_RDAT ns, max RXUSRCLK2 minimum pulse width, High TGPWH_RX2 ns, min RXUSRCLK2 minimum pulse width, Low TGPWL_RX2 ns, min Clock to Out RXNOTINTABLE status outputs Clock 68 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 25: Rocket I/O TXUSRCLK Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (TXUSRCLK2) CONFIGENABLE control input TGCCK_CFGEN/TGCKC_CFGEN ns, min TXBYPASS8B10B control inputs TGCCK_TBYP/TGCKC_TBYP ns, min TXFORCECRCERR control input TGCCK_TCRCE/TGCKC_TCRCE ns, min TXPOLARITY control input TGCCK_TPOL/TGCKC_TPOL ns, min TXINHIBIT control inputs TGCCK_TINH/TGCKC_TINH ns, min TGCCK_LBK/TGCKC_LBK ns, min TXRESET control input TGCCK_TRST/TGCKC_TRST ns, min TXCHARISK control inputs TGCCK_TKCH/TGCKC_TKCH ns, min TXCHARDISPMODE control inputs TGCCK_TCDM/TGCKC_TCDM ns, min TXCHARDISPVAL control inputs TGCCK_TCDV/TGCKC_TCDV ns, min TGDCK_CFGIN/TGCKD_CFGIN ns, min TGDCK_TDAT/TGCKD_TDAT ns, min TXBUFERR status output TGCKST_TBERR ns, max TXKERR status outputs TGCKST_TKERR ns, max TXRUNDISP status outputs TGCKST_TRDIS ns, max TGCKDO_CFGOUT ns, max TXUSRCLK minimum pulse width, High TGPWH_TX ns, min TXUSRCLK minimum pulse width, Low TGPWL_TX ns, min TXUSRCLK2 minimum pulse width, High TGPWH_TX2 ns, min TXUSRCLK2 minimum pulse width, Low TGPWL_TX2 ns, min LOOPBACK control inputs CONFIGIN data input TXDATA data inputs Clock to Out CONFIGOUT data output Clock DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 69 R Virtex-II Pro Switching Characteristics IOB Input Switching Characteristics Input delays associated with the pad are specified for LVCMOS 2.5V levels. For other standards, adjust the delays with the values shown in IOB Input Switching Characteristics Standard Adjustments, page 71. Table 26: IOB Input Switching Characteristics Speed Grade Description Symbol Device -8 Pad to I output, no delay TIOPI All ns, max Pad to I output, with delay TIOPID XC2VP2 ns, max XC2VP4 ns, max XC2VP7 ns, max XC2VP20 ns, max XC2VP50 ns, max TIOPLI All ns, max TIOPLID XC2VP2 ns, max XC2VP4 ns, max XC2VP7 ns, max XC2VP20 ns, max XC2VP50 ns, max TIOCKIQ All ns, max TIOPICK/TIOICKP All ns, min TIOPICKD/TIOICKPD XC2VP2 ns, max XC2VP4 ns, max XC2VP7 ns, max XC2VP20 ns, max XC2VP50 ns, max TIOICECK/TIOCKICE All ns, min TIOSRCKI All ns, min SR input to IQ (asynchronous) TIOSRIQ All ns, max GSR to output IQ TGSRQ All ns, max -7 -6 Units Propagation Delays Propagation Delays Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay Clock CLK to output IQ Setup and Hold Times With Respect to Clock at IOB Input Register Pad, no delay Pad, with delay ICE input SR input (IFF, synchronous) Set/Reset Delays Notes: 1. Input timing for LVCMOS25 is measured at 1.25V. For other I/O standards, see Table 30. 70 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics IOB Input Switching Characteristics Standard Adjustments Table 27: IOB Input Switching Characteristics Standard Adjustments Speed Grade Description Symbol Standard -8 TILVTTL LVTTL ns TILVCMOS33 LVCMOS33 ns TILVCMOS25 LVCMOS25 ns TILVCMOS18 LVCMOS18 ns TILVCMOS15 LVCMOS15 ns TILVDS_25 LVDS_25 ns TILVDS_25_EXT LVDS_25_EXT ns TIPCI33_3 PCI, 33 MHz, 3.3V ns TIPCI66_3 PCI, 66 MHz, 3.3V ns TIGTL GTL ns TIGTLPLUS GTLP ns TIHSTL_I HSTL I ns TIHSTL_II HSTL II ns TIHSTL_III HSTL III ns TIHSTL_IV HSTL IV ns TIHSTL_I_18 HSTL_I_18 ns TIHSTL_II_18 HSTL_II_18 ns TIHSTL_III_18 HSTL_III_18 ns TIHSTL_IV_18 HSTL_IV_18 ns TISSTL2_I SSTL2 I ns TISSTL2_II SSTL2 II ns TISSTL3_I SSTL3 I ns TISSTL3_II SSTL3 II ns TILVDCI33 LVDCI_33 ns TILVDCI25 LVDCI_25 ns TILVDCI18 LVDCI_18 ns TILVDCI15 LVDCI_15 ns TILVDCI_DV2_25 LVDCI_DV2_25 ns TILVDCI_DV2_18 LVDCI_DV2_18 ns TILVDCI_DV2_15 LVDCI_DV2_15 ns TIGTL_DCI GTL_DCI ns TIGTLP_DCI GTLP_DCI ns TIHSTL_I_DCI HSTL_I_DCI ns -7 -6 Units Data Input Delay Adjustments Standard-specific data input delay adjustments DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 71 R Virtex-II Pro Switching Characteristics Table 27: IOB Input Switching Characteristics Standard Adjustments (Continued) Speed Grade -7 -8 -6 Units Description Symbol Standard Standard-specific data input delay adjustments (continued) TIHSTL_II_DCI HSTL_II_DCI ns TIHSTL_III_DCI HSTL_III_DCI ns TIHSTL_IV_DCI HSTL_IV_DCI ns TIHSTL_I_DCI_18 HSTL_I_DCI_18 ns TIHSTL_II_DCI_18 HSTL_II_DCI_18 ns TIHSTL_III_DCI_18 HSTL_III_DCI_18 ns TIHSTL_IV_DCI_18 HSTL_IV_DCI_18 ns TISSTL2_I_DCI SSTL2_I_DCI ns TISSTL2_II_DCI SSTL2_II_DCI ns TISSTL3_I_DCI SSTL3_I_DCI ns TISSTL3_II_DCI SSTL3_II_DCI ns TILDT_25 LDT_25 ns TIULVDS_25 ULVDS_25 ns Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 30. IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 73. Table 28: IOB Output Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Propagation Delays O input to Pad TIOOP ns, max O input to Pad via transparent latch TIOOLP ns, max T input to Pad high-impedance (2) TIOTHZ ns, max T input to valid data on Pad TIOTON ns, max T input to Pad high-impedance via transparent latch (2) TIOTLPHZ ns, max T input to valid data on Pad via transparent latch TIOTLPON ns, max TGTS ns, max Clock CLK to Pad TIOCKP ns, max Clock CLK to Pad high-impedance (synchronous) (2) TIOCKHZ ns, max Clock CLK to valid data on Pad (synchronous) TIOCKON ns, max 3-State Delays GTS to Pad high-impedance (2) Sequential Delays 72 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 28: IOB Output Switching Characteristics (Continued) Speed Grade Description Symbol -7 -8 -6 Units Setup and Hold Times Before/After Clock CLK O input TIOOCK/TIOCKO ns, min OCE input TIOOCECK/TIOCKOCE ns, min SR input (OFF) TIOSRCKO/TIOCKOSR ns, min TIOTCK/TIOCKT ns, min 3-State Setup Times, TCE input TIOTCECK/TIOCKTCE ns, min 3-State Setup Times, SR input (TFF) TIOSRCKT/TIOCKTSR ns, min SR input to Pad (asynchronous) TIOSRP ns, max SR input to Pad high-impedance (asynchronous) (2) TIOSRHZ ns, max SR input to valid data on Pad (asynchronous) TIOSRON ns, max GSR to Pad TIOGSRQ ns, max 3-State Setup Times, T input Set/Reset Delays Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. The 3-state turn-off delays should not be adjusted. IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Table 29: IOB Output Switching Characteristics Standard Adjustments Speed Grade Description Symbol Standard -8 TOLVTTL_S2 LVTTL, Slow, 2 mA ns TOLVTTL_S4 4 mA ns TOLVTTL_S6 6 mA ns TOLVTTL_S8 8 mA ns TOLVTTL_S12 12 mA ns TOLVTTL_S16 16 mA ns TOLVTTL_S24 24 mA ns TOLVTTL_F2 LVTTL, Fast, 2 mA ns TOLVTTL_F4 4 mA ns TOLVTTL_F6 6 mA ns TOLVTTL_F8 8 mA ns TOLVTTL_F12 12 mA ns -7 -6 Units Output Delay Adjustments Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 73 R Virtex-II Pro Switching Characteristics Table 29: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) (continued) 74 -6 Units Standard TOLVTTL_F16 16 mA ns TOLVTTL_F24 24 mA ns TOLVDS_25 LVDS ns TOLVDSEXT_25 LVDS ns TOLDT_25 LDT ns TOBLVDS_25 BLVDS ns TOULVDS_25 ULVDS ns TOPCI33_3 PCI, 33 MHz, 3.3V ns TOPCI66_3 PCI, 66 MHz, 3.3V ns TOGTL GTL ns TOGTLP GTLP ns TOHSTL_I HSTL I ns TOHSTL_II HSTL II ns TOHSTL_IIII HSTL III ns TOHSTL_IV HSTL IV ns TOHSTL_I_18 HSTL_I_18 ns TOHSTL_II_18 HSTL_II_18 ns TOHSTL_IIII_18 HSTL_III_18 ns TOHSTL_IV_18 HSTL_IV_18 ns TOSSTL2_I SSTL2 I ns TOSSTL2_II SSTL2 II ns TOSSTL3_I SSTL3 I ns TOSSTL3_II SSTL3 II ns TOLVCMOS33_S2 LVCMOS33, Slow, 2 mA ns TOLVCMOS33_S4 4 mA ns TOLVCMOS33_S6 6 mA ns TOLVCMOS33_S8 8 mA ns TOLVCMOS33_S12 12 mA ns TOLVCMOS33_S16 16 mA ns TOLVCMOS33_S24 24 mA ns TOLVCMOS33_F2 LVCMOS33, Fast, 2 mA ns TOLVCMOS33_F4 4 mA ns TOLVCMOS33_F6 6 mA ns TOLVCMOS33_F8 8 mA ns TOLVCMOS33_F12 12 mA ns www.xilinx.com 1-800-255-7778 -8 -7 Symbol DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 29: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) (continued) DS083-3 (v1.0) January 31, 2002 Advance Product Specification -6 Units Standard TOLVCMOS33_F16 16 mA ns TOLVCMOS33_F24 24 mA ns TOLVCMOS25_S2 LVCMOS25, Slow, 2 mA ns TOLVCMOS25_S4 4 mA ns TOLVCMOS25_S6 6 mA ns TOLVCMOS25_S8 8 mA ns TOLVCMOS25_S12 12 mA ns TOLVCMOS25_S16 16 mA ns TOLVCMOS25_S24 24 mA ns TOLVCMOS25_F2 LVCMOS25, Fast, 2 mA ns TOLVCMOS25_F4 4 mA ns TOLVCMOS25_F6 6 mA ns TOLVCMOS25_F8 8 mA ns TOLVCMOS25_F12 12 mA ns TOLVCMOS25_F16 16 mA ns TOLVCMOS25_F24 24 mA ns TOLVCMOS18_S2 LVCMOS18, Slow, 2 mA ns TOLVCMOS18_S4 4 mA ns TOLVCMOS18_S6 6 mA ns TOLVCMOS18_S8 8 mA ns TOLVCMOS18_S12 12 mA ns TOLVCMOS18_S16 16 mA ns TOLVCMOS18_F2 LVCMOS18, Fast, 2 mA ns TOLVCMOS18_F4 4 mA ns TOLVCMOS18_F6 6 mA ns TOLVCMOS18_F8 8 mA ns TOLVCMOS18_F12 12 mA ns TOLVCMOS18_F16 16 mA ns TOLVCMOS15_S2 LVCMOS15, Slow, 2 mA ns TOLVCMOS15_S4 4 mA ns TOLVCMOS15_S6 6 mA ns TOLVCMOS15_S8 8 mA ns TOLVCMOS15_S12 12 mA ns TOLVCMOS15_S16 16 mA ns www.xilinx.com 1-800-255-7778 -8 -7 Symbol 75 R Virtex-II Pro Switching Characteristics Table 29: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) (continued) 76 -6 Units Standard TOLVCMOS15_F2 LVCMOS15, Fast, 2 mA ns TOLVCMOS15_F4 4 mA ns TOLVCMOS15_F6 6 mA ns TOLVCMOS15_F8 8 mA ns TOLVCMOS15_F12 12 mA ns TOLVCMOS15_F16 16 mA ns TOLVDCI33 LVDCI_33 ns TOLVDCI25 LVDCI_25 ns TOLVDCI18 LVDCI_18 ns TOLVDCI15 LVDCI_15 ns TOLVDCI_DV2_25 LVDCI_DV2_25 ns TOLVDCI_DV2_18 LVDCI_DV2_18 ns TOLVDCI_DV2_15 LVDCI_DV2_15 ns TOGTL_DCI GTL_DCI ns TOGTLP_DCI GTLP_DCI ns TOHSTL_I_DCI HSTL_I_DCI ns TOHSTL_II_DCI HSTL_II_DCI ns TOHSTL_III_DCI HSTL_III_DCI ns TOHSTL_IV_DCI HSTL_IV_DCI ns TOHSTL_I_DCI_18 HSTL_I_DCI_18 ns TOHSTL_II_DCI_18 HSTL_II_DCI_18 ns TOHSTL_III_DCI_18 HSTL_III_DCI_18 ns TOHSTL_IV_DCI_18 HSTL_IV_DCI_18 ns TOSSTL2_I_DCI SSTL2_I_DCI ns TOSSTL2_II_DCI SSTL2_II_DCI ns TOSSTL3_I_DCI SSTL3_I_DCI ns TOSSTL3_II_DCI SSTL3_II_DCI ns www.xilinx.com 1-800-255-7778 -8 -7 Symbol DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 30: Delay Measurement Methodology VL (1) VH (1) Meas. Point VREF (Typ) (2) LVTTL 0 3 1.4 - LVCMOS33 0 3.3 1.65 - LVCMOS25 0 2.5 1.25 - LVCMOS18 0 1.8 0.9 - LVCMOS15 0 1.5 0.75 - Standard PCI33_3 Per PCI Specification - PCI66_3 Per PCI Specification - GTL VREF - 0.2 VREF + 0.2 VREF 0.80 GTLP VREF - 0.2 VREF + 0.2 VREF 1.0 HSTL Class I VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class II VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class III VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL Class IV VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL Class I (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 HSTL Class II (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 HSTL Class III (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 HSTL Class IV (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 SSTL3 I & II VREF - 1.0 VREF + 1.0 VREF 1.5 SSTL2 I & II VREF - 0.75 VREF + 0.75 VREF 1.25 LVDS_25 1.2 - 0.125 1.2 + 0.125 1.2 LVDSEXT_25 1.2 - 0.125 1.2 + 0.125 1.2 ULVDS_25 0.6 - 0.125 0.6 + 0.125 0.6 LDT_25 0.6 - 0.125 0.6 + 0.125 0.6 Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 77 R Virtex-II Pro Switching Characteristics Table 31: Standard Capacitive Loads Standard Csl (pF) LVTTL Fast Slew Rate, 2mA drive 35 LVTTL Fast Slew Rate, 4mA drive 35 LVTTL Fast Slew Rate, 6mA drive 35 LVTTL Fast Slew Rate, 8mA drive 35 LVTTL Fast Slew Rate, 12mA drive 35 LVTTL Fast Slew Rate, 16mA drive 35 LVTTL Fast Slew Rate, 24mA drive 35 LVTTL Slow Slew Rate, 2mA drive 35 LVTTL Slow Slew Rate, 4mA drive 35 LVTTL Slow Slew Rate, 6mA drive 35 LVTTL Slow Slew Rate, 8mA drive 35 LVTTL Slow Slew Rate, 12mA drive 35 LVTTL Slow Slew Rate, 16mA drive 35 LVTTL Slow Slew Rate, 24mA drive 35 LVCMOS33 35 LVCMOS25 35 LVCMOS18 35 LVCMOS15 35 PCI 33MHZ 3.3V 10 PCI 66 MHz 3.3V 10 GTL 0 GTLP 0 HSTL Class I (1.5V and 1.8V) 20 HSTL Class II (1.5Vand 1.8V 20 HSTL Class III (1.5Vand 1.8V 20 HSTL Class IV1.5Vand 1.8V 20 SSTL2 Class I 30 SSTL2 Class II 30 SSTL3 Class I 30 SSTL3 Class II 30 Notes: 1. I/O parameter measurements are made with the capacitance values shown above. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. 3. Use of IBIS models results in a more accurate prediction of the propagation delay: a. Model the output in an IBIS simulation into the standard capacitive load. b. Record the relative time to the VOH or VOL transition of interest. c. Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS models for driven devices. d. Record the results from the new simulation. e. Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should be added or subtracted from the value above to predict the actual delay. 78 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Clock Distribution Switching Characteristics Table 32: Clock Distribution Switching Characteristics Speed Grade Description Symbol Global Clock Buffer I input to O output -8 -7 -6 TGIO Units ns, max CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used (see Figure 22 in Data Sheet Module 1). The values listed below are worst-case. Precise values are provided by the timing analyzer. Table 33: CLB Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Combinatorial Delays 4-input function: F/G inputs to X/Y outputs TILO ns, max 5-input function: F/G inputs to F5 output TIF5 ns, max 5-input function: F/G inputs to X output TIF5X ns, max FXINA or FXINB inputs to Y output via MUXFX TIFXY ns, max FXINA input to FX output via MUXFX TINAFX ns, max FXINB input to FX output via MUXFX TINBFX ns, max SOPIN input to SOPOUT output via ORCY TSOPSOP ns, max Incremental delay routing through transparent latch to XQ/YQ outputs TIFNCTL ns, max FF Clock CLK to XQ/YQ outputs TCKO ns, max Latch Clock CLK to XQ/YQ outputs TCKLO ns, max BX/BY inputs TDICK/TCKDI ns, min DY inputs TDYCK/TCKDY ns, min DX inputs TDXCK/TCKDX ns, min CE input TCECK/TCKCE ns, min TRCK/TCKR ns, min Minimum Pulse Width, High TCH ns, min Minimum Pulse Width, Low TCL ns, min TRPW ns, min Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) TRQ ns, max Toggle Frequency (MHz) (for export control) FTOG MHz Sequential Delays Setup and Hold Times Before/After Clock CLK SR/BY inputs (synchronous) Clock CLK Set/Reset Minimum Pulse Width, SR/BY inputs Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 79 R Virtex-II Pro Switching Characteristics CLB Distributed RAM Switching Characteristics Table 34: CLB Distributed RAM Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Sequential Delays Clock CLK to X/Y outputs (WE active) in 16 x 1 mode TSHCKO16 ns, max Clock CLK to X/Y outputs (WE active) in 32 x 1 mode TSHCKO32 ns, max Clock CLK to F5 output TSHCKOF5 ns, max BX/BY data inputs (DIN) TDS/TDH ns, min F/G address inputs TAS/TAH ns, min TWES/TWEH ns, min Minimum Pulse Width, High TWPH ns, min Minimum Pulse Width, Low TWPL ns, min Minimum clock period to meet address write cycle time TWC ns, min Setup and Hold Times Before/After Clock CLK CE input (WE) Clock CLK Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. CLB Shift Register Switching Characteristics Table 35: CLB Shift Register Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Sequential Delays Clock CLK to X/Y outputs TREG ns, max Clock CLK to X/Y outputs TREG32 ns, max Clock CLK to XB output via MC15 LUT output TREGXB ns, max Clock CLK to YB output via MC15 LUT output TREGYB ns, max Clock CLK to Shiftout TCKSH ns, max Clock CLK to F5 output TREGF5 ns, max TSRLDS/TSRLDH ns, min TWSS/TWSH ns, min Minimum Pulse Width, High TSRPH ns, min Minimum Pulse Width, Low TSRPL ns, min Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) CE input (WS) Clock CLK Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 80 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Multiplier Switching Characteristics Table 36: Multiplier Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Propagation Delay to Output Pin Input to Pin35 TMULT_P35 ns, max Input to Pin34 TMULT_P34 ns, max Input to Pin33 TMULT_P33 ns, max Input to Pin32 TMULT_P32 ns, max Input to Pin31 TMULT_P31 ns, max Input to Pin30 TMULT_P30 ns, max Input to Pin29 TMULT_P29 ns, max Input to Pin28 TMULT_P28 ns, max Input to Pin27 TMULT_P27 ns, max Input to Pin26 TMULT_P26 ns, max Input to Pin25 TMULT_P25 ns, max Input to Pin24 TMULT_P24 ns, max Input to Pin23 TMULT_P23 ns, max Input to Pin22 TMULT_P22 ns, max Input to Pin21 TMULT_P21 ns, max Input to Pin20 TMULT_P20 ns, max Input to Pin19 TMULT_P19 ns, max Input to Pin18 TMULT_P18 ns, max Input to Pin17 TMULT_P17 ns, max Input to Pin16 TMULT_P16 ns, max Input to Pin15 TMULT_P15 ns, max Input to Pin14 TMULT_P14 ns, max Input to Pin13 TMULT_P13 ns, max Input to Pin12 TMULT_P12 ns, max Input to Pin11 TMULT_P11 ns, max Input to Pin10 TMULT_P10 ns, max Input to Pin9 TMULT_P9 ns, max Input to Pin8 TMULT_P8 ns, max Input to Pin7 TMULT_P7 ns, max Input to Pin6 TMULT_P6 ns, max Input to Pin5 TMULT_P5 ns, max Input to Pin4 TMULT_P4 ns, max Input to Pin3 TMULT_P3 ns, max Input to Pin2 TMULT_P2 ns, max Input to Pin1 TMULT_P1 ns, max Input to Pin0 TMULT_P0 ns, max DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 81 R Virtex-II Pro Switching Characteristics Block SelectRAM Switching Characteristics Table 37: Block SelectRAM Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Sequential Delays Clock CLK to DOUT output TBCKO ns, max ADDR inputs TBACK/TBCKA ns, min DIN inputs TBDCK/TBCKD ns, min EN input TBECK/TBCKE ns, min RST input TBRCK/TBCKR ns, min WEN input TBWCK/TBCKW ns, min Minimum Pulse Width, High TBPWH ns, min Minimum Pulse Width, Low TBPWL ns, min Setup and Hold Times Before Clock CLK Clock CLK Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. TBUF Switching Characteristics Table 38: TBUF Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Combinatorial Delays IN input to OUT output TIO ns, max TRI input to OUT output high-impedance TOFF ns, max TRI input to valid data on OUT output TON ns, max JTAG Test Access Port Switching Characteristics Table 39: JTAG Test Access Port Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units TMS and TDI Setup times before TCK TTAPTK ns, min TMS and TDI Hold times after TCK TTCKTAP ns, min Output delay from clock TCK to output TDO TTCKTDO ns, max FTCK MHz, max Maximum TCK clock frequency 82 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Table 40: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Speed Grade Description Symbol Device -8 TICKOFDCM XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 73. Global Clock and OFF with DCM Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 30. 3. DCM output jitter is already included in the timing calculation. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 83 R Virtex-II Pro Pin-to-Pin Output Parameter Guidelines Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Table 41: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Speed Grade Description Symbol Device -8 TICKOF XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 73. Global Clock and OFF without DCM Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 30. 3. DCM output jitter is already included in the timing calculation. 84 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM Table 42: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM Speed Grade Description Symbol Device -8 TPSDCM/TPHDCM XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 71. No Delay Global Clock and IFF with DCM Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DCM output jitter is already included in the timing calculation. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 85 R DCM Timing Parameters Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM , Table 43: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM Speed Grade Description Symbol Device -8 TPSFD/TPHFD XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 71. Full Delay Global Clock and IFF without DCM Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DCM Timing Parameters Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605; all devices are 100% functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The fol- lowing guidelines reflect worst-case values across the recommended operating conditions. All output jitter and phase specifications are determined through statistical measurement at the package pins. Operating Frequency Ranges e Table 44: Operating Frequency Ranges Speed Grade Description Symbol Constraints -8 -7 -6 Units Output Clocks (Low Frequency Mode) CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180 86 CLKOUT_FREQ_1X_LF_MIN MHz CLKOUT_FREQ_1X_LF_MAX MHz CLKOUT_FREQ_2X_LF_MIN MHz CLKOUT_FREQ_2X_LF_MAX MHz CLKOUT_FREQ_DV_LF_MIN MHz CLKOUT_FREQ_DV_LF_MAX MHz CLKOUT_FREQ_FX_LF_MIN MHz CLKOUT_FREQ_FX_LF_MAX MHz www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Table 44: Operating Frequency Ranges (Continued) Speed Grade Description Symbol Constraints -8 -7 -6 Units Input Clocks (Low Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN (using CLKFX outputs) (2) PSCLK CLKIN_FREQ_DLL_LF_MIN MHz CLKIN_FREQ_DLL_LF_MAX MHz CLKIN_FREQ_FX_LF_MIN MHz CLKIN_FREQ_FX_LF_MAX MHz PSCLK_FREQ_LF_MIN MHz PSCLK_FREQ_LF_MAX MHz Output Clocks (High Frequency Mode) CLK0, CLK180 CLKDV CLKFX, CLKFX180 CLKOUT_FREQ_1X_HF_MIN MHz CLKOUT_FREQ_1X_HF_MAX MHz CLKOUT_FREQ_DV_HF_MIN MHz CLKOUT_FREQ_DV_HF_MAX MHz CLKOUT_FREQ_FX_HF_MIN MHz CLKOUT_FREQ_FX_HF_MAX MHz CLKIN_FREQ_DLL_HF_MIN MHz CLKIN_FREQ_DLL_HF_MAX MHz CLKIN_FREQ_FX_HF_MIN MHz CLKIN_FREQ_FX_HF_MAX MHz PSCLK_FREQ_HF_MIN MHz PSCLK_FREQ_HF_MAX MHz Input Clocks (High Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN (using CLKFX outputs) (2) PSCLK Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 87 R DCM Timing Parameters Input Clock Tolerances Table 45: Input Clock Tolerances Speed Grade -8 Description Symbol Constraints Min -7 Max Min -6 Max Min Max Units Input Clock Low/high Pulse Width PSCLK PSCLK_PULSE < 1MHz ns CLKIN (3) CLKIN_PULSE 1 - 10 MHz ns 10 - 25 MHz ns 25 - 50 MHz ns 50 - 100 MHz ns 100 - 150 MHz ns 150 - 200 MHz ns 200 - 250 MHz ns 250 - 300 MHz ns 300 - 350 MHz ns 350 - 400 MHz ns > 400 MHz ns Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_CYC_JITT_DLL_LF ps CLKIN (using CLKFX outputs) (2) CLKIN_CYC_JITT_FX_LF ps Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_CYC_JITT_DLL_HF ps CLKIN (using CLKFX outputs) (2) CLKIN_CYC_JITT_FX_HF ps Input Clock Period Jitter (Low Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_PER_JITT_DLL_LF ns CLKIN (using CLKFX outputs) (2) CLKIN_PER_JITT_FX_LF ns Input Clock Period Jitter (High Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_PER_JITT_DLL_HF ns CLKIN (using CLKFX outputs) (2) CLKIN_PER_JITT_FX_HF ns Feedback Clock Path Delay Variation CLKFB off-chip feedback ns CLKFB_DELAY_VAR_EXT Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. Specification also applies to PSCLK. 88 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Output Clock Jitter Table 46: Output Clock Jitter Speed Grade -8 Description Symbol Constraints Min -7 Max Min -6 Max Min Max Units Clock Synthesis Period Jitter CLK0 CLKOUT_PER_JITT_0 ps CLK90 CLKOUT_PER_JITT_90 ps CLK180 CLKOUT_PER_JITT_180 ps CLK270 CLKOUT_PER_JITT_270 ps CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ps CLKDV (integer division) CLKOUT_PER_JITT_DV1 ps CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ps CLKFX, CLKFX180 CLKOUT_PER_JITT_FX ps Output Clock Phase Alignment Table 47: Output Clock Phase Alignment Speed Grade -8 Description Symbol Constraints Min -7 Max Min -6 Max Min Max Units Phase Offset Between CLKIN and CLKFB CLKIN/CLKFB CLKIN_CLKFB_PHASE ps Phase Offset Between Any DCM Outputs All CLK outputs CLKOUT_PHASE ps DLL outputs (1) CLKOUT_DUTY_CYCLE_DLL ps CLKFX outputs CLKOUT_DUTY_CYCLE_FX ps Duty Cycle Precision Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 89 R DCM Timing Parameters Miscellaneous Timing Parameters Table 48: Miscellaneous Timing Parameters Speed Grade Description Symbol Constraints FCLKIN -8 -7 -6 Units Time Required to Achieve LOCK Using DLL outputs (1) Using CLKFX outputs Additional lock time with fine phase shifting LOCK_DLL: LOCK_DLL_60 > 60MHz us LOCK_DLL_50_60 50 - 60 MHz us LOCK_DLL_40_50 40 - 50 MHz us LOCK_DLL_30_40 30 - 40 MHz us LOCK_DLL_24_30 24 - 30 MHz us LOCK_FX_MIN ms LOCK_FX_MAX ms LOCK_DLL_FINE_SHIFT us FINE_SHIFT_RANGE ns DCM_TAP_MIN ps DCM_TAP_MAX ps Fine Phase Shifting Absolute shifting range Delay Lines Tap delay resolution Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. Frequency Synthesis Table 49: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 32 CLKFX_DIVIDE 1 32 90 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics Parameter Cross-Reference Table 50: Parameter Cross-Reference Libraries Guide Data Sheet DLL_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_{1X|2X|DV}_LF DFS_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_FX_LF DLL_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_DLL_LF DFS_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_FX_LF DLL_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_{1X|DV}_HF DFS_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_FX_HF DLL_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_DLL_HF DFS_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_FX_HF Revision History This section records the change history for this module of the data sheet. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II ProTM Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II Pro Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II ProTM Platform FPGAs: Functional Description (Module 2) * Virtex-II ProTM Platform FPGAs: Pinout Information (Module 4) DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 91 R Virtex-II Pro Data Sheet Modules 92 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification 0 Virtex-II ProTM Platform FPGAs: Pinout Information R DS083-4 (v1.0) January 31, 2002 0 0 Advance Product Specification This document provides Virtex-II Pro Device/Package Combinations and Maximum I/Os and Virtex-II Pro Pin Definitions, followed by pinout tables for the following packages: * FF672 Flip-Chip Fine-Pitch BGA Package * FF896 Flip-Chip Fine-Pitch BGA Package * FF1152 Flip-Chip Fine-Pitch BGA Package * FG256 Fine-Pitch BGA Package * FG456 Fine-Pitch BGA Package * * FF1517 Flip-Chip Fine-Pitch BGA Package BF957 Flip-Chip BGA Package Virtex-II Pro Device/Package Combinations and Maximum I/Os Wire-bond and flip-chip packages are available. Table 1 and Table 2 show the maximum number of user I/Os possible in wire-bond and flip-chip packages, respectively. Table 1: Wire-Bond Packages Information Package FG256 FG456 * FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). Pitch (mm) 1.00 1.00 * FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). Size (mm) 17 x 17 23 x 23 * BF denotes flip-chip BGA (1.27 mm pitch). I/Os 140 248 Table 2: Flip-Chip Packages Information Package FF672 FF896 FF1152 FF1517 BF957 Pitch (mm) 1.00 1.00 1.00 1.00 1.27 Size (mm) 27 x 27 31 x 31 35 x 35 40 x 40 40 x 40 396 556 692 852 584 I/Os Table 3 shows the number of available I/Os and the number of Rocket I/OTM multi-gigabit transceiver (MGT) pins for each Virtex-II Pro device/package combination. The number of I/Os per package includes all user I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, AND RSVD) and the nine (per transceiver) Rocket I/O MGT pins (TXP, TXN, RXP, RXN, AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA). The number of transceivers in the device is the number of Rocket I/O MGT pins in Table 3 divided by nine. Table 3: Virtex-II Pro Available I/Os and Rocket I/O MGT Pins per Device/Package Combination Device XC2VP2 XC2VP4 XC2VP7 Available User I/Os Rocket I/O MGT Pins Available User I/Os Rocket I/O MGT Pins FG256 140 36 140 36 FG456 156 72 248 FF672 204 72 348 Package FF896 Available User I/Os Rocket I/O MGT Pins 72 248 72 72 396 72 396 72 FF1152 XC2VP20 Available User I/Os Rocket I/O MGT Pins 556 72 564 144 FF1517 BF957 564 108 XC2VP50 Available User I/Os Rocket I/O MGT Pins 692 144 852 144 584 108 (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 93 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 4 shows the number of 3.3V SelectI/Os in each bank and the total for each device/package combination. Table 4: 3.3V SelectI/O Banks Virtex-II Pro Device 2VP2 2VP4 2VP7 Package Bank2 Bank3 FG256 17 18 18 53 FG456 21 18 18 57 FF672 27 24 24 75 FG256 17 17 17 51 FG456 21 40 42 103 FF672 27 60 60 147 FG456 21 40 42 103 FF672 39 60 60 159 FF896 39 60 60 159 2VP20 2VP50 57 FF896 57 55 Bank4 Bank5 Bank6 Bank7 Total 3.3V I/Os Bank1 BF957 Bank0 114 84 139 FF1152 57 57 114 BF957 59 59 118 FF1152 69 69 138 FF1517 81 81 162 Virtex-II Pro Pin Definitions This section describes the pinouts for Virtex-II Pro devices in the following packages: table per package). Pins that are not available for the smallest devices are listed in right-hand columns. * FG256 and FG456: wire-bond fine-pitch BGA of 1.00 mm pitch * FF672, FF896, FF1152, and FF1517: flip-chip fine-pitch BGA of 1.00 mm pitch * BF957: flip-chip BGA of 1.27 mm pitch Each device is split into eight I/O banks to allow for flexibility in the choice of I/O standards (see the Virtex-II Pro Data Sheet). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table 5 provides definitions for all pin types. All of the devices supported in a particular package are pinout compatible and are listed in the same table (one Module 4 of 4 94 All Virtex-II Pro pinout tables are available on the distribution CD-ROM, or on the web (at http://www.xilinx.com). www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Pin Definitions Table 5 provides a description of each pin type listed in Virtex-II Pro pinout tables. Table 5: Virtex-II Pro Pin Definitions Pin Name Direction Description Input/Output All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS, BLVDS, or LDT pairs. Each user I/O is labeled "IO_LXXY_#", where: IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive and negative sides of the differential pair. # indicates the bank number (0 through 7) User I/O Pins IO_LXXY_# Dual-Function Pins IO_LXXY_#/ZZZ The dual-function pins are labelled "IO_LXXY_#/ZZZ", where ZZZ can be one of the following pins: Per Bank - VRP, VRN, or VREF Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 - D7, RDWR_B, or CS_B With /ZZZ: DIN / D0, D1, D2, D3, D4, D5, D6, D7 Input/Output In SelectMAP mode, D0 through D7 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained. CS_B Input In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. RDWR_B Input In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. BUSY/DOUT Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after configuration. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. INIT_B Bidirectional (open-drain) When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. The pin becomes a user I/O after configuration. GCLKx (S/P) Input These are clock input pins that connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. VRP Input This pin is for the DCI voltage reference resistor of P transistor (per bank). VRN Input This pin is for the DCI voltage reference resistor of N transistor (per bank). ALT_VRP Input This is the alternative pin for the DCI voltage reference resistor of P transistor. ALT_VRN Input This is the alternative pin for the DCI voltage reference resistor of N transistor. VREF Input These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank). Input/Output Configuration clock. Output in Master mode or Input in Slave mode. Dedicated Pins(1) CCLK DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 95 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 5: Virtex-II Pro Pin Definitions (Continued) Pin Name Direction Description PROG_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor. DONE Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence. M2, M1, M0 Input Configuration mode selection. HSWAP_EN Input Enable I/O pullups during configuration. TCK Input Boundary Scan Clock. TDI Input Boundary Scan Data Input. TDO Output Boundary Scan Data Output. TMS Input Boundary Scan Mode Select. PWRDWN_B Input Power down pin. DXN, DXP N/A Temperature-sensing diode pins (Anode: DXP, Cathode: DXN). VBATT Input Decryptor key memory backup supply. (Do not connect if battery is not used.) RSVD N/A Reserved pin - do not connect. VCCO Input Power-supply pins for the output drivers (per bank). VCCAUX Input Power-supply pins for auxiliary circuits. VCCINT Input Power-supply pins for the internal core logic. GND Input Ground. AVCCAUXRX# Input Analog power supply for receive circuitry of the Rocket I/O multi-gigabit transceiver (2.5V). AVCCAUXTX# Input Analog power supply for transmit circuitry of the Rocket I/O multi-gigabit transceiver (2.5V). VTRXPAD# Input Receive termination supply for the Rocket I/O multi-gigabit transceiver (1.8V - 2.8V). VTTXPAD# Input Transmit termination supply for the Rocket I/O multi-gigabit transceiver (1.8V - 2.8V). GNDA# (2) Input Ground for the analog circuitry of the Rocket I/O multi-gigabit transceiver. RXPPAD# Output Positive differential receive port of the Rocket I/O multi-gigabit transceiver. RXNPAD# Output Negitive differential receive port of the Rocket I/O multi-gigabit transceiver. TXPPAD# Input Positive differential transmit port of the Rocket I/O multi-gigabit transceiver. TXNPAD# Input Negitive differential transmit port of the Rocket I/O multi-gigabit transceiver. Other Pins Notes: 1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage). 2. Two pads on the die are tied to the same package pin (GNDA) in order to lower the resistance on these connections. Thus, duplicate entries exist for GNDA pins. Module 4 of 4 96 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information FG256 Fine-Pitch BGA Package As shown in Table 6, XC2VP2 and XC2VP4 Virtex-II Pro devices are available in the FG256 fine-pitch BGA package. The pins in each of these devices are identical. Following this table are the FG256 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 C2 0 IO_L01P_0/VRN_0 C3 0 IO_L02N_0 B3 0 IO_L02P_0 C4 0 IO_L03N_0 A2 0 IO_L03P_0/VREF_0 A3 0 IO_L06N_0 D5 0 IO_L06P_0 C5 0 IO_L07P_0 D6 0 IO_L09N_0 E6 0 IO_L09P_0/VREF_0 E7 0 IO_L69N_0 D7 0 IO_L69P_0/VREF_0 C7 0 IO_L74N_0/GCLK7P D8 0 IO_L74P_0/GCLK6S C8 0 IO_L75N_0/GCLK5P B8 0 IO_L75P_0/GCLK4S A8 1 IO_L75N_1/GCLK3P A9 1 IO_L75P_1/GCLK2S B9 1 IO_L74N_1/GCLK1P C9 1 IO_L74P_1/GCLK0S D9 1 IO_L69N_1/VREF_1 C10 1 IO_L69P_1 D10 1 IO_L09N_1/VREF_1 E10 1 IO_L09P_1 E11 1 IO_L07N_1 D11 1 IO_L06N_1 C12 1 IO_L06P_1 D12 1 IO_L03N_1/VREF_1 A14 1 IO_L03P_1 A15 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 97 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 1 IO_L02N_1 C13 1 IO_L02P_1 B14 1 IO_L01N_1/VRP_1 C14 1 IO_L01P_1/VRN_1 C15 2 IO_L01N_2/VRP_2 E14 2 IO_L01P_2/VRN_2 E15 2 IO_L02N_2 E13 2 IO_L02P_2 F12 2 IO_L03N_2 F13 2 IO_L03P_2 F14 2 IO_L04N_2/VREF_2 F15 2 IO_L04P_2 F16 2 IO_L06N_2 G13 2 IO_L06P_2 G14 2 IO_L85N_2 G15 2 IO_L85P_2 G16 2 IO_L86N_2 G12 2 IO_L86P_2 H13 2 IO_L88N_2/VREF_2 H14 2 IO_L88P_2 H15 2 IO_L90N_2 H16 2 IO_L90P_2 J16 3 IO_L90N_3 J15 3 IO_L90P_3 J14 3 IO_L89N_3 J13 3 IO_L89P_3 K12 3 IO_L87N_3/VREF_3 K16 3 IO_L87P_3 K15 3 IO_L85N_3 K14 3 IO_L85P_3 K13 3 IO_L06N_3 L16 3 IO_L06P_3 L15 3 IO_L05N_3 L14 Module 4 of 4 98 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 3 IO_L05P_3 L13 3 IO_L03N_3/VREF_3 L12 3 IO_L03P_3 M13 3 IO_L02N_3 M16 3 IO_L02P_3 N16 3 IO_L01N_3/VRP_3 M15 3 IO_L01P_3/VRN_3 M14 4 IO_L01N_4/DOUT P15 4 IO_L01P_4/INIT_B P14 4 IO_L02N_4/D0 R14 4 IO_L02P_4/D1 P13 4 IO_L03N_4/D2 T15 4 IO_L03P_4/D3 T14 4 IO_L06N_4/VRP_4 N12 4 IO_L06P_4/VRN_4 P12 4 IO_L07P_4/VREF_4 N11 4 IO_L09N_4 M11 4 IO_L09P_4/VREF_4 M10 4 IO_L69N_4 N10 4 IO_L69P_4/VREF_4 P10 4 IO_L74N_4/GCLK3S N9 4 IO_L74P_4/GCLK2P P9 4 IO_L75N_4/GCLK1S R9 4 IO_L75P_4/GCLK0P T9 5 IO_L75N_5/GCLK7S T8 5 IO_L75P_5/GCLK6P R8 5 IO_L74N_5/GCLK5S P8 5 IO_L74P_5/GCLK4P N8 5 IO_L69N_5/VREF_5 P7 5 IO_L69P_5 N7 5 IO_L09N_5/VREF_5 M7 5 IO_L09P_5 M6 5 IO_L07N_5/VREF_5 N6 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 99 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 5 IO_L06N_5/VRP_5 P5 5 IO_L06P_5/VRN_5 N5 5 IO_L03N_5/D4 T3 5 IO_L03P_5/D5 T2 5 IO_L02N_5/D6 P4 5 IO_L02P_5/D7 R3 5 IO_L01N_5/RDWR_B P3 5 IO_L01P_5/CS_B P2 6 IO_L01P_6/VRN_6 M3 6 IO_L01N_6/VRP_6 M2 6 IO_L02P_6 N1 6 IO_L02N_6 M1 6 IO_L03P_6 M4 6 IO_L03N_6/VREF_6 L5 6 IO_L05P_6 L4 6 IO_L05N_6 L3 6 IO_L06P_6 L2 6 IO_L06N_6 L1 6 IO_L85P_6 K4 6 IO_L85N_6 K3 6 IO_L87P_6 K2 6 IO_L87N_6/VREF_6 K1 6 IO_L89P_6 K5 6 IO_L89N_6 J4 6 IO_L90P_6 J3 6 IO_L90N_6 J2 7 IO_L90P_7 J1 7 IO_L90N_7 H1 7 IO_L88P_7 H2 7 IO_L88N_7/VREF_7 H3 7 IO_L86P_7 H4 7 IO_L86N_7 G5 7 IO_L85P_7 G1 Module 4 of 4 100 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 7 IO_L85N_7 G2 7 IO_L06P_7 G3 7 IO_L06N_7 G4 7 IO_L04P_7 F1 7 IO_L04N_7/VREF_7 F2 7 IO_L03P_7 F3 7 IO_L03N_7 F4 7 IO_L02P_7 F5 7 IO_L02N_7 E4 7 IO_L01P_7/VRN_7 E2 7 IO_L01N_7/VRP_7 E3 0 VCCO_0 F8 0 VCCO_0 F7 0 VCCO_0 E8 1 VCCO_1 F9 1 VCCO_1 F10 1 VCCO_1 E9 2 VCCO_2 H12 2 VCCO_2 H11 2 VCCO_2 G11 3 VCCO_3 K11 3 VCCO_3 J12 3 VCCO_3 J11 4 VCCO_4 M9 4 VCCO_4 L9 4 VCCO_4 L10 5 VCCO_5 M8 5 VCCO_5 L8 5 VCCO_5 L7 6 VCCO_6 K6 6 VCCO_6 J6 6 VCCO_6 J5 7 VCCO_7 H6 7 VCCO_7 H5 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 101 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 7 VCCO_7 G6 N/A CCLK N15 N/A PROG_B D1 N/A DONE P16 N/A M0 N3 N/A M1 N2 N/A M2 P1 N/A TCK D16 N/A TDI E1 N/A TDO E16 N/A TMS C16 N/A PWRDWN_B N14 N/A HSWAP_EN C1 N/A RSVD D14 N/A VBATT D15 N/A DXP D2 N/A DXN D3 N/A AVCCAUXTX6 B5 N/A VTTXPAD6 B4 N/A TXNPAD6 A4 N/A TXPPAD6 A5 N/A GNDA6 C6 N/A GNDA6 C6 N/A RXPPAD6 A6 N/A RXNPAD6 A7 N/A VTRXPAD6 B6 N/A AVCCAUXRX6 B7 N/A AVCCAUXTX7 B11 N/A VTTXPAD7 B10 N/A TXNPAD7 A10 N/A TXPPAD7 A11 N/A GNDA7 C11 N/A GNDA7 C11 N/A RXPPAD7 A12 Module 4 of 4 102 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number N/A RXNPAD7 A13 N/A VTRXPAD7 B12 N/A AVCCAUXRX7 B13 N/A AVCCAUXRX18 R13 N/A VTRXPAD18 R12 N/A RXNPAD18 T13 N/A RXPPAD18 T12 N/A GNDA18 P11 N/A GNDA18 P11 N/A TXPPAD18 T11 N/A TXNPAD18 T10 N/A VTTXPAD18 R10 N/A AVCCAUXTX18 R11 N/A AVCCAUXRX19 R7 N/A VTRXPAD19 R6 N/A RXNPAD19 T7 N/A RXPPAD19 T6 N/A GNDA19 P6 N/A GNDA19 P6 N/A TXPPAD19 T5 N/A TXNPAD19 T4 N/A VTTXPAD19 R4 N/A AVCCAUXTX19 R5 N/A VCCINT N4 N/A VCCINT N13 N/A VCCINT M5 N/A VCCINT M12 N/A VCCINT E5 N/A VCCINT E12 N/A VCCINT D4 N/A VCCINT D13 N/A VCCAUX R16 N/A VCCAUX R1 N/A VCCAUX B16 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 103 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 6: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number N/A VCCAUX B1 N/A GND T16 N/A GND T1 N/A GND R2 N/A GND R15 N/A GND L6 N/A GND L11 N/A GND K9 N/A GND K8 N/A GND K7 N/A GND K10 N/A GND J9 N/A GND J8 N/A GND J7 N/A GND J10 N/A GND H9 N/A GND H8 N/A GND H7 N/A GND H10 N/A GND G9 N/A GND G8 N/A GND G7 N/A GND G10 N/A GND F6 N/A GND F11 N/A GND B2 N/A GND B15 N/A GND A16 N/A GND A1 Module 4 of 4 104 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information FG256 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 1: FG256 Fine-Pitch BGA Package Specifications DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 105 R Virtex-II ProTM Platform FPGAs: Pinout Information FG456 Fine-Pitch BGA Package As shown in Table 7, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FG456 fine-pitch BGA package. The pins in these devices are same, except for the differences shown in the "No Connects" column. Following this table are the FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 D5 0 IO_L01P_0/VRN_0 D6 0 IO_L02N_0 E6 0 IO_L02P_0 E7 0 IO_L03N_0 D7 0 IO_L03P_0/VREF_0 C7 0 IO_L05_0/No_Pair E8 0 IO_L06N_0 D8 0 IO_L06P_0 C8 0 IO_L07N_0 F9 0 IO_L07P_0 E9 0 IO_L09N_0 D9 0 IO_L09P_0/VREF_0 D10 0 IO_L67N_0 F10 0 IO_L67P_0 E10 0 IO_L69N_0 C10 0 IO_L69P_0/VREF_0 B11 0 IO_L74N_0/GCLK7P F11 0 IO_L74P_0/GCLK6S E11 0 IO_L75N_0/GCLK5P D11 0 IO_L75P_0/GCLK4S C11 1 IO_L75N_1/GCLK3P C12 1 IO_L75P_1/GCLK2S D12 1 IO_L74N_1/GCLK1P E12 1 IO_L74P_1/GCLK0S F12 1 IO_L69N_1/VREF_1 B12 1 IO_L69P_1 C13 1 IO_L67N_1 E13 1 IO_L67P_1 F13 1 IO_L09N_1/VREF_1 D13 Module 4 of 4 106 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects XC2V P2 Bank Pin Description Pin Number 1 IO_L09P_1 D14 1 IO_L07N_1 E14 1 IO_L07P_1 F14 1 IO_L06N_1 C15 1 IO_L06P_1 D15 1 IO_L05_1/No_Pair E15 1 IO_L03N_1/VREF_1 C16 1 IO_L03P_1 D16 1 IO_L02N_1 E16 1 IO_L02P_1 E17 1 IO_L01N_1/VRP_1 D17 1 IO_L01P_1/VRN_1 D18 2 IO_L01N_2/VRP_2 C21 2 IO_L01P_2/VRN_2 C22 2 IO_L02N_2 D21 2 IO_L02P_2 D22 2 IO_L03N_2 E19 2 IO_L03P_2 E20 2 IO_L04N_2/VREF_2 E21 2 IO_L04P_2 E22 2 IO_L06N_2 F19 2 IO_L06P_2 F20 2 IO_L43N_2 F21 NC 2 IO_L43P_2 F22 NC 2 IO_L46N_2/VREF_2 F18 NC 2 IO_L46P_2 G18 NC 2 IO_L48N_2 G19 NC 2 IO_L48P_2 G20 NC 2 IO_L49N_2 G21 NC 2 IO_L49P_2 G22 NC 2 IO_L50N_2 H19 NC 2 IO_L50P_2 H20 NC 2 IO_L52N_2/VREF_2 H21 NC 2 IO_L52P_2 H22 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 Module 4 of 4 107 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 2 IO_L54N_2 H18 NC 2 IO_L54P_2 J17 NC 2 IO_L55N_2 J19 NC 2 IO_L55P_2 J20 NC 2 IO_L56N_2 J21 NC 2 IO_L56P_2 J22 NC 2 IO_L58N_2/VREF_2 J18 NC 2 IO_L58P_2 K18 NC 2 IO_L60N_2 K19 NC 2 IO_L60P_2 K20 NC 2 IO_L85N_2 K21 2 IO_L85P_2 K22 2 IO_L86N_2 K17 2 IO_L86P_2 L17 2 IO_L88N_2/VREF_2 L18 2 IO_L88P_2 L19 2 IO_L90N_2 L20 2 IO_L90P_2 L21 3 IO_L90N_3 M21 3 IO_L90P_3 M20 3 IO_L89N_3 M19 3 IO_L89P_3 M18 3 IO_L87N_3/VREF_3 M17 3 IO_L87P_3 N17 3 IO_L85N_3 N22 3 IO_L85P_3 N21 3 IO_L60N_3 N20 NC 3 IO_L60P_3 N19 NC 3 IO_L59N_3 N18 NC 3 IO_L59P_3 P18 NC 3 IO_L57N_3/VREF_3 P22 NC 3 IO_L57P_3 P21 NC 3 IO_L55N_3 P20 NC 3 IO_L55P_3 P19 NC Module 4 of 4 108 www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 3 IO_L54N_3 P17 NC 3 IO_L54P_3 R18 NC 3 IO_L53N_3 R22 NC 3 IO_L53P_3 R21 NC 3 IO_L51N_3/VREF_3 R20 NC 3 IO_L51P_3 R19 NC 3 IO_L49N_3 T22 NC 3 IO_L49P_3 T21 NC 3 IO_L48N_3 T20 NC 3 IO_L48P_3 T19 NC 3 IO_L47N_3 T18 NC 3 IO_L47P_3 U18 NC 3 IO_L45N_3/VREF_3 U22 NC 3 IO_L45P_3 U21 NC 3 IO_L43N_3 U20 NC 3 IO_L43P_3 U19 NC 3 IO_L06N_3 V22 3 IO_L06P_3 V21 3 IO_L05N_3 V20 3 IO_L05P_3 V19 3 IO_L03N_3/VREF_3 W22 3 IO_L03P_3 W21 3 IO_L02N_3 Y22 3 IO_L02P_3 Y21 3 IO_L01N_3/VRP_3 AA22 3 IO_L01P_3/VRN_3 AB21 4 IO_L01N_4/DOUT W18 4 IO_L01P_4/INIT_B W17 4 IO_L02N_4/D0 V17 4 IO_L02P_4/D1 V16 4 IO_L03N_4/D2 W16 4 IO_L03P_4/D3 Y16 4 IO_L05_4/No_Pair V15 4 IO_L06N_4/VRP_4 W15 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 Module 4 of 4 109 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 4 IO_L06P_4/VRN_4 Y15 4 IO_L07N_4 U14 4 IO_L07P_4/VREF_4 V14 4 IO_L09N_4 W14 4 IO_L09P_4/VREF_4 W13 4 IO_L67N_4 U13 4 IO_L67P_4 V13 4 IO_L69N_4 Y13 4 IO_L69P_4/VREF_4 AA12 4 IO_L74N_4/GCLK3S U12 4 IO_L74P_4/GCLK2P V12 4 IO_L75N_4/GCLK1S W12 4 IO_L75P_4/GCLK0P Y12 5 IO_L75N_5/GCLK7S Y11 5 IO_L75P_5/GCLK6P W11 5 IO_L74N_5/GCLK5S V11 5 IO_L74P_5/GCLK4P U11 5 IO_L69N_5/VREF_5 AA11 5 IO_L69P_5 Y10 5 IO_L67N_5 V10 5 IO_L67P_5 U10 5 IO_L09N_5/VREF_5 W10 5 IO_L09P_5 W9 5 IO_L07N_5/VREF_5 V9 5 IO_L07P_5 U9 5 IO_L06N_5/VRP_5 Y8 5 IO_L06P_5/VRN_5 W8 5 IO_L05_5/No_Pair V8 5 IO_L03N_5/D4 Y7 5 IO_L03P_5/D5 W7 5 IO_L02N_5/D6 V7 5 IO_L02P_5/D7 V6 5 IO_L01N_5/RDWR_B W6 5 IO_L01P_5/CS_B W5 Module 4 of 4 110 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects XC2V P2 Bank Pin Description Pin Number 6 IO_L01P_6/VRN_6 AB2 6 IO_L01N_6/VRP_6 AA1 6 IO_L02P_6 Y2 6 IO_L02N_6 Y1 6 IO_L03P_6 W2 6 IO_L03N_6/VREF_6 W1 6 IO_L05P_6 V4 6 IO_L05N_6 V3 6 IO_L06P_6 V2 6 IO_L06N_6 V1 6 IO_L43P_6 U4 NC 6 IO_L43N_6 U3 NC 6 IO_L45P_6 U2 NC 6 IO_L45N_6/VREF_6 U1 NC 6 IO_L47P_6 U5 NC 6 IO_L47N_6 T5 NC 6 IO_L48P_6 T4 NC 6 IO_L48N_6 T3 NC 6 IO_L49P_6 T2 NC 6 IO_L49N_6 T1 NC 6 IO_L51P_6 R4 NC 6 IO_L51N_6/VREF_6 R3 NC 6 IO_L53P_6 R2 NC 6 IO_L53N_6 R1 NC 6 IO_L54P_6 R5 NC 6 IO_L54N_6 P6 NC 6 IO_L55P_6 P4 NC 6 IO_L55N_6 P3 NC 6 IO_L57P_6 P2 NC 6 IO_L57N_6/VREF_6 P1 NC 6 IO_L59P_6 P5 NC 6 IO_L59N_6 N5 NC 6 IO_L60P_6 N4 NC 6 IO_L60N_6 N3 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 Module 4 of 4 111 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects XC2V P2 Bank Pin Description Pin Number 6 IO_L85P_6 N2 6 IO_L85N_6 N1 6 IO_L87P_6 N6 6 IO_L87N_6/VREF_6 M6 6 IO_L89P_6 M5 6 IO_L89N_6 M4 6 IO_L90P_6 M3 6 IO_L90N_6 M2 7 IO_L90P_7 L2 7 IO_L90N_7 L3 7 IO_L88P_7 L4 7 IO_L88N_7/VREF_7 L5 7 IO_L86P_7 L6 7 IO_L86N_7 K6 7 IO_L85P_7 K1 7 IO_L85N_7 K2 7 IO_L60P_7 K3 NC 7 IO_L60N_7 K4 NC 7 IO_L58P_7 K5 NC 7 IO_L58N_7/VREF_7 J5 NC 7 IO_L56P_7 J1 NC 7 IO_L56N_7 J2 NC 7 IO_L55P_7 J3 NC 7 IO_L55N_7 J4 NC 7 IO_L54P_7 J6 NC 7 IO_L54N_7 H5 NC 7 IO_L52P_7 H1 NC 7 IO_L52N_7/VREF_7 H2 NC 7 IO_L50P_7 H3 NC 7 IO_L50N_7 H4 NC 7 IO_L49P_7 G1 NC 7 IO_L49N_7 G2 NC 7 IO_L48P_7 G3 NC 7 IO_L48N_7 G4 NC Module 4 of 4 112 www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 7 IO_L46P_7 G5 NC 7 IO_L46N_7/VREF_7 F5 NC 7 IO_L43P_7 F1 NC 7 IO_L43N_7 F2 NC 7 IO_L06P_7 F3 7 IO_L06N_7 F4 7 IO_L04P_7 E1 7 IO_L04N_7/VREF_7 E2 7 IO_L03P_7 E3 7 IO_L03N_7 E4 7 IO_L02P_7 D1 7 IO_L02N_7 D2 7 IO_L01P_7/VRN_7 C1 7 IO_L01N_7/VRP_7 C2 0 VCCO_0 G9 0 VCCO_0 G11 0 VCCO_0 G10 0 VCCO_0 F8 0 VCCO_0 F7 1 VCCO_1 G14 1 VCCO_1 G13 1 VCCO_1 G12 1 VCCO_1 F16 1 VCCO_1 F15 2 VCCO_2 L16 2 VCCO_2 K16 2 VCCO_2 J16 2 VCCO_2 H17 2 VCCO_2 G17 3 VCCO_3 T17 3 VCCO_3 R17 3 VCCO_3 P16 3 VCCO_3 N16 3 VCCO_3 M16 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 Module 4 of 4 113 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 4 VCCO_4 U16 4 VCCO_4 U15 4 VCCO_4 T14 4 VCCO_4 T13 4 VCCO_4 T12 5 VCCO_5 U8 5 VCCO_5 U7 5 VCCO_5 T9 5 VCCO_5 T11 5 VCCO_5 T10 6 VCCO_6 T6 6 VCCO_6 R6 6 VCCO_6 P7 6 VCCO_6 N7 6 VCCO_6 M7 7 VCCO_7 L7 7 VCCO_7 K7 7 VCCO_7 J7 7 VCCO_7 H6 7 VCCO_7 G6 N/A CCLK W20 N/A PROG_B B1 N/A DONE Y18 N/A M0 Y4 N/A M1 W3 N/A M2 Y5 N/A TCK B22 N/A TDI D3 N/A TDO D20 N/A TMS A21 N/A PWRDWN_B Y19 N/A HSWAP_EN A2 N/A RSVD C18 N/A VBATT C19 Module 4 of 4 114 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects XC2V P2 XC2V P4 B4 NC NC VTTXPAD4 B3 NC NC N/A TXNPAD4 A3 NC NC N/A TXPPAD4 A4 NC NC N/A GNDA4 C6 NC NC N/A GNDA4 C6 NC NC N/A RXPPAD4 A5 NC NC N/A RXNPAD4 A6 NC NC N/A VTRXPAD4 B5 NC NC N/A AVCCAUXRX4 B6 NC NC N/A AVCCAUXTX6 B8 N/A VTTXPAD6 B7 N/A TXNPAD6 A7 N/A TXPPAD6 A8 N/A GNDA6 C9 N/A GNDA6 C9 N/A RXPPAD6 A9 N/A RXNPAD6 A10 N/A VTRXPAD6 B9 N/A AVCCAUXRX6 B10 N/A AVCCAUXTX7 B14 N/A VTTXPAD7 B13 N/A TXNPAD7 A13 N/A TXPPAD7 A14 N/A GNDA7 C14 N/A GNDA7 C14 N/A RXPPAD7 A15 N/A RXNPAD7 A16 N/A VTRXPAD7 B15 N/A AVCCAUXRX7 B16 N/A AVCCAUXTX9 B18 NC NC N/A VTTXPAD9 B17 NC NC N/A TXNPAD9 A17 NC NC Bank Pin Description Pin Number N/A DXP C4 N/A DXN C5 N/A AVCCAUXTX4 N/A DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 Module 4 of 4 115 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 N/A TXPPAD9 A18 NC NC N/A GNDA9 C17 NC NC N/A GNDA9 C17 NC NC N/A RXPPAD9 A19 NC NC N/A RXNPAD9 A20 NC NC N/A VTRXPAD9 B19 NC NC N/A AVCCAUXRX9 B20 NC NC N/A AVCCAUXRX16 AA20 NC NC N/A VTRXPAD16 AA19 NC NC N/A RXNPAD16 AB20 NC NC N/A RXPPAD16 AB19 NC NC N/A GNDA16 Y17 NC NC N/A GNDA16 Y17 NC NC N/A TXPPAD16 AB18 NC NC N/A TXNPAD16 AB17 NC NC N/A VTTXPAD16 AA17 NC NC N/A AVCCAUXTX16 AA18 NC NC N/A AVCCAUXRX18 AA16 N/A VTRXPAD18 AA15 N/A RXNPAD18 AB16 N/A RXPPAD18 AB15 N/A GNDA18 Y14 N/A GNDA18 Y14 N/A TXPPAD18 AB14 N/A TXNPAD18 AB13 N/A VTTXPAD18 AA13 N/A AVCCAUXTX18 AA14 N/A AVCCAUXRX19 AA10 N/A VTRXPAD19 AA9 N/A RXNPAD19 AB10 N/A RXPPAD19 AB9 N/A GNDA19 Y9 N/A GNDA19 Y9 N/A TXPPAD19 AB8 N/A TXNPAD19 AB7 Module 4 of 4 116 www.xilinx.com 1-800-255-7778 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects XC2V P2 XC2V P4 AA6 NC NC VTRXPAD21 AA5 NC NC N/A RXNPAD21 AB6 NC NC N/A RXPPAD21 AB5 NC NC N/A GNDA21 Y6 NC NC N/A GNDA21 Y6 NC NC N/A TXPPAD21 AB4 NC NC N/A TXNPAD21 AB3 NC NC N/A VTTXPAD21 AA3 NC NC N/A AVCCAUXTX21 AA4 NC NC N/A VCCINT U6 N/A VCCINT U17 N/A VCCINT T8 N/A VCCINT T7 N/A VCCINT T16 N/A VCCINT T15 N/A VCCINT R7 N/A VCCINT R16 N/A VCCINT H7 N/A VCCINT H16 N/A VCCINT G8 N/A VCCINT G7 N/A VCCINT G16 N/A VCCINT G15 N/A VCCINT F6 N/A VCCINT F17 N/A VCCAUX M22 N/A VCCAUX L1 N/A VCCAUX B21 N/A VCCAUX B2 N/A VCCAUX AB11 N/A VCCAUX AA21 Bank Pin Description Pin Number N/A VTTXPAD19 AA7 N/A AVCCAUXTX19 AA8 N/A AVCCAUXRX21 N/A DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 Module 4 of 4 117 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number N/A VCCAUX AA2 N/A VCCAUX A12 N/A GND Y3 N/A GND Y20 N/A GND W4 N/A GND W19 N/A GND V5 N/A GND V18 N/A GND P9 N/A GND P14 N/A GND P13 N/A GND P12 N/A GND P11 N/A GND P10 N/A GND N9 N/A GND N14 N/A GND N13 N/A GND N12 N/A GND N11 N/A GND N10 N/A GND M9 N/A GND M14 N/A GND M13 N/A GND M12 N/A GND M11 N/A GND M10 N/A GND M1 N/A GND L9 N/A GND L22 N/A GND L14 N/A GND L13 N/A GND L12 N/A GND L11 N/A GND L10 N/A GND K9 Module 4 of 4 118 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 7: FG456 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number N/A GND K14 N/A GND K13 N/A GND K12 N/A GND K11 N/A GND K10 N/A GND J9 N/A GND J14 N/A GND J13 N/A GND J12 N/A GND J11 N/A GND J10 N/A GND E5 N/A GND E18 N/A GND D4 N/A GND D19 N/A GND C3 N/A GND C20 N/A GND AB22 N/A GND AB12 N/A GND AB1 N/A GND A22 N/A GND A11 N/A GND A1 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 Module 4 of 4 119 Virtex-II ProTM Platform FPGAs: Pinout Information R FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 2: FG456 Fine-Pitch BGA Package Specifications Module 4 of 4 120 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information FF672 Flip-Chip Fine-Pitch BGA Package As shown in Table 8, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FF672 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for differences shown in the "No Connects" column. Following this table are the FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 0 IO_L01N_0/VRP_0 B24 0 IO_L01P_0/VRN_0 A24 0 IO_L02N_0 D21 0 IO_L02P_0 C21 0 IO_L03N_0 E20 0 IO_L03P_0/VREF_0 D20 0 IO_L05_0/No_Pair F19 0 IO_L06N_0 E19 0 IO_L06P_0 E18 0 IO_L07N_0 D19 0 IO_L07P_0 C19 0 IO_L08N_0 B19 0 IO_L08P_0 A19 0 IO_L09N_0 G18 0 IO_L09P_0/VREF_0 F18 0 IO_L37N_0 D18 NC NC 0 IO_L37P_0 C18 NC NC 0 IO_L38N_0 G17 NC NC 0 IO_L38P_0 H16 NC NC 0 IO_L39N_0 F17 NC NC 0 IO_L39P_0 F16 NC NC 0 IO_L43N_0 E17 NC NC 0 IO_L43P_0 D17 NC NC 0 IO_L44N_0 G16 NC NC 0 IO_L44P_0 G15 NC NC 0 IO_L45N_0 E16 NC NC 0 IO_L45P_0/VREF_0 D16 NC NC 0 IO_L67N_0 F15 0 IO_L67P_0 E15 0 IO_L68N_0 D15 0 IO_L68P_0 C15 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 Module 4 of 4 121 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 0 IO_L69N_0 H15 0 IO_L69P_0/VREF_0 H14 0 IO_L73N_0 G14 0 IO_L73P_0 F14 0 IO_L74N_0/GCLK7P E14 0 IO_L74P_0/GCLK6S D14 0 IO_L75N_0/GCLK5P C14 0 IO_L75P_0/GCLK4S B14 1 IO_L75N_1/GCLK3P B13 1 IO_L75P_1/GCLK2S C13 1 IO_L74N_1/GCLK1P D13 1 IO_L74P_1/GCLK0S E13 1 IO_L73N_1 F13 1 IO_L73P_1 G13 1 IO_L69N_1/VREF_1 H13 1 IO_L69P_1 H12 1 IO_L68N_1 C12 1 IO_L68P_1 D12 1 IO_L67N_1 E12 1 IO_L67P_1 F12 1 IO_L45N_1/VREF_1 D11 NC NC 1 IO_L45P_1 E11 NC NC 1 IO_L44N_1 G12 NC NC 1 IO_L44P_1 G11 NC NC 1 IO_L43N_1 D10 NC NC 1 IO_L43P_1 E10 NC NC 1 IO_L39N_1 F11 NC NC 1 IO_L39P_1 F10 NC NC 1 IO_L38N_1 H11 NC NC 1 IO_L38P_1 G10 NC NC 1 IO_L37N_1 C9 NC NC 1 IO_L37P_1 D9 NC NC 1 IO_L09N_1/VREF_1 F9 1 IO_L09P_1 G9 Module 4 of 4 122 www.xilinx.com 1-800-255-7778 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 XC2V P7 1 IO_L08N_1 A8 1 IO_L08P_1 B8 1 IO_L07N_1 C8 1 IO_L07P_1 D8 1 IO_L06N_1 E9 1 IO_L06P_1 E8 1 IO_L05_1/No_Pair F8 1 IO_L03N_1/VREF_1 D7 1 IO_L03P_1 E7 1 IO_L02N_1 C6 1 IO_L02P_1 D6 1 IO_L01N_1/VRP_1 A3 1 IO_L01P_1/VRN_1 B3 2 IO_L01N_2/VRP_2 C4 2 IO_L01P_2/VRN_2 D3 2 IO_L02N_2 A2 2 IO_L02P_2 B1 2 IO_L03N_2 C2 2 IO_L03P_2 C1 2 IO_L04N_2/VREF_2 D2 2 IO_L04P_2 D1 2 IO_L05N_2 E4 2 IO_L05P_2 E3 2 IO_L06N_2 E2 2 IO_L06P_2 E1 2 IO_L40N_2/VREF_2 F5 NC NC NC 2 IO_L40P_2 F4 NC NC NC 2 IO_L42N_2 F3 NC NC NC 2 IO_L42P_2 F2 NC NC NC 2 IO_L43N_2 G6 NC 2 IO_L43P_2 G5 NC 2 IO_L44N_2 G4 NC 2 IO_L44P_2 G3 NC 2 IO_L45N_2 F1 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 123 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 2 IO_L45P_2 G1 NC 2 IO_L46N_2/VREF_2 H6 NC 2 IO_L46P_2 H5 NC 2 IO_L47N_2 H4 NC 2 IO_L47P_2 H3 NC 2 IO_L48N_2 H2 NC 2 IO_L48P_2 H1 NC 2 IO_L49N_2 J7 NC 2 IO_L49P_2 J6 NC 2 IO_L50N_2 J5 NC 2 IO_L50P_2 J4 NC 2 IO_L51N_2 J3 NC 2 IO_L51P_2 J2 NC 2 IO_L52N_2/VREF_2 K6 NC 2 IO_L52P_2 K5 NC 2 IO_L53N_2 K4 NC 2 IO_L53P_2 K3 NC 2 IO_L54N_2 J1 NC 2 IO_L54P_2 K1 NC 2 IO_L55N_2 K7 NC 2 IO_L55P_2 L8 NC 2 IO_L56N_2 L7 NC 2 IO_L56P_2 M7 NC 2 IO_L57N_2 L6 NC 2 IO_L57P_2 L5 NC 2 IO_L58N_2/VREF_2 L4 NC 2 IO_L58P_2 L3 NC 2 IO_L59N_2 L2 NC 2 IO_L59P_2 L1 NC 2 IO_L60N_2 M8 NC 2 IO_L60P_2 N8 NC 2 IO_L85N_2 M6 2 IO_L85P_2 M5 2 IO_L86N_2 M4 2 IO_L86P_2 M3 Module 4 of 4 124 www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 2 IO_L87N_2 M2 2 IO_L87P_2 M1 2 IO_L88N_2/VREF_2 N7 2 IO_L88P_2 N6 2 IO_L89N_2 N5 2 IO_L89P_2 N4 2 IO_L90N_2 N3 2 IO_L90P_2 N2 3 IO_L90N_3 P2 3 IO_L90P_3 P3 3 IO_L89N_3 P4 3 IO_L89P_3 P5 3 IO_L88N_3 P6 3 IO_L88P_3 P7 3 IO_L87N_3/VREF_3 R1 3 IO_L87P_3 R2 3 IO_L86N_3 R3 3 IO_L86P_3 R4 3 IO_L85N_3 R5 3 IO_L85P_3 R6 3 IO_L60N_3 P8 NC 3 IO_L60P_3 R8 NC 3 IO_L59N_3 T1 NC 3 IO_L59P_3 T2 NC 3 IO_L58N_3 T3 NC 3 IO_L58P_3 T4 NC 3 IO_L57N_3/VREF_3 T5 NC 3 IO_L57P_3 T6 NC 3 IO_L56N_3 R7 NC 3 IO_L56P_3 T7 NC 3 IO_L55N_3 T8 NC 3 IO_L55P_3 U7 NC 3 IO_L54N_3 U1 NC 3 IO_L54P_3 V1 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 Module 4 of 4 125 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 XC2V P7 3 IO_L53N_3 U3 NC 3 IO_L53P_3 U4 NC 3 IO_L52N_3 U5 NC 3 IO_L52P_3 U6 NC 3 IO_L51N_3/VREF_3 V2 NC 3 IO_L51P_3 V3 NC 3 IO_L50N_3 V4 NC 3 IO_L50P_3 V5 NC 3 IO_L49N_3 V6 NC 3 IO_L49P_3 V7 NC 3 IO_L48N_3 W1 NC 3 IO_L48P_3 W2 NC 3 IO_L47N_3 W3 NC 3 IO_L47P_3 W4 NC 3 IO_L46N_3 W5 NC 3 IO_L46P_3 W6 NC 3 IO_L45N_3/VREF_3 Y1 NC 3 IO_L45P_3 AA1 NC 3 IO_L44N_3 Y3 NC 3 IO_L44P_3 Y4 NC 3 IO_L43N_3 Y5 NC 3 IO_L43P_3 Y6 NC 3 IO_L42N_3 AA2 NC NC NC 3 IO_L42P_3 AA3 NC NC NC 3 IO_L41N_3 AA4 NC NC NC 3 IO_L41P_3 AA5 NC NC NC 3 IO_L39N_3/VREF_3 AB1 NC NC NC 3 IO_L39P_3 AB2 NC NC NC 3 IO_L06N_3 AB3 3 IO_L06P_3 AB4 3 IO_L05N_3 AC1 3 IO_L05P_3 AC2 3 IO_L04N_3 AD1 3 IO_L04P_3 AD2 3 IO_L03N_3/VREF_3 AE1 Module 4 of 4 126 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 3 IO_L03P_3 AF2 3 IO_L02N_3 AC3 3 IO_L02P_3 AD4 3 IO_L01N_3/VRP_3 AE3 3 IO_L01P_3/VRN_3 AF3 4 IO_L01N_4/DOUT AC6 4 IO_L01P_4/INIT_B AD6 4 IO_L02N_4/D0 AB7 4 IO_L02P_4/D1 AC7 4 IO_L03N_4/D2 AA7 4 IO_L03P_4/D3 AA8 4 IO_L05_4/No_Pair Y8 4 IO_L06N_4/VRP_4 AB8 4 IO_L06P_4/VRN_4 AB9 4 IO_L07N_4 AC8 4 IO_L07P_4/VREF_4 AD8 4 IO_L08N_4 AE8 4 IO_L08P_4 AF8 4 IO_L09N_4 Y9 4 IO_L09P_4/VREF_4 AA9 4 IO_L37N_4 AC9 NC NC 4 IO_L37P_4 AD9 NC NC 4 IO_L38N_4 Y10 NC NC 4 IO_L38P_4 W11 NC NC 4 IO_L39N_4 AA10 NC NC 4 IO_L39P_4 AA11 NC NC 4 IO_L43N_4 AB10 NC NC 4 IO_L43P_4 AC10 NC NC 4 IO_L44N_4 Y11 NC NC 4 IO_L44P_4 Y12 NC NC 4 IO_L45N_4 AB11 NC NC 4 IO_L45P_4/VREF_4 AC11 NC NC 4 IO_L67N_4 AA12 4 IO_L67P_4 AB12 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 Module 4 of 4 127 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 4 IO_L68N_4 AC12 4 IO_L68P_4 AD12 4 IO_L69N_4 W12 4 IO_L69P_4/VREF_4 W13 4 IO_L73N_4 Y13 4 IO_L73P_4 AA13 4 IO_L74N_4/GCLK3S AB13 4 IO_L74P_4/GCLK2P AC13 4 IO_L75N_4/GCLK1S AD13 4 IO_L75P_4/GCLK0P AE13 5 IO_L75N_5/GCLK7S AE14 5 IO_L75P_5/GCLK6P AD14 5 IO_L74N_5/GCLK5S AC14 5 IO_L74P_5/GCLK4P AB14 5 IO_L73N_5 AA14 5 IO_L73P_5 Y14 5 IO_L69N_5/VREF_5 W14 5 IO_L69P_5 W15 5 IO_L68N_5 AD15 5 IO_L68P_5 AC15 5 IO_L67N_5 AB15 5 IO_L67P_5 AA15 5 IO_L45N_5/VREF_5 AC16 NC NC 5 IO_L45P_5 AB16 NC NC 5 IO_L44N_5 Y15 NC NC 5 IO_L44P_5 Y16 NC NC 5 IO_L43N_5 AC17 NC NC 5 IO_L43P_5 AB17 NC NC 5 IO_L39N_5 AA16 NC NC 5 IO_L39P_5 AA17 NC NC 5 IO_L38N_5 W16 NC NC 5 IO_L38P_5 Y17 NC NC 5 IO_L37N_5 AD18 NC NC 5 IO_L37P_5 AC18 NC NC Module 4 of 4 128 www.xilinx.com 1-800-255-7778 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 XC2V P7 5 IO_L09N_5/VREF_5 AA18 5 IO_L09P_5 Y18 5 IO_L08N_5 AF19 5 IO_L08P_5 AE19 5 IO_L07N_5/VREF_5 AD19 5 IO_L07P_5 AC19 5 IO_L06N_5/VRP_5 AB18 5 IO_L06P_5/VRN_5 AB19 5 IO_L05_5/No_Pair Y19 5 IO_L03N_5/D4 AA19 5 IO_L03P_5/D5 AA20 5 IO_L02N_5/D6 AC20 5 IO_L02P_5/D7 AB20 5 IO_L01N_5/RDWR_B AD21 5 IO_L01P_5/CS_B AC21 6 IO_L01P_6/VRN_6 AF24 6 IO_L01N_6/VRP_6 AE24 6 IO_L02P_6 AD23 6 IO_L02N_6 AC24 6 IO_L03P_6 AE26 6 IO_L03N_6/VREF_6 AF25 6 IO_L04P_6 AD25 6 IO_L04N_6 AD26 6 IO_L05P_6 AC25 6 IO_L05N_6 AC26 6 IO_L06P_6 AB23 6 IO_L06N_6 AB24 6 IO_L39P_6 AB25 NC NC NC 6 IO_L39N_6/VREF_6 AB26 NC NC NC 6 IO_L41P_6 AA22 NC NC NC 6 IO_L41N_6 AA23 NC NC NC 6 IO_L42P_6 AA24 NC NC NC 6 IO_L42N_6 AA25 NC NC NC 6 IO_L43P_6 Y21 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 129 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 6 IO_L43N_6 Y22 NC 6 IO_L44P_6 Y23 NC 6 IO_L44N_6 Y24 NC 6 IO_L45P_6 AA26 NC 6 IO_L45N_6/VREF_6 Y26 NC 6 IO_L46P_6 W21 NC 6 IO_L46N_6 W22 NC 6 IO_L47P_6 W23 NC 6 IO_L47N_6 W24 NC 6 IO_L48P_6 W25 NC 6 IO_L48N_6 W26 NC 6 IO_L49P_6 V20 NC 6 IO_L49N_6 V21 NC 6 IO_L50P_6 V22 NC 6 IO_L50N_6 V23 NC 6 IO_L51P_6 V24 NC 6 IO_L51N_6/VREF_6 V25 NC 6 IO_L52P_6 U21 NC 6 IO_L52N_6 U22 NC 6 IO_L53P_6 U23 NC 6 IO_L53N_6 U24 NC 6 IO_L54P_6 V26 NC 6 IO_L54N_6 U26 NC 6 IO_L55P_6 U20 NC 6 IO_L55N_6 T19 NC 6 IO_L56P_6 T20 NC 6 IO_L56N_6 R20 NC 6 IO_L57P_6 T21 NC 6 IO_L57N_6/VREF_6 T22 NC 6 IO_L58P_6 T23 NC 6 IO_L58N_6 T24 NC 6 IO_L59P_6 T25 NC 6 IO_L59N_6 T26 NC 6 IO_L60P_6 R19 NC 6 IO_L60N_6 P19 NC Module 4 of 4 130 www.xilinx.com 1-800-255-7778 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 6 IO_L85P_6 R21 6 IO_L85N_6 R22 6 IO_L86P_6 R23 6 IO_L86N_6 R24 6 IO_L87P_6 R25 6 IO_L87N_6/VREF_6 R26 6 IO_L88P_6 P20 6 IO_L88N_6 P21 6 IO_L89P_6 P22 6 IO_L89N_6 P23 6 IO_L90P_6 P24 6 IO_L90N_6 P25 7 IO_L90P_7 N25 7 IO_L90N_7 N24 7 IO_L89P_7 N23 7 IO_L89N_7 N22 7 IO_L88P_7 N21 7 IO_L88N_7/VREF_7 N20 7 IO_L87P_7 M26 7 IO_L87N_7 M25 7 IO_L86P_7 M24 7 IO_L86N_7 M23 7 IO_L85P_7 M22 7 IO_L85N_7 M21 7 IO_L60P_7 N19 NC 7 IO_L60N_7 M19 NC 7 IO_L59P_7 L26 NC 7 IO_L59N_7 L25 NC 7 IO_L58P_7 L24 NC 7 IO_L58N_7/VREF_7 L23 NC 7 IO_L57P_7 L22 NC 7 IO_L57N_7 L21 NC 7 IO_L56P_7 M20 NC 7 IO_L56N_7 L20 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 Module 4 of 4 131 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 XC2V P7 7 IO_L55P_7 L19 NC 7 IO_L55N_7 K20 NC 7 IO_L54P_7 K26 NC 7 IO_L54N_7 J26 NC 7 IO_L53P_7 K24 NC 7 IO_L53N_7 K23 NC 7 IO_L52P_7 K22 NC 7 IO_L52N_7/VREF_7 K21 NC 7 IO_L51P_7 J25 NC 7 IO_L51N_7 J24 NC 7 IO_L50P_7 J23 NC 7 IO_L50N_7 J22 NC 7 IO_L49P_7 J21 NC 7 IO_L49N_7 J20 NC 7 IO_L48P_7 H26 NC 7 IO_L48N_7 H25 NC 7 IO_L47P_7 H24 NC 7 IO_L47N_7 H23 NC 7 IO_L46P_7 H22 NC 7 IO_L46N_7/VREF_7 H21 NC 7 IO_L45P_7 G26 NC 7 IO_L45N_7 F26 NC 7 IO_L44P_7 G24 NC 7 IO_L44N_7 G23 NC 7 IO_L43P_7 G22 NC 7 IO_L43N_7 G21 NC 7 IO_L42P_7 F25 NC NC NC 7 IO_L42N_7 F24 NC NC NC 7 IO_L40P_7 F23 NC NC NC 7 IO_L40N_7/VREF_7 F22 NC NC NC 7 IO_L06P_7 E26 7 IO_L06N_7 E25 7 IO_L05P_7 E24 7 IO_L05N_7 E23 7 IO_L04P_7 D26 Module 4 of 4 132 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 7 IO_L04N_7/VREF_7 D25 7 IO_L03P_7 C26 7 IO_L03N_7 C25 7 IO_L02P_7 B26 7 IO_L02N_7 A25 7 IO_L01P_7/VRN_7 D24 7 IO_L01N_7/VRP_7 C23 0 VCCO_0 C17 0 VCCO_0 C20 0 VCCO_0 H17 0 VCCO_0 H18 0 VCCO_0 J14 0 VCCO_0 J15 0 VCCO_0 J16 1 VCCO_1 C7 1 VCCO_1 H9 1 VCCO_1 C10 1 VCCO_1 H10 1 VCCO_1 J11 1 VCCO_1 J12 1 VCCO_1 J13 2 VCCO_2 G2 2 VCCO_2 J8 2 VCCO_2 K2 2 VCCO_2 K8 2 VCCO_2 L9 2 VCCO_2 M9 2 VCCO_2 N9 3 VCCO_3 P9 3 VCCO_3 R9 3 VCCO_3 T9 3 VCCO_3 U2 3 VCCO_3 U8 3 VCCO_3 V8 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 Module 4 of 4 133 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number 3 VCCO_3 Y2 4 VCCO_4 W9 4 VCCO_4 AD7 4 VCCO_4 V11 4 VCCO_4 V12 4 VCCO_4 V13 4 VCCO_4 W10 4 VCCO_4 AD10 5 VCCO_5 V14 5 VCCO_5 V15 5 VCCO_5 V16 5 VCCO_5 W17 5 VCCO_5 W18 5 VCCO_5 AD17 5 VCCO_5 AD20 6 VCCO_6 P18 6 VCCO_6 R18 6 VCCO_6 T18 6 VCCO_6 U19 6 VCCO_6 U25 6 VCCO_6 V19 6 VCCO_6 Y25 7 VCCO_7 G25 7 VCCO_7 J19 7 VCCO_7 K19 7 VCCO_7 K25 7 VCCO_7 L18 7 VCCO_7 M18 7 VCCO_7 N18 N/A CCLK W7 N/A PROG_B D22 N/A DONE AB6 N/A M0 AC22 N/A M1 W20 Module 4 of 4 134 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 N/A M2 AB21 N/A TCK G8 N/A TDI H20 N/A TDO H7 N/A TMS F7 N/A PWRDWN_B AC5 N/A HSWAP_EN E21 N/A RSVD D5 N/A VBATT E6 N/A DXP F20 N/A DXN G19 N/A AVCCAUXTX7 B11 N/A VTTXPAD7 B12 N/A TXNPAD7 A12 N/A TXPPAD7 A11 N/A GNDA7 C11 N/A GNDA7 C11 N/A RXPPAD7 A10 N/A RXNPAD7 A9 N/A VTRXPAD7 B10 N/A AVCCAUXRX7 B9 N/A AVCCAUXTX9 B6 NC NC N/A VTTXPAD9 B7 NC NC N/A TXNPAD9 A7 NC NC N/A TXPPAD9 A6 NC NC N/A GNDA9 C5 NC NC N/A GNDA9 C5 NC NC N/A RXPPAD9 A5 NC NC N/A RXNPAD9 A4 NC NC N/A VTRXPAD9 B5 NC NC N/A AVCCAUXRX9 B4 NC NC N/A AVCCAUXRX16 AE4 NC NC N/A VTRXPAD16 AE5 NC NC N/A RXNPAD16 AF4 NC NC N/A RXPPAD16 AF5 NC NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 Module 4 of 4 135 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 N/A GNDA16 AD5 NC NC N/A GNDA16 AD5 NC NC N/A TXPPAD16 AF6 NC NC N/A TXNPAD16 AF7 NC NC N/A VTTXPAD16 AE7 NC NC N/A AVCCAUXTX16 AE6 NC NC N/A AVCCAUXRX18 AE9 N/A VTRXPAD18 AE10 N/A RXNPAD18 AF9 N/A RXPPAD18 AF10 N/A GNDA18 AD11 N/A GNDA18 AD11 N/A TXPPAD18 AF11 N/A TXNPAD18 AF12 N/A VTTXPAD18 AE12 N/A AVCCAUXTX18 AE11 N/A AVCCAUXTX4 B22 NC NC N/A VTTXPAD4 B23 NC NC N/A TXNPAD4 A23 NC NC N/A TXPPAD4 A22 NC NC N/A GNDA4 C22 NC NC N/A GNDA4 C22 NC NC N/A RXPPAD4 A21 NC NC N/A RXNPAD4 A20 NC NC N/A VTRXPAD4 B21 NC NC N/A AVCCAUXRX4 B20 NC NC N/A AVCCAUXTX6 B17 N/A VTTXPAD6 B18 N/A TXNPAD6 A18 N/A TXPPAD6 A17 N/A GNDA6 C16 N/A GNDA6 C16 N/A RXPPAD6 A16 N/A RXNPAD6 A15 N/A VTRXPAD6 B16 Module 4 of 4 136 www.xilinx.com 1-800-255-7778 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number XC2V P2 XC2V P4 N/A AVCCAUXRX6 B15 N/A AVCCAUXRX19 AE15 N/A VTRXPAD19 AE16 N/A RXNPAD19 AF15 N/A RXPPAD19 AF16 N/A GNDA19 AD16 N/A GNDA19 AD16 N/A TXPPAD19 AF17 N/A TXNPAD19 AF18 N/A VTTXPAD19 AE18 N/A AVCCAUXTX19 AE17 N/A AVCCAUXRX21 AE20 NC NC N/A VTRXPAD21 AE21 NC NC N/A RXNPAD21 AF20 NC NC N/A RXPPAD21 AF21 NC NC N/A GNDA21 AD22 NC NC N/A GNDA21 AD22 NC NC N/A TXPPAD21 AF22 NC NC N/A TXNPAD21 AF23 NC NC N/A VTTXPAD21 AE23 NC NC N/A AVCCAUXTX21 AE22 NC NC N/A VCCINT H8 N/A VCCINT J9 N/A VCCINT K9 N/A VCCINT U9 N/A VCCINT V9 N/A VCCINT W8 N/A VCCINT H19 N/A VCCINT J10 N/A VCCINT J17 N/A VCCINT J18 N/A VCCINT K11 N/A VCCINT K16 N/A VCCINT K18 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 Module 4 of 4 137 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number N/A VCCINT L10 N/A VCCINT L17 N/A VCCINT T10 N/A VCCINT T17 N/A VCCINT U11 N/A VCCINT U16 N/A VCCINT U18 N/A VCCINT V10 N/A VCCINT V17 N/A VCCINT V18 N/A VCCINT W19 N/A VCCAUX B2 N/A VCCAUX N1 N/A VCCAUX P1 N/A VCCAUX A13 N/A VCCAUX A14 N/A VCCAUX AE2 N/A VCCAUX B25 N/A VCCAUX N26 N/A VCCAUX P26 N/A VCCAUX AE25 N/A VCCAUX AF13 N/A VCCAUX AF14 N/A GND C3 N/A GND D4 N/A GND E5 N/A GND F6 N/A GND G7 N/A GND Y7 N/A GND AA6 N/A GND AB5 N/A GND AC4 N/A GND AD3 N/A GND C24 N/A GND D23 Module 4 of 4 138 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number N/A GND E22 N/A GND F21 N/A GND G20 N/A GND K10 N/A GND K12 N/A GND K13 N/A GND K14 N/A GND K15 N/A GND K17 N/A GND L11 N/A GND L12 N/A GND L13 N/A GND L14 N/A GND L15 N/A GND L16 N/A GND M10 N/A GND M11 N/A GND M12 N/A GND M13 N/A GND M14 N/A GND M15 N/A GND M16 N/A GND M17 N/A GND N10 N/A GND N11 N/A GND N12 N/A GND N13 N/A GND N14 N/A GND N15 N/A GND N16 N/A GND N17 N/A GND P10 N/A GND P11 N/A GND P12 N/A GND P13 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 Module 4 of 4 139 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 8: FF672 -- XC2VP2, XC2VP4, and XC2VP7 No Connects Bank Pin Description Pin Number N/A GND P14 N/A GND P15 N/A GND P16 N/A GND P17 N/A GND R10 N/A GND R11 N/A GND R12 N/A GND R13 N/A GND R14 N/A GND R15 N/A GND R16 N/A GND R17 N/A GND T11 N/A GND T12 N/A GND T13 N/A GND T14 N/A GND T15 N/A GND T16 N/A GND U10 N/A GND U12 N/A GND U13 N/A GND U14 N/A GND U15 N/A GND U17 N/A GND Y20 N/A GND AA21 N/A GND AB22 N/A GND AC23 N/A GND AD24 Module 4 of 4 140 www.xilinx.com 1-800-255-7778 XC2V P2 XC2V P4 XC2V P7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 3: FF672 Flip-Chip Fine-Pitch BGA Package Specifications DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 141 R Virtex-II ProTM Platform FPGAs: Pinout Information FF896 Flip-Chip Fine-Pitch BGA Package As shown in Table 9, the XC2VP7 and XC2VP20 Virtex-II Pro devices are available in the FF896 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for differences shown in the "No Connects" column. Following this table are the FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 E25 0 IO_L01P_0/VRN_0 E24 0 IO_L02N_0 F24 0 IO_L02P_0 F23 0 IO_L03N_0 E23 0 IO_L03P_0/VREF_0 E22 0 IO_L05_0/No_Pair G23 0 IO_L06N_0 H22 0 IO_L06P_0 G22 0 IO_L07N_0 F22 0 IO_L07P_0 F21 0 IO_L08N_0 D24 0 IO_L08P_0 C24 0 IO_L09N_0 H21 0 IO_L09P_0/VREF_0 G21 0 IO_L37N_0 E21 0 IO_L37P_0 D21 0 IO_L38N_0 D23 0 IO_L38P_0 C23 0 IO_L39N_0 H20 0 IO_L39P_0 G20 0 IO_L43N_0 E20 0 IO_L43P_0 D20 0 IO_L44N_0 B23 0 IO_L44P_0 A23 0 IO_L45N_0 H19 0 IO_L45P_0/VREF_0 G19 0 IO_L46N_0 E19 NC 0 IO_L46P_0 E18 NC 0 IO_L47N_0 C22 NC 0 IO_L47P_0 B22 NC 0 IO_L48N_0 F20 NC 0 IO_L48P_0 F19 NC Module 4 of 4 142 www.xilinx.com 1-800-255-7778 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number XC2V P7 0 IO_L49N_0 G17 NC 0 IO_L49P_0 F17 NC 0 IO_L50_0/No_Pair B21 NC 0 IO_L53_0/No_Pair A21 NC 0 IO_L54N_0 H18 NC 0 IO_L54P_0 G18 NC 0 IO_L56N_0 C21 NC 0 IO_L56P_0 C20 NC 0 IO_L57N_0 J17 NC 0 IO_L57P_0/VREF_0 H17 NC 0 IO_L67N_0 E17 0 IO_L67P_0 D17 0 IO_L68N_0 D18 0 IO_L68P_0 C18 0 IO_L69N_0 J16 0 IO_L69P_0/VREF_0 H16 0 IO_L73N_0 E16 0 IO_L73P_0 D16 0 IO_L74N_0/GCLK7P C16 0 IO_L74P_0/GCLK6S B16 0 IO_L75N_0/GCLK5P G16 0 IO_L75P_0/GCLK4S F16 1 IO_L75N_1/GCLK3P F15 1 IO_L75P_1/GCLK2S G15 1 IO_L74N_1/GCLK1P B15 1 IO_L74P_1/GCLK0S C15 1 IO_L73N_1 D15 1 IO_L73P_1 E15 1 IO_L69N_1/VREF_1 H15 1 IO_L69P_1 J15 1 IO_L68N_1 C13 1 IO_L68P_1 D13 1 IO_L67N_1 D14 1 IO_L67P_1 E14 1 IO_L57N_1/VREF_1 H14 NC 1 IO_L57P_1 J14 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 Module 4 of 4 143 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number XC2V P7 1 IO_L56N_1 C11 NC 1 IO_L56P_1 C10 NC 1 IO_L54N_1 G13 NC 1 IO_L54P_1 H13 NC 1 IO_L53_1/No_Pair A10 NC 1 IO_L50_1/No_Pair B10 NC 1 IO_L49N_1 F14 NC 1 IO_L49P_1 G14 NC 1 IO_L48N_1 F12 NC 1 IO_L48P_1 F11 NC 1 IO_L47N_1 B9 NC 1 IO_L47P_1 C9 NC 1 IO_L46N_1 E13 NC 1 IO_L46P_1 E12 NC 1 IO_L45N_1/VREF_1 G12 1 IO_L45P_1 H12 1 IO_L44N_1 A8 1 IO_L44P_1 B8 1 IO_L43N_1 D11 1 IO_L43P_1 E11 1 IO_L39N_1 G11 1 IO_L39P_1 H11 1 IO_L38N_1 C8 1 IO_L38P_1 D8 1 IO_L37N_1 D10 1 IO_L37P_1 E10 1 IO_L09N_1/VREF_1 G10 1 IO_L09P_1 H10 1 IO_L08N_1 C7 1 IO_L08P_1 D7 1 IO_L07N_1 F10 1 IO_L07P_1 F9 1 IO_L06N_1 G9 1 IO_L06P_1 H9 1 IO_L05_1/No_Pair G8 1 IO_L03N_1/VREF_1 E9 1 IO_L03P_1 E8 Module 4 of 4 144 www.xilinx.com 1-800-255-7778 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 1 IO_L02N_1 F8 1 IO_L02P_1 F7 1 IO_L01N_1/VRP_1 E7 1 IO_L01P_1/VRN_1 E6 2 IO_L01N_2/VRP_2 A3 2 IO_L01P_2/VRN_2 B3 2 IO_L02N_2 G6 2 IO_L02P_2 G5 2 IO_L03N_2 C5 2 IO_L03P_2 D5 2 IO_L04N_2/VREF_2 C2 2 IO_L04P_2 C1 2 IO_L05N_2 J8 2 IO_L05P_2 J7 2 IO_L06N_2 C4 2 IO_L06P_2 D3 2 IO_L31N_2 D2 NC 2 IO_L31P_2 D1 NC 2 IO_L32N_2 H6 NC 2 IO_L32P_2 H5 NC 2 IO_L33N_2 E4 NC 2 IO_L33P_2 E3 NC 2 IO_L34N_2/VREF_2 E2 NC 2 IO_L34P_2 E1 NC 2 IO_L35N_2 K8 NC 2 IO_L35P_2 K7 NC 2 IO_L36N_2 F4 NC 2 IO_L36P_2 F3 NC 2 IO_L37N_2 F2 NC 2 IO_L37P_2 F1 NC 2 IO_L38N_2 J6 NC 2 IO_L38P_2 J5 NC 2 IO_L39N_2 G4 NC 2 IO_L39P_2 G3 NC 2 IO_L40N_2/VREF_2 G2 NC 2 IO_L40P_2 G1 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 Module 4 of 4 145 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number XC2V P7 2 IO_L41N_2 L8 NC 2 IO_L41P_2 L7 NC 2 IO_L42N_2 H4 NC 2 IO_L42P_2 H3 NC 2 IO_L43N_2 H2 2 IO_L43P_2 J2 2 IO_L44N_2 M8 2 IO_L44P_2 M7 2 IO_L45N_2 K6 2 IO_L45P_2 K5 2 IO_L46N_2/VREF_2 J1 2 IO_L46P_2 K1 2 IO_L47N_2 M6 2 IO_L47P_2 M5 2 IO_L48N_2 J4 2 IO_L48P_2 J3 2 IO_L49N_2 K2 2 IO_L49P_2 L2 2 IO_L50N_2 N8 2 IO_L50P_2 N7 2 IO_L51N_2 K4 2 IO_L51P_2 K3 2 IO_L52N_2/VREF_2 L1 2 IO_L52P_2 M1 2 IO_L53N_2 N6 2 IO_L53P_2 N5 2 IO_L54N_2 L5 2 IO_L54P_2 L4 2 IO_L55N_2 M2 2 IO_L55P_2 N2 2 IO_L56N_2 P9 2 IO_L56P_2 R9 2 IO_L57N_2 M4 2 IO_L57P_2 M3 2 IO_L58N_2/VREF_2 N1 2 IO_L58P_2 P1 2 IO_L59N_2 P8 Module 4 of 4 146 www.xilinx.com 1-800-255-7778 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 2 IO_L59P_2 P7 2 IO_L60N_2 N4 2 IO_L60P_2 N3 2 IO_L85N_2 P3 2 IO_L85P_2 P2 2 IO_L86N_2 R8 2 IO_L86P_2 R7 2 IO_L87N_2 P5 2 IO_L87P_2 P4 2 IO_L88N_2/VREF_2 R2 2 IO_L88P_2 T2 2 IO_L89N_2 R6 2 IO_L89P_2 R5 2 IO_L90N_2 R4 2 IO_L90P_2 R3 3 IO_L90N_3 U1 3 IO_L90P_3 V1 3 IO_L89N_3 T5 3 IO_L89P_3 T6 3 IO_L88N_3 T3 3 IO_L88P_3 T4 3 IO_L87N_3/VREF_3 U2 3 IO_L87P_3 U3 3 IO_L86N_3 T7 3 IO_L86P_3 T8 3 IO_L85N_3 U4 3 IO_L85P_3 U5 3 IO_L60N_3 V2 3 IO_L60P_3 W2 3 IO_L59N_3 T9 3 IO_L59P_3 U9 3 IO_L58N_3 V3 3 IO_L58P_3 V4 3 IO_L57N_3/VREF_3 W1 3 IO_L57P_3 Y1 3 IO_L56N_3 U7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 147 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 3 IO_L56P_3 U8 3 IO_L55N_3 V5 3 IO_L55P_3 V6 3 IO_L54N_3 Y2 3 IO_L54P_3 AA2 3 IO_L53N_3 V7 3 IO_L53P_3 V8 3 IO_L52N_3 W3 3 IO_L52P_3 W4 3 IO_L51N_3/VREF_3 AA1 3 IO_L51P_3 AB1 3 IO_L50N_3 W5 3 IO_L50P_3 W6 3 IO_L49N_3 Y4 3 IO_L49P_3 Y5 3 IO_L48N_3 AA3 3 IO_L48P_3 AA4 3 IO_L47N_3 W7 3 IO_L47P_3 W8 3 IO_L46N_3 AB3 3 IO_L46P_3 AB4 3 IO_L45N_3/VREF_3 AB2 3 IO_L45P_3 AC2 3 IO_L44N_3 AA5 3 IO_L44P_3 AA6 3 IO_L43N_3 AC3 3 IO_L43P_3 AC4 3 IO_L42N_3 AD1 NC 3 IO_L42P_3 AD2 NC 3 IO_L41N_3 Y7 NC 3 IO_L41P_3 Y8 NC 3 IO_L40N_3 AB5 NC 3 IO_L40P_3 AB6 NC 3 IO_L39N_3/VREF_3 AE1 NC 3 IO_L39P_3 AE2 NC 3 IO_L38N_3 AA7 NC 3 IO_L38P_3 AA8 NC Module 4 of 4 148 www.xilinx.com 1-800-255-7778 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number XC2V P7 3 IO_L37N_3 AD3 NC 3 IO_L37P_3 AD4 NC 3 IO_L36N_3 AF1 NC 3 IO_L36P_3 AF2 NC 3 IO_L35N_3 AC5 NC 3 IO_L35P_3 AC6 NC 3 IO_L34N_3 AF3 NC 3 IO_L34P_3 AF4 NC 3 IO_L33N_3/VREF_3 AE3 NC 3 IO_L33P_3 AE4 NC 3 IO_L32N_3 AB7 NC 3 IO_L32P_3 AB8 NC 3 IO_L31N_3 AE5 NC 3 IO_L31P_3 AF6 NC 3 IO_L06N_3 AG1 3 IO_L06P_3 AG2 3 IO_L05N_3 AD5 3 IO_L05P_3 AD6 3 IO_L04N_3 AG3 3 IO_L04P_3 AH4 3 IO_L03N_3/VREF_3 AH1 3 IO_L03P_3 AH2 3 IO_L02N_3 AG5 3 IO_L02P_3 AH5 3 IO_L01N_3/VRP_3 AJ3 3 IO_L01P_3/VRN_3 AK3 4 IO_L01N_4/DOUT AG6 4 IO_L01P_4/INIT_B AF7 4 IO_L02N_4/D0 AC9 4 IO_L02P_4/D1 AD9 4 IO_L03N_4/D2 AG7 4 IO_L03P_4/D3 AH7 4 IO_L05_4/No_Pair AD8 4 IO_L06N_4/VRP_4 AG8 4 IO_L06P_4/VRN_4 AH8 4 IO_L07N_4 AC10 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 Module 4 of 4 149 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 4 IO_L07P_4/VREF_4 AD10 4 IO_L08N_4 AE7 4 IO_L08P_4 AE8 4 IO_L09N_4 AJ8 4 IO_L09P_4/VREF_4 AK8 4 IO_L37N_4 AC11 4 IO_L37P_4 AD11 4 IO_L38N_4 AF8 4 IO_L38P_4 AF9 4 IO_L39N_4 AF10 4 IO_L39P_4 AG10 4 IO_L43N_4 AC12 4 IO_L43P_4 AD12 4 IO_L44N_4 AE9 4 IO_L44P_4 AE10 4 IO_L45N_4 AH9 4 IO_L45P_4/VREF_4 AJ9 4 IO_L46N_4 AC13 NC 4 IO_L46P_4 AD13 NC 4 IO_L47N_4 AE11 NC 4 IO_L47P_4 AE12 NC 4 IO_L48N_4 AH10 NC 4 IO_L48P_4 AH11 NC 4 IO_L49N_4 AB14 NC 4 IO_L49P_4 AC14 NC 4 IO_L50_4/No_Pair AF11 NC 4 IO_L53_4/No_Pair AG11 NC 4 IO_L54N_4 AJ10 NC 4 IO_L54P_4 AK10 NC 4 IO_L56N_4 AF12 NC 4 IO_L56P_4 AF13 NC 4 IO_L57N_4 AG13 NC 4 IO_L57P_4/VREF_4 AH13 NC 4 IO_L67N_4 AB15 4 IO_L67P_4 AC15 4 IO_L68N_4 AD14 4 IO_L68P_4 AE14 Module 4 of 4 150 www.xilinx.com 1-800-255-7778 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 4 IO_L69N_4 AF14 4 IO_L69P_4/VREF_4 AG14 4 IO_L73N_4 AD15 4 IO_L73P_4 AE15 4 IO_L74N_4/GCLK3S AF15 4 IO_L74P_4/GCLK2P AG15 4 IO_L75N_4/GCLK1S AH15 4 IO_L75P_4/GCLK0P AJ15 5 IO_L75N_5/GCLK7S AJ16 5 IO_L75P_5/GCLK6P AH16 5 IO_L74N_5/GCLK5S AG16 5 IO_L74P_5/GCLK4P AF16 5 IO_L73N_5 AE16 5 IO_L73P_5 AD16 5 IO_L69N_5/VREF_5 AG17 5 IO_L69P_5 AF17 5 IO_L68N_5 AE17 5 IO_L68P_5 AD17 5 IO_L67N_5 AC16 5 IO_L67P_5 AB16 5 IO_L57N_5/VREF_5 AH18 NC 5 IO_L57P_5 AG18 NC 5 IO_L56N_5 AF18 NC 5 IO_L56P_5 AF19 NC 5 IO_L54N_5 AK21 NC 5 IO_L54P_5 AJ21 NC 5 IO_L53_5/No_Pair AG20 NC 5 IO_L50_5/No_Pair AF20 NC 5 IO_L49N_5 AC17 NC 5 IO_L49P_5 AB17 NC 5 IO_L48N_5 AH20 NC 5 IO_L48P_5 AH21 NC 5 IO_L47N_5 AE19 NC 5 IO_L47P_5 AE20 NC 5 IO_L46N_5 AD18 NC 5 IO_L46P_5 AC18 NC DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 Module 4 of 4 151 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 5 IO_L45N_5/VREF_5 AJ22 5 IO_L45P_5 AH22 5 IO_L44N_5 AE21 5 IO_L44P_5 AE22 5 IO_L43N_5 AD19 5 IO_L43P_5 AC19 5 IO_L39N_5 AG21 5 IO_L39P_5 AF21 5 IO_L38N_5 AF22 5 IO_L38P_5 AF23 5 IO_L37N_5 AD20 5 IO_L37P_5 AC20 5 IO_L09N_5/VREF_5 AK23 5 IO_L09P_5 AJ23 5 IO_L08N_5 AE23 5 IO_L08P_5 AE24 5 IO_L07N_5/VREF_5 AD21 5 IO_L07P_5 AC21 5 IO_L06N_5/VRP_5 AH23 5 IO_L06P_5/VRN_5 AG23 5 IO_L05_5/No_Pair AD23 5 IO_L03N_5/D4 AH24 5 IO_L03P_5/D5 AG24 5 IO_L02N_5/D6 AD22 5 IO_L02P_5/D7 AC22 5 IO_L01N_5/RDWR_B AF24 5 IO_L01P_5/CS_B AG25 6 IO_L01P_6/VRN_6 AK28 6 IO_L01N_6/VRP_6 AJ28 6 IO_L02P_6 AH26 6 IO_L02N_6 AG26 6 IO_L03P_6 AH29 6 IO_L03N_6/VREF_6 AH30 6 IO_L04P_6 AH27 6 IO_L04N_6 AG28 6 IO_L05P_6 AD25 Module 4 of 4 152 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 6 IO_L05N_6 AD26 6 IO_L06P_6 AG29 6 IO_L06N_6 AG30 6 IO_L31P_6 AF25 NC 6 IO_L31N_6 AE26 NC 6 IO_L32P_6 AB23 NC 6 IO_L32N_6 AB24 NC 6 IO_L33P_6 AE27 NC 6 IO_L33N_6/VREF_6 AE28 NC 6 IO_L34P_6 AF27 NC 6 IO_L34N_6 AF28 NC 6 IO_L35P_6 AC25 NC 6 IO_L35N_6 AC26 NC 6 IO_L36P_6 AF29 NC 6 IO_L36N_6 AF30 NC 6 IO_L37P_6 AD27 NC 6 IO_L37N_6 AD28 NC 6 IO_L38P_6 AA23 NC 6 IO_L38N_6 AA24 NC 6 IO_L39P_6 AE29 NC 6 IO_L39N_6/VREF_6 AE30 NC 6 IO_L40P_6 AB25 NC 6 IO_L40N_6 AB26 NC 6 IO_L41P_6 Y23 NC 6 IO_L41N_6 Y24 NC 6 IO_L42P_6 AD29 NC 6 IO_L42N_6 AD30 NC 6 IO_L43P_6 AC27 6 IO_L43N_6 AC28 6 IO_L44P_6 AA25 6 IO_L44N_6 AA26 6 IO_L45P_6 AC29 6 IO_L45N_6/VREF_6 AB29 6 IO_L46P_6 AB27 6 IO_L46N_6 AB28 6 IO_L47P_6 W23 6 IO_L47N_6 W24 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 Module 4 of 4 153 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 6 IO_L48P_6 AA27 6 IO_L48N_6 AA28 6 IO_L49P_6 Y26 6 IO_L49N_6 Y27 6 IO_L50P_6 W25 6 IO_L50N_6 W26 6 IO_L51P_6 AB30 6 IO_L51N_6/VREF_6 AA30 6 IO_L52P_6 W27 6 IO_L52N_6 W28 6 IO_L53P_6 V23 6 IO_L53N_6 V24 6 IO_L54P_6 AA29 6 IO_L54N_6 Y29 6 IO_L55P_6 V25 6 IO_L55N_6 V26 6 IO_L56P_6 U23 6 IO_L56N_6 U24 6 IO_L57P_6 Y30 6 IO_L57N_6/VREF_6 W30 6 IO_L58P_6 V27 6 IO_L58N_6 V28 6 IO_L59P_6 U22 6 IO_L59N_6 T22 6 IO_L60P_6 W29 6 IO_L60N_6 V29 6 IO_L85P_6 U26 6 IO_L85N_6 U27 6 IO_L86P_6 T23 6 IO_L86N_6 T24 6 IO_L87P_6 U28 6 IO_L87N_6/VREF_6 U29 6 IO_L88P_6 T27 6 IO_L88N_6 T28 6 IO_L89P_6 T25 6 IO_L89N_6 T26 6 IO_L90P_6 V30 Module 4 of 4 154 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 6 IO_L90N_6 U30 7 IO_L90P_7 R28 7 IO_L90N_7 R27 7 IO_L89P_7 R26 7 IO_L89N_7 R25 7 IO_L88P_7 T29 7 IO_L88N_7/VREF_7 R29 7 IO_L87P_7 P27 7 IO_L87N_7 P26 7 IO_L86P_7 R24 7 IO_L86N_7 R23 7 IO_L85P_7 P29 7 IO_L85N_7 P28 7 IO_L60P_7 N28 7 IO_L60N_7 N27 7 IO_L59P_7 P24 7 IO_L59N_7 P23 7 IO_L58P_7 P30 7 IO_L58N_7/VREF_7 N30 7 IO_L57P_7 M28 7 IO_L57N_7 M27 7 IO_L56P_7 R22 7 IO_L56N_7 P22 7 IO_L55P_7 N29 7 IO_L55N_7 M29 7 IO_L54P_7 L27 7 IO_L54N_7 L26 7 IO_L53P_7 N26 7 IO_L53N_7 N25 7 IO_L52P_7 M30 7 IO_L52N_7/VREF_7 L30 7 IO_L51P_7 K28 7 IO_L51N_7 K27 7 IO_L50P_7 N24 7 IO_L50N_7 N23 7 IO_L49P_7 L29 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 155 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects XC2V P7 Bank Pin Description Pin Number 7 IO_L49N_7 K29 7 IO_L48P_7 J28 7 IO_L48N_7 J27 7 IO_L47P_7 M26 7 IO_L47N_7 M25 7 IO_L46P_7 K30 7 IO_L46N_7/VREF_7 J30 7 IO_L45P_7 K26 7 IO_L45N_7 K25 7 IO_L44P_7 M24 7 IO_L44N_7 M23 7 IO_L43P_7 J29 7 IO_L43N_7 H29 7 IO_L42P_7 H28 NC 7 IO_L42N_7 H27 NC 7 IO_L41P_7 L24 NC 7 IO_L41N_7 L23 NC 7 IO_L40P_7 G30 NC 7 IO_L40N_7/VREF_7 G29 NC 7 IO_L39P_7 G28 NC 7 IO_L39N_7 G27 NC 7 IO_L38P_7 J26 NC 7 IO_L38N_7 J25 NC 7 IO_L37P_7 F30 NC 7 IO_L37N_7 F29 NC 7 IO_L36P_7 F28 NC 7 IO_L36N_7 F27 NC 7 IO_L35P_7 K24 NC 7 IO_L35N_7 K23 NC 7 IO_L34P_7 E30 NC 7 IO_L34N_7/VREF_7 E29 NC 7 IO_L33P_7 E28 NC 7 IO_L33N_7 E27 NC 7 IO_L32P_7 H26 NC 7 IO_L32N_7 H25 NC 7 IO_L31P_7 D30 NC 7 IO_L31N_7 D29 NC Module 4 of 4 156 www.xilinx.com 1-800-255-7778 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 7 IO_L06P_7 D28 7 IO_L06N_7 C27 7 IO_L05P_7 J24 7 IO_L05N_7 J23 7 IO_L04P_7 C30 7 IO_L04N_7/VREF_7 C29 7 IO_L03P_7 D26 7 IO_L03N_7 C26 7 IO_L02P_7 G26 7 IO_L02N_7 G25 7 IO_L01P_7/VRN_7 B28 7 IO_L01N_7/VRP_7 A28 0 VCCO_0 K21 0 VCCO_0 K20 0 VCCO_0 K19 0 VCCO_0 K18 0 VCCO_0 K17 0 VCCO_0 K16 0 VCCO_0 J21 0 VCCO_0 J20 0 VCCO_0 J19 0 VCCO_0 J18 1 VCCO_1 K15 1 VCCO_1 K14 1 VCCO_1 K13 1 VCCO_1 K12 1 VCCO_1 K11 1 VCCO_1 K10 1 VCCO_1 J13 1 VCCO_1 J12 1 VCCO_1 J11 1 VCCO_1 J10 2 VCCO_2 R10 2 VCCO_2 P10 2 VCCO_2 N10 2 VCCO_2 N9 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 157 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 2 VCCO_2 M10 2 VCCO_2 M9 2 VCCO_2 L10 2 VCCO_2 L9 2 VCCO_2 K9 2 VCCO_2 J9 3 VCCO_3 AB9 3 VCCO_3 AA9 3 VCCO_3 Y10 3 VCCO_3 Y9 3 VCCO_3 W10 3 VCCO_3 W9 3 VCCO_3 V10 3 VCCO_3 V9 3 VCCO_3 U10 3 VCCO_3 T10 4 VCCO_4 AB13 4 VCCO_4 AB12 4 VCCO_4 AB11 4 VCCO_4 AB10 4 VCCO_4 AA15 4 VCCO_4 AA14 4 VCCO_4 AA13 4 VCCO_4 AA12 4 VCCO_4 AA11 4 VCCO_4 AA10 5 VCCO_5 AB21 5 VCCO_5 AB20 5 VCCO_5 AB19 5 VCCO_5 AB18 5 VCCO_5 AA21 5 VCCO_5 AA20 5 VCCO_5 AA19 5 VCCO_5 AA18 5 VCCO_5 AA17 5 VCCO_5 AA16 6 VCCO_6 AB22 Module 4 of 4 158 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number 6 VCCO_6 AA22 6 VCCO_6 Y22 6 VCCO_6 Y21 6 VCCO_6 W22 6 VCCO_6 W21 6 VCCO_6 V22 6 VCCO_6 V21 6 VCCO_6 U21 6 VCCO_6 T21 7 VCCO_7 R21 7 VCCO_7 P21 7 VCCO_7 N22 7 VCCO_7 N21 7 VCCO_7 M22 7 VCCO_7 M21 7 VCCO_7 L22 7 VCCO_7 L21 7 VCCO_7 K22 7 VCCO_7 J22 N/A CCLK AC7 N/A PROG_B G24 N/A DONE AC8 N/A M0 AD24 N/A M1 AC24 N/A M2 AC23 N/A TCK G7 N/A TDI F26 N/A TDO F5 N/A TMS H8 N/A PWRDWN_B AD7 N/A HSWAP_EN H23 N/A RSVD D6 N/A VBATT H7 N/A DXP H24 N/A DXN D25 N/A AVCCAUXTX4 B26 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 159 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A VTTXPAD4 B27 N/A TXNPAD4 A27 N/A TXPPAD4 A26 N/A GNDA4 C25 N/A GNDA4 C25 N/A RXPPAD4 A25 N/A RXNPAD4 A24 N/A VTRXPAD4 B25 N/A AVCCAUXRX4 B24 N/A AVCCAUXTX6 B19 N/A VTTXPAD6 B20 N/A TXNPAD6 A20 N/A TXPPAD6 A19 N/A GNDA6 C19 N/A GNDA6 C19 N/A RXPPAD6 A18 N/A RXNPAD6 A17 N/A VTRXPAD6 B18 N/A AVCCAUXRX6 B17 N/A AVCCAUXTX7 B13 N/A VTTXPAD7 B14 N/A TXNPAD7 A14 N/A TXPPAD7 A13 N/A GNDA7 C12 N/A GNDA7 C12 N/A RXPPAD7 A12 N/A RXNPAD7 A11 N/A VTRXPAD7 B12 N/A AVCCAUXRX7 B11 N/A AVCCAUXTX9 B6 N/A VTTXPAD9 B7 N/A TXNPAD9 A7 N/A TXPPAD9 A6 N/A GNDA9 C6 N/A GNDA9 C6 N/A RXPPAD9 A5 N/A RXNPAD9 A4 Module 4 of 4 160 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A VTRXPAD9 B5 N/A AVCCAUXRX9 B4 N/A AVCCAUXRX16 AJ4 N/A VTRXPAD16 AJ5 N/A RXNPAD16 AK4 N/A RXPPAD16 AK5 N/A GNDA16 AH6 N/A GNDA16 AH6 N/A TXPPAD16 AK6 N/A TXNPAD16 AK7 N/A VTTXPAD16 AJ7 N/A AVCCAUXTX16 AJ6 N/A AVCCAUXRX18 AJ11 N/A VTRXPAD18 AJ12 N/A RXNPAD18 AK11 N/A RXPPAD18 AK12 N/A GNDA18 AH12 N/A GNDA18 AH12 N/A TXPPAD18 AK13 N/A TXNPAD18 AK14 N/A VTTXPAD18 AJ14 N/A AVCCAUXTX18 AJ13 N/A AVCCAUXRX19 AJ17 N/A VTRXPAD19 AJ18 N/A RXNPAD19 AK17 N/A RXPPAD19 AK18 N/A GNDA19 AH19 N/A GNDA19 AH19 N/A TXPPAD19 AK19 N/A TXNPAD19 AK20 N/A VTTXPAD19 AJ20 N/A AVCCAUXTX19 AJ19 N/A AVCCAUXRX21 AJ24 N/A VTRXPAD21 AJ25 N/A RXNPAD21 AK24 N/A RXPPAD21 AK25 N/A GNDA21 AH25 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 161 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A GNDA21 AH25 N/A TXPPAD21 AK26 N/A TXNPAD21 AK27 N/A VTTXPAD21 AJ27 N/A AVCCAUXTX21 AJ26 N/A VCCAUX AK29 N/A VCCAUX AK16 N/A VCCAUX AK15 N/A VCCAUX AK2 N/A VCCAUX AJ30 N/A VCCAUX AJ1 N/A VCCAUX T30 N/A VCCAUX T1 N/A VCCAUX R30 N/A VCCAUX R1 N/A VCCAUX B30 N/A VCCAUX B1 N/A VCCAUX A29 N/A VCCAUX A16 N/A VCCAUX A15 N/A VCCAUX A2 N/A VCCINT Y19 N/A VCCINT Y18 N/A VCCINT Y17 N/A VCCINT Y16 N/A VCCINT Y15 N/A VCCINT Y14 N/A VCCINT Y13 N/A VCCINT Y12 N/A VCCINT W20 N/A VCCINT W11 N/A VCCINT V20 N/A VCCINT V11 N/A VCCINT U20 N/A VCCINT U11 N/A VCCINT T20 Module 4 of 4 162 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A VCCINT T11 N/A VCCINT R20 N/A VCCINT R11 N/A VCCINT P20 N/A VCCINT P11 N/A VCCINT N20 N/A VCCINT N11 N/A VCCINT M20 N/A VCCINT M11 N/A VCCINT L19 N/A VCCINT L18 N/A VCCINT L17 N/A VCCINT L16 N/A VCCINT L15 N/A VCCINT L14 N/A VCCINT L13 N/A VCCINT L12 N/A GND AK22 N/A GND AK9 N/A GND AJ29 N/A GND AJ2 N/A GND AH28 N/A GND AH17 N/A GND AH14 N/A GND AH3 N/A GND AG27 N/A GND AG22 N/A GND AG19 N/A GND AG12 N/A GND AG9 N/A GND AG4 N/A GND AF26 N/A GND AF5 N/A GND AE25 N/A GND AE18 N/A GND AE13 N/A GND AE6 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 163 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A GND AC30 N/A GND AC1 N/A GND Y28 N/A GND Y25 N/A GND Y20 N/A GND Y11 N/A GND Y6 N/A GND Y3 N/A GND W19 N/A GND W18 N/A GND W17 N/A GND W16 N/A GND W15 N/A GND W14 N/A GND W13 N/A GND W12 N/A GND V19 N/A GND V18 N/A GND V17 N/A GND V16 N/A GND V15 N/A GND V14 N/A GND V13 N/A GND V12 N/A GND U25 N/A GND U19 N/A GND U18 N/A GND U17 N/A GND U16 N/A GND U15 N/A GND U14 N/A GND U13 N/A GND U12 N/A GND U6 N/A GND T19 N/A GND T18 N/A GND T17 Module 4 of 4 164 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A GND T16 N/A GND T15 N/A GND T14 N/A GND T13 N/A GND T12 N/A GND R19 N/A GND R18 N/A GND R17 N/A GND R16 N/A GND R15 N/A GND R14 N/A GND R13 N/A GND R12 N/A GND P25 N/A GND P19 N/A GND P18 N/A GND P17 N/A GND P16 N/A GND P15 N/A GND P14 N/A GND P13 N/A GND P12 N/A GND P6 N/A GND N19 N/A GND N18 N/A GND N17 N/A GND N16 N/A GND N15 N/A GND N14 N/A GND N13 N/A GND N12 N/A GND M19 N/A GND M18 N/A GND M17 N/A GND M16 N/A GND M15 N/A GND M14 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 Module 4 of 4 165 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 9: FF896 -- XC2VP7 and XC2VP20 No Connects Bank Pin Description Pin Number N/A GND M13 N/A GND M12 N/A GND L28 N/A GND L25 N/A GND L20 N/A GND L11 N/A GND L6 N/A GND L3 N/A GND H30 N/A GND H1 N/A GND F25 N/A GND F18 N/A GND F13 N/A GND F6 N/A GND E26 N/A GND E5 N/A GND D27 N/A GND D22 N/A GND D19 N/A GND D12 N/A GND D9 N/A GND D4 N/A GND C28 N/A GND C17 N/A GND C14 N/A GND C3 N/A GND B29 N/A GND B2 N/A GND A22 N/A GND A9 Module 4 of 4 166 www.xilinx.com 1-800-255-7778 XC2V P7 XC2V P20 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 4: FF896 Flip-Chip Fine-Pitch BGA Package Specifications DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 167 R Virtex-II ProTM Platform FPGAs: Pinout Information FF1152 Flip-Chip Fine-Pitch BGA Package As shown in Table 10, XC2VP20 and XC2VP50 Virtex-II Pro devices are available in the FF1152 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the differences shown in the No Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 E29 0 IO_L01P_0/VRN_0 E28 0 IO_L02N_0 H26 0 IO_L02P_0 G26 0 IO_L03N_0 H25 0 IO_L03P_0/VREF_0 G25 0 IO_L05_0/No_Pair J25 0 IO_L06N_0 K24 0 IO_L06P_0 J24 0 IO_L07N_0 F26 0 IO_L07P_0 E26 0 IO_L08N_0 D30 0 IO_L08P_0 D29 0 IO_L09N_0 K23 0 IO_L09P_0/VREF_0 J23 0 IO_L19N_0 F24 NC 0 IO_L19P_0 E24 NC 0 IO_L20N_0 D28 NC 0 IO_L20P_0 C28 NC 0 IO_L21N_0 H24 NC 0 IO_L21P_0 G24 NC 0 IO_L25N_0 G23 NC 0 IO_L25P_0 F23 NC 0 IO_L26N_0 E27 NC 0 IO_L26P_0 D27 NC 0 IO_L27N_0 K22 NC 0 IO_L27P_0/VREF_0 J22 NC 0 IO_L37N_0 H22 0 IO_L37P_0 G22 0 IO_L38N_0 D26 0 IO_L38P_0 C26 0 IO_L39N_0 K21 Module 4 of 4 168 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 0 IO_L39P_0 J21 0 IO_L43N_0 F22 0 IO_L43P_0 E22 0 IO_L44N_0 E25 0 IO_L44P_0 D25 0 IO_L45N_0 H21 0 IO_L45P_0/VREF_0 G21 0 IO_L46N_0 D22 0 IO_L46P_0 D23 0 IO_L47N_0 D24 0 IO_L47P_0 C24 0 IO_L48N_0 K20 0 IO_L48P_0 J20 0 IO_L49N_0 F21 0 IO_L49P_0 E21 0 IO_L50_0/No_Pair C21 0 IO_L53_0/No_Pair C22 0 IO_L54N_0 L19 0 IO_L54P_0 K19 0 IO_L55N_0 G20 0 IO_L55P_0 F20 0 IO_L56N_0 D21 0 IO_L56P_0 D20 0 IO_L57N_0 J19 0 IO_L57P_0/VREF_0 H19 0 IO_L67N_0 G19 0 IO_L67P_0 F19 0 IO_L68N_0 E19 0 IO_L68P_0 D19 0 IO_L69N_0 L18 0 IO_L69P_0/VREF_0 K18 0 IO_L73N_0 G18 0 IO_L73P_0 F18 0 IO_L74N_0/GCLK7P E18 0 IO_L74P_0/GCLK6S D18 0 IO_L75N_0/GCLK5P J18 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 169 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 0 IO_L75P_0/GCLK4S H18 1 IO_L75N_1/GCLK3P H17 1 IO_L75P_1/GCLK2S J17 1 IO_L74N_1/GCLK1P D17 1 IO_L74P_1/GCLK0S E17 1 IO_L73N_1 F17 1 IO_L73P_1 G17 1 IO_L69N_1/VREF_1 K17 1 IO_L69P_1 L17 1 IO_L68N_1 D16 1 IO_L68P_1 E16 1 IO_L67N_1 F16 1 IO_L67P_1 G16 1 IO_L57N_1/VREF_1 H16 1 IO_L57P_1 J16 1 IO_L56N_1 D15 1 IO_L56P_1 D14 1 IO_L55N_1 F15 1 IO_L55P_1 G15 1 IO_L54N_1 K16 1 IO_L54P_1 L16 1 IO_L53_1/No_Pair C13 1 IO_L50_1/No_Pair C14 1 IO_L49N_1 E14 1 IO_L49P_1 F14 1 IO_L48N_1 J15 1 IO_L48P_1 K15 1 IO_L47N_1 C11 1 IO_L47P_1 D11 1 IO_L46N_1 D12 1 IO_L46P_1 D13 1 IO_L45N_1/VREF_1 G14 1 IO_L45P_1 H14 1 IO_L44N_1 D10 1 IO_L44P_1 E10 Module 4 of 4 170 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 1 IO_L43N_1 E13 1 IO_L43P_1 F13 1 IO_L39N_1 J14 1 IO_L39P_1 K14 1 IO_L38N_1 C9 1 IO_L38P_1 D9 1 IO_L37N_1 G13 1 IO_L37P_1 H13 1 IO_L27N_1/VREF_1 J13 NC 1 IO_L27P_1 K13 NC 1 IO_L26N_1 D8 NC 1 IO_L26P_1 E8 NC 1 IO_L25N_1 F12 NC 1 IO_L25P_1 G12 NC 1 IO_L21N_1 G11 NC 1 IO_L21P_1 H11 NC 1 IO_L20N_1 C7 NC 1 IO_L20P_1 D7 NC 1 IO_L19N_1 E11 NC 1 IO_L19P_1 F11 NC 1 IO_L09N_1/VREF_1 J12 1 IO_L09P_1 K12 1 IO_L08N_1 D6 1 IO_L08P_1 D5 1 IO_L07N_1 E9 1 IO_L07P_1 F9 1 IO_L06N_1 J11 1 IO_L06P_1 K11 1 IO_L05_1/No_Pair J10 1 IO_L03N_1/VREF_1 G10 1 IO_L03P_1 H10 1 IO_L02N_1 G9 1 IO_L02P_1 H9 1 IO_L01N_1/VRP_1 E7 1 IO_L01P_1/VRN_1 E6 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 171 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 2 IO_L01N_2/VRP_2 D2 2 IO_L01P_2/VRN_2 D1 2 IO_L02N_2 F8 2 IO_L02P_2 F7 2 IO_L03N_2 E4 2 IO_L03P_2 E3 2 IO_L04N_2/VREF_2 E2 2 IO_L04P_2 E1 2 IO_L05N_2 J8 2 IO_L05P_2 J7 2 IO_L06N_2 F5 2 IO_L06P_2 F4 2 IO_L07N_2 G4 NC 2 IO_L07P_2 G3 NC 2 IO_L09N_2 G6 NC 2 IO_L09P_2 G5 NC 2 IO_L10N_2/VREF_2 F2 NC 2 IO_L10P_2 F1 NC 2 IO_L11N_2 L10 NC 2 IO_L11P_2 L9 NC 2 IO_L12N_2 H6 NC 2 IO_L12P_2 H5 NC 2 IO_L13N_2 G2 NC 2 IO_L13P_2 G1 NC 2 IO_L15N_2 J6 NC 2 IO_L15P_2 J5 NC 2 IO_L16N_2/VREF_2 J4 NC 2 IO_L16P_2 J3 NC 2 IO_L17N_2 K8 NC 2 IO_L17P_2 K7 NC 2 IO_L18N_2 H4 NC 2 IO_L18P_2 H3 NC 2 IO_L31N_2 H2 2 IO_L31P_2 H1 2 IO_L32N_2 M10 2 IO_L32P_2 M9 Module 4 of 4 172 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 2 IO_L33N_2 K5 2 IO_L33P_2 K4 2 IO_L34N_2/VREF_2 J2 2 IO_L34P_2 K2 2 IO_L35N_2 L8 2 IO_L35P_2 L7 2 IO_L36N_2 L6 2 IO_L36P_2 L5 2 IO_L37N_2 K1 2 IO_L37P_2 L1 2 IO_L38N_2 N10 2 IO_L38P_2 N9 2 IO_L39N_2 M7 2 IO_L39P_2 M6 2 IO_L40N_2/VREF_2 L2 2 IO_L40P_2 M2 2 IO_L41N_2 N8 2 IO_L41P_2 N7 2 IO_L42N_2 L4 2 IO_L42P_2 L3 2 IO_L43N_2 M4 2 IO_L43P_2 M3 2 IO_L44N_2 P10 2 IO_L44P_2 P9 2 IO_L45N_2 N6 2 IO_L45P_2 N5 2 IO_L46N_2/VREF_2 M1 2 IO_L46P_2 N1 2 IO_L47N_2 P8 2 IO_L47P_2 P7 2 IO_L48N_2 N4 2 IO_L48P_2 N3 2 IO_L49N_2 N2 2 IO_L49P_2 P2 2 IO_L50N_2 R10 2 IO_L50P_2 R9 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 173 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 2 IO_L51N_2 P6 2 IO_L51P_2 P5 2 IO_L52N_2/VREF_2 P4 2 IO_L52P_2 P3 2 IO_L53N_2 T11 2 IO_L53P_2 U11 2 IO_L54N_2 R7 2 IO_L54P_2 R6 2 IO_L55N_2 P1 2 IO_L55P_2 R1 2 IO_L56N_2 T10 2 IO_L56P_2 T9 2 IO_L57N_2 R4 2 IO_L57P_2 R3 2 IO_L58N_2/VREF_2 R2 2 IO_L58P_2 T2 2 IO_L59N_2 T8 2 IO_L59P_2 T7 2 IO_L60N_2 T6 2 IO_L60P_2 T5 2 IO_L85N_2 T4 2 IO_L85P_2 T3 2 IO_L86N_2 U10 2 IO_L86P_2 U9 2 IO_L87N_2 U6 2 IO_L87P_2 U5 2 IO_L88N_2/VREF_2 U2 2 IO_L88P_2 V2 2 IO_L89N_2 U8 2 IO_L89P_2 U7 2 IO_L90N_2 U4 2 IO_L90P_2 U3 3 IO_L90N_3 V3 3 IO_L90P_3 V4 3 IO_L89N_3 V7 Module 4 of 4 174 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 3 IO_L89P_3 V8 3 IO_L88N_3 V5 3 IO_L88P_3 V6 3 IO_L87N_3/VREF_3 W2 3 IO_L87P_3 Y2 3 IO_L86N_3 V9 3 IO_L86P_3 V10 3 IO_L85N_3 W3 3 IO_L85P_3 W4 3 IO_L60N_3 Y1 3 IO_L60P_3 AA1 3 IO_L59N_3 V11 3 IO_L59P_3 W11 3 IO_L58N_3 W5 3 IO_L58P_3 W6 3 IO_L57N_3/VREF_3 Y3 3 IO_L57P_3 Y4 3 IO_L56N_3 W7 3 IO_L56P_3 W8 3 IO_L55N_3 Y6 3 IO_L55P_3 Y7 3 IO_L54N_3 AA2 3 IO_L54P_3 AB2 3 IO_L53N_3 W9 3 IO_L53P_3 W10 3 IO_L52N_3 AA3 3 IO_L52P_3 AA4 3 IO_L51N_3/VREF_3 AB1 3 IO_L51P_3 AC1 3 IO_L50N_3 Y9 3 IO_L50P_3 Y10 3 IO_L49N_3 AA5 3 IO_L49P_3 AA6 3 IO_L48N_3 AB3 3 IO_L48P_3 AB4 3 IO_L47N_3 AA7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 175 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 3 IO_L47P_3 AA8 3 IO_L46N_3 AB5 3 IO_L46P_3 AB6 3 IO_L45N_3/VREF_3 AC2 3 IO_L45P_3 AD2 3 IO_L44N_3 AA9 3 IO_L44P_3 AA10 3 IO_L43N_3 AC3 3 IO_L43P_3 AC4 3 IO_L42N_3 AD1 3 IO_L42P_3 AE1 3 IO_L41N_3 AB7 3 IO_L41P_3 AB8 3 IO_L40N_3 AC6 3 IO_L40P_3 AC7 3 IO_L39N_3/VREF_3 AD3 3 IO_L39P_3 AD4 3 IO_L38N_3 AB9 3 IO_L38P_3 AB10 3 IO_L37N_3 AD5 3 IO_L37P_3 AD6 3 IO_L36N_3 AE2 3 IO_L36P_3 AF2 3 IO_L35N_3 AD7 3 IO_L35P_3 AD8 3 IO_L34N_3 AE4 3 IO_L34P_3 AE5 3 IO_L33N_3/VREF_3 AG1 3 IO_L33P_3 AG2 3 IO_L32N_3 AC9 3 IO_L32P_3 AC10 3 IO_L31N_3 AF3 3 IO_L31P_3 AF4 3 IO_L18N_3 AH1 NC 3 IO_L18P_3 AH2 NC 3 IO_L17N_3 AE7 NC Module 4 of 4 176 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number XC2V P20 3 IO_L17P_3 AE8 NC 3 IO_L16N_3 AF5 NC 3 IO_L16P_3 AF6 NC 3 IO_L15N_3/VREF_3 AG3 NC 3 IO_L15P_3 AG4 NC 3 IO_L14N_3 AD9 NC 3 IO_L14P_3 AD10 NC 3 IO_L13N_3 AH3 NC 3 IO_L13P_3 AH4 NC 3 IO_L12N_3 AJ1 NC 3 IO_L12P_3 AJ2 NC 3 IO_L11N_3 AF7 NC 3 IO_L11P_3 AF8 NC 3 IO_L09N_3/VREF_3 AK1 NC 3 IO_L09P_3 AK2 NC 3 IO_L07N_3 AG5 NC 3 IO_L07P_3 AG6 NC 3 IO_L06N_3 AL1 3 IO_L06P_3 AL2 3 IO_L05N_3 AG7 3 IO_L05P_3 AH8 3 IO_L04N_3 AH5 3 IO_L04P_3 AH6 3 IO_L03N_3/VREF_3 AK3 3 IO_L03P_3 AK4 3 IO_L02N_3 AJ7 3 IO_L02P_3 AJ8 3 IO_L01N_3/VRP_3 AJ4 3 IO_L01P_3/VRN_3 AJ5 4 IO_L01N_4/DOUT AL5 4 IO_L01P_4/INIT_B AL6 4 IO_L02N_4/D0 AG9 4 IO_L02P_4/D1 AH9 4 IO_L03N_4/D2 AK6 4 IO_L03P_4/D3 AK7 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 177 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 4 IO_L05_4/No_Pair AF10 4 IO_L06N_4/VRP_4 AL7 4 IO_L06P_4/VRN_4 AM7 4 IO_L07N_4 AE11 4 IO_L07P_4/VREF_4 AF11 4 IO_L08N_4 AG10 4 IO_L08P_4 AH10 4 IO_L09N_4 AK8 4 IO_L09P_4/VREF_4 AL8 4 IO_L19N_4 AE12 NC 4 IO_L19P_4 AF12 NC 4 IO_L20N_4 AJ9 NC 4 IO_L20P_4 AK9 NC 4 IO_L21N_4 AL9 NC 4 IO_L21P_4 AM9 NC 4 IO_L25N_4 AG11 NC 4 IO_L25P_4 AH11 NC 4 IO_L26N_4 AH12 NC 4 IO_L26P_4 AJ12 NC 4 IO_L27N_4 AK10 NC 4 IO_L27P_4/VREF_4 AL10 NC 4 IO_L37N_4 AE13 4 IO_L37P_4 AF13 4 IO_L38N_4 AG13 4 IO_L38P_4 AH13 4 IO_L39N_4 AJ11 4 IO_L39P_4 AK11 4 IO_L43N_4 AE14 4 IO_L43P_4 AF14 4 IO_L44N_4 AJ13 4 IO_L44P_4 AK13 4 IO_L45N_4 AL11 4 IO_L45P_4/VREF_4 AM11 4 IO_L46N_4 AE15 4 IO_L46P_4 AF15 4 IO_L47N_4 AG14 Module 4 of 4 178 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 4 IO_L47P_4 AH14 4 IO_L48N_4 AL13 4 IO_L48P_4 AL12 4 IO_L49N_4 AD16 4 IO_L49P_4 AE16 4 IO_L50_4/No_Pair AJ14 4 IO_L53_4/No_Pair AK14 4 IO_L54N_4 AM14 4 IO_L54P_4 AM13 4 IO_L55N_4 AF16 4 IO_L55P_4 AG16 4 IO_L56N_4 AH15 4 IO_L56P_4 AJ15 4 IO_L57N_4 AL14 4 IO_L57P_4/VREF_4 AL15 4 IO_L67N_4 AD17 4 IO_L67P_4 AE17 4 IO_L68N_4 AH16 4 IO_L68P_4 AJ16 4 IO_L69N_4 AK16 4 IO_L69P_4/VREF_4 AL16 4 IO_L73N_4 AF17 4 IO_L73P_4 AG17 4 IO_L74N_4/GCLK3S AH17 4 IO_L74P_4/GCLK2P AJ17 4 IO_L75N_4/GCLK1S AK17 4 IO_L75P_4/GCLK0P AL17 5 IO_L75N_5/GCLK7S AL18 5 IO_L75P_5/GCLK6P AK18 5 IO_L74N_5/GCLK5S AJ18 5 IO_L74P_5/GCLK4P AH18 5 IO_L73N_5 AG18 5 IO_L73P_5 AF18 5 IO_L69N_5/VREF_5 AL19 5 IO_L69P_5 AK19 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 179 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 5 IO_L68N_5 AJ19 5 IO_L68P_5 AH19 5 IO_L67N_5 AE18 5 IO_L67P_5 AD18 5 IO_L57N_5/VREF_5 AL20 5 IO_L57P_5 AL21 5 IO_L56N_5 AJ20 5 IO_L56P_5 AH20 5 IO_L55N_5 AG19 5 IO_L55P_5 AF19 5 IO_L54N_5 AM22 5 IO_L54P_5 AM21 5 IO_L53_5/No_Pair AK21 5 IO_L50_5/No_Pair AJ21 5 IO_L49N_5 AE19 5 IO_L49P_5 AD19 5 IO_L48N_5 AL23 5 IO_L48P_5 AL22 5 IO_L47N_5 AH21 5 IO_L47P_5 AG21 5 IO_L46N_5 AF20 5 IO_L46P_5 AE20 5 IO_L45N_5/VREF_5 AM24 5 IO_L45P_5 AL24 5 IO_L44N_5 AK22 5 IO_L44P_5 AJ22 5 IO_L43N_5 AF21 5 IO_L43P_5 AE21 5 IO_L39N_5 AK24 5 IO_L39P_5 AJ24 5 IO_L38N_5 AH22 5 IO_L38P_5 AG22 5 IO_L37N_5 AF22 5 IO_L37P_5 AE22 5 IO_L27N_5/VREF_5 AL25 NC 5 IO_L27P_5 AK25 NC Module 4 of 4 180 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number XC2V P20 5 IO_L26N_5 AJ23 NC 5 IO_L26P_5 AH23 NC 5 IO_L25N_5 AH24 NC 5 IO_L25P_5 AG24 NC 5 IO_L21N_5 AM26 NC 5 IO_L21P_5 AL26 NC 5 IO_L20N_5 AK26 NC 5 IO_L20P_5 AJ26 NC 5 IO_L19N_5 AF23 NC 5 IO_L19P_5 AE23 NC 5 IO_L09N_5/VREF_5 AL27 5 IO_L09P_5 AK27 5 IO_L08N_5 AH25 5 IO_L08P_5 AG25 5 IO_L07N_5/VREF_5 AF24 5 IO_L07P_5 AE24 5 IO_L06N_5/VRP_5 AM28 5 IO_L06P_5/VRN_5 AL28 5 IO_L05_5/No_Pair AF25 5 IO_L03N_5/D4 AK28 5 IO_L03P_5/D5 AK29 5 IO_L02N_5/D6 AH26 5 IO_L02P_5/D7 AG26 5 IO_L01N_5/RDWR_B AL29 5 IO_L01P_5/CS_B AL30 6 IO_L01P_6/VRN_6 AJ30 6 IO_L01N_6/VRP_6 AJ31 6 IO_L02P_6 AJ27 6 IO_L02N_6 AJ28 6 IO_L03P_6 AK31 6 IO_L03N_6/VREF_6 AK32 6 IO_L04P_6 AH29 6 IO_L04N_6 AH30 6 IO_L05P_6 AH27 6 IO_L05N_6 AG28 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 181 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 6 IO_L06P_6 AL33 6 IO_L06N_6 AL34 6 IO_L07P_6 AG29 NC 6 IO_L07N_6 AG30 NC 6 IO_L09P_6 AK33 NC 6 IO_L09N_6/VREF_6 AK34 NC 6 IO_L11P_6 AF27 NC 6 IO_L11N_6 AF28 NC 6 IO_L12P_6 AJ33 NC 6 IO_L12N_6 AJ34 NC 6 IO_L13P_6 AH31 NC 6 IO_L13N_6 AH32 NC 6 IO_L14P_6 AD25 NC 6 IO_L14N_6 AD26 NC 6 IO_L15P_6 AG31 NC 6 IO_L15N_6/VREF_6 AG32 NC 6 IO_L16P_6 AF29 NC 6 IO_L16N_6 AF30 NC 6 IO_L17P_6 AE27 NC 6 IO_L17N_6 AE28 NC 6 IO_L18P_6 AH33 NC 6 IO_L18N_6 AH34 NC 6 IO_L31P_6 AF31 6 IO_L31N_6 AF32 6 IO_L32P_6 AC25 6 IO_L32N_6 AC26 6 IO_L33P_6 AG33 6 IO_L33N_6/VREF_6 AG34 6 IO_L34P_6 AE30 6 IO_L34N_6 AE31 6 IO_L35P_6 AD27 6 IO_L35N_6 AD28 6 IO_L36P_6 AF33 6 IO_L36N_6 AE33 6 IO_L37P_6 AD29 6 IO_L37N_6 AD30 Module 4 of 4 182 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 6 IO_L38P_6 AB25 6 IO_L38N_6 AB26 6 IO_L39P_6 AD31 6 IO_L39N_6/VREF_6 AD32 6 IO_L40P_6 AC28 6 IO_L40N_6 AC29 6 IO_L41P_6 AB27 6 IO_L41N_6 AB28 6 IO_L42P_6 AE34 6 IO_L42N_6 AD34 6 IO_L43P_6 AC31 6 IO_L43N_6 AC32 6 IO_L44P_6 AA25 6 IO_L44N_6 AA26 6 IO_L45P_6 AD33 6 IO_L45N_6/VREF_6 AC33 6 IO_L46P_6 AB29 6 IO_L46N_6 AB30 6 IO_L47P_6 AA27 6 IO_L47N_6 AA28 6 IO_L48P_6 AB31 6 IO_L48N_6 AB32 6 IO_L49P_6 AA29 6 IO_L49N_6 AA30 6 IO_L50P_6 Y25 6 IO_L50N_6 Y26 6 IO_L51P_6 AC34 6 IO_L51N_6/VREF_6 AB34 6 IO_L52P_6 AA31 6 IO_L52N_6 AA32 6 IO_L53P_6 W25 6 IO_L53N_6 W26 6 IO_L54P_6 AB33 6 IO_L54N_6 AA33 6 IO_L55P_6 Y28 6 IO_L55N_6 Y29 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 183 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 6 IO_L56P_6 W27 6 IO_L56N_6 W28 6 IO_L57P_6 Y31 6 IO_L57N_6/VREF_6 Y32 6 IO_L58P_6 W29 6 IO_L58N_6 W30 6 IO_L59P_6 W24 6 IO_L59N_6 V24 6 IO_L60P_6 AA34 6 IO_L60N_6 Y34 6 IO_L85P_6 W31 6 IO_L85N_6 W32 6 IO_L86P_6 V25 6 IO_L86N_6 V26 6 IO_L87P_6 Y33 6 IO_L87N_6/VREF_6 W33 6 IO_L88P_6 V29 6 IO_L88N_6 V30 6 IO_L89P_6 V27 6 IO_L89N_6 V28 6 IO_L90P_6 V31 6 IO_L90N_6 V32 7 IO_L90P_7 U32 7 IO_L90N_7 U31 7 IO_L89P_7 U28 7 IO_L89N_7 U27 7 IO_L88P_7 V33 7 IO_L88N_7/VREF_7 U33 7 IO_L87P_7 U30 7 IO_L87N_7 U29 7 IO_L86P_7 U26 7 IO_L86N_7 U25 7 IO_L85P_7 T32 7 IO_L85N_7 T31 7 IO_L60P_7 T30 Module 4 of 4 184 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 7 IO_L60N_7 T29 7 IO_L59P_7 T28 7 IO_L59N_7 T27 7 IO_L58P_7 T33 7 IO_L58N_7/VREF_7 R33 7 IO_L57P_7 R32 7 IO_L57N_7 R31 7 IO_L56P_7 T26 7 IO_L56N_7 T25 7 IO_L55P_7 R34 7 IO_L55N_7 P34 7 IO_L54P_7 R29 7 IO_L54N_7 R28 7 IO_L53P_7 U24 7 IO_L53N_7 T24 7 IO_L52P_7 P32 7 IO_L52N_7/VREF_7 P31 7 IO_L51P_7 P30 7 IO_L51N_7 P29 7 IO_L50P_7 R26 7 IO_L50N_7 R25 7 IO_L49P_7 P33 7 IO_L49N_7 N33 7 IO_L48P_7 N32 7 IO_L48N_7 N31 7 IO_L47P_7 P28 7 IO_L47N_7 P27 7 IO_L46P_7 N34 7 IO_L46N_7/VREF_7 M34 7 IO_L45P_7 N30 7 IO_L45N_7 N29 7 IO_L44P_7 P26 7 IO_L44N_7 P25 7 IO_L43P_7 M32 7 IO_L43N_7 M31 7 IO_L42P_7 L32 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 185 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 7 IO_L42N_7 L31 7 IO_L41P_7 N28 7 IO_L41N_7 N27 7 IO_L40P_7 M33 7 IO_L40N_7/VREF_7 L33 7 IO_L39P_7 M29 7 IO_L39N_7 M28 7 IO_L38P_7 N26 7 IO_L38N_7 N25 7 IO_L37P_7 L34 7 IO_L37N_7 K34 7 IO_L36P_7 L30 7 IO_L36N_7 L29 7 IO_L35P_7 L28 7 IO_L35N_7 L27 7 IO_L34P_7 K33 7 IO_L34N_7/VREF_7 J33 7 IO_L33P_7 K31 7 IO_L33N_7 K30 7 IO_L32P_7 M26 7 IO_L32N_7 M25 7 IO_L31P_7 H34 7 IO_L31N_7 H33 7 IO_L18P_7 H32 NC 7 IO_L18N_7 H31 NC 7 IO_L17P_7 K28 NC 7 IO_L17N_7 K27 NC 7 IO_L16P_7 J32 NC 7 IO_L16N_7/VREF_7 J31 NC 7 IO_L15P_7 J30 NC 7 IO_L15N_7 J29 NC 7 IO_L13P_7 G34 NC 7 IO_L13N_7 G33 NC 7 IO_L12P_7 H30 NC 7 IO_L12N_7 H29 NC 7 IO_L11P_7 L26 NC Module 4 of 4 186 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number XC2V P20 7 IO_L11N_7 L25 NC 7 IO_L10P_7 F34 NC 7 IO_L10N_7/VREF_7 F33 NC 7 IO_L09P_7 G30 NC 7 IO_L09N_7 G29 NC 7 IO_L07P_7 G32 NC 7 IO_L07N_7 G31 NC 7 IO_L06P_7 F31 7 IO_L06N_7 F30 7 IO_L05P_7 J28 7 IO_L05N_7 J27 7 IO_L04P_7 E34 7 IO_L04N_7/VREF_7 E33 7 IO_L03P_7 E32 7 IO_L03N_7 E31 7 IO_L02P_7 F28 7 IO_L02N_7 F27 7 IO_L01P_7/VRN_7 D34 7 IO_L01N_7/VRP_7 D33 0 VCCO_0 C29 0 VCCO_0 E20 0 VCCO_0 F25 0 VCCO_0 L20 0 VCCO_0 L21 0 VCCO_0 L22 0 VCCO_0 L23 0 VCCO_0 M18 0 VCCO_0 M19 0 VCCO_0 M20 0 VCCO_0 M21 0 VCCO_0 M22 1 VCCO_1 C6 1 VCCO_1 E15 1 VCCO_1 F10 1 VCCO_1 L12 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 187 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 1 VCCO_1 L13 1 VCCO_1 L14 1 VCCO_1 L15 1 VCCO_1 M13 1 VCCO_1 M14 1 VCCO_1 M15 1 VCCO_1 M16 1 VCCO_1 M17 2 VCCO_2 F3 2 VCCO_2 K6 2 VCCO_2 M11 2 VCCO_2 N11 2 VCCO_2 N12 2 VCCO_2 P11 2 VCCO_2 P12 2 VCCO_2 R5 2 VCCO_2 R11 2 VCCO_2 R12 2 VCCO_2 T12 2 VCCO_2 U12 3 VCCO_3 V12 3 VCCO_3 W12 3 VCCO_3 Y5 3 VCCO_3 Y11 3 VCCO_3 Y12 3 VCCO_3 AA11 3 VCCO_3 AA12 3 VCCO_3 AB11 3 VCCO_3 AB12 3 VCCO_3 AC11 3 VCCO_3 AE6 3 VCCO_3 AJ3 4 VCCO_4 AC13 4 VCCO_4 AC14 4 VCCO_4 AC15 4 VCCO_4 AC16 Module 4 of 4 188 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 4 VCCO_4 AC17 4 VCCO_4 AD12 4 VCCO_4 AD13 4 VCCO_4 AD14 4 VCCO_4 AD15 4 VCCO_4 AJ10 4 VCCO_4 AK15 4 VCCO_4 AM6 5 VCCO_5 AC18 5 VCCO_5 AC19 5 VCCO_5 AC20 5 VCCO_5 AC21 5 VCCO_5 AC22 5 VCCO_5 AD20 5 VCCO_5 AD21 5 VCCO_5 AD22 5 VCCO_5 AD23 5 VCCO_5 AJ25 5 VCCO_5 AK20 5 VCCO_5 AM29 6 VCCO_6 V23 6 VCCO_6 W23 6 VCCO_6 Y23 6 VCCO_6 Y24 6 VCCO_6 Y30 6 VCCO_6 AA23 6 VCCO_6 AA24 6 VCCO_6 AB23 6 VCCO_6 AB24 6 VCCO_6 AC24 6 VCCO_6 AE29 6 VCCO_6 AJ32 7 VCCO_7 F32 7 VCCO_7 K29 7 VCCO_7 M24 7 VCCO_7 N23 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 189 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 7 VCCO_7 N24 7 VCCO_7 P23 7 VCCO_7 P24 7 VCCO_7 R23 7 VCCO_7 R24 7 VCCO_7 R30 7 VCCO_7 T23 7 VCCO_7 U23 N/A CCLK AE9 N/A PROG_B J26 N/A DONE AE10 N/A M0 AF26 N/A M1 AE26 N/A M2 AE25 N/A TCK J9 N/A TDI H28 N/A TDO H7 N/A TMS K10 N/A PWRDWN_B AF9 N/A HSWAP_EN K25 N/A RSVD G8 N/A VBATT K9 N/A DXP K26 N/A DXN G27 N/A AVCCAUXTX2 B32 NC N/A VTTXPAD2 B33 NC N/A TXNPAD2 A33 NC N/A TXPPAD2 A32 NC N/A GNDA2 C30 NC N/A GNDA2 C30 NC N/A RXPPAD2 A31 NC N/A RXNPAD2 A30 NC N/A VTRXPAD2 B31 NC N/A AVCCAUXRX2 B30 NC N/A AVCCAUXTX4 B28 Module 4 of 4 190 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number N/A VTTXPAD4 B29 N/A TXNPAD4 A29 N/A TXPPAD4 A28 N/A GNDA4 C27 N/A GNDA4 C27 N/A RXPPAD4 A27 N/A RXNPAD4 A26 N/A VTRXPAD4 B27 N/A AVCCAUXRX4 B26 N/A AVCCAUXTX5 B24 NC N/A VTTXPAD5 B25 NC N/A TXNPAD5 A25 NC N/A TXPPAD5 A24 NC N/A GNDA5 C23 NC N/A GNDA5 C23 NC N/A RXPPAD5 A23 NC N/A RXNPAD5 A22 NC N/A VTRXPAD5 B23 NC N/A AVCCAUXRX5 B22 NC N/A AVCCAUXTX6 B20 N/A VTTXPAD6 B21 N/A TXNPAD6 A21 N/A TXPPAD6 A20 N/A GNDA6 C20 N/A GNDA6 C20 N/A RXPPAD6 A19 N/A RXNPAD6 A18 N/A VTRXPAD6 B19 N/A AVCCAUXRX6 B18 N/A AVCCAUXTX7 B16 N/A VTTXPAD7 B17 N/A TXNPAD7 A17 N/A TXPPAD7 A16 N/A GNDA7 C15 N/A GNDA7 C15 N/A RXPPAD7 A15 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 191 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number N/A RXNPAD7 A14 N/A VTRXPAD7 B15 N/A AVCCAUXRX7 B14 N/A AVCCAUXTX8 B12 NC N/A VTTXPAD8 B13 NC N/A TXNPAD8 A13 NC N/A TXPPAD8 A12 NC N/A GNDA8 C12 NC N/A GNDA8 C12 NC N/A RXPPAD8 A11 NC N/A RXNPAD8 A10 NC N/A VTRXPAD8 B11 NC N/A AVCCAUXRX8 B10 NC N/A AVCCAUXTX9 B8 N/A VTTXPAD9 B9 N/A TXNPAD9 A9 N/A TXPPAD9 A8 N/A GNDA9 C8 N/A GNDA9 C8 N/A RXPPAD9 A7 N/A RXNPAD9 A6 N/A VTRXPAD9 B7 N/A AVCCAUXRX9 B6 N/A AVCCAUXTX11 B4 NC N/A VTTXPAD11 B5 NC N/A TXNPAD11 A5 NC N/A TXPPAD11 A4 NC N/A GNDA11 C5 NC N/A GNDA11 C5 NC N/A RXPPAD11 A3 NC N/A RXNPAD11 A2 NC N/A VTRXPAD11 B3 NC N/A AVCCAUXRX11 B2 NC N/A AVCCAUXRX14 AN2 NC N/A VTRXPAD14 AN3 NC N/A RXNPAD14 AP2 NC Module 4 of 4 192 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number XC2V P20 N/A RXPPAD14 AP3 NC N/A GNDA14 AM5 NC N/A GNDA14 AM5 NC N/A TXPPAD14 AP4 NC N/A TXNPAD14 AP5 NC N/A VTTXPAD14 AN5 NC N/A AVCCAUXTX14 AN4 NC N/A AVCCAUXRX16 AN6 N/A VTRXPAD16 AN7 N/A RXNPAD16 AP6 N/A RXPPAD16 AP7 N/A GNDA16 AM8 N/A GNDA16 AM8 N/A TXPPAD16 AP8 N/A TXNPAD16 AP9 N/A VTTXPAD16 AN9 N/A AVCCAUXTX16 AN8 N/A AVCCAUXRX17 AN10 NC N/A VTRXPAD17 AN11 NC N/A RXNPAD17 AP10 NC N/A RXPPAD17 AP11 NC N/A GNDA17 AM12 NC N/A GNDA17 AM12 NC N/A TXPPAD17 AP12 NC N/A TXNPAD17 AP13 NC N/A VTTXPAD17 AN13 NC N/A AVCCAUXTX17 AN12 NC N/A AVCCAUXRX18 AN14 N/A VTRXPAD18 AN15 N/A RXNPAD18 AP14 N/A RXPPAD18 AP15 N/A GNDA18 AM15 N/A GNDA18 AM15 N/A TXPPAD18 AP16 N/A TXNPAD18 AP17 N/A VTTXPAD18 AN17 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 193 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number N/A AVCCAUXTX18 AN16 N/A AVCCAUXRX19 AN18 N/A VTRXPAD19 AN19 N/A RXNPAD19 AP18 N/A RXPPAD19 AP19 N/A GNDA19 AM20 N/A GNDA19 AM20 N/A TXPPAD19 AP20 N/A TXNPAD19 AP21 N/A VTTXPAD19 AN21 N/A AVCCAUXTX19 AN20 N/A AVCCAUXRX20 AN22 NC N/A VTRXPAD20 AN23 NC N/A RXNPAD20 AP22 NC N/A RXPPAD20 AP23 NC N/A GNDA20 AM23 NC N/A GNDA20 AM23 NC N/A TXPPAD20 AP24 NC N/A TXNPAD20 AP25 NC N/A VTTXPAD20 AN25 NC N/A AVCCAUXTX20 AN24 NC N/A AVCCAUXRX21 AN26 N/A VTRXPAD21 AN27 N/A RXNPAD21 AP26 N/A RXPPAD21 AP27 N/A GNDA21 AM27 N/A GNDA21 AM27 N/A TXPPAD21 AP28 N/A TXNPAD21 AP29 N/A VTTXPAD21 AN29 N/A AVCCAUXTX21 AN28 N/A AVCCAUXRX23 AN30 NC N/A VTRXPAD23 AN31 NC N/A RXNPAD23 AP30 NC N/A RXPPAD23 AP31 NC N/A GNDA23 AM30 NC Module 4 of 4 194 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number XC2V P20 N/A GNDA23 AM30 NC N/A TXPPAD23 AP32 NC N/A TXNPAD23 AP33 NC N/A VTTXPAD23 AN33 NC N/A AVCCAUXTX23 AN32 NC N/A VCCINT L11 N/A VCCINT L24 N/A VCCINT M12 N/A VCCINT M23 N/A VCCINT N13 N/A VCCINT N14 N/A VCCINT N15 N/A VCCINT N16 N/A VCCINT N17 N/A VCCINT N18 N/A VCCINT N19 N/A VCCINT N20 N/A VCCINT N21 N/A VCCINT N22 N/A VCCINT P13 N/A VCCINT P22 N/A VCCINT R13 N/A VCCINT R22 N/A VCCINT T13 N/A VCCINT T22 N/A VCCINT U13 N/A VCCINT U22 N/A VCCINT V13 N/A VCCINT V22 N/A VCCINT W13 N/A VCCINT W22 N/A VCCINT Y13 N/A VCCINT Y22 N/A VCCINT AA13 N/A VCCINT AA22 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 195 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A VCCINT AB13 N/A VCCINT AB14 N/A VCCINT AB15 N/A VCCINT AB16 N/A VCCINT AB17 N/A VCCINT AB18 N/A VCCINT AB19 N/A VCCINT AB20 N/A VCCINT AB21 N/A VCCINT AB22 N/A VCCINT AC12 N/A VCCINT AC23 N/A VCCINT AD11 N/A VCCINT AD24 N/A VCCAUX C3 N/A VCCAUX C4 N/A VCCAUX C17 N/A VCCAUX C18 N/A VCCAUX C31 N/A VCCAUX C32 N/A VCCAUX D3 N/A VCCAUX D32 N/A VCCAUX U1 N/A VCCAUX V1 N/A VCCAUX U34 N/A VCCAUX V34 N/A VCCAUX AL3 N/A VCCAUX AL32 N/A VCCAUX AM3 N/A VCCAUX AM4 N/A VCCAUX AM17 N/A VCCAUX AM18 N/A VCCAUX AM31 N/A VCCAUX AM32 N/A GND AF34 Module 4 of 4 196 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND B34 N/A GND C1 N/A GND C2 N/A GND C10 N/A GND C16 N/A GND C19 N/A GND C25 N/A GND C33 N/A GND C34 N/A GND D4 N/A GND D31 N/A GND E5 N/A GND E12 N/A GND E23 N/A GND E30 N/A GND F6 N/A GND F29 N/A GND G7 N/A GND G28 N/A GND B1 N/A GND H8 N/A GND H12 N/A GND H15 N/A GND H20 N/A GND J1 N/A GND H27 N/A GND AF1 N/A GND K3 N/A GND K32 N/A GND M5 N/A GND M8 N/A GND M27 N/A GND M30 N/A GND P14 N/A GND P15 N/A GND P16 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 197 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND P17 N/A GND P18 N/A GND P19 N/A GND P20 N/A GND P21 N/A GND R8 N/A GND R14 N/A GND R15 N/A GND R16 N/A GND R17 N/A GND R18 N/A GND R19 N/A GND R20 N/A GND R21 N/A GND R27 N/A GND T1 N/A GND T14 N/A GND T15 N/A GND T16 N/A GND T17 N/A GND T18 N/A GND T19 N/A GND T20 N/A GND T21 N/A GND T34 N/A GND U14 N/A GND U15 N/A GND U16 N/A GND U17 N/A GND U18 N/A GND U19 N/A GND U20 N/A GND U21 N/A GND V14 N/A GND V15 N/A GND V16 Module 4 of 4 198 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND V17 N/A GND V18 N/A GND V19 N/A GND V20 N/A GND V21 N/A GND W1 N/A GND W14 N/A GND W15 N/A GND W16 N/A GND W17 N/A GND W18 N/A GND W19 N/A GND W20 N/A GND W21 N/A GND W34 N/A GND Y8 N/A GND Y14 N/A GND Y15 N/A GND Y16 N/A GND Y17 N/A GND Y18 N/A GND Y19 N/A GND Y20 N/A GND Y21 N/A GND Y27 N/A GND AA14 N/A GND AA15 N/A GND AA16 N/A GND AA17 N/A GND AA18 N/A GND AA19 N/A GND AA20 N/A GND AA21 N/A GND AC5 N/A GND AC8 N/A GND AC27 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 199 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 10: FF1152 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND AC30 N/A GND AE3 N/A GND AE32 N/A GND H23 N/A GND AG8 N/A GND AG12 N/A GND AG15 N/A GND AG20 N/A GND AG23 N/A GND AG27 N/A GND J34 N/A GND AH7 N/A GND AH28 N/A GND AJ6 N/A GND AJ29 N/A GND AK5 N/A GND AK12 N/A GND AK23 N/A GND AK30 N/A GND AL4 N/A GND AL31 N/A GND AM1 N/A GND AM2 N/A GND AM10 N/A GND AM16 N/A GND AM19 N/A GND AM25 N/A GND AM33 N/A GND AM34 N/A GND AN1 N/A GND AN34 Module 4 of 4 200 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 5: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 201 R Virtex-II ProTM Platform FPGAs: Pinout Information FF1517 Flip-Chip Fine-Pitch BGA Package As shown in Table 11, the XC2VP50 Virtex-II Pro device is available in the FF1517 flip-chip fine-pitch BGA package. Following this table are the FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch). Table 11: FF1517 -- XC2VP50 Module 4 of 4 202 Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 F32 0 IO_L01P_0/VRN_0 E32 0 IO_L02N_0 K29 0 IO_L02P_0 J29 0 IO_L03N_0 K28 0 IO_L03P_0/VREF_0 K27 0 IO_L05_0/No_Pair H30 0 IO_L06N_0 H29 0 IO_L06P_0 G29 0 IO_L07N_0 G31 0 IO_L07P_0 F31 0 IO_L08N_0 D32 0 IO_L08P_0 C32 0 IO_L09N_0 J28 0 IO_L09P_0/VREF_0 H28 0 IO_L19N_0 G30 0 IO_L19P_0 F30 0 IO_L20N_0 E31 0 IO_L20P_0 D31 0 IO_L21N_0 J27 0 IO_L21P_0 H27 0 IO_L25N_0 F29 0 IO_L25P_0 E29 0 IO_L26N_0 E30 0 IO_L26P_0 D30 0 IO_L27N_0 K26 0 IO_L27P_0/VREF_0 J26 0 IO_L37N_0 G28 0 IO_L37P_0 F28 0 IO_L38N_0 D29 0 IO_L38P_0 C29 0 IO_L39N_0 K25 0 IO_L39P_0 J25 0 IO_L43N_0 G27 0 IO_L43P_0 F27 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 0 IO_L44N_0 D28 0 IO_L44P_0 C28 0 IO_L45N_0 L24 0 IO_L45P_0/VREF_0 K24 0 IO_L46N_0 H26 0 IO_L46P_0 G26 0 IO_L47N_0 E27 0 IO_L47P_0 D27 0 IO_L48N_0 H25 0 IO_L48P_0 G25 0 IO_L49N_0 F25 0 IO_L49P_0 E25 0 IO_L50_0/No_Pair E26 0 IO_L53_0/No_Pair D26 0 IO_L54N_0 J24 0 IO_L54P_0 H24 0 IO_L55N_0 G24 0 IO_L55P_0 F24 0 IO_L56N_0 D25 0 IO_L56P_0 C25 0 IO_L57N_0 K23 0 IO_L57P_0/VREF_0 J23 0 IO_L58N_0 G23 0 IO_L58P_0 F23 0 IO_L59N_0 E24 0 IO_L59P_0 D24 0 IO_L60N_0 K22 0 IO_L60P_0 J22 0 IO_L64N_0 H22 0 IO_L64P_0 G22 0 IO_L65N_0 D23 0 IO_L65P_0 C23 0 IO_L66N_0 K21 0 IO_L66P_0/VREF_0 J21 0 IO_L67N_0 F22 0 IO_L67P_0 E22 0 IO_L68N_0 D22 0 IO_L68P_0 C22 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 203 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 204 Bank Pin Description Pin Number 0 IO_L69N_0 H21 0 IO_L69P_0/VREF_0 G21 0 IO_L73N_0 F21 0 IO_L73P_0 E21 0 IO_L74N_0/GCLK7P D21 0 IO_L74P_0/GCLK6S C21 0 IO_L75N_0/GCLK5P F20 0 IO_L75P_0/GCLK4S E20 1 IO_L75N_1/GCLK3P H20 1 IO_L75P_1/GCLK2S J20 1 IO_L74N_1/GCLK1P C19 1 IO_L74P_1/GCLK0S D19 1 IO_L73N_1 E19 1 IO_L73P_1 F19 1 IO_L69N_1/VREF_1 G19 1 IO_L69P_1 H19 1 IO_L68N_1 C18 1 IO_L68P_1 D18 1 IO_L67N_1 E18 1 IO_L67P_1 F18 1 IO_L66N_1/VREF_1 J19 1 IO_L66P_1 K19 1 IO_L65N_1 C17 1 IO_L65P_1 D17 1 IO_L64N_1 G18 1 IO_L64P_1 H18 1 IO_L60N_1 J18 1 IO_L60P_1 K18 1 IO_L59N_1 D16 1 IO_L59P_1 E16 1 IO_L58N_1 F17 1 IO_L58P_1 G17 1 IO_L57N_1/VREF_1 J17 1 IO_L57P_1 K17 1 IO_L56N_1 C15 1 IO_L56P_1 D15 1 IO_L55N_1 F16 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 1 IO_L55P_1 G16 1 IO_L54N_1 H16 1 IO_L54P_1 J16 1 IO_L53_1/No_Pair D14 1 IO_L50_1/No_Pair E14 1 IO_L49N_1 E15 1 IO_L49P_1 F15 1 IO_L48N_1 G15 1 IO_L48P_1 H15 1 IO_L47N_1 D13 1 IO_L47P_1 E13 1 IO_L46N_1 G14 1 IO_L46P_1 H14 1 IO_L45N_1/VREF_1 K16 1 IO_L45P_1 L16 1 IO_L44N_1 C12 1 IO_L44P_1 D12 1 IO_L43N_1 F13 1 IO_L43P_1 G13 1 IO_L39N_1 J15 1 IO_L39P_1 K15 1 IO_L38N_1 C11 1 IO_L38P_1 D11 1 IO_L37N_1 F12 1 IO_L37P_1 G12 1 IO_L27N_1/VREF_1 J14 1 IO_L27P_1 K14 1 IO_L26N_1 D10 1 IO_L26P_1 E10 1 IO_L25N_1 E11 1 IO_L25P_1 F11 1 IO_L21N_1 H13 1 IO_L21P_1 J13 1 IO_L20N_1 D9 1 IO_L20P_1 E9 1 IO_L19N_1 F10 1 IO_L19P_1 G10 1 IO_L09N_1/VREF_1 H12 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 205 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 206 Bank Pin Description Pin Number 1 IO_L09P_1 J12 1 IO_L08N_1 C8 1 IO_L08P_1 D8 1 IO_L07N_1 F9 1 IO_L07P_1 G9 1 IO_L06N_1 G11 1 IO_L06P_1 H11 1 IO_L05_1/No_Pair H10 1 IO_L03N_1/VREF_1 K13 1 IO_L03P_1 K12 1 IO_L02N_1 J11 1 IO_L02P_1 K11 1 IO_L01N_1/VRP_1 E8 1 IO_L01P_1/VRN_1 F8 2 IO_L01N_2/VRP_2 E4 2 IO_L01P_2/VRN_2 E3 2 IO_L02N_2 G8 2 IO_L02P_2 H7 2 IO_L03N_2 C5 2 IO_L03P_2 D5 2 IO_L04N_2/VREF_2 D2 2 IO_L04P_2 D1 2 IO_L05N_2 J8 2 IO_L05P_2 J7 2 IO_L06N_2 E6 2 IO_L06P_2 F5 2 IO_L07N_2 E2 2 IO_L07P_2 E1 2 IO_L08N_2 K9 2 IO_L08P_2 K8 2 IO_L09N_2 G6 2 IO_L09P_2 G5 2 IO_L10N_2/VREF_2 G4 2 IO_L10P_2 G3 2 IO_L11N_2 N12 2 IO_L11P_2 N11 2 IO_L12N_2 F4 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 2 IO_L12P_2 F3 2 IO_L13N_2 F2 2 IO_L13P_2 F1 2 IO_L14N_2 L8 2 IO_L14P_2 L7 2 IO_L15N_2 H6 2 IO_L15P_2 H5 2 IO_L16N_2/VREF_2 H4 2 IO_L16P_2 H3 2 IO_L17N_2 P12 2 IO_L17P_2 P11 2 IO_L18N_2 J6 2 IO_L18P_2 J5 2 IO_L19N_2 G2 2 IO_L19P_2 G1 2 IO_L20N_2 N10 2 IO_L20P_2 N9 2 IO_L21N_2 K7 2 IO_L21P_2 K6 2 IO_L22N_2/VREF_2 H2 2 IO_L22P_2 H1 2 IO_L23N_2 R12 2 IO_L23P_2 R11 2 IO_L24N_2 J4 2 IO_L24P_2 J3 2 IO_L25N_2 J2 2 IO_L25P_2 J1 2 IO_L26N_2 P10 2 IO_L26P_2 P9 2 IO_L27N_2 K5 2 IO_L27P_2 K4 2 IO_L28N_2/VREF_2 K2 2 IO_L28P_2 K1 2 IO_L29N_2 P8 2 IO_L29P_2 P7 2 IO_L30N_2 L6 2 IO_L30P_2 L5 2 IO_L31N_2 L3 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 207 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 208 Bank Pin Description Pin Number 2 IO_L31P_2 L2 2 IO_L32N_2 R10 2 IO_L32P_2 R9 2 IO_L33N_2 N8 2 IO_L33P_2 N7 2 IO_L34N_2/VREF_2 M4 2 IO_L34P_2 M3 2 IO_L35N_2 T12 2 IO_L35P_2 T11 2 IO_L36N_2 M6 2 IO_L36P_2 M5 2 IO_L37N_2 M2 2 IO_L37P_2 M1 2 IO_L38N_2 T10 2 IO_L38P_2 T9 2 IO_L39N_2 N6 2 IO_L39P_2 N5 2 IO_L40N_2/VREF_2 N4 2 IO_L40P_2 N3 2 IO_L41N_2 U12 2 IO_L41P_2 U11 2 IO_L42N_2 P5 2 IO_L42P_2 P4 2 IO_L43N_2 N2 2 IO_L43P_2 N1 2 IO_L44N_2 T8 2 IO_L44P_2 T7 2 IO_L45N_2 R7 2 IO_L45P_2 R6 2 IO_L46N_2/VREF_2 P2 2 IO_L46P_2 P1 2 IO_L47N_2 U10 2 IO_L47P_2 U9 2 IO_L48N_2 R5 2 IO_L48P_2 R4 2 IO_L49N_2 R3 2 IO_L49P_2 R2 2 IO_L50N_2 V12 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 2 IO_L50P_2 V11 2 IO_L51N_2 T6 2 IO_L51P_2 T5 2 IO_L52N_2/VREF_2 T2 2 IO_L52P_2 T1 2 IO_L53N_2 V10 2 IO_L53P_2 V9 2 IO_L54N_2 T4 2 IO_L54P_2 T3 2 IO_L55N_2 U4 2 IO_L55P_2 U3 2 IO_L56N_2 V8 2 IO_L56P_2 V7 2 IO_L57N_2 U7 2 IO_L57P_2 U6 2 IO_L58N_2/VREF_2 U2 2 IO_L58P_2 U1 2 IO_L59N_2 W12 2 IO_L59P_2 W11 2 IO_L60N_2 V6 2 IO_L60P_2 V5 2 IO_L85N_2 V4 2 IO_L85P_2 V3 2 IO_L86N_2 W10 2 IO_L86P_2 W9 2 IO_L87N_2 W6 2 IO_L87P_2 W5 2 IO_L88N_2/VREF_2 V2 2 IO_L88P_2 V1 2 IO_L89N_2 W8 2 IO_L89P_2 W7 2 IO_L90N_2 W4 2 IO_L90P_2 W3 3 IO_L90N_3 AA3 3 IO_L90P_3 AA4 3 IO_L89N_3 AA7 3 IO_L89P_3 AA8 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 209 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 210 Bank Pin Description Pin Number 3 IO_L88N_3 AA5 3 IO_L88P_3 AA6 3 IO_L87N_3/VREF_3 AB1 3 IO_L87P_3 AB2 3 IO_L86N_3 AA9 3 IO_L86P_3 AA10 3 IO_L85N_3 AB3 3 IO_L85P_3 AB4 3 IO_L60N_3 AC1 3 IO_L60P_3 AC2 3 IO_L59N_3 AA11 3 IO_L59P_3 AA12 3 IO_L58N_3 AB5 3 IO_L58P_3 AB6 3 IO_L57N_3/VREF_3 AC3 3 IO_L57P_3 AC4 3 IO_L56N_3 AB7 3 IO_L56P_3 AB8 3 IO_L55N_3 AC6 3 IO_L55P_3 AC7 3 IO_L54N_3 AD1 3 IO_L54P_3 AD2 3 IO_L53N_3 AB9 3 IO_L53P_3 AB10 3 IO_L52N_3 AD5 3 IO_L52P_3 AD6 3 IO_L51N_3/VREF_3 AD3 3 IO_L51P_3 AD4 3 IO_L50N_3 AB11 3 IO_L50P_3 AB12 3 IO_L49N_3 AE4 3 IO_L49P_3 AE5 3 IO_L48N_3 AE2 3 IO_L48P_3 AE3 3 IO_L47N_3 AC9 3 IO_L47P_3 AC10 3 IO_L46N_3 AE6 3 IO_L46P_3 AE7 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 3 IO_L45N_3/VREF_3 AF1 3 IO_L45P_3 AF2 3 IO_L44N_3 AD7 3 IO_L44P_3 AD8 3 IO_L43N_3 AF4 3 IO_L43P_3 AF5 3 IO_L42N_3 AG1 3 IO_L42P_3 AG2 3 IO_L41N_3 AC11 3 IO_L41P_3 AC12 3 IO_L40N_3 AG3 3 IO_L40P_3 AG4 3 IO_L39N_3/VREF_3 AH1 3 IO_L39P_3 AH2 3 IO_L38N_3 AD9 3 IO_L38P_3 AD10 3 IO_L37N_3 AF7 3 IO_L37P_3 AF8 3 IO_L36N_3 AH3 3 IO_L36P_3 AH4 3 IO_L35N_3 AD11 3 IO_L35P_3 AD12 3 IO_L34N_3 AG5 3 IO_L34P_3 AG6 3 IO_L33N_3/VREF_3 AJ2 3 IO_L33P_3 AJ3 3 IO_L32N_3 AE9 3 IO_L32P_3 AE10 3 IO_L31N_3 AH5 3 IO_L31P_3 AH6 3 IO_L30N_3 AK1 3 IO_L30P_3 AK2 3 IO_L29N_3 AG7 3 IO_L29P_3 AG8 3 IO_L28N_3 AJ5 3 IO_L28P_3 AJ6 3 IO_L27N_3/VREF_3 AL1 3 IO_L27P_3 AL2 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 211 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 212 Bank Pin Description Pin Number 3 IO_L26N_3 AF9 3 IO_L26P_3 AF10 3 IO_L25N_3 AK4 3 IO_L25P_3 AK5 3 IO_L24N_3 AM1 3 IO_L24P_3 AM2 3 IO_L23N_3 AE11 3 IO_L23P_3 AE12 3 IO_L22N_3 AM3 3 IO_L22P_3 AM4 3 IO_L21N_3/VREF_3 AL3 3 IO_L21P_3 AL4 3 IO_L20N_3 AG9 3 IO_L20P_3 AG10 3 IO_L19N_3 AK6 3 IO_L19P_3 AK7 3 IO_L18N_3 AN1 3 IO_L18P_3 AN2 3 IO_L17N_3 AF11 3 IO_L17P_3 AF12 3 IO_L16N_3 AL5 3 IO_L16P_3 AL6 3 IO_L15N_3/VREF_3 AP1 3 IO_L15P_3 AP2 3 IO_L14N_3 AJ7 3 IO_L14P_3 AJ8 3 IO_L13N_3 AM5 3 IO_L13P_3 AM6 3 IO_L12N_3 AN3 3 IO_L12P_3 AN4 3 IO_L11N_3 AG11 3 IO_L11P_3 AG12 3 IO_L10N_3 AN5 3 IO_L10P_3 AN6 3 IO_L09N_3/VREF_3 AR1 3 IO_L09P_3 AR2 3 IO_L08N_3 AK8 3 IO_L08P_3 AK9 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 3 IO_L07N_3 AR3 3 IO_L07P_3 AR4 3 IO_L06N_3 AP3 3 IO_L06P_3 AP4 3 IO_L05N_3 AL7 3 IO_L05P_3 AL8 3 IO_L04N_3 AP5 3 IO_L04P_3 AR6 3 IO_L03N_3/VREF_3 AT1 3 IO_L03P_3 AT2 3 IO_L02N_3 AM7 3 IO_L02P_3 AN8 3 IO_L01N_3/VRP_3 AT5 3 IO_L01P_3/VRN_3 AU5 4 IO_L01N_4/DOUT AP7 4 IO_L01P_4/INIT_B AR7 4 IO_L02N_4/D0 AP8 4 IO_L02P_4/D1 AR8 4 IO_L03N_4/D2 AT8 4 IO_L03P_4/D3 AU8 4 IO_L05_4/No_Pair AM10 4 IO_L06N_4/VRP_4 AR9 4 IO_L06P_4/VRN_4 AT9 4 IO_L07N_4 AK11 4 IO_L07P_4/VREF_4 AL11 4 IO_L08N_4 AN9 4 IO_L08P_4 AP9 4 IO_L09N_4 AR10 4 IO_L09P_4/VREF_4 AT10 4 IO_L19N_4 AK12 4 IO_L19P_4 AK13 4 IO_L20N_4 AN10 4 IO_L20P_4 AP10 4 IO_L21N_4 AP11 4 IO_L21P_4 AR11 4 IO_L25N_4 AL12 4 IO_L25P_4 AM12 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 213 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 214 Bank Pin Description Pin Number 4 IO_L26N_4 AM11 4 IO_L26P_4 AN11 4 IO_L27N_4 AT11 4 IO_L27P_4/VREF_4 AU11 4 IO_L37N_4 AL13 4 IO_L37P_4 AM13 4 IO_L38N_4 AN12 4 IO_L38P_4 AP12 4 IO_L39N_4 AT12 4 IO_L39P_4 AU12 4 IO_L43N_4 AK14 4 IO_L43P_4 AL14 4 IO_L44N_4 AN13 4 IO_L44P_4 AP13 4 IO_L45N_4 AR13 4 IO_L45P_4/VREF_4 AT13 4 IO_L46N_4 AK15 4 IO_L46P_4 AL15 4 IO_L47N_4 AM14 4 IO_L47P_4 AN14 4 IO_L48N_4 AR14 4 IO_L48P_4 AT14 4 IO_L49N_4 AJ16 4 IO_L49P_4 AK16 4 IO_L50_4/No_Pair AP15 4 IO_L53_4/No_Pair AR15 4 IO_L54N_4 AT15 4 IO_L54P_4 AU15 4 IO_L55N_4 AM15 4 IO_L55P_4 AN15 4 IO_L56N_4 AN16 4 IO_L56P_4 AP16 4 IO_L57N_4 AR16 4 IO_L57P_4/VREF_4 AT16 4 IO_L58N_4 AL16 4 IO_L58P_4 AM16 4 IO_L59N_4 AN17 4 IO_L59P_4 AP17 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 4 IO_L60N_4 AT17 4 IO_L60P_4 AU17 4 IO_L64N_4 AK17 4 IO_L64P_4 AL17 4 IO_L65N_4 AM18 4 IO_L65P_4 AN18 4 IO_L66N_4 AP18 4 IO_L66P_4/VREF_4 AR18 4 IO_L67N_4 AK18 4 IO_L67P_4 AL18 4 IO_L68N_4 AM19 4 IO_L68P_4 AN19 4 IO_L69N_4 AT18 4 IO_L69P_4/VREF_4 AU18 4 IO_L73N_4 AK19 4 IO_L73P_4 AL19 4 IO_L74N_4/GCLK3S AP19 4 IO_L74P_4/GCLK2P AR19 4 IO_L75N_4/GCLK1S AT19 4 IO_L75P_4/GCLK0P AU19 5 IO_L75N_5/GCLK7S AU21 5 IO_L75P_5/GCLK6P AT21 5 IO_L74N_5/GCLK5S AR21 5 IO_L74P_5/GCLK4P AP21 5 IO_L73N_5 AL21 5 IO_L73P_5 AK21 5 IO_L69N_5/VREF_5 AU22 5 IO_L69P_5 AT22 5 IO_L68N_5 AN21 5 IO_L68P_5 AM21 5 IO_L67N_5 AL22 5 IO_L67P_5 AK22 5 IO_L66N_5/VREF_5 AR22 5 IO_L66P_5 AP22 5 IO_L65N_5 AN22 5 IO_L65P_5 AM22 5 IO_L64N_5 AL23 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 215 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 216 Bank Pin Description Pin Number 5 IO_L64P_5 AK23 5 IO_L60N_5 AU23 5 IO_L60P_5 AT23 5 IO_L59N_5 AP23 5 IO_L59P_5 AN23 5 IO_L58N_5 AM24 5 IO_L58P_5 AL24 5 IO_L57N_5/VREF_5 AT24 5 IO_L57P_5 AR24 5 IO_L56N_5 AP24 5 IO_L56P_5 AN24 5 IO_L55N_5 AN25 5 IO_L55P_5 AM25 5 IO_L54N_5 AU25 5 IO_L54P_5 AT25 5 IO_L53_5/No_Pair AR25 5 IO_L50_5/No_Pair AP25 5 IO_L49N_5 AK24 5 IO_L49P_5 AJ24 5 IO_L48N_5 AT26 5 IO_L48P_5 AR26 5 IO_L47N_5 AN26 5 IO_L47P_5 AM26 5 IO_L46N_5 AL25 5 IO_L46P_5 AK25 5 IO_L45N_5/VREF_5 AT27 5 IO_L45P_5 AR27 5 IO_L44N_5 AP27 5 IO_L44P_5 AN27 5 IO_L43N_5 AL26 5 IO_L43P_5 AK26 5 IO_L39N_5 AU28 5 IO_L39P_5 AT28 5 IO_L38N_5 AP28 5 IO_L38P_5 AN28 5 IO_L37N_5 AM27 5 IO_L37P_5 AL27 5 IO_L27N_5/VREF_5 AU29 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 5 IO_L27P_5 AT29 5 IO_L26N_5 AN29 5 IO_L26P_5 AM29 5 IO_L25N_5 AM28 5 IO_L25P_5 AL28 5 IO_L21N_5 AR29 5 IO_L21P_5 AP29 5 IO_L20N_5 AP30 5 IO_L20P_5 AN30 5 IO_L19N_5 AK27 5 IO_L19P_5 AK28 5 IO_L09N_5/VREF_5 AT30 5 IO_L09P_5 AR30 5 IO_L08N_5 AP31 5 IO_L08P_5 AN31 5 IO_L07N_5/VREF_5 AL29 5 IO_L07P_5 AK29 5 IO_L06N_5/VRP_5 AT31 5 IO_L06P_5/VRN_5 AR31 5 IO_L05_5/No_Pair AM30 5 IO_L03N_5/D4 AU32 5 IO_L03P_5/D5 AT32 5 IO_L02N_5/D6 AR32 5 IO_L02P_5/D7 AP32 5 IO_L01N_5/RDWR_B AR33 5 IO_L01P_5/CS_B AP33 6 IO_L01P_6/VRN_6 AU35 6 IO_L01N_6/VRP_6 AT35 6 IO_L02P_6 AN32 6 IO_L02N_6 AM33 6 IO_L03P_6 AT38 6 IO_L03N_6/VREF_6 AT39 6 IO_L04P_6 AR34 6 IO_L04N_6 AP35 6 IO_L05P_6 AL32 6 IO_L05N_6 AL33 6 IO_L06P_6 AP36 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 217 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 218 Bank Pin Description Pin Number 6 IO_L06N_6 AP37 6 IO_L07P_6 AR36 6 IO_L07N_6 AR37 6 IO_L08P_6 AK31 6 IO_L08N_6 AK32 6 IO_L09P_6 AR38 6 IO_L09N_6/VREF_6 AR39 6 IO_L10P_6 AN34 6 IO_L10N_6 AN35 6 IO_L11P_6 AG28 6 IO_L11N_6 AG29 6 IO_L12P_6 AN36 6 IO_L12N_6 AN37 6 IO_L13P_6 AM34 6 IO_L13N_6 AM35 6 IO_L14P_6 AJ32 6 IO_L14N_6 AJ33 6 IO_L15P_6 AP38 6 IO_L15N_6/VREF_6 AP39 6 IO_L16P_6 AL34 6 IO_L16N_6 AL35 6 IO_L17P_6 AF28 6 IO_L17N_6 AF29 6 IO_L18P_6 AN38 6 IO_L18N_6 AN39 6 IO_L19P_6 AK33 6 IO_L19N_6 AK34 6 IO_L20P_6 AG30 6 IO_L20N_6 AG31 6 IO_L21P_6 AL36 6 IO_L21N_6/VREF_6 AL37 6 IO_L22P_6 AM36 6 IO_L22N_6 AM37 6 IO_L23P_6 AE28 6 IO_L23N_6 AE29 6 IO_L24P_6 AM38 6 IO_L24N_6 AM39 6 IO_L25P_6 AK35 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 6 IO_L25N_6 AK36 6 IO_L26P_6 AF30 6 IO_L26N_6 AF31 6 IO_L27P_6 AL38 6 IO_L27N_6/VREF_6 AL39 6 IO_L28P_6 AJ34 6 IO_L28N_6 AJ35 6 IO_L29P_6 AG32 6 IO_L29N_6 AG33 6 IO_L30P_6 AK38 6 IO_L30N_6 AK39 6 IO_L31P_6 AH34 6 IO_L31N_6 AH35 6 IO_L32P_6 AE30 6 IO_L32N_6 AE31 6 IO_L33P_6 AJ37 6 IO_L33N_6/VREF_6 AJ38 6 IO_L34P_6 AG34 6 IO_L34N_6 AG35 6 IO_L35P_6 AD28 6 IO_L35N_6 AD29 6 IO_L36P_6 AH36 6 IO_L36N_6 AH37 6 IO_L37P_6 AF32 6 IO_L37N_6 AF33 6 IO_L38P_6 AD30 6 IO_L38N_6 AD31 6 IO_L39P_6 AH38 6 IO_L39N_6/VREF_6 AH39 6 IO_L40P_6 AG36 6 IO_L40N_6 AG37 6 IO_L41P_6 AC28 6 IO_L41N_6 AC29 6 IO_L42P_6 AG38 6 IO_L42N_6 AG39 6 IO_L43P_6 AF35 6 IO_L43N_6 AF36 6 IO_L44P_6 AD32 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 219 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 220 Bank Pin Description Pin Number 6 IO_L44N_6 AD33 6 IO_L45P_6 AF38 6 IO_L45N_6/VREF_6 AF39 6 IO_L46P_6 AE33 6 IO_L46N_6 AE34 6 IO_L47P_6 AC30 6 IO_L47N_6 AC31 6 IO_L48P_6 AE37 6 IO_L48N_6 AE38 6 IO_L49P_6 AE35 6 IO_L49N_6 AE36 6 IO_L50P_6 AB28 6 IO_L50N_6 AB29 6 IO_L51P_6 AD36 6 IO_L51N_6/VREF_6 AD37 6 IO_L52P_6 AD34 6 IO_L52N_6 AD35 6 IO_L53P_6 AB30 6 IO_L53N_6 AB31 6 IO_L54P_6 AD38 6 IO_L54N_6 AD39 6 IO_L55P_6 AC33 6 IO_L55N_6 AC34 6 IO_L56P_6 AB32 6 IO_L56N_6 AB33 6 IO_L57P_6 AC36 6 IO_L57N_6/VREF_6 AC37 6 IO_L58P_6 AB34 6 IO_L58N_6 AB35 6 IO_L59P_6 AA28 6 IO_L59N_6 AA29 6 IO_L60P_6 AC38 6 IO_L60N_6 AC39 6 IO_L85P_6 AB36 6 IO_L85N_6 AB37 6 IO_L86P_6 AA30 6 IO_L86N_6 AA31 6 IO_L87P_6 AB38 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 6 IO_L87N_6/VREF_6 AB39 6 IO_L88P_6 AA34 6 IO_L88N_6 AA35 6 IO_L89P_6 AA32 6 IO_L89N_6 AA33 6 IO_L90P_6 AA36 6 IO_L90N_6 AA37 7 IO_L90P_7 W37 7 IO_L90N_7 W36 7 IO_L89P_7 W33 7 IO_L89N_7 W32 7 IO_L88P_7 V39 7 IO_L88N_7/VREF_7 V38 7 IO_L87P_7 W35 7 IO_L87N_7 W34 7 IO_L86P_7 W31 7 IO_L86N_7 W30 7 IO_L85P_7 V37 7 IO_L85N_7 V36 7 IO_L60P_7 V35 7 IO_L60N_7 V34 7 IO_L59P_7 W29 7 IO_L59N_7 W28 7 IO_L58P_7 U39 7 IO_L58N_7/VREF_7 U38 7 IO_L57P_7 U34 7 IO_L57N_7 U33 7 IO_L56P_7 V33 7 IO_L56N_7 V32 7 IO_L55P_7 U37 7 IO_L55N_7 U36 7 IO_L54P_7 T37 7 IO_L54N_7 T36 7 IO_L53P_7 V31 7 IO_L53N_7 V30 7 IO_L52P_7 T39 7 IO_L52N_7/VREF_7 T38 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 221 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 222 Bank Pin Description Pin Number 7 IO_L51P_7 T35 7 IO_L51N_7 T34 7 IO_L50P_7 V29 7 IO_L50N_7 V28 7 IO_L49P_7 R38 7 IO_L49N_7 R37 7 IO_L48P_7 R36 7 IO_L48N_7 R35 7 IO_L47P_7 U31 7 IO_L47N_7 U30 7 IO_L46P_7 P39 7 IO_L46N_7/VREF_7 P38 7 IO_L45P_7 R34 7 IO_L45N_7 R33 7 IO_L44P_7 T33 7 IO_L44N_7 T32 7 IO_L43P_7 N39 7 IO_L43N_7 N38 7 IO_L42P_7 P36 7 IO_L42N_7 P35 7 IO_L41P_7 U29 7 IO_L41N_7 U28 7 IO_L40P_7 N37 7 IO_L40N_7/VREF_7 N36 7 IO_L39P_7 N35 7 IO_L39N_7 N34 7 IO_L38P_7 T31 7 IO_L38N_7 T30 7 IO_L37P_7 M39 7 IO_L37N_7 M38 7 IO_L36P_7 M35 7 IO_L36N_7 M34 7 IO_L35P_7 T29 7 IO_L35N_7 T28 7 IO_L34P_7 M37 7 IO_L34N_7/VREF_7 M36 7 IO_L33P_7 N33 7 IO_L33N_7 N32 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 7 IO_L32P_7 R31 7 IO_L32N_7 R30 7 IO_L31P_7 L38 7 IO_L31N_7 L37 7 IO_L30P_7 L35 7 IO_L30N_7 L34 7 IO_L29P_7 P33 7 IO_L29N_7 P32 7 IO_L28P_7 K39 7 IO_L28N_7/VREF_7 K38 7 IO_L27P_7 K36 7 IO_L27N_7 K35 7 IO_L26P_7 P31 7 IO_L26N_7 P30 7 IO_L25P_7 J39 7 IO_L25N_7 J38 7 IO_L24P_7 J37 7 IO_L24N_7 J36 7 IO_L23P_7 R29 7 IO_L23N_7 R28 7 IO_L22P_7 H39 7 IO_L22N_7/VREF_7 H38 7 IO_L21P_7 K34 7 IO_L21N_7 K33 7 IO_L20P_7 N31 7 IO_L20N_7 N30 7 IO_L19P_7 G39 7 IO_L19N_7 G38 7 IO_L18P_7 J35 7 IO_L18N_7 J34 7 IO_L17P_7 P29 7 IO_L17N_7 P28 7 IO_L16P_7 H37 7 IO_L16N_7/VREF_7 H36 7 IO_L15P_7 H35 7 IO_L15N_7 H34 7 IO_L14P_7 L33 7 IO_L14N_7 L32 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 223 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 224 Bank Pin Description Pin Number 7 IO_L13P_7 F39 7 IO_L13N_7 F38 7 IO_L12P_7 F37 7 IO_L12N_7 F36 7 IO_L11P_7 N29 7 IO_L11N_7 N28 7 IO_L10P_7 G37 7 IO_L10N_7/VREF_7 G36 7 IO_L09P_7 G35 7 IO_L09N_7 G34 7 IO_L08P_7 K32 7 IO_L08N_7 K31 7 IO_L07P_7 E39 7 IO_L07N_7 E38 7 IO_L06P_7 F35 7 IO_L06N_7 E34 7 IO_L05P_7 J33 7 IO_L05N_7 J32 7 IO_L04P_7 D39 7 IO_L04N_7/VREF_7 D38 7 IO_L03P_7 D35 7 IO_L03N_7 C35 7 IO_L02P_7 H33 7 IO_L02N_7 G32 7 IO_L01P_7/VRN_7 E37 7 IO_L01N_7/VRP_7 E36 0 VCCO_0 P25 0 VCCO_0 P24 0 VCCO_0 P23 0 VCCO_0 P22 0 VCCO_0 P21 0 VCCO_0 N26 0 VCCO_0 N25 0 VCCO_0 N24 0 VCCO_0 N23 0 VCCO_0 N22 0 VCCO_0 N21 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 0 VCCO_0 N20 0 VCCO_0 H23 0 VCCO_0 F26 0 VCCO_0 E28 1 VCCO_1 P20 1 VCCO_1 P19 1 VCCO_1 P18 1 VCCO_1 P17 1 VCCO_1 P16 1 VCCO_1 P15 1 VCCO_1 N19 1 VCCO_1 N18 1 VCCO_1 N17 1 VCCO_1 N16 1 VCCO_1 N15 1 VCCO_1 N14 1 VCCO_1 H17 1 VCCO_1 F14 1 VCCO_1 E12 2 VCCO_2 Y13 2 VCCO_2 W14 2 VCCO_2 W13 2 VCCO_2 V14 2 VCCO_2 V13 2 VCCO_2 U14 2 VCCO_2 U13 2 VCCO_2 T14 2 VCCO_2 T13 2 VCCO_2 R14 2 VCCO_2 R13 2 VCCO_2 R8 2 VCCO_2 P13 2 VCCO_2 M7 2 VCCO_2 L4 3 VCCO_3 AJ4 3 VCCO_3 AH7 3 VCCO_3 AF13 3 VCCO_3 AE14 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 225 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 226 Bank Pin Description Pin Number 3 VCCO_3 AE13 3 VCCO_3 AE8 3 VCCO_3 AD14 3 VCCO_3 AD13 3 VCCO_3 AC14 3 VCCO_3 AC13 3 VCCO_3 AB14 3 VCCO_3 AB13 3 VCCO_3 AA14 3 VCCO_3 AA13 3 VCCO_3 Y14 4 VCCO_4 AR12 4 VCCO_4 AP14 4 VCCO_4 AM17 4 VCCO_4 AG20 4 VCCO_4 AG19 4 VCCO_4 AG18 4 VCCO_4 AG17 4 VCCO_4 AG16 4 VCCO_4 AG15 4 VCCO_4 AG14 4 VCCO_4 AF19 4 VCCO_4 AF18 4 VCCO_4 AF17 4 VCCO_4 AF16 4 VCCO_4 AF15 5 VCCO_5 AR28 5 VCCO_5 AP26 5 VCCO_5 AM23 5 VCCO_5 AG26 5 VCCO_5 AG25 5 VCCO_5 AG24 5 VCCO_5 AG23 5 VCCO_5 AG22 5 VCCO_5 AG21 5 VCCO_5 AF25 5 VCCO_5 AF24 5 VCCO_5 AF23 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number 5 VCCO_5 AF22 5 VCCO_5 AF21 5 VCCO_5 AF20 6 VCCO_6 AJ36 6 VCCO_6 AH33 6 VCCO_6 AF27 6 VCCO_6 AE32 6 VCCO_6 AE27 6 VCCO_6 AE26 6 VCCO_6 AD27 6 VCCO_6 AD26 6 VCCO_6 AC27 6 VCCO_6 AC26 6 VCCO_6 AB27 6 VCCO_6 AB26 6 VCCO_6 AA27 6 VCCO_6 AA26 6 VCCO_6 Y27 7 VCCO_7 Y26 7 VCCO_7 W27 7 VCCO_7 W26 7 VCCO_7 V27 7 VCCO_7 V26 7 VCCO_7 U27 7 VCCO_7 U26 7 VCCO_7 T27 7 VCCO_7 T26 7 VCCO_7 R32 7 VCCO_7 R27 7 VCCO_7 R26 7 VCCO_7 P27 7 VCCO_7 M33 7 VCCO_7 L36 N/A CCLK AT6 N/A PROG_B E33 N/A DONE AL10 N/A M0 AT33 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 227 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 228 Bank Pin Description Pin Number N/A M1 AT34 N/A M2 AL30 N/A TCK E7 N/A TDI F33 N/A TDO F7 N/A TMS D6 N/A PWRDWN_B AT7 N/A HSWAP_EN D34 N/A RSVD D7 N/A VBATT J10 N/A DXP J30 N/A DXN D33 N/A AVCCAUXTX2 B35 N/A VTTXPAD2 B36 N/A TXNPAD2 A36 N/A TXPPAD2 A35 N/A GNDA2 C34 N/A GNDA2 C34 N/A RXPPAD2 A34 N/A RXNPAD2 A33 N/A VTRXPAD2 B34 N/A AVCCAUXRX2 B33 N/A AVCCAUXTX4 B31 N/A VTTXPAD4 B32 N/A TXNPAD4 A32 N/A TXPPAD4 A31 N/A GNDA4 C31 N/A GNDA4 C31 N/A RXPPAD4 A30 N/A RXNPAD4 A29 N/A VTRXPAD4 B30 N/A AVCCAUXRX4 B29 N/A AVCCAUXTX5 B27 N/A VTTXPAD5 B28 N/A TXNPAD5 A28 N/A TXPPAD5 A27 N/A GNDA5 C27 N/A GNDA5 C27 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number N/A RXPPAD5 A26 N/A RXNPAD5 A25 N/A VTRXPAD5 B26 N/A AVCCAUXRX5 B25 N/A AVCCAUXTX6 B23 N/A VTTXPAD6 B24 N/A TXNPAD6 A24 N/A TXPPAD6 A23 N/A GNDA6 C24 N/A GNDA6 C24 N/A RXPPAD6 A22 N/A RXNPAD6 A21 N/A VTRXPAD6 B22 N/A AVCCAUXRX6 B21 N/A AVCCAUXTX7 B18 N/A VTTXPAD7 B19 N/A TXNPAD7 A19 N/A TXPPAD7 A18 N/A GNDA7 C16 N/A GNDA7 C16 N/A RXPPAD7 A17 N/A RXNPAD7 A16 N/A VTRXPAD7 B17 N/A AVCCAUXRX7 B16 N/A AVCCAUXTX8 B14 N/A VTTXPAD8 B15 N/A TXNPAD8 A15 N/A TXPPAD8 A14 N/A GNDA8 C13 N/A GNDA8 C13 N/A RXPPAD8 A13 N/A RXNPAD8 A12 N/A VTRXPAD8 B13 N/A AVCCAUXRX8 B12 N/A AVCCAUXTX9 B10 N/A VTTXPAD9 B11 N/A TXNPAD9 A11 N/A TXPPAD9 A10 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 229 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 230 Bank Pin Description Pin Number N/A GNDA9 C9 N/A GNDA9 C9 N/A RXPPAD9 A9 N/A RXNPAD9 A8 N/A VTRXPAD9 B9 N/A AVCCAUXRX9 B8 N/A AVCCAUXTX11 B6 N/A VTTXPAD11 B7 N/A TXNPAD11 A7 N/A TXPPAD11 A6 N/A GNDA11 C6 N/A GNDA11 C6 N/A RXPPAD11 A5 N/A RXNPAD11 A4 N/A VTRXPAD11 B5 N/A AVCCAUXRX11 B4 N/A AVCCAUXRX14 AV4 N/A VTRXPAD14 AV5 N/A RXNPAD14 AW4 N/A RXPPAD14 AW5 N/A GNDA14 AU6 N/A GNDA14 AU6 N/A TXPPAD14 AW6 N/A TXNPAD14 AW7 N/A VTTXPAD14 AV7 N/A AVCCAUXTX14 AV6 N/A AVCCAUXRX16 AV8 N/A VTRXPAD16 AV9 N/A RXNPAD16 AW8 N/A RXPPAD16 AW9 N/A GNDA16 AU9 N/A GNDA16 AU9 N/A TXPPAD16 AW10 N/A TXNPAD16 AW11 N/A VTTXPAD16 AV11 N/A AVCCAUXTX16 AV10 N/A AVCCAUXRX17 AV12 N/A VTRXPAD17 AV13 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number N/A RXNPAD17 AW12 N/A RXPPAD17 AW13 N/A GNDA17 AU13 N/A GNDA17 AU13 N/A TXPPAD17 AW14 N/A TXNPAD17 AW15 N/A VTTXPAD17 AV15 N/A AVCCAUXTX17 AV14 N/A AVCCAUXRX18 AV16 N/A VTRXPAD18 AV17 N/A RXNPAD18 AW16 N/A RXPPAD18 AW17 N/A GNDA18 AU16 N/A GNDA18 AU16 N/A TXPPAD18 AW18 N/A TXNPAD18 AW19 N/A VTTXPAD18 AV19 N/A AVCCAUXTX18 AV18 N/A AVCCAUXRX19 AV21 N/A VTRXPAD19 AV22 N/A RXNPAD19 AW21 N/A RXPPAD19 AW22 N/A GNDA19 AU24 N/A GNDA19 AU24 N/A TXPPAD19 AW23 N/A TXNPAD19 AW24 N/A VTTXPAD19 AV24 N/A AVCCAUXTX19 AV23 N/A AVCCAUXRX20 AV25 N/A VTRXPAD20 AV26 N/A RXNPAD20 AW25 N/A RXPPAD20 AW26 N/A GNDA20 AU27 N/A GNDA20 AU27 N/A TXPPAD20 AW27 N/A TXNPAD20 AW28 N/A VTTXPAD20 AV28 N/A AVCCAUXTX20 AV27 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 231 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 232 Bank Pin Description Pin Number N/A AVCCAUXRX21 AV29 N/A VTRXPAD21 AV30 N/A RXNPAD21 AW29 N/A RXPPAD21 AW30 N/A GNDA21 AU31 N/A GNDA21 AU31 N/A TXPPAD21 AW31 N/A TXNPAD21 AW32 N/A VTTXPAD21 AV32 N/A AVCCAUXTX21 AV31 N/A AVCCAUXRX23 AV33 N/A VTRXPAD23 AV34 N/A RXNPAD23 AW33 N/A RXPPAD23 AW34 N/A GNDA23 AU34 N/A GNDA23 AU34 N/A TXPPAD23 AW35 N/A TXNPAD23 AW36 N/A VTTXPAD23 AV36 N/A AVCCAUXTX23 AV35 N/A VCCINT AH28 N/A VCCINT AH12 N/A VCCINT AG27 N/A VCCINT AG13 N/A VCCINT AF26 N/A VCCINT AF14 N/A VCCINT AE25 N/A VCCINT AE24 N/A VCCINT AE23 N/A VCCINT AE22 N/A VCCINT AE21 N/A VCCINT AE20 N/A VCCINT AE19 N/A VCCINT AE18 N/A VCCINT AE17 N/A VCCINT AE16 N/A VCCINT AE15 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number N/A VCCINT AD25 N/A VCCINT AD24 N/A VCCINT AD16 N/A VCCINT AD15 N/A VCCINT AC25 N/A VCCINT AC15 N/A VCCINT AB25 N/A VCCINT AB15 N/A VCCINT AA25 N/A VCCINT AA15 N/A VCCINT Y25 N/A VCCINT Y15 N/A VCCINT W25 N/A VCCINT W15 N/A VCCINT V25 N/A VCCINT V15 N/A VCCINT U25 N/A VCCINT U15 N/A VCCINT T25 N/A VCCINT T24 N/A VCCINT T16 N/A VCCINT T15 N/A VCCINT R25 N/A VCCINT R24 N/A VCCINT R23 N/A VCCINT R22 N/A VCCINT R21 N/A VCCINT R20 N/A VCCINT R19 N/A VCCINT R18 N/A VCCINT R17 N/A VCCINT R16 N/A VCCINT R15 N/A VCCINT P26 N/A VCCINT P14 N/A VCCINT N27 N/A VCCINT N13 N/A VCCINT M28 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 233 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 234 Bank Pin Description Pin Number N/A VCCINT M12 N/A VCCAUX AV20 N/A VCCAUX AU36 N/A VCCAUX AU20 N/A VCCAUX AU4 N/A VCCAUX AT37 N/A VCCAUX AT3 N/A VCCAUX AL31 N/A VCCAUX AL9 N/A VCCAUX AK30 N/A VCCAUX AK10 N/A VCCAUX AA39 N/A VCCAUX AA1 N/A VCCAUX Y39 N/A VCCAUX Y38 N/A VCCAUX Y2 N/A VCCAUX Y1 N/A VCCAUX W39 N/A VCCAUX W1 N/A VCCAUX K30 N/A VCCAUX K10 N/A VCCAUX J31 N/A VCCAUX J9 N/A VCCAUX D37 N/A VCCAUX D3 N/A VCCAUX C36 N/A VCCAUX C20 N/A VCCAUX C4 N/A VCCAUX B20 N/A GND AW38 N/A GND AW37 N/A GND AW20 N/A GND AW3 N/A GND AW2 N/A GND AV39 N/A GND AV38 N/A GND AV37 N/A GND AV3 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number N/A GND AV2 N/A GND AV1 N/A GND AU39 N/A GND AU38 N/A GND AU37 N/A GND AU30 N/A GND AU26 N/A GND AU14 N/A GND AU10 N/A GND AU3 N/A GND AU2 N/A GND AU1 N/A GND AT36 N/A GND AT20 N/A GND AT4 N/A GND AR35 N/A GND AR23 N/A GND AR17 N/A GND AR5 N/A GND AP34 N/A GND AP6 N/A GND AN33 N/A GND AN20 N/A GND AN7 N/A GND AM32 N/A GND AM8 N/A GND AK37 N/A GND AK20 N/A GND AK3 N/A GND AJ39 N/A GND AJ1 N/A GND AF37 N/A GND AF34 N/A GND AF6 N/A GND AF3 N/A GND AE39 N/A GND AE1 N/A GND AD23 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 235 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 236 Bank Pin Description Pin Number N/A GND AD22 N/A GND AD21 N/A GND AD20 N/A GND AD19 N/A GND AD18 N/A GND AD17 N/A GND AC35 N/A GND AC32 N/A GND AC24 N/A GND AC23 N/A GND AC22 N/A GND AC21 N/A GND AC20 N/A GND AC19 N/A GND AC18 N/A GND AC17 N/A GND AC16 N/A GND AC8 N/A GND AC5 N/A GND AB24 N/A GND AB23 N/A GND AB22 N/A GND AB21 N/A GND AB20 N/A GND AB19 N/A GND AB18 N/A GND AB17 N/A GND AB16 N/A GND AA38 N/A GND AA24 N/A GND AA23 N/A GND AA22 N/A GND AA21 N/A GND AA20 N/A GND AA19 N/A GND AA18 N/A GND AA17 N/A GND AA16 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number N/A GND AA2 N/A GND Y37 N/A GND Y36 N/A GND Y33 N/A GND Y30 N/A GND Y24 N/A GND Y23 N/A GND Y22 N/A GND Y21 N/A GND Y20 N/A GND Y19 N/A GND Y18 N/A GND Y17 N/A GND Y16 N/A GND Y10 N/A GND Y7 N/A GND Y4 N/A GND Y3 N/A GND W38 N/A GND W24 N/A GND W23 N/A GND W22 N/A GND W21 N/A GND W20 N/A GND W19 N/A GND W18 N/A GND W17 N/A GND W16 N/A GND W2 N/A GND V24 N/A GND V23 N/A GND V22 N/A GND V21 N/A GND V20 N/A GND V19 N/A GND V18 N/A GND V17 N/A GND V16 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 237 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Module 4 of 4 238 Bank Pin Description Pin Number N/A GND U35 N/A GND U32 N/A GND U24 N/A GND U23 N/A GND U22 N/A GND U21 N/A GND U20 N/A GND U19 N/A GND U18 N/A GND U17 N/A GND U16 N/A GND U8 N/A GND U5 N/A GND T23 N/A GND T22 N/A GND T21 N/A GND T20 N/A GND T19 N/A GND T18 N/A GND T17 N/A GND R39 N/A GND R1 N/A GND P37 N/A GND P34 N/A GND P6 N/A GND P3 N/A GND L39 N/A GND L1 N/A GND K37 N/A GND K20 N/A GND K3 N/A GND H32 N/A GND H8 N/A GND G33 N/A GND G20 N/A GND G7 N/A GND F34 N/A GND F6 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 11: FF1517 -- XC2VP50 Bank Pin Description Pin Number N/A GND E35 N/A GND E23 N/A GND E17 N/A GND E5 N/A GND D36 N/A GND D20 N/A GND D4 N/A GND C39 N/A GND C38 N/A GND C37 N/A GND C30 N/A GND C26 N/A GND C14 N/A GND C10 N/A GND C3 N/A GND C2 N/A GND C1 N/A GND B39 N/A GND B38 N/A GND B37 N/A GND B3 N/A GND B2 N/A GND B1 N/A GND A38 N/A GND A37 N/A GND A20 N/A GND A3 N/A GND A2 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 239 R Virtex-II ProTM Platform FPGAs: Pinout Information FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 6: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications Module 4 of 4 240 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information BF957 Flip-Chip BGA Package As shown in Table 12, XC2VP20 and XC2VP50 Virtex-II Pro devices are available in the BF957 flip-chip BGA package. Pins in each of these devices are the same, except for the differences shown in the "No Connects" column. Following this table are the BF957 Flip-Chip BGA Package Specifications (1.27mm pitch). Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 E26 0 IO_L01P_0/VRN_0 E25 0 IO_L02N_0 H23 0 IO_L02P_0 G23 0 IO_L03N_0 F25 0 IO_L03P_0/VREF_0 F24 0 IO_L05_0/No_Pair G24 0 IO_L06N_0 J22 0 IO_L06P_0 H22 0 IO_L07N_0 F23 0 IO_L07P_0 E23 0 IO_L08N_0 D25 0 IO_L08P_0 C25 0 IO_L09N_0 K21 0 IO_L09P_0/VREF_0 J21 0 IO_L19N_0 G22 NC 0 IO_L19P_0 F22 NC 0 IO_L37N_0 H21 0 IO_L37P_0 G21 0 IO_L38N_0 E24 0 IO_L38P_0 D24 0 IO_L39N_0 K20 0 IO_L39P_0 J20 0 IO_L43N_0 F21 0 IO_L43P_0 E21 0 IO_L44N_0 D23 0 IO_L44P_0 D22 0 IO_L45N_0 H20 0 IO_L45P_0/VREF_0 G20 0 IO_L46N_0 F20 0 IO_L46P_0 E20 0 IO_L47N_0 C22 0 IO_L47P_0 C21 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 241 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 0 IO_L48N_0 K19 0 IO_L48P_0 J19 0 IO_L49N_0 H19 0 IO_L49P_0 G19 0 IO_L50_0/No_Pair D21 0 IO_L53_0/No_Pair D20 0 IO_L54N_0 K18 0 IO_L54P_0 J18 0 IO_L55N_0 F18 0 IO_L55P_0 E18 0 IO_L56N_0 E19 0 IO_L56P_0 D19 0 IO_L57N_0 H18 0 IO_L57P_0/VREF_0 G18 0 IO_L67N_0 H17 0 IO_L67P_0 G17 0 IO_L68N_0 D18 0 IO_L68P_0 C18 0 IO_L69N_0 K17 0 IO_L69P_0/VREF_0 J17 0 IO_L73N_0 F17 0 IO_L73P_0 E17 0 IO_L74N_0/GCLK7P D17 0 IO_L74P_0/GCLK6S C17 0 IO_L75N_0/GCLK5P F16 0 IO_L75P_0/GCLK4S E16 1 IO_L75N_1/GCLK3P H16 1 IO_L75P_1/GCLK2S J16 1 IO_L74N_1/GCLK1P C15 1 IO_L74P_1/GCLK0S D15 1 IO_L73N_1 E15 1 IO_L73P_1 F15 1 IO_L69N_1/VREF_1 J15 1 IO_L69P_1 K15 1 IO_L68N_1 C14 1 IO_L68P_1 D14 1 IO_L67N_1 G15 Module 4 of 4 242 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 1 IO_L67P_1 H15 1 IO_L57N_1/VREF_1 G14 1 IO_L57P_1 H14 1 IO_L56N_1 D13 1 IO_L56P_1 E13 1 IO_L55N_1 E14 1 IO_L55P_1 F14 1 IO_L54N_1 J14 1 IO_L54P_1 K14 1 IO_L53_1/No_Pair D12 1 IO_L50_1/No_Pair D11 1 IO_L49N_1 G13 1 IO_L49P_1 H13 1 IO_L48N_1 J13 1 IO_L48P_1 K13 1 IO_L47N_1 C11 1 IO_L47P_1 C10 1 IO_L46N_1 E12 1 IO_L46P_1 F12 1 IO_L45N_1/VREF_1 G12 1 IO_L45P_1 H12 1 IO_L44N_1 D10 1 IO_L44P_1 D9 1 IO_L43N_1 E11 1 IO_L43P_1 F11 1 IO_L39N_1 J12 1 IO_L39P_1 K12 1 IO_L38N_1 D8 1 IO_L38P_1 E8 1 IO_L37N_1 G11 1 IO_L37P_1 H11 1 IO_L19N_1 F10 NC 1 IO_L19P_1 G10 NC 1 IO_L09N_1/VREF_1 J11 1 IO_L09P_1 K11 1 IO_L08N_1 C7 1 IO_L08P_1 D7 1 IO_L07N_1 E9 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 243 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 1 IO_L07P_1 F9 1 IO_L06N_1 H10 1 IO_L06P_1 J10 1 IO_L05_1/No_Pair G8 1 IO_L03N_1/VREF_1 F8 1 IO_L03P_1 F7 1 IO_L02N_1 G9 1 IO_L02P_1 H9 1 IO_L01N_1/VRP_1 E7 1 IO_L01P_1/VRN_1 E6 2 IO_L01N_2/VRP_2 D2 2 IO_L01P_2/VRN_2 D1 2 IO_L02N_2 K9 2 IO_L02P_2 K8 2 IO_L03N_2 C4 2 IO_L03P_2 D3 2 IO_L04N_2/VREF_2 E2 2 IO_L04P_2 E1 2 IO_L05N_2 L10 2 IO_L05P_2 L9 2 IO_L06N_2 E4 2 IO_L06P_2 E3 2 IO_L18N_2 F5 NC 2 IO_L18P_2 F4 NC 2 IO_L31N_2 G4 2 IO_L31P_2 G3 2 IO_L32N_2 J7 2 IO_L32P_2 J6 2 IO_L33N_2 G6 2 IO_L33P_2 G5 2 IO_L34N_2/VREF_2 F2 2 IO_L34P_2 F1 2 IO_L35N_2 K7 2 IO_L35P_2 K6 2 IO_L36N_2 H5 2 IO_L36P_2 H4 2 IO_L37N_2 G2 Module 4 of 4 244 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 2 IO_L37P_2 G1 2 IO_L38N_2 M10 2 IO_L38P_2 M9 2 IO_L39N_2 J4 2 IO_L39P_2 J3 2 IO_L40N_2/VREF_2 H2 2 IO_L40P_2 H1 2 IO_L41N_2 L8 2 IO_L41P_2 L7 2 IO_L42N_2 K5 2 IO_L42P_2 K4 2 IO_L43N_2 J2 2 IO_L43P_2 J1 2 IO_L44N_2 M8 2 IO_L44P_2 M7 2 IO_L45N_2 L6 2 IO_L45P_2 L5 2 IO_L46N_2/VREF_2 K2 2 IO_L46P_2 K1 2 IO_L47N_2 N10 2 IO_L47P_2 N9 2 IO_L48N_2 L4 2 IO_L48P_2 L3 2 IO_L49N_2 L2 2 IO_L49P_2 L1 2 IO_L50N_2 M6 2 IO_L50P_2 M5 2 IO_L51N_2 M4 2 IO_L51P_2 M3 2 IO_L52N_2/VREF_2 M2 2 IO_L52P_2 M1 2 IO_L53N_2 N8 2 IO_L53P_2 N7 2 IO_L54N_2 N5 2 IO_L54P_2 N4 2 IO_L55N_2 N2 2 IO_L55P_2 N1 2 IO_L56N_2 P10 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 245 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 2 IO_L56P_2 P9 2 IO_L57N_2 P6 2 IO_L57P_2 P5 2 IO_L58N_2/VREF_2 P4 2 IO_L58P_2 P3 2 IO_L59N_2 P8 2 IO_L59P_2 P7 2 IO_L60N_2 R6 2 IO_L60P_2 R5 2 IO_L85N_2 P2 2 IO_L85P_2 P1 2 IO_L86N_2 R10 2 IO_L86P_2 R9 2 IO_L87N_2 R4 2 IO_L87P_2 R3 2 IO_L88N_2/VREF_2 R2 2 IO_L88P_2 R1 2 IO_L89N_2 R8 2 IO_L89P_2 R7 2 IO_L90N_2 T5 2 IO_L90P_2 T6 3 IO_L90N_3 U1 3 IO_L90P_3 U2 3 IO_L89N_3 T8 3 IO_L89P_3 T9 3 IO_L88N_3 U3 3 IO_L88P_3 U4 3 IO_L87N_3/VREF_3 V1 3 IO_L87P_3 V2 3 IO_L86N_3 U7 3 IO_L86P_3 U8 3 IO_L85N_3 U5 3 IO_L85P_3 U6 3 IO_L60N_3 V3 3 IO_L60P_3 V4 3 IO_L59N_3 U9 3 IO_L59P_3 U10 Module 4 of 4 246 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 3 IO_L58N_3 V5 3 IO_L58P_3 V6 3 IO_L57N_3/VREF_3 W1 3 IO_L57P_3 W2 3 IO_L56N_3 V7 3 IO_L56P_3 V8 3 IO_L55N_3 W4 3 IO_L55P_3 W5 3 IO_L54N_3 Y1 3 IO_L54P_3 Y2 3 IO_L53N_3 V9 3 IO_L53P_3 V10 3 IO_L52N_3 Y3 3 IO_L52P_3 Y4 3 IO_L51N_3/VREF_3 AA1 3 IO_L51P_3 AA2 3 IO_L50N_3 W7 3 IO_L50P_3 W8 3 IO_L49N_3 Y5 3 IO_L49P_3 Y6 3 IO_L48N_3 AB1 3 IO_L48P_3 AB2 3 IO_L47N_3 W9 3 IO_L47P_3 W10 3 IO_L46N_3 AA3 3 IO_L46P_3 AA4 3 IO_L45N_3/VREF_3 AC1 3 IO_L45P_3 AC2 3 IO_L44N_3 Y7 3 IO_L44P_3 Y8 3 IO_L43N_3 AA5 3 IO_L43P_3 AA6 3 IO_L42N_3 AD1 3 IO_L42P_3 AD2 3 IO_L41N_3 AA7 3 IO_L41P_3 AA8 3 IO_L40N_3 AB4 3 IO_L40P_3 AB5 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 247 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 3 IO_L39N_3/VREF_3 AC3 3 IO_L39P_3 AC4 3 IO_L38N_3 Y9 3 IO_L38P_3 Y10 3 IO_L37N_3 AD4 3 IO_L37P_3 AD5 3 IO_L36N_3 AE1 3 IO_L36P_3 AE2 3 IO_L35N_3 AB6 3 IO_L35P_3 AB7 3 IO_L34N_3 AE3 3 IO_L34P_3 AE4 3 IO_L33N_3/VREF_3 AF1 3 IO_L33P_3 AF2 3 IO_L32N_3 AC6 3 IO_L32P_3 AC7 3 IO_L31N_3 AE5 3 IO_L31P_3 AE6 3 IO_L18N_3 AG1 NC 3 IO_L18P_3 AG2 NC 3 IO_L17N_3 AA9 NC 3 IO_L17P_3 AA10 NC 3 IO_L06N_3 AH1 3 IO_L06P_3 AH2 3 IO_L05N_3 AB8 3 IO_L05P_3 AB9 3 IO_L04N_3 AF4 3 IO_L04P_3 AF5 3 IO_L03N_3/VREF_3 AG3 3 IO_L03P_3 AG4 3 IO_L02N_3 AD6 3 IO_L02P_3 AD7 3 IO_L01N_3/VRP_3 AH3 3 IO_L01P_3/VRN_3 AJ4 4 IO_L01N_4/DOUT AG6 4 IO_L01P_4/INIT_B AG7 4 IO_L02N_4/D0 AF7 Module 4 of 4 248 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 4 IO_L02P_4/D1 AF8 4 IO_L03N_4/D2 AH7 4 IO_L03P_4/D3 AJ7 4 IO_L05_4/No_Pair AE8 4 IO_L06N_4/VRP_4 AG8 4 IO_L06P_4/VRN_4 AH8 4 IO_L07N_4 AC10 4 IO_L07P_4/VREF_4 AD10 4 IO_L08N_4 AD9 4 IO_L08P_4 AE9 4 IO_L09N_4 AF9 4 IO_L09P_4/VREF_4 AG9 4 IO_L19N_4 AB11 NC 4 IO_L19P_4 AC11 NC 4 IO_L37N_4 AB12 4 IO_L37P_4 AC12 4 IO_L38N_4 AE10 4 IO_L38P_4 AF10 4 IO_L39N_4 AH9 4 IO_L39P_4 AH10 4 IO_L43N_4 AD11 4 IO_L43P_4 AE11 4 IO_L44N_4 AF11 4 IO_L44P_4 AG11 4 IO_L45N_4 AJ10 4 IO_L45P_4/VREF_4 AJ11 4 IO_L46N_4 AB13 4 IO_L46P_4 AC13 4 IO_L47N_4 AD12 4 IO_L47P_4 AE12 4 IO_L48N_4 AH11 4 IO_L48P_4 AH12 4 IO_L49N_4 AB14 4 IO_L49P_4 AC14 4 IO_L50_4/No_Pair AF12 4 IO_L53_4/No_Pair AG12 4 IO_L54N_4 AG13 4 IO_L54P_4 AH13 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 249 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 4 IO_L55N_4 AD14 4 IO_L55P_4 AE14 4 IO_L56N_4 AD13 4 IO_L56P_4 AE13 4 IO_L57N_4 AF14 4 IO_L57P_4/VREF_4 AG14 4 IO_L67N_4 AB15 4 IO_L67P_4 AC15 4 IO_L68N_4 AD15 4 IO_L68P_4 AE15 4 IO_L69N_4 AH14 4 IO_L69P_4/VREF_4 AJ14 4 IO_L73N_4 AC16 4 IO_L73P_4 AD16 4 IO_L74N_4/GCLK3S AF15 4 IO_L74P_4/GCLK2P AG15 4 IO_L75N_4/GCLK1S AH15 4 IO_L75P_4/GCLK0P AJ15 5 IO_L75N_5/GCLK7S AJ17 5 IO_L75P_5/GCLK6P AH17 5 IO_L74N_5/GCLK5S AG17 5 IO_L74P_5/GCLK4P AF17 5 IO_L73N_5 AG16 5 IO_L73P_5 AF16 5 IO_L69N_5/VREF_5 AJ18 5 IO_L69P_5 AH18 5 IO_L68N_5 AE17 5 IO_L68P_5 AD17 5 IO_L67N_5 AC17 5 IO_L67P_5 AB17 5 IO_L57N_5/VREF_5 AG18 5 IO_L57P_5 AF18 5 IO_L56N_5 AE19 5 IO_L56P_5 AD19 5 IO_L55N_5 AE18 5 IO_L55P_5 AD18 5 IO_L54N_5 AH19 Module 4 of 4 250 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 5 IO_L54P_5 AG19 5 IO_L53_5/No_Pair AG20 5 IO_L50_5/No_Pair AF20 5 IO_L49N_5 AC18 5 IO_L49P_5 AB18 5 IO_L48N_5 AH20 5 IO_L48P_5 AH21 5 IO_L47N_5 AE20 5 IO_L47P_5 AD20 5 IO_L46N_5 AC19 5 IO_L46P_5 AB19 5 IO_L45N_5/VREF_5 AJ21 5 IO_L45P_5 AJ22 5 IO_L44N_5 AG21 5 IO_L44P_5 AF21 5 IO_L43N_5 AE21 5 IO_L43P_5 AD21 5 IO_L39N_5 AH22 5 IO_L39P_5 AH23 5 IO_L38N_5 AF22 5 IO_L38P_5 AE22 5 IO_L37N_5 AC20 5 IO_L37P_5 AB20 5 IO_L19N_5 AC21 NC 5 IO_L19P_5 AB21 NC 5 IO_L09N_5/VREF_5 AG23 5 IO_L09P_5 AF23 5 IO_L08N_5 AE23 5 IO_L08P_5 AD23 5 IO_L07N_5/VREF_5 AD22 5 IO_L07P_5 AC22 5 IO_L06N_5/VRP_5 AH24 5 IO_L06P_5/VRN_5 AG24 5 IO_L05_5/No_Pair AE24 5 IO_L03N_5/D4 AJ25 5 IO_L03P_5/D5 AH25 5 IO_L02N_5/D6 AF24 5 IO_L02P_5/D7 AF25 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 251 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 5 IO_L01N_5/RDWR_B AG25 5 IO_L01P_5/CS_B AG26 6 IO_L01P_6/VRN_6 AJ28 6 IO_L01N_6/VRP_6 AH29 6 IO_L02P_6 AD25 6 IO_L02N_6 AD26 6 IO_L03P_6 AG28 6 IO_L03N_6/VREF_6 AG29 6 IO_L04P_6 AF27 6 IO_L04N_6 AF28 6 IO_L05P_6 AB23 6 IO_L05N_6 AB24 6 IO_L06P_6 AH30 6 IO_L06N_6 AH31 6 IO_L17P_6 AA22 NC 6 IO_L17N_6 AA23 NC 6 IO_L18P_6 AG30 NC 6 IO_L18N_6 AG31 NC 6 IO_L31P_6 AE26 6 IO_L31N_6 AE27 6 IO_L32P_6 AC25 6 IO_L32N_6 AC26 6 IO_L33P_6 AF30 6 IO_L33N_6/VREF_6 AF31 6 IO_L34P_6 AE28 6 IO_L34N_6 AE29 6 IO_L35P_6 AB25 6 IO_L35N_6 AB26 6 IO_L36P_6 AE30 6 IO_L36N_6 AE31 6 IO_L37P_6 AD27 6 IO_L37N_6 AD28 6 IO_L38P_6 Y22 6 IO_L38N_6 Y23 6 IO_L39P_6 AC28 6 IO_L39N_6/VREF_6 AC29 6 IO_L40P_6 AB27 Module 4 of 4 252 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 6 IO_L40N_6 AB28 6 IO_L41P_6 AA24 6 IO_L41N_6 AA25 6 IO_L42P_6 AD30 6 IO_L42N_6 AD31 6 IO_L43P_6 AA26 6 IO_L43N_6 AA27 6 IO_L44P_6 Y24 6 IO_L44N_6 Y25 6 IO_L45P_6 AC30 6 IO_L45N_6/VREF_6 AC31 6 IO_L46P_6 AA28 6 IO_L46N_6 AA29 6 IO_L47P_6 W22 6 IO_L47N_6 W23 6 IO_L48P_6 AB30 6 IO_L48N_6 AB31 6 IO_L49P_6 Y26 6 IO_L49N_6 Y27 6 IO_L50P_6 W24 6 IO_L50N_6 W25 6 IO_L51P_6 AA30 6 IO_L51N_6/VREF_6 AA31 6 IO_L52P_6 Y28 6 IO_L52N_6 Y29 6 IO_L53P_6 V22 6 IO_L53N_6 V23 6 IO_L54P_6 Y30 6 IO_L54N_6 Y31 6 IO_L55P_6 W27 6 IO_L55N_6 W28 6 IO_L56P_6 V24 6 IO_L56N_6 V25 6 IO_L57P_6 W30 6 IO_L57N_6/VREF_6 W31 6 IO_L58P_6 V26 6 IO_L58N_6 V27 6 IO_L59P_6 U22 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 253 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 6 IO_L59N_6 U23 6 IO_L60P_6 V28 6 IO_L60N_6 V29 6 IO_L85P_6 U26 6 IO_L85N_6 U27 6 IO_L86P_6 U24 6 IO_L86N_6 U25 6 IO_L87P_6 V30 6 IO_L87N_6/VREF_6 V31 6 IO_L88P_6 U28 6 IO_L88N_6 U29 6 IO_L89P_6 T23 6 IO_L89N_6 T24 6 IO_L90P_6 U30 6 IO_L90N_6 U31 7 IO_L90P_7 T26 7 IO_L90N_7 T27 7 IO_L89P_7 R25 7 IO_L89N_7 R24 7 IO_L88P_7 R31 7 IO_L88N_7/VREF_7 R30 7 IO_L87P_7 R29 7 IO_L87N_7 R28 7 IO_L86P_7 R23 7 IO_L86N_7 R22 7 IO_L85P_7 P31 7 IO_L85N_7 P30 7 IO_L60P_7 R27 7 IO_L60N_7 R26 7 IO_L59P_7 P25 7 IO_L59N_7 P24 7 IO_L58P_7 P29 7 IO_L58N_7/VREF_7 P28 7 IO_L57P_7 P27 7 IO_L57N_7 P26 7 IO_L56P_7 P23 7 IO_L56N_7 P22 Module 4 of 4 254 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 7 IO_L55P_7 N31 7 IO_L55N_7 N30 7 IO_L54P_7 N28 7 IO_L54N_7 N27 7 IO_L53P_7 N25 7 IO_L53N_7 N24 7 IO_L52P_7 M31 7 IO_L52N_7/VREF_7 M30 7 IO_L51P_7 M29 7 IO_L51N_7 M28 7 IO_L50P_7 M27 7 IO_L50N_7 M26 7 IO_L49P_7 L31 7 IO_L49N_7 L30 7 IO_L48P_7 L29 7 IO_L48N_7 L28 7 IO_L47P_7 N23 7 IO_L47N_7 N22 7 IO_L46P_7 K31 7 IO_L46N_7/VREF_7 K30 7 IO_L45P_7 L27 7 IO_L45N_7 L26 7 IO_L44P_7 M25 7 IO_L44N_7 M24 7 IO_L43P_7 J31 7 IO_L43N_7 J30 7 IO_L42P_7 K28 7 IO_L42N_7 K27 7 IO_L41P_7 L25 7 IO_L41N_7 L24 7 IO_L40P_7 H31 7 IO_L40N_7/VREF_7 H30 7 IO_L39P_7 J29 7 IO_L39N_7 J28 7 IO_L38P_7 M23 7 IO_L38N_7 M22 7 IO_L37P_7 G31 7 IO_L37N_7 G30 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 255 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number 7 IO_L36P_7 H28 7 IO_L36N_7 H27 7 IO_L35P_7 K26 7 IO_L35N_7 K25 7 IO_L34P_7 F31 7 IO_L34N_7/VREF_7 F30 7 IO_L33P_7 G27 7 IO_L33N_7 G26 7 IO_L32P_7 J26 7 IO_L32N_7 J25 7 IO_L31P_7 G29 7 IO_L31N_7 G28 7 IO_L18P_7 F28 NC 7 IO_L18N_7 F27 NC 7 IO_L06P_7 E29 7 IO_L06N_7 E28 7 IO_L05P_7 L23 7 IO_L05N_7 L22 7 IO_L04P_7 E31 7 IO_L04N_7/VREF_7 E30 7 IO_L03P_7 D29 7 IO_L03N_7 C28 7 IO_L02P_7 K24 7 IO_L02N_7 K23 7 IO_L01P_7/VRN_7 D31 7 IO_L01N_7/VRP_7 D30 0 VCCO_0 M19 0 VCCO_0 M18 0 VCCO_0 M17 0 VCCO_0 L20 0 VCCO_0 L19 0 VCCO_0 L18 0 VCCO_0 L17 0 VCCO_0 E22 0 VCCO_0 C26 0 VCCO_0 C19 1 VCCO_1 M15 Module 4 of 4 256 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 1 VCCO_1 M14 1 VCCO_1 M13 1 VCCO_1 L15 1 VCCO_1 L14 1 VCCO_1 L13 1 VCCO_1 L12 1 VCCO_1 E10 1 VCCO_1 C13 1 VCCO_1 C6 2 VCCO_2 R12 2 VCCO_2 R11 2 VCCO_2 P12 2 VCCO_2 P11 2 VCCO_2 N12 2 VCCO_2 N11 2 VCCO_2 N3 2 VCCO_2 M11 2 VCCO_2 J5 2 VCCO_2 F3 3 VCCO_3 AF3 3 VCCO_3 AC5 3 VCCO_3 Y11 3 VCCO_3 W12 3 VCCO_3 W11 3 VCCO_3 W3 3 VCCO_3 V12 3 VCCO_3 V11 3 VCCO_3 U12 3 VCCO_3 U11 4 VCCO_4 AJ13 4 VCCO_4 AJ6 4 VCCO_4 AG10 4 VCCO_4 AA15 4 VCCO_4 AA14 4 VCCO_4 AA13 4 VCCO_4 AA12 4 VCCO_4 Y15 4 VCCO_4 Y14 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 257 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number 4 VCCO_4 Y13 5 VCCO_5 AJ26 5 VCCO_5 AJ19 5 VCCO_5 AG22 5 VCCO_5 AA20 5 VCCO_5 AA19 5 VCCO_5 AA18 5 VCCO_5 AA17 5 VCCO_5 Y19 5 VCCO_5 Y18 5 VCCO_5 Y17 6 VCCO_6 AF29 6 VCCO_6 AC27 6 VCCO_6 Y21 6 VCCO_6 W29 6 VCCO_6 W21 6 VCCO_6 W20 6 VCCO_6 V21 6 VCCO_6 V20 6 VCCO_6 U21 6 VCCO_6 U20 7 VCCO_7 R21 7 VCCO_7 R20 7 VCCO_7 P21 7 VCCO_7 P20 7 VCCO_7 N29 7 VCCO_7 N21 7 VCCO_7 N20 7 VCCO_7 M21 7 VCCO_7 J27 7 VCCO_7 F29 N/A CCLK AC8 N/A PROG_B J24 N/A DONE AH6 N/A M0 AH27 N/A M1 AC24 N/A M2 AH26 Module 4 of 4 258 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number N/A TCK J8 N/A TDI H26 N/A TDO H6 N/A TMS H7 N/A PWRDWN_B AH5 N/A HSWAP_EN H25 N/A RSVD D6 N/A VBATT D5 N/A DXP D27 N/A DXN D26 N/A AVCCAUXTX2 B27 NC N/A VTTXPAD2 B28 NC N/A TXNPAD2 A28 NC N/A TXPPAD2 A27 NC N/A GNDA2 C27 NC N/A GNDA2 C27 NC N/A RXPPAD2 A26 NC N/A RXNPAD2 A25 NC N/A VTRXPAD2 B26 NC N/A AVCCAUXRX2 B25 NC N/A AVCCAUXTX4 B23 N/A VTTXPAD4 B24 N/A TXNPAD4 A24 N/A TXPPAD4 A23 N/A GNDA4 C24 N/A GNDA4 C24 N/A RXPPAD4 A22 N/A RXNPAD4 A21 N/A VTRXPAD4 B22 N/A AVCCAUXRX4 B21 N/A AVCCAUXTX6 B19 N/A VTTXPAD6 B20 N/A TXNPAD6 A20 N/A TXPPAD6 A19 N/A GNDA6 C20 N/A GNDA6 C20 N/A RXPPAD6 A18 N/A RXNPAD6 A17 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 259 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number N/A VTRXPAD6 B18 N/A AVCCAUXRX6 B17 N/A AVCCAUXTX7 B14 N/A VTTXPAD7 B15 N/A TXNPAD7 A15 N/A TXPPAD7 A14 N/A GNDA7 C12 N/A GNDA7 C12 N/A RXPPAD7 A13 N/A RXNPAD7 A12 N/A VTRXPAD7 B13 N/A AVCCAUXRX7 B12 N/A AVCCAUXTX9 B10 N/A VTTXPAD9 B11 N/A TXNPAD9 A11 N/A TXPPAD9 A10 N/A GNDA9 C8 N/A GNDA9 C8 N/A RXPPAD9 A9 N/A RXNPAD9 A8 N/A VTRXPAD9 B9 N/A AVCCAUXRX9 B8 N/A AVCCAUXTX11 B6 NC N/A VTTXPAD11 B7 NC N/A TXNPAD11 A7 NC N/A TXPPAD11 A6 NC N/A GNDA11 C5 NC N/A GNDA11 C5 NC N/A RXPPAD11 A5 NC N/A RXNPAD11 A4 NC N/A VTRXPAD11 B5 NC N/A AVCCAUXRX11 B4 NC N/A AVCCAUXRX14 AK4 NC N/A VTRXPAD14 AK5 NC N/A RXNPAD14 AL4 NC N/A RXPPAD14 AL5 NC N/A GNDA14 AJ5 NC N/A GNDA14 AJ5 NC Module 4 of 4 260 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number XC2V P20 N/A TXPPAD14 AL6 NC N/A TXNPAD14 AL7 NC N/A VTTXPAD14 AK7 NC N/A AVCCAUXTX14 AK6 NC N/A AVCCAUXRX16 AK8 N/A VTRXPAD16 AK9 N/A RXNPAD16 AL8 N/A RXPPAD16 AL9 N/A GNDA16 AJ8 N/A GNDA16 AJ8 N/A TXPPAD16 AL10 N/A TXNPAD16 AL11 N/A VTTXPAD16 AK11 N/A AVCCAUXTX16 AK10 N/A AVCCAUXRX18 AK12 N/A VTRXPAD18 AK13 N/A RXNPAD18 AL12 N/A RXPPAD18 AL13 N/A GNDA18 AJ12 N/A GNDA18 AJ12 N/A TXPPAD18 AL14 N/A TXNPAD18 AL15 N/A VTTXPAD18 AK15 N/A AVCCAUXTX18 AK14 N/A AVCCAUXRX19 AK17 N/A VTRXPAD19 AK18 N/A RXNPAD19 AL17 N/A RXPPAD19 AL18 N/A GNDA19 AJ20 N/A GNDA19 AJ20 N/A TXPPAD19 AL19 N/A TXNPAD19 AL20 N/A VTTXPAD19 AK20 N/A AVCCAUXTX19 AK19 N/A AVCCAUXRX21 AK21 N/A VTRXPAD21 AK22 N/A RXNPAD21 AL21 N/A RXPPAD21 AL22 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P50 Module 4 of 4 261 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects XC2V P20 Bank Pin Description Pin Number N/A GNDA21 AJ24 N/A GNDA21 AJ24 N/A TXPPAD21 AL23 N/A TXNPAD21 AL24 N/A VTTXPAD21 AK24 N/A AVCCAUXTX21 AK23 N/A AVCCAUXRX23 AK25 NC N/A VTRXPAD23 AK26 NC N/A RXNPAD23 AL25 NC N/A RXPPAD23 AL26 NC N/A GNDA23 AJ27 NC N/A GNDA23 AJ27 NC N/A TXPPAD23 AL27 NC N/A TXNPAD23 AL28 NC N/A VTTXPAD23 AK28 NC N/A AVCCAUXTX23 AK27 NC N/A VCCAUX AK29 N/A VCCAUX AK16 N/A VCCAUX AK3 N/A VCCAUX AJ30 N/A VCCAUX AJ16 N/A VCCAUX AJ2 N/A VCCAUX T30 N/A VCCAUX T29 N/A VCCAUX T3 N/A VCCAUX T2 N/A VCCAUX C30 N/A VCCAUX C16 N/A VCCAUX C2 N/A VCCAUX B29 N/A VCCAUX B16 N/A VCCAUX B3 N/A VCCINT AA21 N/A VCCINT AA16 N/A VCCINT AA11 N/A VCCINT Y20 N/A VCCINT Y16 Module 4 of 4 262 www.xilinx.com 1-800-255-7778 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A VCCINT Y12 N/A VCCINT W19 N/A VCCINT W18 N/A VCCINT W17 N/A VCCINT W16 N/A VCCINT W15 N/A VCCINT W14 N/A VCCINT W13 N/A VCCINT V19 N/A VCCINT V13 N/A VCCINT U19 N/A VCCINT U13 N/A VCCINT T21 N/A VCCINT T20 N/A VCCINT T19 N/A VCCINT T13 N/A VCCINT T12 N/A VCCINT T11 N/A VCCINT R19 N/A VCCINT R13 N/A VCCINT P19 N/A VCCINT P13 N/A VCCINT N19 N/A VCCINT N18 N/A VCCINT N17 N/A VCCINT N16 N/A VCCINT N15 N/A VCCINT N14 N/A VCCINT N13 N/A VCCINT M20 N/A VCCINT M16 N/A VCCINT M12 N/A VCCINT L21 N/A VCCINT L16 N/A VCCINT L11 N/A GND AL30 N/A GND AL29 N/A GND AL16 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 263 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND AL3 N/A GND AL2 N/A GND AK31 N/A GND AK30 N/A GND AK2 N/A GND AK1 N/A GND AJ31 N/A GND AJ29 N/A GND AJ23 N/A GND AJ9 N/A GND AJ3 N/A GND AJ1 N/A GND AH28 N/A GND AH16 N/A GND AH4 N/A GND AG27 N/A GND AG5 N/A GND AF26 N/A GND AF19 N/A GND AF13 N/A GND AF6 N/A GND AE25 N/A GND AE16 N/A GND AE7 N/A GND AD29 N/A GND AD24 N/A GND AD8 N/A GND AD3 N/A GND AC23 N/A GND AC9 N/A GND AB29 N/A GND AB22 N/A GND AB16 N/A GND AB10 N/A GND AB3 N/A GND W26 N/A GND W6 N/A GND V18 Module 4 of 4 264 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND V17 N/A GND V16 N/A GND V15 N/A GND V14 N/A GND U18 N/A GND U17 N/A GND U16 N/A GND U15 N/A GND U14 N/A GND T31 N/A GND T28 N/A GND T25 N/A GND T22 N/A GND T18 N/A GND T17 N/A GND T16 N/A GND T15 N/A GND T14 N/A GND T10 N/A GND T7 N/A GND T4 N/A GND T1 N/A GND R18 N/A GND R17 N/A GND R16 N/A GND R15 N/A GND R14 N/A GND P18 N/A GND P17 N/A GND P16 N/A GND P15 N/A GND P14 N/A GND N26 N/A GND N6 N/A GND K29 N/A GND K22 N/A GND K16 N/A GND K10 DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 Module 4 of 4 265 R Virtex-II ProTM Platform FPGAs: Pinout Information Table 12: BF957 -- XC2VP20 and XC2VP50 No Connects Bank Pin Description Pin Number N/A GND K3 N/A GND J23 N/A GND J9 N/A GND H29 N/A GND H24 N/A GND H8 N/A GND H3 N/A GND G25 N/A GND G16 N/A GND G7 N/A GND F26 N/A GND F19 N/A GND F13 N/A GND F6 N/A GND E27 N/A GND E5 N/A GND D28 N/A GND D16 N/A GND D4 N/A GND C31 N/A GND C29 N/A GND C23 N/A GND C9 N/A GND C3 N/A GND C1 N/A GND B31 N/A GND B30 N/A GND B2 N/A GND B1 N/A GND A30 N/A GND A29 N/A GND A16 N/A GND A3 N/A GND A2 Module 4 of 4 266 www.xilinx.com 1-800-255-7778 XC2V P20 XC2V P50 DS083-4 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II ProTM Platform FPGAs: Pinout Information BF957 Flip-Chip BGA Package Specifications (1.27mm pitch) Figure 7: BF957 Flip-Chip BGA Package Specifications DS083-4 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 267 R Virtex-II ProTM Platform FPGAs: Pinout Information Revision History This section records the change history for this module of the data sheet. Date Version 1/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II ProTM Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II ProTM Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II ProTM Platform FPGAs: Functional Description (Module 2) * Virtex-II Pro Platform FPGAs: Pinout Information (Module 4) Module 4 of 4 268 www.xilinx.com 1-800-255-7778 DS083-4 (v1.0) January 31, 2002 Advance Product Specification