NCV4274C Regulator, 400 mA, Low Dropout Voltage Description The NCV4274C is a precision micro-power voltage regulator with an output current capability of 400 mA available in the DPAK, D2PAK and SOT-223 packages. The output voltage is accurate within 2.0% with a maximum dropout voltage of 0.5 V with an input up to 40 V. Low quiescent current is a feature drawing only 125 mA with a 1 mA load. This part is ideal for automotive and all battery operated microprocessor equipment. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. www.onsemi.com MARKING DIAGRAMS 4 DPAK DT SUFFIX CASE 369C Features * * * * * * * * 3.3 V, 5.0 V, 2.0% Output Options Low 125 mA Quiescent Current at 1 mA load current 400 mA Output Current Capability Fault Protection +60 V Peak Transient Voltage with Respect to GND S -42 V Reverse Voltage S Short Circuit S Thermal Overload Very Low Dropout Voltage NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable These are Pb-Free Devices D2PAK DS SUFFIX CASE 418AF SOT-223 ST SUFFIX CASE 318E 1 Input 2, 4 Ground 3 Output 74C-xxG ALYWW x 1 2 3 NC V4274C-xx AWLYYWWG 1 Input 2, 4 Ground 3 Output AYW 74CxxG G 1 xx = 33 (3.3 V) = 50 (5.0 V) A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. (c) Semiconductor Components Industries, LLC, 2016 November, 2018 - Rev. 4 1 Publication Order Number: NCV4274C/D NCV4274C I Q Bandgap Refernece Current Limit and Saturation Sense - + Thermal Shutdown GND Figure 1. Block Diagram Pin Definitions and Functions Pin No. Symbol 1 I 2,4 GND 3 Q Function Input; Bypass directly at the IC with a ceramic capacitor to GND. Ground Output; Bypass with a capacitor to GND. ABSOLUTE MAXIMUM RATINGS Pin Symbol, Parameter I, Input-to-Regulator Symbol Condition Min Max Unit V Voltage VI -42 45 Current II Internally Limited Internally Limited I, Input peak Transient Voltage to Regulator with Respect to GND (Note 1) VI 60 V Q, Regulated Output Voltage VQ -1.0 40 V Current IQ Internally Limited Internally Limited GND, Ground Current IGND - 100 mA Junction Temperature Storage Temperature TJ TStg -40 -50 150 150 C C ESDHB 4 ESD Capability, Machine Model (Note 2) ESDMM 200 V ESD Capability, Charged Device Model (Note 2) ESDCDM 1 kV ESD Capability, Human Body Model (Note 2) VQ = VI kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Load Dump Test B (with centralized load dump suppression) according to ISO16750-2 standard. Guaranteed by design. Not tested in production. Passed Class C. 2. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC-Q100-002 (EIA/JESD22-A114) ESD MM tested per AEC-Q100-003 (EIA/JESD22-A115) Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes <50mm2 due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform characteristic defined in JEDEC JS-002-2014. www.onsemi.com 2 NCV4274C OPERATING RANGE Min Max Unit Input Voltage (5.0 V Version) Parameter Symbol VI Condition 5.5 40 V Input Voltage (3.3 V Version) VI 4.5 40 V Junction Temperature TJ -40 150 C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. THERMAL RESISTANCE Parameter Symbol Condition Min Max Unit Junction-to-Ambient DPAK Rthja - 72.5 (Note 3) C/W Junction-to-Ambient D2PAK Rthja - 56.7 (Note 3) C/W Junction-to-Case DPAK Rthjc - 5.8 C/W Junction-to-Case D2PAK Rthjc - 5.8 C/W SOT-223 Y-JLX, - 15.6 (Note 3) C/W - 87 (Note 3) C/W Min Max Unit 1 3 - - Junction-to-Tab YLX Junction-to-Ambient SOT-223 RqJA, qJA 3. 1 oz copper, 300 mm2 copper area, single-sided FR4 PCB. MOISTURE SENSITIVITY LEVEL (Note 4) Parameter Moisture Sensitivity Level Symbol MSL Condition DPAK and D2PAK SOT-223 4. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 3 NCV4274C ELECTRICAL CHARACTERISTICS -40C < TJ < 150C; VI = 13.5 V unless otherwise noted. Parameter Symbol Test Conditions Min Typ Max Unit REGULATOR Output Voltage (5.0 V Version) VQ 5 mA < IQ < 400 mA 6 V < VI < 28 V 4.9 5.0 5.1 V Output Voltage (5.0 V Version) VQ 5 mA < IQ < 200 mA 6 V < VI < 40 V 4.9 5.0 5.1 V Output Voltage (3.3 V Version) VQ 5 mA < IQ < 400 mA 4.5 V < VI < 28 V 3.23 3.3 3.37 V Output Voltage (3.3 V Version) VQ 5 mA < IQ < 200 mA 4.5 V < VI < 40 V 3.23 3.3 3.37 V Current Limit (All Versions) IQ VQ = 90% VQTYP 400 600 - mA Quiescent Current Iq IQ = 1 mA VQ = 5.0 V VQ = 3.3 V IQ = 250 mA VQ = 5.0 V VQ = 3.3 V IQ = 400 mA VQ = 5.0 V VQ = 3.3 V - - 125 125 250 250 mA mA - - 5 5 15 15 mA mA - - 10 10 35 35 mA mA IQ = 250 mA, VDR = VI - VQ VI = 5.0 V - 250 500 mV Dropout Voltage VDR 5.0 V Version Load Regulation (3.3 V and 5 V Versions) DVQ IQ = 5 mA to 400 mA - 3 20 mV Line Regulation (3.3 V and 5 V Versions) DVQ DVI = 12 V to 32 V IQ = 5 mA - 4 25 mV r = 100 Hz, Vr = 0.5 VPP - 60 - dB 150 - 210 C Power Supply Ripple Rejection PSRR Thermal Shutdown Temperature* TSD IQ = 5 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. *Guaranteed by design, not tested in production VI VI II C11 1.0 mF I C12 100 nF 1 NCV4274C 3 Q 2,4 GND IGND IQ CQ 10 mF or 22 mF VQ VQ VI Input Rload CI 100 nF 1 NCV4274C 3 VQ CQ* Output 2,4 GND *CQ = 10 mF for VQ 3.3 V CQ = 22 mF for VQ 5 V Figure 2. Measuring Circuit Figure 3. Application Circuit www.onsemi.com 4 NCV4274C TYPICAL CHARACTERISTIC CURVES - 5 V VERSION 5.1 Unstable Region 10 ESR (W) VQ, OUTPUT VOLTAGE (V) 100 1 Stable Region 0.1 5.05 5 4.95 CQ = 22 mF 0.01 0 100 200 300 4.9 -40 400 40 80 120 TJ, JUNCTION TEMPERATURE (C) Figure 4. Output Stability with Output Capacitor ESR Figure 5. Output Voltage vs. Junction Temperature 160 400 VDR, DROPOUT VOLTAGE (mV) 5 4 3 2 1 TJ = 25C RL = 20 W 0 2 4 6 8 350 300 200 TJ = 25C 150 100 50 0 50 100 150 100 250 300 350 400 VI, INPUT VOLTAGE (V) IQ, OUTPUT CURRENT (mA) Figure 6. Output Voltage vs. Input Voltage Figure 7. Dropout Voltage vs. Output Current 1.6 700 1.2 600 0.8 0.4 0 -0.4 -0.8 -1.2 -50 TJ = 125C 250 0 10 IQ, OUTPUT CURRENT (mA) VQ, OUTPUT VOLTAGE (V) II, INPUT CURRENT (mA) 0 IQ, OUTPUT CURRENT (mA) 6 0 VI = 13.5 V RL = 1 kW RL = 6.8 kW TJ = 25C -30 -10 10 30 500 400 300 200 100 0 50 TJ = 25C VQ = 0 V 0 5 10 15 20 25 30 35 40 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 8. Input Current vs. Input Voltage Figure 9. Maximum Output Current vs. Input Voltage www.onsemi.com 5 45 NCV4274C TYPICAL CHARACTERISTIC CURVES - 5 V VERSION 0.7 Iq, QUIESCENT CURRENT (mA) 9 8 7 6 5 4 3 2 VI = 13.5 V TJ = 25C 1 0 0 50 100 150 200 250 300 350 400 0.6 0.5 0.4 0.3 0.2 0.1 0 450 VI = 13.5 V TJ = 25C 0 10 20 30 40 50 IQ, OUTPUT CURRENT (mA) IQ, OUTPUT CURRENT (mA) Figure 10. Quiescent Current vs. Output Current (High Load) Figure 11. Quiescent Current vs. Output Current (Low Load) 10 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 11 10 TJ = 25C RL = 20 W 9 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 VI, INPUT VOLTAGE (V) Figure 12. Quiescent Current vs. Input Voltage www.onsemi.com 6 45 60 NCV4274C TYPICAL CHARACTERISTIC CURVES - 3.3 V VERSION 3.36 Unstable Region 10 ESR (W) VQ, OUTPUT VOLTAGE (V) 100 1 Stable Region 0.1 CQ = 10 mF 0.01 0 100 200 300 3.3 3.28 3.26 VI = 13.5 V RL = 660 W 0 120 Figure 13. Output Stability with Output Capacitor ESR Figure 14. Output Voltage vs. Junction Temperature 2 1 TJ = 25C RL = 20 W 0 2 4 6 10 8 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 160 TJ = 25C RL = 3.3 kW -30 -10 10 30 50 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 15. Output Voltage vs. Input Voltage Figure 16. Input Current vs. Input Voltage 4 IQ, QUIESCENT CURRENT (mA) 700 IQ, OUTPUT CURRENT (mA) 80 TJ, JUNCTION TEMPERATURE (C) 3 600 500 400 300 200 100 0 0 40 IQ, OUTPUT CURRENT (mA) II, INPUT CURRENT (mA) VQ, OUTPUT VOLTAGE (V) 3.32 3.24 -40 400 4 0 3.34 TJ = 25C VQ = 0 V 5 10 15 20 25 30 35 40 3.5 3 2.5 2 1.5 1 0 45 TJ = 25C RL = 20 W 0.5 0 5 10 15 20 25 30 35 40 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 17. Maximum Output Current vs. Input Voltage Figure 18. Quiescent Current vs. Input Voltage www.onsemi.com 7 45 NCV4274C TYPICAL CHARACTERISTIC CURVES - 3.3 V VERSION 0.7 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 11 10 9 8 7 6 5 4 3 2 VI = 13.5 V TJ = 25C 1 0 0 50 100 150 200 250 300 350 400 0.6 0.5 0.4 0.3 0.2 0.1 0 450 VI = 13.5 V TJ = 25C 0 10 20 30 40 50 IQ, OUTPUT CURRENT (mA) IQ, OUTPUT CURRENT (mA) Figure 19. Quiescent Current vs. Output Current (High Load) Figure 20. Quiescent Current vs. Output Current (Low Load) www.onsemi.com 8 60 NCV4274C APPLICATION DESCRIPTION Output Regulator Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: 150 C * T A The output is controlled by a precision trimmed reference and error amplifier. The PNP output has saturation control for regulation while the input voltage is low, preventing over saturation. Current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. Pq JA + PD (eq. 2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in Equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required. The current flow and voltages are shown in the Measurement Circuit Diagram. Stability Considerations The input capacitor CI1 in Figure 2 is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1 W in series with CI2. The output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer's data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 2 should work for most applications; however, it is not necessarily the optimized solution. Actual Stability Regions are shown in a graphs in the Typical Performance Characteristics section. Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: R qJA + R qJC ) R qCS ) R qSA (eq. 3) Where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heat sink thermal resistance, and RqSA = the heat sink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heat sink and the interface between them. These values appear in data sheets of heat sink manufacturers. Thermal, mounting, and heat sinking are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor Website. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 3) is: P D(max) + [V I(max) * V Q(min)]I Q(max) ) V I(max)I q (eq. 1) Where: VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, and Iq is the quiescent current the regulator consumes at IQ(max). www.onsemi.com 9 180 RqJA, THERMAL RESISTANCE (C/W) RqJA, THERMAL RESISTANCE (C/W) NCV4274C 160 140 120 100 1 oz 80 2 oz 60 40 0 100 200 300 400 500 COPPER SPREADER AREA 600 800 700 130 120 110 100 90 80 70 1 oz 60 2 oz 50 40 30 100 0 (mm2) 300 400 500 COPPER SPREADER AREA Figure 21. RqJA vs. Copper Spreader Area, DPAK 3-Lead RqJA, THERMAL RESISTANCE (C/W) 200 600 800 700 (mm2) Figure 22. RqJA vs. Copper Spreader Area, D2PAK 3-Lead 210 190 170 150 130 110 1 oz 90 2 oz 70 50 0 100 200 300 400 500 600 800 700 COPPER SPREADER AREA (mm2) Figure 23. RqJA vs. Copper Spreader Area, SOT 223-Lead 1000 1 oz Cu Area 100 mm2 R(t) (C/W) 100 1 oz Cu Area 645 mm2 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 PULSE TIME (s) Figure 24. Single-Pulse Heating Curves, DPAK 3-Lead www.onsemi.com 10 10 100 1000 NCV4274C R(t) (C/W) 100 1 oz Cu Area 100 mm2 1 oz Cu Area 645 mm2 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (s) Figure 25. Single-Pulse Heating Curves, D2PAK 3-Lead 1000 1 oz Cu Area 100 mm2 R(t) (C/W) 100 1 oz Cu Area 645 mm2 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 10 100 1000 PULSE TIME (s) Figure 26. Single-Pulse Heating Curves, SOT 223-Lead 100 50% Duty Cycle R(t) (C/W) 20% 10 10% 5% 1 2% 1% Non-normalized Response 0.1 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 PULSE TIME (s) Figure 27. Duty Cycle for 1 inch2 (645 mm2) Spreader Board, DPAK 3-Lead www.onsemi.com 11 NCV4274C 100 R(t) (C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% Non-normalized Response Single Pulse 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 100 1000 PULSE TIME (s) Figure 28. Duty Cycle for 1 inch2 (645 mm2) Spreader Board, D2PAK 3-Lead 100 50% Duty Cycle R(t) (C/W) 20% 10 10% 5% 2% 1 1% Non-normalized Response 0.1 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 PULSE TIME (s) Figure 29. Duty Cycle for 1 inch2 (645 mm2) Spreader Board, SOT 223-Lead ORDERING INFORMATION Device* Output Voltage Accuracy Output Voltage Package Shipping NCV4274CDT33RKG 2% 3.3 V DPAK (Pb-Free) 2500 / Tape & Reel NCV4274CDS33R4G 2% 3.3 V D2PAK (Pb-Free) 800 / Tape & Reel NCV4274CDT50RKG 2% 5.0 V DPAK (Pb-Free) 2500 / Tape & Reel NCV4274CDS50R4G 2% 5.0 V D2PAK (Pb-Free) 800 / Tape & Reel NCV4274CST33T3G 2% 3.3 V SOT-223 (Pb-Free) 4000 / Tape & Reel NCV4274CST50T3G 2% 5.0 V SOT-223 (Pb-Free) 4000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E C A b3 B c2 4 L3 Z D 1 2 H DETAIL A 3 L4 NOTE 7 c SIDE VIEW b2 e b 0.005 (0.13) TOP VIEW BOTTOM VIEW C M Z H L2 GAUGE PLANE C L SEATING PLANE BOTTOM VIEW A1 L1 DETAIL A Z ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 --- 0.040 0.155 --- MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 --- 1.01 3.93 --- GENERIC MARKING DIAGRAM* STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. 2.58 0.102 1.60 0.063 IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. 6.17 0.243 SCALE 3:1 AYWW XXX XXXXXG XXXXXX A L Y WW G 3.00 0.118 5.80 0.228 XXXXXXG ALYWW mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: 98AON10527D ON SEMICONDUCTOR STANDARD REF TO JEDEC TO-252 http://onsemi.com DPAK SINGLE GAUGE SURFACE 1 MOUNT (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON10527D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001 A ADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008 B ADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009 C ADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009 D RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A. CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010 E ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAMBALIZA. 06 FEB 2014 F ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K. MUSTAFA. 21 JUL 2015 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2015 July, 2015 - Rev. F Case Outline Number: 369C MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK CASE 418AF ISSUE E DATE 15 SEP 2015 SCALE 1:1 T C A K S B T C OPTIONAL CHAMFER ES V H 2 U ED OPTIONAL CHAMFER 1 TERMINAL 4 DETAIL C DETAIL C 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCHES. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 4. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. 6. SINGLE GAUGE DESIGN WILL BE SHIPPED AFTER FPCN EXPIRATION IN OCTOBER 2011. J F G SIDE VIEW D 0.010 (0.254) 3X TOP VIEW N M R SIDE VIEW SINGLE GAUGE CONSTRUCTION DUAL GAUGE CONSTRUCTION T M T SEATING PLANE L P BOTTOM VIEW BOTTOM VIEW DETAIL C OPTIONAL CONSTRUCTIONS SOLDERING FOOTPRINT* 10.490 DIM A B C D ED ES F G H J K L M N P R S U V INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.018 0.026 0.051 REF 0.100 BSC 0.539 0.579 0.125 MAX 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 0_ 8_ 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 0.457 0.660 1.295 REF 2.540 BSC 13.691 14.707 3.175 MAX 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 0_ 8_ 2.946 REF 5.080 MIN 6.350 MIN GENERIC MARKING DIAGRAM* XX XXXXXXXXX AWLYYWWG 8.380 16.155 3X 3.504 3X 1.016 2.540 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON21981D XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G", may or not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped "CONTROLLED COPY" in red. NEW STANDARD: (c) Semiconductor Components Industries, LLC, 2002 Case Outline Number: http://onsemi.com http://onsemi.com D2PAK, 3 LEAD, NON-CROPPED DESCRIPTION: October, 2002 - Rev. 0 PAGE 1 OFXXX 2 11 DOCUMENT NUMBER: 98AON21981D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY A. NOAH. 13 FEB 2006 A ADDED SOLDERING FOOTPRINT. REQ. BY M. FILLION. 18 JUN 2007 B ADDED SINGLE AND DUAL GAUGE SIDE VIEWS AND BOTTOM VIEW. REQ. BY J. KREMMER. 08 NOV 2011 C CORRECTED SOLDERING FOOTPRINT TO VERSION FROM ISSUE A. REQ. BY J. KREMMER. 13 APR 2012 D CORRECTED SOLDERING FOOTPRINT BACK TO VERSION FROM ISSUE B. REQ. BY J. KREMMER. 24 MAY 2012 E REVISED DIMENSION R FROM 5 DEGREES REFERENCE TO 0 & 8 DEGREES MIN & MAX. REQ. BY K. MUSTAFA. 15 SEP 2015 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. http://onsemi.com (c) Semiconductor Components Industries, LLC, 2015 September, 2015 - Rev. E 2 Case Outline Number: 418AF MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT-223 (TO-261) CASE 318E-04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT-223 (TO-261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT-223 (TO-261) CASE 318E-04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb-Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "G", may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT-223 (TO-261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2018 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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"Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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