NCV4274CDT50RKG - ON SEMICONDUCTOR

November, 2018 − Rev. 4

1Publication Order Number:

NCV4274C/D

NCV4274C

Regulator, 400 mA,

Low Dropout Voltage

Description

The NCV4274C is a precision micro−power voltage regulator with

an output current capability of 400 mA available in the DPAK,

D2PAK and SOT−223 packages.

The output voltage is accurate within ±2.0% with a maximum

dropout voltage of 0.5 V with an input up to 40 V. Low quiescent

current is a feature drawing only 125 mA with a 1 mA load. This part is

ideal for automotive and all battery operated microprocessor

equipment.

The regulator is protected against reverse battery, short circuit, and

thermal overload conditions. The device can withstand load dump

transients making it suitable for use in automotive environments.

Features

•3.3 V, 5.0 V, ±2.0% Output Options

•Low 125 mA Quiescent Current at 1 mA load current

•400 mA Output Current Capability

•Fault Protection

•+60 V Peak Transient Voltage with Respect to GND

S −42 V Reverse Voltage

S Short Circuit

S Thermal Overload

•Very Low Dropout Voltage

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These are Pb−Free Devices

MARKING DIAGRAMS

DPAK

DT SUFFIX

CASE 369C

See detailed ordering and shipping information on page 12 of

this data sheet.

ORDERING INFORMATION

www.onsemi.com

74C−xxG

ALYWW

xx = 33 (3.3 V)

= 50 (5.0 V)

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

1 Input

2, 4 Ground

3 Output

D2PAK

DS SUFFIX

CASE 418AF

V4274C−xx

AWLYYWWG

1 Input

2, 4 Ground

3 Output

AYW

74CxxG

(Note: Microdot may be in either location)

SOT−223

ST SUFFIX

CASE 318E

NCV4274C

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Figure 1. Block Diagram

−

Bandgap

Refernece

Thermal

Shutdown

Current Limit and

Saturation Sense

GND

Pin Definitions and Functions

Pin No. Symbol Function

1 I Input; Bypass directly at the IC with a ceramic capacitor to GND.

2,4 GND Ground

3 Q Output; Bypass with a capacitor to GND.

ABSOLUTE MAXIMUM RATINGS

Pin Symbol, Parameter Symbol Condition Min Max Unit

I, Input−to−Regulator Voltage VI−42 45 V

Current IIInternally

Limited

Internally

Limited

I, Input peak Transient Voltage to Regulator with Respect

to GND (Note 1)

VI60 V

Q, Regulated Output Voltage VQVQ = VI−1.0 40 V

Current IQInternally

Limited

Internally

Limited

GND, Ground Current IGND −100 mA

Junction Temperature

Storage Temperature

TStg

−40

−50

150

°C

ESD Capability, Human Body Model (Note 2) ESDHB 4 kV

ESD Capability, Machine Model (Note 2) ESDMM 200 V

ESD Capability, Charged Device Model (Note 2) ESDCDM 1 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Load Dump Test B (with centralized load dump suppression) according to ISO16750-2 standard. Guaranteed by design. Not tested in

production. Passed Class C.

2. This device series incorporates ESD protection and is tested by the following methods:

ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)

Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes <50mm2 due to the

inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform characteristic

defined in JEDEC JS−002−2014.

NCV4274C

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OPERATING RANGE

Parameter Symbol Condition Min Max Unit

Input Voltage (5.0 V Version) VI5.5 40 V

Input Voltage (3.3 V Version) VI4.5 40 V

Junction Temperature TJ−40 150 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

THERMAL RESISTANCE

Parameter Symbol Condition Min Max Unit

Junction−to−Ambient DPAK Rthja −72.5

(Note 3)

°C/W

Junction−to−Ambient D2PAK Rthja −56.7

(Note 3)

°C/W

Junction−to−Case DPAK Rthjc −5.8 °C/W

Junction−to−Case D2PAK Rthjc −5.8 °C/W

Junction−to−Tab SOT−223 Y-JLX,

YLX

−15.6

(Note 3)

°C/W

Junction−to−Ambient SOT−223 RqJA, qJA −87

(Note 3)

°C/W

3. 1 oz copper, 300 mm2 copper area, single−sided FR4 PCB.

MOISTURE SENSITIVITY LEVEL (Note 4)

Parameter Symbol Condition Min Max Unit

Moisture Sensitivity Level MSL DPAK and D2PAK

SOT−223

−

4. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

NCV4274C

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ELECTRICAL CHARACTERISTICS

−40°C < TJ < 150°C; VI = 13.5 V unless otherwise noted.

Parameter Symbol Test Conditions Min Typ Max Unit

REGULATOR

Output Voltage (5.0 V Version) VQ5 mA < IQ < 400 mA

6 V < VI < 28 V

4.9 5.0 5.1 V

Output Voltage (5.0 V Version) VQ5 mA < IQ < 200 mA

6 V < VI < 40 V

4.9 5.0 5.1 V

Output Voltage (3.3 V Version) VQ5 mA < IQ < 400 mA

4.5 V < VI < 28 V

3.23 3.3 3.37 V

Output Voltage (3.3 V Version) VQ5 mA < IQ < 200 mA

4.5 V < VI < 40 V

3.23 3.3 3.37 V

Current Limit (All Versions) IQVQ = 90% VQTYP 400 600 −mA

Quiescent Current IqIQ = 1 mA

VQ = 5.0 V

VQ = 3.3 V

IQ = 250 mA

VQ = 5.0 V

VQ = 3.3 V

IQ = 400 mA

VQ = 5.0 V

VQ = 3.3 V

−

125

250

Dropout Voltage

5.0 V Version

VDR IQ = 250 mA,

VDR = VI − VQ

VI = 5.0 V −250 500 mV

Load Regulation (3.3 V and 5 V Versions) DVQIQ = 5 mA to 400 mA −3 20 mV

Line Regulation (3.3 V and 5 V Versions) DVQDVI = 12 V to 32 V

IQ = 5 mA

−4 25 mV

Power Supply Ripple Rejection PSRR ƒr = 100 Hz,

Vr = 0.5 VPP

−60 −dB

Thermal Shutdown Temperature* TSD IQ = 5 mA 150 −210 °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

*Guaranteed by design, not tested in production

Figure 2. Measuring Circuit

NCV4274C

Rload

10 mF

22 mF

C12

100 nF

C11

1.0 mF

QIII

IGND

GND

2,4

Figure 3. Application Circuit

Output

CQ*CI

100 nF

GND

NCV4274C

2,4

Input

*CQ = 10 mF for VQ ≤ 3.3 V

CQ = 22 mF for VQ ≥ 5 V

NCV4274C

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TYPICAL CHARACTERISTIC CURVES − 5 V VERSION

IQ, OUTPUT CURRENT (mA)

VI, INPUT VOLTAGE (V)

4003002001000

100

503010−10−30−50

1.6

ESR (W)

CQ = 22 mF

II, INPUT CURRENT (mA)

RL = 6.8 kW

TJ = 25°C

VI, INPUT VOLTAGE (V)

100

VQ, OUTPUT VOLTAGE (V)

TJ = 25°C

RL = 20 W

Figure 4. Output Stability with Output

Capacitor ESR

TJ, JUNCTION TEMPERATURE (°C)

IQ, OUTPUT CURRENT (mA)

16012080400−40

5.1

400350300100500

400

VQ, OUTPUT VOLTAGE (V)

VI = 13.5 V

RL = 1 kW

VDR, DROPOUT VOLTAGE (mV)

VI, INPUT VOLTAGE (V)

4535302050

700

IQ, OUTPUT CURRENT (mA)

TJ = 25°C

VQ = 0 V

Figure 5. Output Voltage vs.

Junction Temperature

Figure 6. Output Voltage vs. Input Voltage Figure 7. Dropout Voltage vs. Output Current

Figure 8. Input Current vs. Input Voltage Figure 9. Maximum Output Current vs. Input

Voltage

0.1

0.01

Unstable Region

Stable Region

5.05

4.95

4.9

8642

TJ = 125°C

TJ = 25°C

150 250100

350

300

250

200

150

100

1.2

0.8

0.4

−0.4

−0.8

−1.2

600

500

400

300

200

100

02510 15

NCV4274C

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TYPICAL CHARACTERISTIC CURVES − 5 V VERSION

IQ, OUTPUT CURRENT (mA)

4003002001000

IQ, OUTPUT CURRENT (mA)

6050403020100

0.7

Iq, QUIESCENT CURRENT (mA)

VI = 13.5 V

TJ = 25°C

Iq, QUIESCENT CURRENT (mA)

Figure 10. Quiescent Current vs.

Output Current (High Load)

Figure 11. Quiescent Current vs. Output

Current (Low Load)

VI = 13.5 V

TJ = 25°C

45035025015050

0.6

0.5

0.4

0.3

0.2

0.1

VI, INPUT VOLTAGE (V)

45403020100

Iq, QUIESCENT CURRENT (mA)

Figure 12. Quiescent Current vs. Input Voltage

TJ = 25°C

RL = 20 W

3525515

NCV4274C

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TYPICAL CHARACTERISTIC CURVES − 3.3 V VERSION

IQ, OUTPUT CURRENT (mA)

VI, INPUT VOLTAGE (V)

4003002001000

100

700

ESR (W)

CQ = 10 mF

IQ, OUTPUT CURRENT (mA)

VI, INPUT VOLTAGE (V)

100

VQ, OUTPUT VOLTAGE (V)

TJ = 25°C

RL = 20 W

Figure 13. Output Stability with Output

Capacitor ESR

TJ, JUNCTION TEMPERATURE (°C)

VI, INPUT VOLTAGE (V)

16012080400−40

3.36

1.4

VQ, OUTPUT VOLTAGE (V)

VI = 13.5 V

RL = 660 W

II, INPUT CURRENT (mA)

VI, INPUT VOLTAGE (V)

4535302050

IQ, QUIESCENT CURRENT (mA)

TJ = 25°C

VQ = 0 V

Figure 14. Output Voltage vs.

Junction Temperature

Figure 15. Output Voltage vs. Input Voltage Figure 16. Input Current vs. Input Voltage

Figure 17. Maximum Output Current vs. Input

Voltage

Figure 18. Quiescent Current vs. Input Voltage

0.1

0.01

Unstable Region

Stable Region

8642

2510 15

3.34

3.32

3.3

3.28

3.26

3.24

503010−10−30−50

1.2

0.8

0.6

0.4

0.2

−0.2

−0.4

−0.6

−0.8

−1

TJ = 25°C

RL = 3.3 kW

4535302050402510 15

600

500

400

300

200

100

TJ = 25°C

RL = 20 W

3.5

2.5

1.5

0.5

NCV4274C

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TYPICAL CHARACTERISTIC CURVES − 3.3 V VERSION

IQ, OUTPUT CURRENT (mA)

4003002001000

IQ, OUTPUT CURRENT (mA)

6050403020100

0.7

Iq, QUIESCENT CURRENT (mA)

VI = 13.5 V

TJ = 25°C

Iq, QUIESCENT CURRENT (mA)

Figure 19. Quiescent Current vs.

Output Current (High Load)

Figure 20. Quiescent Current vs.

Output Current (Low Load)

VI = 13.5 V

TJ = 25°C

45035025015050

0.6

0.5

0.4

0.3

0.2

0.1

NCV4274C

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APPLICATION DESCRIPTION

Output Regulator

The output is controlled by a precision trimmed reference

and error amplifier. The PNP output has saturation control

for regulation while the input voltage is low, preventing over

saturation. Current limit and voltage monitors complement

the regulator design to give safe operating signals to the

processor and control circuits.

Stability Considerations

The input capacitor CI1 in Figure 2 is necessary for

compensating input line reactance. Possible oscillations

caused by input inductance and input capacitance can be

damped by using a resistor of approximately 1 W in series

with CI2.

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: startup delay,

load transient response and loop stability.

The capacitor value and type should be based on cost,

availability, size and temperature constraints. The

aluminum electrolytic capacitor is the least expensive

solution, but, if the circuit operates at low temperatures

(−25°C to −40°C), both the value and ESR of the capacitor

will vary considerably. The capacitor manufacturer’s data

sheet usually provides this information.

The value for the output capacitor CQ shown in Figure 2

should work for most applications; however, it is not

necessarily the optimized solution. Actual Stability Regions

are shown in a graphs in the Typical Performance

Characteristics section.

Calculating Power Dissipation in a Single Output

Linear Regulator

The maximum power dissipation for a single output

regulator (Figure 3) is:

PD(max) +[VI(max) *VQ(min)]IQ(max) )VI(max)Iq(eq. 1)

Where:

VI(max) is the maximum input voltage,

VQ(min) is the minimum output voltage,

IQ(max) is the maximum output current for the application,

and

Iq is the quiescent current the regulator consumes at IQ(max).

Once the value of PD(max) is known, the maximum

permissible value of RqJA can be calculated:

PqJA +ǒ150 C *TAǓ

(eq. 2)

The value of RqJA can then be compared with those in the

package section of the data sheet. Those packages with

RqJA

’s less than the calculated value in Equation 2 will keep

the die temperature below 150°C. In some cases, none of the

packages will be sufficient to dissipate the heat generated by

the IC, and an external heat sink will be required. The current

flow and voltages are shown in the Measurement Circuit

Diagram.

Heat Sinks

A heat sink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

determine the value of RqJA:

RqJA +RqJC )RqCS )RqSA (eq. 3)

Where:

RqJC = the junction−to−case thermal resistance,

RqCS = the case−to−heat sink thermal resistance, and

RqSA = the heat sink−to−ambient thermal resistance.

RqJC appears in the package section of the data sheet. Like

RqJA, it too is a function of package type. RqCS and RqSA are

functions of the package type, heat sink and the interface

between them. These values appear in data sheets of heat

sink manufacturers.

Thermal, mounting, and heat sinking are discussed in the

ON Semiconductor application note AN1040/D, available

on the ON Semiconductor Website.

NCV4274C

www.onsemi.com

COPPER SPREADER AREA (mm2)

7003002000

180

RqJA, THERMAL RESISTANCE (°C/W)

Figure 21. RqJA vs. Copper Spreader Area,

DPAK 3−Lead

800100

1 oz

2 oz

400 500 600

160

140

120

100

COPPER SPREADER AREA (mm2)

7003002000

130

RqJA, THERMAL RESISTANCE (°C/W)

Figure 22. RqJA vs. Copper Spreader Area,

D2PAK 3−Lead

800100

1 oz

2 oz

400 500 600

120

100

110

COPPER SPREADER AREA (mm2)

7003002000

210

RqJA, THERMAL RESISTANCE (°C/W)

Figure 23. RqJA vs. Copper Spreader Area,

SOT 223−Lead

800100

1 oz

2 oz

400 500 600

190

150

130

110

170

0.1

100

1000

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 24. Single−Pulse Heating Curves, DPAK 3−Lead

PULSE TIME (s)

R(t) (°C/W)

1 oz Cu Area 100 mm2

1 oz Cu Area 645 mm2

NCV4274C

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0.1

100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 25. Single−Pulse Heating Curves, D2PAK 3−Lead

PULSE TIME (s)

R(t) (°C/W)

1 oz Cu Area 100 mm2

1 oz Cu Area 645 mm2

0.1

1000

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 26. Single−Pulse Heating Curves, SOT 223−Lead

PULSE TIME (s)

R(t) (°C/W)

1 oz Cu Area 100 mm2

1 oz Cu Area 645 mm2

100

0.1

100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 27. Duty Cycle for 1 inch2 (645 mm2) Spreader Board, DPAK 3−Lead

PULSE TIME (s)

R(t) (°C/W)

50% Duty Cycle

20%

10%

Single Pulse

Non−normalized Response

NCV4274C

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0.1

100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 28. Duty Cycle for 1 inch2 (645 mm2) Spreader Board, D2PAK 3−Lead

PULSE TIME (s)

R(t) (°C/W)

50% Duty Cycle

20%

10%

Single Pulse

Non−normalized Response

0.1

100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 29. Duty Cycle for 1 inch2 (645 mm2) Spreader Board, SOT 223−Lead

PULSE TIME (s)

R(t) (°C/W)

50% Duty Cycle

20%

10%

Single Pulse

Non−normalized Response

ORDERING INFORMATION

Device* Output Voltage Accuracy Output Voltage Package Shipping†

NCV4274CDT33RKG 2% 3.3 V DPAK

(Pb−Free)

2500 / Tape & Reel

NCV4274CDS33R4G 2% 3.3 V D2PAK

(Pb−Free)

800 / Tape & Reel

NCV4274CDT50RKG 2% 5.0 V DPAK

(Pb−Free)

2500 / Tape & Reel

NCV4274CDS50R4G 2% 5.0 V D2PAK

(Pb−Free)

800 / Tape & Reel

NCV4274CST33T3G 2% 3.3 V SOT−223

(Pb−Free)

4000 / Tape & Reel

NCV4274CST50T3G 2% 5.0 V SOT−223

(Pb−Free)

4000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

DPAK (SINGLE GAUGE)

CASE 369C

ISSUE F DATE 21 JUL 2015

SCALE 1:1

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

STYLE 3:

PIN 1. ANODE

2. CATHODE

3. ANODE

4. CATHODE

STYLE 4:

PIN 1. CATHODE

2. ANODE

3. GATE

4. ANODE

STYLE 5:

PIN 1. GATE

2. ANODE

3. CATHODE

4. ANODE

STYLE 6:

PIN 1. MT1

2. MT2

3. GATE

4. MT2

STYLE 7:

PIN 1. GATE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

123

STYLE 8:

PIN 1. N/C

2. CATHODE

3. ANODE

4. CATHODE

STYLE 9:

PIN 1. ANODE

2. CATHODE

3. RESISTOR ADJUST

4. CATHODE

STYLE 10:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. ANODE

L4b2

0.005 (0.13) C

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

D0.235 0.245 5.97 6.22

E0.250 0.265 6.35 6.73

A0.086 0.094 2.18 2.38

b0.025 0.035 0.63 0.89

c2 0.018 0.024 0.46 0.61

b2 0.028 0.045 0.72 1.14

c0.018 0.024 0.46 0.61

e0.090 BSC 2.29 BSC

b3 0.180 0.215 4.57 5.46

L4 −−− 0.040 −−− 1.01

L0.055 0.070 1.40 1.78

L3 0.035 0.050 0.89 1.27

Z0.155 −−− 3.93 −−−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-

MENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

7. OPTIONAL MOLD FEATURE.

12 3

XXXXXX = Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Package

AYWW

XXX

XXXXXG

XXXXXXG

ALYWW

DiscreteIC

5.80

0.228

2.58

0.102

1.60

0.063

6.20

0.244

3.00

0.118

6.17

0.243

ǒmm

inchesǓ

SCALE 3:1

GENERIC

MARKING DIAGRAM*

*This information is generic. Please refer

to device data sheet for actual part

marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

H0.370 0.410 9.40 10.41

A1 0.000 0.005 0.00 0.13

L1 0.114 REF 2.90 REF

L2 0.020 BSC 0.51 BSC

DET AIL A

SEATING

PLANE

L2 GAUGE

PLANE

DETAIL A

ROTATED 90 CW5

eBOTTOM VIEW

BOTTOM VIEW

SIDE VIEW

TOP VIEW

ALTERNATE

CONSTRUCTIONS

NOTE 7

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98AON10527D

ON SEMICONDUCTOR STANDARD

REF TO JEDEC TO−252

DPAK SINGLE GAUGE SURFACE MOUNT

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98AON10527D

PAGE 2 OF 2

ISSUE REVISION DATE

ORELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001

AADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008

BADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009

CADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009

DRELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.

CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010

EADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS

b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-

BALIZA.

06 FEB 2014

FADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.

MUSTAFA. 21 JUL 2015

July, 2015 − Rev. F Case Outline Number

369C

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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D2PAK

CASE 418AF

ISSUE E DATE 15 SEP 2015

SCALE 1:1

XXXXXXXXX

AWLYYWWG

XXXXX = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

GENERIC

MARKING DIAGRAM*

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

TERMINAL 4

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCHES.

3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS

A AND K.

4. DIMENSIONS U AND V ESTABLISH A MINIMUM

MOUNTING SURFACE FOR TERMINAL 4.

5. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH OR GATE PROTRUSIONS. MOLD FLASH

AND GATE PROTRUSIONS NOT TO EXCEED

0.025 (0.635) MAXIMUM.

6. SINGLE GAUGE DESIGN WILL BE SHIPPED

AFTER FPCN EXPIRATION IN OCTOBER 2011.

DIM

MIN MAX MIN MAX

MILLIMETERS

0.386 0.403 9.804 10.236

INCHES

B0.356 0.368 9.042 9.347

C0.170 0.180 4.318 4.572

D0.026 0.036 0.660 0.914

E0.045 0.055 1.143 1.397

F0.051 REF 1.295 REF

G0.100 BSC 2.540 BSC

H0.539 0.579 13.691 14.707

J0.125 MAX 3.175 MAX

K0.050 REF 1.270 REF

L0.000 0.010 0.000 0.254

M0.088 0.102 2.235 2.591

N0.018 0.026 0.457 0.660

P0.058 0.078 1.473 1.981

S0.116 REF 2.946 REF

U0.200 MIN 5.080 MIN

V0.250 MIN 6.350 MIN

12 3

0.010 (0.254) T

OPTIONAL

CHAMFER

BOTTOM VIEW

OPTIONAL CONSTRUCTIONS

T OP VIEW

SIDE VIEW

DUAL GAUGE BOTTOM VIEW

RDETAIL C

SEATING

PLANE

CONSTRUCTION

DETAIL C

OPTIONAL

CHAMFER

SIDE VIEW

SINGLE GAUGE

CONSTRUCTION

DETAIL C

E0.018 0.026 0.457 0.660

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

8.380

2.540

DIMENSIONS: MILLIMETERS

PITCH

16.155

1.016

10.490

3.504

0_8_0_8_

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98AON21981D

ON SEMICONDUCTOR STANDARD

D2PAK, 3 LEAD, NON−CROPPED

Electronic versions are uncontrolled except when

acc essed dir ectly from the Document Repos itory. Pr inted

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

http://onsemi.com

DOCUMENT NUMBER:

98AON21981D

PAGE 2 OF 2

ISSUE REVISION DATE

ORELEASED FOR PRODUCTION. REQ. BY A. NOAH. 13 FEB 2006

AADDED SOLDERING FOOTPRINT. REQ. BY M. FILLION. 18 JUN 2007

BADDED SINGLE AND DUAL GAUGE SIDE VIEWS AND BOTTOM VIEW. REQ. BY

J. KREMMER. 08 NOV 2011

CCORRECTED SOLDERING FOOTPRINT TO VERSION FROM ISSUE A. REQ. BY

J. KREMMER. 13 APR 2012

DCORRECTED SOLDERING FOOTPRINT BACK TO VERSION FROM ISSUE B.

REQ. BY J. KREMMER. 24 MAY 2012

EREVISED DIMENSION R FROM 5 DEGREES REFERENCE TO 0 & 8 DEGREES

MIN & MAX. REQ. BY K. MUSTAFA. 15 SEP 2015

September, 2015 − Rev. E Case Outline Number

418AF

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer ’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

SOT−223 (TO−261)

CASE 318E−04

ISSUE R

DATE 02 OCT 2018

SCALE 1:1

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42680B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SOT−223 (TO−261)

CASE 318E−04

ISSUE R

DATE 02 OCT 2018

STYLE 4:

PIN 1. SOURCE

2. DRAIN

3. GATE

4. DRAIN

STYLE 6:

PIN 1. RETURN

2. INPUT

3. OUTPUT

4. INPUT

STYLE 8:

CANCELLED

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 10:

PIN 1. CATHODE

2. ANODE

3. GATE

4. ANODE

STYLE 7:

PIN 1. ANODE 1

2. CATHODE

3. ANODE 2

4. CATHODE

STYLE 3:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

STYLE 2:

PIN 1. ANODE

2. CATHODE

3. NC

4. CATHODE

STYLE 9:

PIN 1. INPUT

2. GROUND

3. LOGIC

4. GROUND

STYLE 5:

PIN 1. DRAIN

2. GATE

3. SOURCE

4. GATE

STYLE 11:

PIN 1. MT 1

2. MT 2

3. GATE

4. MT 2

STYLE 12:

PIN 1. INPUT

2. OUTPUT

3. NC

4. OUTPUT

STYLE 13:

PIN 1. GATE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

A = Assembly Location

Y = Year

W = Work Week

XXXXX = Specific Device Code

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

AYW

XXXXXG

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42680B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

SOT−223 (TO−261)

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor ’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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