MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
1JUNE 2002MILITARY AND COMMERCIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2002 Integrated Device Technology, Inc. DSC-5426/3
FEATURES:
• Equivalent to AMD's Am29823 bipolar registers in pinout/
function, speed, and output drive over full temperature and
voltage supply extremes
• IDT54/74FCT823A equivalent to FAST™ speed
• IDT54FCT823B 25% faster than FAST
• IDT74FCT823C 40% faster than FAST
• Buffered common Clock Enable (EN) and Asynchronous Clear
Input (CLR)
•IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD's bilopar
Am29800 series (5µµ
µµ
µA max.)
• MIlitary product compliant to MIL-STD-883, Class B
• Available in the following packages:
– Commercial: SOIC
– Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT823 series is built using an advanced dual metal CMOS
technology. The FCT823 bus interface registers are designed to eliminate
the extra packages required to buffer existing registers and provide extra
data width for wider address/data paths or buses carrying parity. The
FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear
(CLR) – ideal for parity bus interfacing in high-performance microprogram-
med systems.
The FCT823 high-performance interface family is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
IDT54/74FCT823A/B/C
HIGH PERFORMANCE
CMOS BUS INTERFACE
REGISTER
D
CP
Q
Q
CL
DND0
D
CP
Q
Q
CL
EN
CLR
CP
OE
Y0YN
14
11
13
1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
PIN CONFIGURATION
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
COUT Output Capacitance VOUT = 0V 8 12 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC
TOP VIEW LCC
TOP VIEW
2
3
1
20
19
18
15
16
9
10
D6
D7
D2
D5
D3
D4
D8
23
22
24
21
17
5
6
7
4
8
D0
VCC
CP
OE
13
14
11
12
D1
GND
CLR
Y6
Y7
Y2
Y5
Y3
Y4
Y8
Y0
Y1
EN
15 16
NC
12 13 14
GND
D
8
17 18
CP
EN
Y
8
NC
V
CC
OE
D
1
D
0
Y
0
Y
1
Y3
NC
Y4
5
6
8
7
9
10
11
1
2843 2 2726
25
24
22
23
21
20
19
D5
NC
D3
D4
D2
D7
D6
INDEX
Y5
CLR
Y2
Y7
Y6
LOGIC SYMBOL
CP
D
OE
Q
D
CP
Y
9
9
EN CLR
CLR
EN
Symbol Rating Commercial Military Unit
VTERM(2) Terminal Voltage –0.5 to +7 –0.5 to +7 V
with Respect to GND
VTERM(3) Terminal Voltage –0.5 to VCC –0.5 to VCC V
with Respect to GND
TAOperating Temperature 0 to +70 –55 to +125 °C
TBIAS Temperature under BIAS –55 to +125 –65 to +135 °C
TSTG Storage Temperature –55 to +125 –65 to +150 °C
PTPower Dissipation 0.5 0.5 W
IOUT DC Output Current 120 120 mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
Pin Name I/O Description
Dx I D flip-flop data inputs
CLR I For both inverting and non-inverting registers, when
the clear input is LOW and OE is LOW, the Qx
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
C P I Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Yx O Register 3-state outputs
EN I Clock Enable. When the clock enable is LOW, data
on the DI input is transferred to the QI output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the QI outputs do not change state,
regardless of the data or clock input transitions.
OE I Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the OE
input is LOW, the TRUE register data is present at the
Yx outputs.
PIN DESCRIPTION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
3
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current VI = VCC —— 5
VCC = Max. VI = 2.7V — — 5(4) µA
IIL Input LOW Current VI = 0.5V — — –5(4)
VI = GND — — –5
IOZH VO = VCC —— 10
Off State (High Impedance) VCC = Max. VO = 2.7V — — 10(4) µA
IOZL Output Current VO = 0.5V — — –10(4)
VO = GND — — –10
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –75 –120 — mA
VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —
VCC = Min IOH = –300µAVHC VCC —V
VIN = VIH or VIL IOH = –15mA MIL 2.4 4.3 —
IOH = –24mA COM'L 2.4 4.3 —
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC
VCC = Min IOL = 300µA — GND VLC(4) V
VIN = VIH or VIL IOL = 32mA MIL — 0.3 0.5
IOL = 48mA COM'L — 0.3 0.5
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ±5%, Military: TA = -55°C to +125°C, VCC = 5.0V ±10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
NOTE:
1 . H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
FUNCTION TABLE(1)
Inputs Internal/
Outputs
OE CLR EN Dx CP Qx Yx Function
HHLL↑L Z High Z
HHLH↑HZ
H L X X X L Z Clear
LLXXXLL
H H H X X NC Z Hold
LHHXXNCNC
HHLL↑L Z Load
HHLH↑HZ
LHLL↑LL
LHLH↑HH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
4
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ICC Quiescent Power Supply Current VCC = Max. — 0.2 1.5 mA
VIN ≥ VHC; VIN ≤ VLC
∆ICC Quiescent Power Supply Current VCC = Max. — 0.5 2 mA
TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply VCC = Max. VIN ≥ VHC — 0.15 0.25 mA/
Current(4) Outputs Open VIN ≤ VLC MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max. VIN ≥ VHC — 1.7 4 mA
Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle
OE = EN = GND VIN = 3.4V — 2.2 6
One Bit Toggling VIN = GND
at fi = 5MHz
50% Duty Cycle
VCC = Max. VIN ≥ VHC — 4 7.8(5)
Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle VIN = 3.4V — 6.2 16.8(5)
OE = EN = GND VIN = GND
at fi = 2.5MHz
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for register devices (zero for non-register devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
54/74FCT823A 54FCT823B 74FCT823C
Com'l. Mil. Mil. Com'l.
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF — 10 — 11.5 — 8.5 — 6 ns
tPHL CP to Yx (OE = LOW) RL = 500Ω
CL = 300pF(3) — 20 — 20 — 16 — 12.5
RL = 500Ω
tPZH Output Enable Time, CL = 50pF — 12 — 13 — 9 — 7 ns
tPZL OE to Yx RL = 500Ω
CL = 300pF(3) — 23 — 25 — 16 — 12.5
RL = 500Ω
tPHZ Output Disable Time, CL = 5pF(3) — 7 — 8 — 7 — 6.2 ns
tPLZ OE to Yx RL = 500Ω
CL = 50pF — 8 — 9 — 8 — 6.5
RL = 500Ω
tSU Set-up Time HIGH or LOW, Dx to CP C L = 50pF 4 — 4 — 3 — 3 — ns
Set-up Time HIGH or LOW, EN to CP RL = 500Ω
tHHold Time HIGH or LOW, Dx to CP 2 — 2 — 1.5 — 1.5 — ns
tHHold Time HIGH or LOW, EN to CP 2 — 2 — 0 — 0 — ns
tPHL Propagation Delay, CLR to Yx — 1 4 — 1 5 — 9 .5 — 8 n s
tREM Recovery Time, CLR to CP 6 — 7 — 6 — 6 — ns
tWCP Pulse Width HIGH or LOW 7 — 7 — 6 — 6 — ns
tWCLR Pulse Width HIGH or LOW 6 — 7 — 6 — 6 — n s
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
Pulse
Generator
RT
D.U.T
.
VCC
VIN
CL
VOUT
50pF 500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONO US CO NTRO L
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU tH
tREM
tSU tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPU T TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPU T TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal l ink
Octal link
Octal l ink
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
7
ORDERING INFORMATION
IDT XX
Temp. Range XXXX
Device Type XX
Package X
Process
SO Commercial Options
Small Outline IC
High Performance CMOS Bus
Interface Register, 9-Bit
54
74 – 55°C to +125°C
– 40°C to +85°C
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
BCommercial
MIL-STD-883, Class B
FCT
823A
823B
823C
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
6/27/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
DATA SHEET DOCUMENT HISTORY
