Wide Dynamic Range, Miniature MEMs IMU
Data Sheet ADIS16470
Rev. C Document Feedback
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FEATURES
Triaxial, digital gyroscope, ±2000°/sec dynamic range
8°/hr in run bias stability
0.008°/sec/√Hz rms rate noise density
Triaxial, digital accelerometer dynamic range: ±40 g
13 μg in run bias stability
Triaxial, delta angle and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −10°C to +75°C
SPI compatible data communications
Programmable operation and control
Automatic and manual bias correction controls
Data ready indicator for synchronous data acquisition
External sync modes: direct, pulse, scaled, and output
On demand self test of inertial sensors
On demand self test of flash memory
Single-supply operation (VDD): 3.0 V to 3.6 V
2000 g mechanical shock survivability
Operating temperature range: −25°C to +85°C
APPLICATIONS
Navigation, stabilization, and instrumentation
Unmanned and autonomous vehicles
Smart agriculture/construction machinery
Factory/industrial automation, robotics
Virtual/augmented reality
Internet of Moving Things
GENERAL DESCRIPTION
The ADIS16470 is a miniature MEMS inertial measurement
unit (IMU) that includes a triaxial gyroscope and a triaxial
accelerometer. Each inertial sensor in the ADIS16470 combines
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, linear acceleration (gyroscope bias), and point
of percussion (accelerometer location). As a result, each sensor
has dynamic compensation formulas that provide accurate
sensor measurements over a broad set of conditions.
The ADIS16470 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation
systems. The serial peripheral interface (SPI) and register
structure provide a simple interface for data collection and
configuration control.
The ADIS16470 is in a 44-ball, ball grid array (BGA) package
that is approximately 11 mm × 15 mm × 11 mm.
FUNCTIONAL BLOCK DIAGRAM
CONTROLLER
TRIAXIAL
GYROSCOPE
TRIAXIAL
ACCELEROMETER
POWER
MANAGEMENT
CS
SCLK
DIN
DOUT
GND
VDD
TEMPERATURE
DR
SYNC
RST
SPI
SELF TEST INPUT/OUTPUT
OUTPUT
DATA
REGISTERS
USER
CONTROL
REGISTERS
CALIBRATION
AND
FILTERS
ADIS16470
CLOCK
15343-001
Figure 1.
ADIS16470 Data Sheet
Rev. C | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ....................................................... 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 11
Introduction ................................................................................ 11
Inertial Sensor Signal Chain ..................................................... 11
Register Structure ....................................................................... 12
Serial Peripheral Interface (SPI) ............................................... 13
Data Ready (DR) ........................................................................ 13
Reading Sensor Data .................................................................. 14
Device Configuration ................................................................ 15
User Register Memory Map .......................................................... 16
User Register Defintions ................................................................ 18
Gyroscope Data .......................................................................... 18
Delta Angles ................................................................................ 21
Delta Velocity .............................................................................. 22
Calibration ................................................................................... 24
Applications Information .............................................................. 31
Assembly and Handling Tips .................................................... 31
Power Supply Considerations ................................................... 32
Serial Port Operation ................................................................. 32
Digital Resolution of Gyroscopes and Accelerometers ......... 32
Evaluation Tools ......................................................................... 33
Tray Drawing .............................................................................. 35
Packaging and Ordering Information ......................................... 36
Outline Dimensions ................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
4/2019—Rev. B to Rev. C
Changes to Serial Peripheral Interface (SPI) Section ................. 13
Changes to Figure 28 ...................................................................... 14
Changes to Table 10 and Gyroscope Data Section ..................... 18
Changes to Acceleration Data Section ......................................... 19
Added Accelerometer Data Formatting Section ........................ 20
Deleted Accelerometer Resolution Section Header ................... 20
Added Serial Port Operation Section, Maximum Throughput
Section, Serial Port SCLK Underrun/Overrun Conditions, and
Digital Resolution of Gyroscopes and Accelerometers Section ..... 32
Moved Gyroscope Data Width (Digital Resolution) Section and
Accelerometer Data Width (Digital Resolution) Section .......... 32
Added Tray Drawing Section ........................................................ 35
Added Figure 50 .............................................................................. 35
2/2019—Rev. A to Rev. B
Changes to Table 2 ............................................................................ 5
Changes to Figure 5 .......................................................................... 6
Changes to Figure 9, Figure 10, Figure 11, Figure 12, and
Figure 13 .......................................................................................... 10
Changes to Figure 14, Figure 15, and Figure 16 ......................... 11
Changes to Figure 18 and Figure 19............................................. 12
Added Gyroscope Data Width (Digital Resolution) Section ... 18
Added Accelerometer Data Width (Digital Resolution) Section .. 20
Change to Calibration, Accelerometer Bias (XA_BIAS_LOW
and XA_BIAS_HIGH) Section ..................................................... 25
Change to Filter Control Register (FILT_CTRL) Section ......... 26
Changes to Direct Sync Mode Section and Pulse Sync Mode
Sec tion .............................................................................................. 27
Changed Self Test Section to Sensor Self Test Section .............. 28
Changes to Sensor Self Test Section ............................................. 28
11/2017—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 3
10/2017—Rev. 0: Initial Version
Data Sheet ADIS16470
Rev. C | Page 3 of 36
SPECIFICATIONS
TC = 25°C, VDD = 3.3 V, angular rate = 0°/sec, dynamic range = ±2000°/sec ± 1 g, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
GYROSCOPES
Dynamic Range ±2000 °/sec
Sensitivity 16-bit format 10 LSB/°/sec
32-bit format 655,360 LSB/°/sec
Error over Temperature −10°C ≤ TC ≤ +75°C ±0.25 %
Misalignment Axis to axis ±0.1 Degrees
Nonlinearity1 Full scale (FS) = 2000°/sec ±0.25 %FS
Bias
In Run Stability 1 σ 8 °/hr
Angular Random Walk 1 σ 0.34 °/√hr
Error over Temperature −10°C ≤ TC ≤ +75°C, 1 σ 0.2 °/sec
Linear Acceleration Effect Any direction, 1 σ 0.015 °/sec/g
Vibration Rectification Error 0.0005 °/sec/g2
Output Noise 1 σ, no filtering 0.17 °/sec rms
Rate Noise Density 1 σ, f = 10 Hz to 40 Hz 0.008 °/sec/√Hz rms
3 dB Bandwidth 550 Hz
Sensor Resonant Frequency 66 kHz
ACCELEROMETERS2 Each axis
Dynamic Range ±40 g
Sensitivity 16-bit format 800 LSB/g
32-bit format 52,428,800 LSB/g
Error over temperature −10°C ≤ TC ≤ +75°C ±0.1 %
Misalignment Axis to axis ±0.1 Degrees
Nonlinearity Best fit straight line, FS = ±10 g 0.02 % FS
Best fit straight line, FS = ±20 g 0.4 % FS
Best fit straight line, FS = ±40 g 1.5 % FS
Bias
In Run Stability 1 σ 13 μg
Velocity Random Walk 1 σ 0.037 m/sec/√Hr
Error over Temperature −10°C ≤ TC ≤ +75°C, 1 σ ±4 mg
Output Noise No filtering 2.3 mg rms
Noise Density f = 10 Hz to 40 Hz, no filtering 100 μg/√Hz rms
3 dB Bandwidth 600 Hz
Sensor Resonant Frequency Y-axis, z-axis 5.65 kHz
X-axis 5.25 kHz
TEMPERATURE SENSOR
Scale Factor 0.1 °C/LSB
LOGIC INPUTS3
Input Voltage
High, VIH 2.0 V
Low, VIL 0.8 V
RST Pulse Width 1 μs
CS Wake-Up Pulse Width 20 μs
ADIS16470 Data Sheet
Rev. C | Page 4 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
Input Current
Logic 1, IIH V
IH = 3.3 V 10 μA
Logic 0, IIL V
IL = 0 V
All Pins Except RST 10 μA
RST Pin 0.33 mA
Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS
Output Voltage
High, VOH I
SOURCE = 0.5 mA 2.4 V
Low, VOL I
SINK = 2.0 mA 0.4 V
FLASH MEMORY Endurance4 10000 Cycles
Data Retention5 T
J = 85°C 20 Years
FUNCTIONAL TIMES6 Time until data is available
Power-On Start-Up Time VDD > 3.0 V to DR pulsing (see Figure 23) 252 ms
Hardware Reset Recovery Time7 RST > VOH to DR pulsing (see Figure 25) 193 ms
Software Reset Recovery Time Register GLOB_CMD, Bit 7 = 1 (see Table 109) 193 ms
Flash Memory Update Time Register GLOB_CMD, Bit 3 = 1 (see Table 109 72 ms
Flash Memory Test Time Register GLOB_CMD, Bit 4 = 1 (see Table 109 32 ms
Factory Calibration Restore Time Register GLOB_CMD, Bit 1 = 1 (see Table 109) 142 ms
Sensor Self Test Time8 Register GLOB_CMD, Bit 2 = 1 (see Table 109) 14 ms
CONVERSION RATE 2000 SPS
Initial Clock Accuracy 3 %
Sync Input Clock 1.9 2.1 kHz
POWER SUPPLY, VDD Operating voltage range 3.0 3.6 V
Power Supply Current9 Normal mode, VDD = 3.3 V 42 50 mA
1 Linearity is based on the deviation from a best fit linear model.
2 All specifications associated with the accelerometers relate to the full-scale range of ±40 g, unless otherwise noted.
3 The digital input/output signals use a 3.3 V system.
4 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
5 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
6 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
7 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.
8 Sensor self test time can extend when using external clock rates that are lower than 2000 Hz.
9 Supply current transients can reach 250 mA during initial startup or reset recovery.
Data Sheet ADIS16470
Rev. C | Page 5 of 36
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter Description
Normal Mode Burst Read
Unit Min1 Typ Max Min1, 2 Typ Max
fSCLK Serial clock 0.1 2.0 0.1 1.0 MHz
tSTALL Stall period3 between data 16 N/A μs
tREADRATE Read rate 24 μs
tCS Chip select to SCLK edge 200 200 ns
tDAV DOUT valid after SCLK edge 25 25 ns
tDSU DIN setup time before SCLK rising edge 25 25 ns
tDHD DIN hold time after SCLK rising edge 50 50 ns
tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns
tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 ns
tSFS CS high after SCLK edge 0 0 ns
t1 Input sync positive pulse width
Pulse sync mode, MSC_CTRL = 101 (binary, see Table 101) 5 5 μs
tSTDR Input sync to data ready valid transition
Direct sync mode, MSC_CTRL = 001 (binary, see Table 101) 256 256 μs
Pulse sync mode, MSC_CTRL = 101 (binary, see Table 101) 256 256 μs
tNV Data invalid time 20 20 μs
t2 Input sync period4 477 477 μs
1 Guaranteed by design and characterization, but not tested in production.
2 N/A means not applicable.
3 When using the burst read mode, the stall period is not applicable.
4 This specification is rounded up from the cycle time that comes from the maximum input clock frequency (2100 Hz).
Timing Diagrams
CS
SCLK
DOUT
DIN
1 2 3 4 5 6 15 16
R/W A5A6 A4 A3 A2 DC2
MSB D14
DC1 LSB
D13 D12 D10D11 D2 LSBD1
t
CS
t
SFS
t
DAV
t
DHD
t
DSU
t
SCLKR
t
DR
t
DF
t
SCLKF
15343-002
Figure 2. SPI Timing and Sequence
CS
SCLK
t
READRATE
t
STALL
15343-003
Figure 3. Stall Time and Data Rate
Data Sheet ADIS16470
Rev. C | Page 7 of 36
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Mechanical Shock Survivability
Any Axis, Unpowered 2000 g
Any Axis, Powered 2000 g
VDD to GND −0.3 V to +3.6 V
Digital Input Voltage to GND −0.3 V to VDD + 0.2 V
Digital Output Voltage to GND −0.3 V to VDD + 0.2 V
Operating Temperature Range −25°C to +85°C
Storage Temperature Range1 −65°C to +150°C
Barometric Pressure 2 bar
1 Extended exposure to temperatures that are lower than −20°C or higher
than +85°C can adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
The ADIS16470 is a multichip module that includes many
active components. The values in Table 4 identify the thermal
response of the hottest component inside of the ADIS16470,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient or
case temperature.
For example, when the ambient temperature is 70°C, the hottest
junction temperature (TJ) inside of the ADIS16470 is 93°C.
TJ = θJA × VDD × IDD + 70°C
TJ = 158.2°C/W × 3.3 V × 0.044 A + 70°C
TJ = 93°C
Table 4. Package Characteristics
Package Type θJA1 θ
JC2 Device Weight
ML-44-13 158.2°C/W 106.1°C/W 1.3 grams
1 θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
2 θJC is the junction to case thermal resistance.
3 Thermal impedance values come from direct observation of the hottest
temperature inside of the ADIS16470, when it is attached to a FR4-08 PCB
that has two metal layers and has a thickness of 0.063”.
ESD CAUTION
ADIS16470 Data Sheet
Rev. C | Page 8 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A
1
BCDEFGH J
2
3
4
5
6
7
8
K
BOTTOM VIEW OF PACKAGE
ADIS16470
A1 PIN
INDICATOR
15343-005
Figure 6. Pin Assignments, Bottom View
PIN A8
PIN A1
PIN K8
A1 PIN
INDICATOR
15343-006
Figure 7. Pin Assignments, Package Level View
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type Description
A1 GND Supply Power Ground
A2 GND Supply Power Ground
A3 GND Supply Power Ground
A4 GND Supply Power Ground
A5 GND Supply Power Ground
A6 GND Supply Power Ground
A7 GND Supply Power Ground
A8 GND Supply Power Ground
B3 GND Supply Power Ground
B4 GND Supply Power Ground
B5 GND Supply Power Ground
B6 GND Supply Power Ground
C2 GND Supply Power Ground
C3 DNC Not applicable Do Not Connect
C6 GND Supply Power Ground
C7 VDD Supply Power Supply
D3 GND Supply Power Ground
D6 VDD Supply Power Supply
E2 GND Supply Power Ground
E3 VDD Supply Power Supply
E6 GND Supply Power Ground
E7 GND Supply Power Ground
F1 GND Supply Power Ground
F3 RST Input Reset
F6 GND Supply Power Ground
F8 GND Supply Power Ground
G2 GND Supply Power Ground
G3 CS Input SPI, Chip Select
G6 DIN Input SPI, Data Input
G7 GND Supply Power Supply
H1 VDD Supply Power Supply
H3 DOUT Output SPI, Data Output
H6 SCLK Input SPI, Serial Clock
H8 GND Supply Power Ground
Data Sheet ADIS16470
Rev. C | Page 9 of 36
Pin No. Mnemonic Type Description
J2 GND Supply Power Ground
J3 SYNC Input Sync (External Clock)
J4 VDD Supply Power Supply
J5 VDD Supply Power Supply
J6 DR Output Data Ready
J7 GND Supply Power Ground
K1 GND Supply Power Ground
K3 GND Supply Power Ground
K6 VDD Supply Power Supply
K8 GND Supply Power Ground
ADIS16470 Data Sheet
Rev. C | Page 10 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
1k
1
10
100
0.01 10k1k1001010.1
ROOT ALLAN VARIANCE (°/Hour)
Tau (Seconds)
15343-007
Figure 8. Gyroscope Root Allan Variance, TC = 25°C
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–10 0 10 20 30 40 50 60 70
GYROSCOPE BIAS ERROR (°/Seconds)
CASE TEMPERATURE (°C)
µ + 1σ
µ – 1σ
µ
15343-008
Figure 9. Gyroscope Bias Error vs. Case Temperature
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–10 0 10 20 30 40 50 60 70
GYROSCOPE SCALE ERROR (% FS)
CASE TEMPERATURE (°C)
µ + 1σ
µ – 1σ
µ
15343-009
Figure 10. Gyroscope Scale (Sensitivity) Error vs. Case Temperature
1k
1
10
100
0.01 10k1k1001010.1
ROOT ALLAN VARIANCE (µg/Hour)
Tau (Seconds)
15343-311
µ + 1σ
µ – 1σ
µ
Figure 11. Accelerometer Root Allan Variance, TC = 25°C
5
–5
–3
–4
–2
–1
0
1
2
3
4
–100 10203040506070
ACCELEROMETER BIAS ERROR (mg)
CASE TEMPERATURE (°C)
µ + 1σ
µ – 1σ
µ
15343-011
Figure 12. Accelerometer Bias Error vs. Case Temperature
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
–10 0 10 20 30 40 50 60 70
ACCELEROMETER SCALE ERROR (% FS)
CASE TEMPERATURE (°C)
µ + 1σ
µ – 1σ
µ
15343-012
Figure 13. Accelerometer Scale (Sensitivity) Error vs. Case Temperature
Data Sheet ADIS16470
Rev. C | Page 11 of 36
THEORY OF OPERATION
INTRODUCTION
When using the factory default configuration for all user
configurable control registers, the ADIS16470 initializes itself
and automatically starts a continuous process of sampling,
processing, and loading calibrated sensor data into its output
registers at a rate of 2000 SPS.
INERTIAL SENSOR SIGNAL CHAIN
Figure 14 provides the basic signal chain for the inertial sensors
in the ADIS16470. This signal chain produces an update rate
of 2000 SPS in the output data registers when it operates in
internal clock mode (default, see Register MSC_CTRL,
Bits [4:2] in Table 101).
OUTPUT
DATA
REGISTERS
AVERAGING
DECIMATING
FILTER
CALIBRATION
BARTLETT
WINDOW
FIR
FILTER
MEMS
SENSORS
15343-019
Figure 14. Signal Processing Diagram, Inertial Sensors
Gyroscope Data Sampling
The three gyroscopes produce angular rate measurements around
three orthogonal axes (x, y, and z). Figure 15 shows the sampling
plan for each gyroscope when the ADIS16470 operates in the
internal clock mode (default, see Register MSC_CTRL, Bits[4:2]
in Table 101). Each gyroscope has an analog-to-digital converter
(ADC) and sample clock (fSG) that drives data sampling at a rate of
4100 Hz (±5%). The internal processor reads and processes this
data from each gyroscope at a rate of 2000 Hz (fSM).
MEMS
GYROSCOPE
f
SM
= 2000Hz
INTERNAL
DATA
REGISTER
f
SG
= 4100Hz
ADC
15343-014
TO
BARTLETT
WINDOW
FIR FILTER
Figure 15. Gyroscope Data Sampling
Accelerometer Data Sampling
The three accelerometers produce linear acceleration measurements
along the same orthogonal axes (x, y, and z) as the gyroscopes.
Figure 16 provides the sampling plan for each accelerometer
when the ADIS16470 operates in the internal clock mode
(default, see Register MSC_CTRL, Bits[4:2] in Table 101).
MEMS
ACCELEROMETER
2 × f
SM
= 4000Hz
ADC
Σ
1
2
2
n = 1
a(n)
÷2
15343-020
TO
BARTLETT
WINDOW
FIR FILTER
Figure 16. Accelerometer Data Sampling
External Clock Options
The ADIS16470 provides three different modes of operation
that support the device using an external clock to control the
internal processing rate (fSM in Figure 15 and Figure 16) through
the SYNC pin. The MSC_CTRL register (see Table 101)
provides the configuration options for these external clock
modes in Bits[4:2].
Inertial Sensor Calibration
The inertial sensor calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and user
calibration (see Figure 17).
TO
DIGITAL
FILTERS
USER
CALIBRATION
FROM
MEMS
SENSOR
FACTORY
CALIBRATION
15343-021
Figure 17. Inertial Sensor Calibration Processing
The factory calibration of the gyroscope applies the following
correction formulas to the data of each gyroscope:
ZC
YC
XC
333231
232221
131211
Z
Y
X
Z
Y
X
333231
232221
131211
ZC
YC
XC
a
a
a
lll
lll
lll
b
b
b
ω
ω
ω
mmm
mmm
mmm
ω
ω
ω
where:
ωXC, ωYC, and ωZC are the gyroscope outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
ωX, ωY, and ωZ are the gyroscope outputs (precalibration).
bX, bY, and bZ provide bias correction.
l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear g correction
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
All of the correction factors in this relationship come from
direct observation of the response of each gyroscope at multiple
temperatures over the calibration temperature range (−10°C ≤
TC ≤ +75°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration. Register MSC_CTRL, Bit 7 (see Table 101)
provides the only user configuration option for the factory
calibration of the gyroscopes: an on/off control for the linear g
compensation. See Figure 40 for more details on the user
calibration options that are available for the gyroscopes.
ADIS16470 Data Sheet
Rev. C | Page 12 of 36
The factory calibration of the accelerometer applies the following
correction formulas to the data of each accelerometer:
2
2
2
3231
2321
1312
333231
232221
131211
0
0
0
ZC
YC
XC
Z
Y
X
Z
Y
X
ZC
YC
XC
pp
pp
pp
b
b
b
a
a
a
mmm
mmm
mmm
a
a
a
where:
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
aX, aY, and aZ are the accelerometer outputs (precalibration).
bX, bY, and bZ provide bias correction.
p12, p13, p21, p23, p31 and p32 provide point of percussion alignment
correction to (see Figure 43).
ω2XC, ω2YC, and ω2ZC are the square of the gyroscope outputs
(post calibration).
All of the correction factors in this relationship come from
direct observation of the response of each accelerometer at
multiple temperatures, over the calibration temperature range
(−10°C ≤ TC ≤ +75°C). These correction factors are stored
in the flash memory bank; but they are not available for
observation or configuration. MSC_CTRL, Bit 6 (see Table 101)
provides the only user configuration option for the factory
calibration of the accelerometers: an on/off control for the point of
percussion, alignment function. See Figure 41 for more details
on the user calibration options that are available for the
accelerometers.
Bartlett Window FIR Filter
The Bartlett window finite impulse response (FIR) filter (see
Figure 18) contains two averaging filter stages, in a cascade
configuration. The FILT_CTRL register (see Table 99) provides
the configuration controls for this filter.
FROM
MEMS
SENSOR
TO
FACTORY
CALIBRATION
Σ
1
N
N
n = 1
ω(n)
Σ
1
N
N
n = 1
ω(n)
15343-222
Figure 18. Bartlett Window FIR Filter Signal Path
Averaging/Decimating Filter
The second digital filter averages multiple samples together to
produce each register update. In this type of filter structure, the
number of samples in the average is equal to the reduction in
the update rate for the output data registers. The DEC_RATE
register (see Table 105) provides the configuration controls for
this filter.
FROM
USER
CALIBRATION ÷N
TO OUTPUT
REGISTERS
Σ
1
N
N
n = 1
ω(n)
15343-223
Figure 19. Averaging/Decimating Filter Diagram
REGISTER STRUCTURE
All communication between the ADIS16470 and an external
processor involves either reading the contents of an output
register or writing configuration/command information to a
control register. The output data registers include the latest
sensor data, error flags, and identification information. The
control registers include sample rate, filtering, calibration, and
diagnostic options. Each user accessible register has two bytes
(upper and lower), each of which have their own unique
address. See Table 8 for a detailed list of all user registers, along
with their addresses.
TRIAXIAL
GYROSCOPE
TEMPERATURE
SENSOR
TRIAXIAL
ACCELEROMETER
OUTPUT
REGISTERS
CONTROL
REGISTERS
CONTROLLER
SENSOR
SIGNAL
PROCESSING
SPI
15343-022
Figure 20. Basic Operation of the ADIS16470
Data Sheet ADIS16470
Rev. C | Page 13 of 36
SERIAL PERIPHERAL INTERFACE (SPI)
The SPI provides access to the user registers (see Table 8). Figure 21
provides the most common connections between the ADIS16470
and a SPI master, which is often an embedded processor that
has a SPI-compatible interface. In this example, the SPI master
uses an interrupt service routine to collect data every time the
data ready (DR) signal pulses.
Additional information on the ADIS16470 SPI can be found in
the Applications Information section of this data sheet.
CS
SYSTEM
PROCESSOR
SPI MASTER
VDD
INPUT/OUTPUT LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
SCLK
DIN
DR
DOUT
SS
SCLK
MOSI
IRQ
MISO
ADIS16470
+3.3V
15343-023
Figure 21. Electrical Connection Diagram
Table 6. Generic SPI Master Pin Names and Functions
Mnemonic Function
SS Slave select
SCLK Serial clock
MOSI Master output, slave input
MISO Master input, slave output
IRQ Interrupt request
Embedded processors typically use control registers to configure
their serial ports for communicating with SPI slave devices such
as the ADIS16470. Table 7 provides a list of settings that describe
the SPI protocol of the ADIS16470. The initialization routine
of the master processor typically establishes these settings using
firmware commands to write them into its control registers.
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
Master ADIS16470 operates as slave
SCLK ≤ 2 MHz1 Maximum serial clock rate
SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase)
MSB First Mode Bit sequence, see Figure 26 for coding
16-Bit Mode Shift register and data length
1 Burst mode read requires this to be ≤1 MHz (see Table 2 for more
information).
DATA READY (DR)
The factory default configuration provides users with a DR
signal on the DR pin (see Table 5), which pulses when the
output data registers are updating. Connect this with a pin on
the embedded processor, which triggers data collection, on the
second edge of this pulse. The MSC_CTRL register, Bit 0 (see
Table 101), controls the polarity of this signal. In Figure 22,
Register MSC_CTRL, Bit 0 = 1, which means that data
collection must start on the rising edges of the DR pulses.
DR
ACTIVE INACTIVE
15343-025
Figure 22. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)
During the startup and reset recovery processes, the DR signal
may exhibit some transient behavior before data production
begins. Figure 23 provides an example of the DR behavior
during startup, and Figure 24 and Figure 25 provide examples
of the DR behavior during recovery from reset commands.
VDD
DR
START-UP TIME
TIME THAT VDD > 3V
PULSING INDICATES
DATA PRODUCTION
15343-228
Figure 23. Data Ready Response During Startup
DR
RESET RECOVERY TIME
SOFTWARE RESET COMMAND
GLOB_CMD[7] = 1
DR PULSING
RESUMES
15343-229
Figure 24. Data Ready Response During Reset
(Register GLOB_CMD, Bit 7 = 1) Recovery
DR
RST
RESET RECOVERY TIME
RST PIN
RELEASED
DR PULSING
RESUMES
15343-230
Figure 25. Data Ready Response During Reset (RST = 0) Recovery
ADIS16470 Data Sheet
Rev. C | Page 14 of 36
R/W R/W
A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
CS
SCLK
DIN
DOUT
A6 A5
D13D14D15
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
15343-024
Figure 26. SPI Communication Bit Sequence
CS12311
SCLK
DIN
DOUT
0x6800
DIAG_STAT X_GYRO_OUT CHECKSUM
15343-030
Figure 27. Burst Read Sequence
CS
SCLK
DIN
DOUT
DIN = 0x7200 = 0111 0010 0000 0000
DOUT = 0100 0000 0101 0110 = 0x4056 = 16470 (PROD_ID)
15343-029
HIGH-Z HIGH-Z
Figure 28. SPI Signal Pattern Showing a Read of the PROD_ID Register
READING SENSOR DATA
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 26) for a
read request on the SPI has three parts: the read bit (R/W = 0),
either address of the register, [A6:A0], and eight don’t care bits,
[DC7:DC0]. Figure 29 provides an example that includes two
register reads in succession. This example starts with DIN =
0x0C00, to request the contents of the Z_GYRO_LOW
register, and follows with 0x0E00, to request the contents of
the Z_GYRO_OUT register. The sequence in Figure 29 also
illustrates full duplex mode of operation, which means that the
ADIS16470 can receive requests on DIN while also transmitting
data out on DOUT within the same 16-bit SPI cycle.
DIN
DOUT
0x0C00 0x0E00 NEXT
ADDRESS
Z_GYRO_LOW Z_GYRO_OUT
15343-028
Figure 29. SPI Read Example
Figure 28 provides an example of the four SPI signals when reading
the PROD_ID register (see Table 117) in a repeating pattern.
This pattern can be helpful when troubleshooting the SPI
interface setup and communications because the signals are
the same for each 16-bit sequence, except during the first cycle.
Burst Read Function
The burst read function provides a way to read a batch of
output data registers, using a continuous stream of bits, at a rate
of up to 1 MHz (SCLK). This method does not require a stall
time between each 16-bit segment (see Figure 3). As shown in
Figure 27, start this mode by setting DIN = 0x6800, and then
read each of the registers in the sequence out of DOUT while
keeping CS low for the entire 176-bit sequence.
The sequence of registers (and checksum value) in the burst read
response depends on which sample clock mode that the ADIS16470
is operating in (Register MSC_CTRL, Bits[4:2], see Table 101).
In all clock modes, except when operating in scaled sync mode
(Register MSC_CTRL, Bits[4:2] = 010), the burst read response
includes the following registers and checksum value: DIAG_STAT,
X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_
OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, DATA_
CNTR, and checksum. In these cases, use the following formula
to verify the checksum value, treating each byte in the formula as
an independent, unsigned, 8-bit number:
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
Data Sheet ADIS16470
Rev. C | Page 15 of 36
When operating in scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010), the burst read response includes the following
registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO_OUT,
Z_GYRO_OUT, X_ACCL_OUT, Y_ACCL_OUT, Z_ACCL_OUT,
TEMP_OUT, TIME_STMP, and the checksum value. In this
case, use the following formula to verify the checksum value,
treating each byte in the formula as an independent, unsigned,
8-bit number.
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits 7:0] +
TIME_STMP, Bits[15:8] + TIME_STMP, Bits[7:0]
DEVICE CONFIGURATION
Each configuration register contains 16 bits (two bytes). Bits[7:0]
contain the low byte, and Bits[15:8] contain the high byte of
each register. Each byte has its own unique address in the user
register map (see Table 8). Updating the contents of a register
requires writing to both of its bytes in the following sequence:
low byte first, high byte second. There are three parts to coding
a SPI command (see Figure 26) that write a new byte of data to
a register: the write bit (R/W = 1), the address of the byte, [A6:A0],
and the new data for that location, [DC7:DC0]. Figure 30
provides a coding example for writing 0x0004 to the
FILT_CTRL register (see Table 99). In Figure 30, the 0xDC04
command writes 0x04 to Address 0x5C (lower byte) and the
0xDD00 command writes 0x00 to Address 0x5D (upper byte).
CS
SCLK
DIN 0xDC04 0xDD00
15343-031
Figure 30. SPI Sequence for Writing 0x0004 to FILT_CTRL
Memory Structure
Figure 31 provides a functional diagram for the memory
structure of the ADIS16470. The flash memory bank contains
the operational code, unit specific calibration coefficients and
user configuration settings. During initialization (power
application or reset recover), this information loads from the
flash memory into the SRAM, which supports all normal
operation, including register access through the SPI port.
Writing to a configuration register (using the SPI) updates its
SRAM location but does not automatically update its settings
in the flash memory bank. The manual flash memory update
command (Register GLOB_CMD, Bit 3, see Table 109) provides
a convenient method for saving all of these settings to the flash
memory bank at one time. A Yes in the flash back-up column of
Table 8 identifies the registers that have storage support in the
flash memory bank.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
15343-032
Figure 31. SRAM and Flash Memory Diagram
ADIS16470 Data Sheet
Rev. C | Page 16 of 36
USER REGISTER MEMORY MAP
Table 8. User Register Memory Map (N/A Means Not Applicable)
Name R/W Flash Backup Address Default Register Description
Reserved N/A N/A 0x00, 0x01 N/A Reserved
DIAG_STAT R No 0x02, 0x03 0x0000 Output, system error flags
X_GYRO_LOW R No 0x04, 0x05 N/A Output, x-axis gyroscope, low word
X_GYRO_OUT R No 0x06, 0x07 N/A Output, x-axis gyroscope, high word
Y_GYRO_LOW R No 0x08, 0x09 N/A Output, y-axis gyroscope, low word
Y_GYRO_OUT R No 0x0A, 0x0B N/A Output, y-axis gyroscope, high word
Z_GYRO_LOW R No 0x0C, 0x0D N/A Output, z-axis gyroscope, low word
Z_GYRO_OUT R No 0x0E, 0x0F N/A Output, z-axis gyroscope, high word
X_ACCL_LOW R No 0x10, 0x11 N/A Output, x-axis accelerometer, low word
X_ACCL_OUT R No 0x12, 0x13 N/A Output, x-axis accelerometer, high word
Y_ACCL_LOW R No 0x14, 0x15 N/A Output, y-axis accelerometer, low word
Y_ACCL_OUT R No 0x16, 0x17 N/A Output, y-axis accelerometer, high word
Z_ACCL_LOW R No 0x18, 0x19 N/A Output, z-axis accelerometer, low word
Z_ACCL_OUT R No 0x1A, 0x1B N/A Output, z-axis accelerometer, high word
TEMP_OUT R No 0x1C, 0x1D N/A Output, temperature
TIME_STAMP R No 0x1E, 0x1F N/A Output, time stamp
Reserved N/A N/A 0x20, 0x21 N/A Reserved
DATA_CNTR R No 0x22, 0x23 N/A New data counter
X_DELTANG_LOW R No 0x24, 0x25 N/A Output, x-axis delta angle, low word
X_DELTANG_OUT R No 0x26, 0x27 N/A Output, x-axis delta angle, high word
Y_DELTANG_LOW R No 0x28, 0x29 N/A Output, y-axis delta angle, low word
Y_DELTANG_OUT R No 0x2A, 0x2B N/A Output, y-axis delta angle, high word
Z_DELTANG_LOW R No 0x2C, 0x2D N/A Output, z-axis delta angle, low word
Z_DELTANG_OUT R No 0x2E, 0x2F N/A Output, z-axis delta angle, high word
X_DELTVEL_LOW R No 0x30, 0x31 N/A Output, x-axis delta velocity, low word
X_DELTVEL_OUT R No 0x32, 0x33 N/A Output, x-axis delta velocity, high word
Y_DELTVEL_LOW R No 0x34, 0x35 N/A Output, y-axis delta velocity, low word
Y_DELTVEL_OUT R No 0x36, 0x37 N/A Output, y-axis delta velocity, high word
Z_DELTVEL_LOW R No 0x38, 0x39 N/A Output, z-axis delta velocity, low word
Z_DELTVEL_OUT R No 0x3A, 0x3B N/A Output, z-axis delta velocity, high word
Reserved N/A N/A 0x3C to 0x3F N/A Reserved
XG_BIAS_LOW R/W Yes 0x40, 0x41 0x0000 Calibration, offset, gyroscope, x-axis, low word
XG_BIAS_HIGH R/W Yes 0x42, 0x43 0x0000 Calibration, offset, gyroscope, x-axis, high word
YG_BIAS_LOW R/W Yes 0x44, 0x45 0x0000 Calibration, offset, gyroscope, y-axis, low word
YG_BIAS_HIGH R/W Yes 0x46, 0x47 0x0000 Calibration, offset, gyroscope, y-axis, high word
ZG_BIAS_LOW R/W Yes 0x48, 0x49 0x0000 Calibration, offset, gyroscope, z-axis, low word
ZG_BIAS_HIGH R/W Yes 0x4A, 0x4B 0x0000 Calibration, offset, gyroscope, z-axis, high word
XA_BIAS_LOW R/W Yes 0x4C, 0x4D 0x0000 Calibration, offset, accelerometer, x-axis, low word
XA_BIAS_HIGH R/W Yes 0x4E, 0x4F 0x0000 Calibration, offset, accelerometer, x-axis, high word
YA_BIAS_LOW R/W Yes 0x50, 0x51 0x0000 Calibration, offset, accelerometer, y-axis, low word
YA_BIAS_HIGH R/W Yes 0x52, 0x53 0x0000 Calibration, offset, accelerometer, y-axis, high word
ZA_BIAS_LOW R/W Yes 0x54, 0x55 0x0000 Calibration, offset, accelerometer, z-axis, low word
ZA_BIAS_HIGH R/W Yes 0x56, 0x57 0x0000 Calibration, offset, accelerometer, z-axis, high word
Reserved N/A N/A 0x58 to 0x5B N/A Reserved
FILT_CTRL R/W Yes 0x5C, 0x5D 0x0000 Control, Bartlett window FIR filter
Reserved N/A N/A 0x5E, 0x5F N/A Reserved
MSC_CTRL R/W Yes 0x60, 0x61 0x00C1 Control, input/output and other miscellaneous options
UP_SCALE R/W Yes 0x62, 0x63 0x07D0
Control, scale factor for input clock, pulse per second (PPS)
mode
DEC_RATE R/W Yes 0x64, 0x65 0x0000 Control, decimation filter (output data rate)
Data Sheet ADIS16470
Rev. C | Page 17 of 36
Name R/W Flash Backup Address Default Register Description
NULL_CNFG R/W Yes 0x66, 0x67 0x070A Control, bias estimation period
GLOB_CMD W No 0x68, 0x69 N/A Control, global commands
Reserved N/A N/A 0x6A to 0x6B N/A Reserved
FIRM_REV R N/A 0x6C, 0x6D N/A Identification, firmware revision
FIRM_DM R N/A 0x6E, 0x6F N/A Identification, date code, day and month
FIRM_Y R N/A 0x70, 0x71 N/A Identification, date code, year
PROD_ID R N/A 0x72, 0x73 0x4056 Identification, part number
SERIAL_NUM R N/A 0x74, 0x75 N/A Identification, serial number
USER_SCR1 R/W N/A 0x76, 0x77 N/A User Scratch Register 1
USER_SCR2 R/W N/A 0x78, 0x79 N/A User Scratch Register 2
USER_SCR3 R/W N/A 0x7A, 0x7B N/A User Scratch Register 3
FLSHCNT_LOW R N/A 0x7C, 0x7D N/A Output, flash memory write cycle counter, lower word
FLSHCNT_HIGH R N/A 0x7E, 0x7E N/A Output, flash memory write cycle counter, upper word
ADIS16470 Data Sheet
Rev. C | Page 18 of 36
USER REGISTER DEFINTIONS
Status/Error Flag Indicators (DIAG_STAT)
Table 9. DIAG_STAT Register Definition
Addresses Default Access Flash Backup
0x02, 0x03 0x0000 R No
Table 10. DIAG_STAT Bit Assignments
Bits Description
[15:8] Reserved.
7 Clock error. A 1 indicates that the internal data sampling
clock (fSM, see Figure 15 and Figure 16) does not
synchronize with the external clock, which only applies
when using scale sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 101). When this occurs, adjust
the frequency of the clock signal on the SYNC pin to
operate within the appropriate range.
6 Memory failure. A 1 indicates a failure in the flash memory
test (Register GLOB_CMD, Bit 4, see Table 109), which
involves a comparison between a cyclic redundancy
check (CRC) computation of the present flash memory
and a CRC computation from the same memory
locations at the time of initial programming (during
production process). If this occurs, repeat the same test.
If this error persists, replace the ADIS16470 device.
5 Sensor failure. A 1 indicates failure of at least one sensor,
at the conclusion of the self test (Register GLOB_CMD,
Bit 2, see Table 109). If this occurs, repeat the same test.
If this error persists, replace the ADIS16470. Motion, during
the execution of this test, can cause a false failure.
4 Standby mode. A 1 indicates that the voltage across
VDD and GND is <2.8 V, which causes data processing to
stop. When VDD ≥ 2.8 V for 250 ms, the ADIS16470
reinitializes itself and starts producing data again.
3 SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer multiple of
16. When this occurs, repeat the previous communication
sequence. Persistence in this error may indicate a weakness
in the SPI service that the ADIS16470 is receiving from
the system it is supporting.
2 Flash memory update failure. A 1 indicates that the most
recent flash memory update (Register GLOB_CMD, Bit 3,
see Table 109) failed. If this occurs, ensure that VDD ≥ 3 V
and repeat the update attempt. If this error persists,
replace the ADIS16470.
1 Data path overrun. A 1 indicates that one of the data
paths have experienced an overrun condition. If this
occurs, initiate a reset, using the RST pin (see Table 5,
Pin F3) or Register GLOB_CMD, Bit 7 (see Table 109). See
the Serial Port Operation section for more details on
conditions that may cause this bit to be set to 1.
0 Reserved
The DIAG_STAT register (see Table 9 and Table 10) provides
error flags for monitoring the integrity and operation of the
ADIS16470. Reading this register causes all of its bits to return
to 0. The error flags in DIAG_STAT are sticky, meaning that
when they raise to a 1 value that they remain there until a read
request clears them. If an error condition persists, its flag (bit)
automatically returns to an alarm value of 1.
GYROSCOPE DATA
The gyroscopes in the ADIS16470 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 32
illustrates the orientation of each gyroscope axis, along with the
direction of rotation that produces a positive response in each
of their measurements.
15343-033
ω
Z
ω
Y
Y
ω
X
Z
X
PIN A8 PIN K1
Figure 32. Gyroscope Axis and Polarity Assignments
Each gyroscope has two output data registers. Figure 33 illustrates
how these two registers combine to support a 32-bit, twos
complement data format for the x-axis gyroscope measurements.
This format also applies to the y- and z-axes.
Additional information on the precision and resolution of the
accelerometers can be found in the Digital Resolution of
Gyroscopes and Accelerometers section of this data sheet.
X-AXIS GYROSCOPE DATA
01515 0
X_GYRO_OUT X_GYRO_LOW
15343-034
Figure 33. Gyroscope Output Data Structure
Gyroscope Data Formatting
Table 11 and Table 12 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats.
Table 11. 16-Bit Gyroscope Data Format Examples
Rotation Rate Decimal Hex Binary
+2000°/sec +20,000 0x4E20 0100 1110 0010 0000
+0.2°/sec +2 0x0002 0000 0000 0000 0010
+0.1°/sec +1 0x0001 0000 0000 0000 0001
0°/sec 0 0x0000 0000 0000 0000 0000
−0.1°/sec −1 0xFFFF 1111 1111 1111 1111
−0.2°/sec −2 0xFFFE 1111 1111 1111 1110
−2000°/sec −20,000 0xB1E0 1011 0001 1110 0000
Table 12. 32-Bit Gyroscope Data Format Examples
Rotation Rate Decimal Hex
+2000°/sec +1,310,720,000 0x4E200000
+0.1°/sec/215 +2 0x00000002
+0.1°/sec/216 +1 0x00000001
0°/sec 0 0x0000000
−0.1°/sec/216 −1 0xFFFFFFFF
−0.1°/sec/215 −2 0xFFFFFFFE
−2000°/sec −1,310,720,000 0xB1E00000
Data Sheet ADIS16470
Rev. C | Page 19 of 36
X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT)
Table 13. X_GYRO_LOW Register Definition
Addresses Default Access Flash Backup
0x04, 0x05 Not applicable R No
Table 14. X_GYRO_LOW Bit Definitions
Bits Description
[15:0] X-axis gyroscope data; additional resolution bits
Table 15. X_GYRO_OUT Register Definition
Addresses Default Access Flash Backup
0x06, 0x07 Not applicable R No
Table 16. X_GYRO_OUT Bit Definitions
Bits Description
[15:0] X-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 0.1°/sec
The X_GYRO_LOW (see Table 13 and Table 14) and X_GYRO_
OUT (see Table 15 and Table 16) registers contain the gyroscope
data for the x-axis.
Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT)
Table 17. Y_GYRO_LOW Register Definition
Addresses Default Access Flash Backup
0x08, 0x09 Not applicable R No
Table 18. Y_GYRO_LOW Bit Definitions
Bits Description
[15:0] Y-axis gyroscope data; additional resolution bits
Table 19. Y_GYRO_OUT Register Definition
Addresses Default Access Flash Backup
0x0A, 0x0B Not applicable R No
Table 20. Y_GYRO_OUT Bit Definitions
Bits Description
[15:0] Y-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 0.1°/sec
The Y_GYRO_LOW (see Table 17 and Table 18) and Y_GYRO_
OUT (see Table 19 and Table 20) registers contain the gyroscope
data for the y-axis.
Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT)
Table 21. Z_GYRO_LOW Register Definition
Addresses Default Access Flash Backup
0x0C, 0x0D Not applicable R No
Table 22. Z_GYRO_LOW Bit Definitions
Bits Description
[15:0] Z-axis gyroscope data; additional resolution bits
Table 23. Z_GYRO_OUT Register Definition
Addresses Default Access Flash Backup
0x0E, 0x0F Not applicable R No
Table 24. Z_GYRO_OUT Bit Definitions
Bits Description
[15:0] Z-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 0.1°/sec
The Z_GYRO_LOW (see Table 21 and Table 22) and Z_GYRO_
OUT (see Table 23 and Table 24) registers contain the gyroscope
data for the z-axis.
Acceleration Data
The accelerometers in the ADIS16470 measure both dynamic
and static (response to gravity) acceleration along the same three
orthogonal axes that define the axes of rotation for the gyroscopes
(x, y, and z). Figure 34 illustrates the orientation of each
accelerometer axis, along with the direction of acceleration
that produces a positive response in each of their measurements.
a
z
a
x
a
y
Z
X
Y
PIN A8 PIN K1
15343-035
Figure 34. Accelerometer Axis and Polarity Assignments
Each accelerometer has two output data registers. Figure 35
shows how these two registers combine to support a 32-bit,
twos complement data format for the x-axis accelerometer
measurements. This format also applies to the y- and z-axes.
Additional information on the precision and resolution of the
accelerometers can be found in the Digital Resolution of
Gyroscopes and Accelerometers section of this data sheet.
X-AXIS ACCELEROMETER DATA
01515 0
X_ACCL_OUT X_ACCL_LOW
15343-036
Figure 35. Accelerometer Output Data Structure
ADIS16470 Data Sheet
Rev. C | Page 20 of 36
Accelerometer Data Formatting
Table 25 and Table 26 offer various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
Table 25. 16-Bit Accelerometer Data Format Examples
Acceleration Decimal Hex Binary
+40 g +32,000 0x7D00 0111 1101 0000 0000
+2.5 mg +2 0x0002 0000 0000 0000 0010
+1.25 mg +1 0x0001 0000 0000 0000 0001
0 mg 0 0x0000 0000 0000 0000 0000
−1.25 mg −1 0xFFFF 1111 1111 1111 1111
−2.5 mg −2 0xFFFE 1111 1111 1111 1110
−40 g −32,000 0x8300 1000 0011 0000 0000
Table 26. 32-Bit Accelerometer Data Format Examples
Acceleration (g) Decimal Hex
+40 g +2,097,152,000 0x7D000000
+1.25/215 mg +2 0x00000002
+1.25/216 mg +1 0x00000001
0 0 0x00000000
−1.25/216 mg −1 0xFFFFFFFF
−1.25/215 mg −2 0xFFFFFFFE
−40 g −2,097,152,000 0x83000000
X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT)
Table 27. X_ACCL_LOW Register Definition
Addresses Default Access Flash Backup
0x10, 0x11 Not applicable R No
Table 28. X_ACCL_LOW Bit Definitions
Bits Description
[15:0] X-axis accelerometer data; additional resolution bits
Table 29. X_ACCL_OUT Register Definition
Addresses Default Access Flash Backup
0x12, 0x13 Not applicable R No
Table 30. X_ACCL_OUT Bit Definitions
Bits Description
[15:0] X-axis accelerometer data, high word; twos
complement, ±40g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The X_ACCL_LOW (see Table 27 and Table 28) and X_ACCL_
OUT (see Table 29 and Table 30) registers contain the
accelerometer data for the x-axis.
Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT)
Table 31. Y_ACCL_LOW Register Definition
Addresses Default Access Flash Backup
0x14, 0x15 Not applicable R No
Table 32. Y_ACCL_LOW Bit Definitions
Bits Description
[15:0] Y-axis accelerometer data; additional resolution bits
Table 33. Y_ACCL_OUT Register Definition
Addresses Default Access Flash Backup
0x16, 0x17 Not applicable R No
Table 34. Y_ACCL_OUT Bit Definitions
Bits Description
[15:0] Y-axis accelerometer data, high word; twos
complement, ±40g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The Y_ACCL_LOW (see Table 31 and Table 32) and Y_ACCL_
OUT (see Table 33 and Table 34) registers contain the
accelerometer data for the y-axis.
Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)
Table 35. Z_ACCL_LOW Register Definition
Addresses Default Access Flash Backup
0x18, 0x19 Not applicable R No
Table 36. Z_ACCL_LOW Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data; additional resolution bits
Table 37. Z_ACCL_OUT Register Definition
Addresses Default Access Flash Backup
0x1A, 0x1B Not applicable R No
Table 38. Z_ACCL_OUT Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data, high word; twos
complement, ±40g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The Z_ACCL_LOW (see Table 35 and Table 36) and Z_ACCL_
OUT (see Table 37 and Table 38) registers contain the
accelerometer data for the z-axis.
Internal Temperature (TEMP_OUT)
Table 39. TEMP_OUT Register Definition
Addresses Default Access Flash Backup
0x1C, 0x1D Not applicable R No
Table 40. TEMP_OUT Bit Definitions
Bits Description
[15:0] Temperature data; twos complement,
1 LSB = 0.1°C, 0°C = 0x0000
The TEMP_OUT register (see Table 39 and Table 40) provides a
coarse measurement of the temperature inside of the ADIS16470.
This data is most useful for monitoring relative changes in the
thermal environment.
Table 41. TEMP_OUT Data Format Examples
Temperature (°C) Decimal Hex Binary
+85 +850 0x0352 0000 0011 0101 0010
+70 +700 0x02BC 0000 0010 1011 1100
+25 +250 0x00FA 0000 0000 1111 1010
+0.2 +2 0x0002 0000 0000 0000 0010
+0.1 +1 0x0001 0000 0000 0000 0001
+0 0 0x0000 0000 0000 0000 0000
Data Sheet ADIS16470
Rev. C | Page 21 of 36
Temperature (°C) Decimal Hex Binary
+0.1 −1 0xFFFF 1111 1111 1111 1111
+0.2 −2 0xFFFE 1111 1111 1111 1110
−25 −250 0xFF06 1111 1111 0000 0110
Time Stamp (TIME_STAMP)
Table 42. TIME_STAMP Register Definition
Addresses Default Access Flash Backup
0x1E, 0x1F Not applicable R No
Table 43. TIME_STAMP Bit Definitions
Bits Description
[15:0] Time from the last pulse on the SYNC pin; offset binary
format, 1 LSB = 49.02 μs
The TIME_STAMP (see Table 42 and Table 43) register works
in conjunction with scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 101). The 16-bit number in
TIME_STAMP contains the time associated with the last
sample in each data update relative to the most recent edge
of the clock signal in the SYNC pin. For example, when the
value in the UP_SCALE register (see Table 103) represents a
scale factor of 20, DEC_RATE = 0, and the external SYNC rate
of 100 Hz results in the following time stamp sequence: 0 LSB,
10 LSB, 21 LSB, 31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, …,
194 LSB for the 20th sample, which translates to 0 μs, 490 μs, …,
9510 μs which is the time from the first SYNC edge.
Data Update Counter (DATA_CNTR)
Table 44. DATA_CNTR Register Definition
Addresses Default Access Flash Backup
0x22, 0x23 Not applicable R No
Table 45. DATA_CNTR Bit Definitions
Bits Description
[15:0] Data update counter, offset binary format
When the ADIS16470 goes through its power-on sequence or
when it recovers from a reset command, DATA_CNTR (see
Table 44 and Table 45) starts with a value of 0x0000 and
increments every time new data loads into the output registers.
When it reaches 0xFFFF, the next data update causes it to wrap
back around to 0x0000, where it continues to increment every
time new data loads into the output registers.
DELTA ANGLES
In addition to the angular rate of rotation (gyroscope)
measurements around each axis (x, y, and z), the ADIS16470 also
provides delta angle measurements that represent a computation of
angular displacement between each sample update.
15343-037
Δθ
Z
Δθ
Y
Y
Δθ
X
Z
X
PIN A8 PIN K1
Figure 36. Delta Angle Axis and Polarity Assignments
The delta angle outputs represent an integration of the gyroscope
measurements and use the following formula for all three axes
(x-axis displayed):
1
0
1,,
,2
1D
d
dDnxdDnx
S
Dnx f
where:
x is the x-axis.
n is the sample time, prior to the decimation filter.
D is the decimation rate = DEC_RATE + 1 (see Table 105).
fs is the sample rate.
d is the incremental variable in the summation formula.
ωX is the x-axis rate of rotation (gyroscope).
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 104), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency and multiply it by 2000. Each axis of
the delta angle measurements has two output data registers.
Figure 37 illustrates how these two registers combine to support
a 32-bit, twos complement data format for the x-axis delta angle
measurements. This format also applies to the y- and z-axes.
X-AXIS DELTA ANGLE DATA
01515 0
X_DELTANG_OUT X_DELTANG_LOW
15343-038
Figure 37. Delta Angle Output Data Structure
X-Axis Delta Angle (X_DELTANG_LOW and
X_DELTANG_OUT)
Table 46. X_DELTANG_LOW Register Definition
Addresses Default Access Flash Backup
0x24, 0x25 Not applicable R No
Table 47. X_DELTANG_LOW Bit Definitions
Bits Description
[15:0] X-axis delta angle data; additional resolution bits
Table 48. X_DELTANG_OUT Register Definition
Addresses Default Access Flash Backup
0x26, 0x27 Not applicable R No
ADIS16470 Data Sheet
Rev. C | Page 22 of 36
Table 49. X_DELTANG_OUT Bit Definitions
Bits Description
[15:0] X-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = 2160°/215
The X_DELTANG_LOW (see Table 46 and Table 47) and
X_DELTANG_OUT (see Table 48 and Table 49) registers
contain the delta angle data for the x-axis.
Y-Axis Delta Angle (Y_DELTANG_LOW and
Y_DELTANG_OUT)
Table 50. Y_DELTANG_LOW Register Definition
Addresses Default Access Flash Backup
0x28, 0x29 Not applicable R No
Table 51. Y_DELTANG_LOW Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; additional resolution bits
Table 52. Y_DELTANG_OUT Register Definition
Addresses Default Access Flash Backup
0x2A, 0x2B Not applicable R No
Table 53. Y_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = 2160°/215
The Y_DELTANG_LOW (see Table 50 and Table 51) and
Y_DELTANG_OUT (see Table 52 and Table 53) registers
contain the delta angle data for the y-axis.
Z-Axis Delta Angle (Z_DELTANG_LOW and
Z_DELTANG_OUT)
Table 54. Z_DELTANG_LOW Register Definition
Addresses Default Access Flash Backup
0x2C, 0x2D Not applicable R No
Table 55. Z_DELTANG_LOW Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; additional resolution bits
Table 56. Z_DELTANG_OUT Register Definition
Addresses Default Access Flash Backup
0x2E, 0x2F Not applicable R No
Table 57. Z_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = 2160°/215
The Z_DELTANG_LOW (see Table 54 and Table 55) and
Z_DELTANG_OUT (see Table 56 and Table 57) registers
contain the delta angle data for the z-axis.
Delta Angle Resolution
Table 58 and Table 59 offers various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 58. 16-Bit Delta Angle Data Format Examples
Delta Angle (°) Decimal Hex Binary
2160° × (215−1)/215 +32,767 0x7FFF 0111 1111 1111 1111
+2160°/214 +2 0x0002 0000 0000 0000 0010
+2160°/215 +1 0x0001 0000 0000 0000 0001
0 0 0x0000 0000 0000 0000 0000
−2160°/215 −1 0xFFFF 1111 1111 1111 1111
−2160°/214 −2 0xFFFE 1111 1111 1111 1110
−2160° −32,768 0x8000 1000 0000 0000 0000
Table 59. 32-Bit Delta Angle Data Format Examples
Delta Angle (°) Decimal Hex
+2160° × (231 − 1)/231 +2,147,483,647 0x7FFFFFFF
+2160°/230 +2 0x00000002
+2160°/231 +1 0x00000001
0 0 0x00000000
−2160°/231 −1 0xFFFFFFFF
−2160°/230 −2 0xFFFFFFFE
−2160° −2,147,483,648 0x80000000
DELTA VELOCITY
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16470 also provides delta velocity
measurements that represent a computation of linear velocity
change between each sample update.
Z
X
Y
PIN A8 PIN K1
ΔVZ
ΔVXΔVY
15343-039
Figure 38. Delta Velocity Axis and Polarity Assignments
The delta velocity outputs represent an integration of the
acceleration measurements and use the following formula for all
three axes (x-axis displayed):
1
0
1,,
,2
1D
d
dDnxdDnx
S
Dnx aa
f
V
where:
x is the x-axis.
n is the sample time, prior to the decimation filter.
D is the decimation rate = DEC_RATE + 1 (see Table 105).
fs is the sample rate.
d is the incremental variable in the summation formula.
aX is the x-axis acceleration.
Data Sheet ADIS16470
Rev. C | Page 23 of 36
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 104), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency and multiply it by 2000. Each axis of
the delta velocity measurements has two output data registers.
Figure 39 illustrates how these two registers combine to support
32-bit, twos complement data format for the delta velocity
measurements along the x-axis. This format also applies to the
y-axis and z-axis.
X-AXIS DELTA VELOCITY DATA
01515 0
X_ DELTVEL_OUT X_ DELTVEL_LOW
15343-040
Figure 39. Delta Angle Output Data Structure
X-Axis Delta Velocity (X_DELTVEL_LOW and
X_DELTVEL_OUT)
Table 60. X_DELTVEL_LOW Register Definition
Addresses Default Access Flash Backup
0x30, 0x31 Not applicable R No
Table 61. X_DELTVEL_LOW Bit Definitions
Bits Description
[15:0] X-axis delta velocity data; additional resolution bits
Table 62. X_DELTVEL_OUT Register Definition
Addresses Default Access Flash Backup
0x32, 0x33 Not applicable R No
Table 63. X_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] X-axis delta velocity data; twos complement,
±400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The X_DELTVEL_LOW (see Table 60 and Table 61) and
X_DELTVEL_OUT (see Table 62 and Table 63) registers
contain the delta velocity data for the x-axis.
Y-Axis Delta Velocity (Y_DELTVEL_LOW and
Y_DELTVEL_OUT)
Table 64. Y_DELTVEL_LOW Register Definition
Addresses Default Access Flash Backup
0x34, 0x35 Not applicable R No
Table 65. Y_DELTVEL_LOW Bit Definitions
Bits Description
[15:0] Y-axis delta velocity data; additional resolution bits
Table 66. Y_DELTVEL_OUT Register Definition
Addresses Default Access Flash Backup
0x36, 0x37 Not applicable R No
Table 67. Y_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta velocity data; twos complement,
±400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The Y_DELTVEL_LOW (see Table 64 and Table 65) and
Y_DELTVEL_OUT (see Table 66 and Table 67) registers
contain the delta velocity data for the y-axis.
Z-Axis Delta Velocity (Z_DELTVEL_LOW and
Z_DELTVEL_OUT)
Table 68. Z_DELTVEL_LOW Register Definition
Addresses Default Access Flash Backup
0x38, 0x39 Not applicable R No
Table 69. Z_DELTVEL_LOW Bit Definitions
Bits Description
[15:0] Z-axis delta velocity data; additional resolution bits
Table 70. Z_DELTVEL_OUT Register Definition
Addresses Default Access Flash Backup
0x3A, 0x3B Not applicable R No
Table 71. Z_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta velocity data; twos complement,
±400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The Z_DELTVEL_LOW (see Table 68 and Table 69) and
Z_DELTVEL_OUT (see Table 70 and Table 71) registers
contain the delta velocity data for the z-axis.
Delta Velocity Resolution
Table 72 and Table 73 offer various numerical examples that
demonstrate the format of the delta velocity data in both 16-bit
and 32-bit formats.
Table 72. 16-Bit Delta Velocity Data Format Examples
Velocity (m/sec) Decimal Hex Binary
+400 × (215 − 1)/215 +32,767 0x7FFF 0111 1111 1111 1111
+400/214 +2 0x0002 0000 0000 0000 0010
+400/215 +1 0x0001 0000 0000 0000 0001
0 0 0x0000 0000 0000 0000 0000
−400/215 −1 0xFFFF 1111 1111 1111 1111
−400/214 −2 0xFFFE 1111 1111 1111 1110
−400 −32,768 0x8000 1000 0000 0000 0000
Table 73. 32-Bit Delta Velocity Data Format Examples
Velocity (m/sec) Decimal Hex
+400 × (231 − 1)/231 +2,147,483,647 0x7FFFFFFF
+400/230 +2 0x00000002
+400/231 +1 0x00000001
0 0 0x00000000
−400/231 −1 0xFFFFFFFF
−400/230 −2 0xFFFFFFFE
−400 +2,147,483,648 0x80000000
ADIS16470 Data Sheet
Rev. C | Page 24 of 36
CALIBRATION
The signal chain of each inertial sensor (accelerometers and
gyroscopes) includes application of unique correction formulas,
which come from extensive characterization of bias, sensitivity,
alignment, response to linear acceleration (gyroscopes), and
point of percussion (accelerometer location) over a temperature
range of −10°C to +75°C, for every ADIS16470. These correction
formulas are not accessible, but users do have the opportunity
to adjust the bias for each sensor (individually) through user
accessible registers. These correction factors follow immediately
after the factory derived correction formulas in the signal chain,
which processes at a rate of 2000 Hz when using the internal
sample clock.
Calibration, Gyroscope Bias (XG_BIAS_LOW and
XG_BIAS_HIGH)
Table 74. XG_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x40, 0x41 0x0000 R/W Yes
Table 75. XG_BIAS_LOW Bit Definitions
Bits Description
[15:0] X-axis gyroscope offset correction; lower word
Table 76. XG_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x42, 0x43 0x0000 R/W Yes
Table 77. XG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] X-axis gyroscope offset correction factor, upper word
The XG_BIAS_LOW (see Table 74 and Table 75) and XG_BIAS_
HIGH (see Table 76 and Table 77) registers combine to allow
users to adjust the bias of the x-axis gyroscopes. The digital format
examples in Table 11 also apply to the XG_BIAS_HIGH register
and the digital format examples in Table 12 apply to the 32-bit
combination of the XG_BIAS_LOW and XG_BIAS_HIGH
registers. See Figure 40 for an illustration of how these two
registers combine and influence the x-axis gyroscope
measurements.
X-AXIS
GYRO
FACTORY
CALIBRATION
AND
FILTERING
X_GYRO_OUT X_GYRO_LOW
XG_BIAS_HIGH XG_BIAS_LOW
15343-041
Figure 40. User Calibration Signal Path, Gyroscopes
Calibration, Gyroscope Bias (YG_BIAS_LOW and
YG_BIAS_HIGH)
Table 78. YG_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x44, 0x45 0x0000 R/W Yes
Table 79. YG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction; lower word
Table 80. YG_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x46, 0x47 0x0000 R/W Yes
Table 81. YG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction factor, upper word
The YG_BIAS_LOW (see Table 78 and Table 79) and YG_BIAS_
HIGH (see Table 80 and Table 81) registers combine to allow
users to adjust the bias of the y-axis gyroscopes. The digital format
examples in Table 11 also apply to the YG_BIAS_HIGH register
and the digital format examples in Table 12 apply to the 32-bit
combination of the YG_BIAS_LOW and YG_BIAS_HIGH
registers. These registers influence the y-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 40).
Calibration, Gyroscope Bias (ZG_BIAS_LOW and
ZG_BIAS_HIGH)
Table 82. ZG_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x48, 0x49 0x0000 R/W Yes
Table 83. ZG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Z-axis gyroscope offset correction; lower word
Table 84. ZG_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x4A, 0x4B 0x0000 R/W Yes
Table 85. ZG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis gyroscope offset correction factor, upper word
Th e Z G_ BIA S_ LOW ( se e Tabl e 82 and Table 83) and ZG_BIAS_
HIGH (see Table 84 and Table 85) registers combine to allow
users to adjust the bias of the z-axis gyroscopes. The digital
format examples in Table 11 also apply to the ZG_BIAS_HIGH
register and the digital format examples in Table 12 apply to the
32-bit combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH
registers. These registers influence the z-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 40).
Calibration, Accelerometer Bias (XA_BIAS_LOW and
XA_BIAS_HIGH)
Table 86. XA_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x4C, 0x4D 0x0000 R/W Yes
Data Sheet ADIS16470
Rev. C | Page 25 of 36
Table 87. XA_BIAS_LOW Bit Definitions
Bits Description
[15:0] X-axis accelerometer offset correction; lower word
Table 88. XA_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x4E, 0x4F 0x0000 R/W Yes
Table 89. XA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] X-axis accelerometer offset correction, upper word
The XA_BIAS_LOW (see Table 86 and Table 87) and XA_BIAS_
HIGH (see Table 88 and Table 89) registers combine to allow
users to adjust the bias of the x-axis accelerometers. The digital
format examples in Table 25 also apply to the XA_BIAS_ HIGH
register and the digital format examples in Table 26 apply to the
32-bit combination of the XA_BIAS_LOW and XA_BIAS_HIGH
registers. See Figure 41 for an illustration of how these two registers
combine and influence the x-axis accelerometer measurements.
X-AXIS
ACCL
FACTORY
CALIBRATION
AND
FILTERING
X_ACCL_OUT X_ACCL_LOW
XA_BIAS_HIGH XA_BIAS_LOW
15343-042
Figure 41. User Calibration Signal Path, Accelerometers
Calibration, Accelerometer Bias (YA_BIAS_LOW and
YA_BIAS_HIGH)
Table 90. YA_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x50, 0x51 0x0000 R/W Yes
Table 91. YA_BIAS_LOW Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction; lower word
Table 92. YA_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x52, 0x53 0x0000 R/W Yes
Table 93. YA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction, upper word
The YA_BIAS_LOW (see Table 90 and Table 91) and
YA_BIAS_HIGH (see Table 92 and Table 93) registers combine
to allow users to adjust the bias of the y-axis accelerometers. The
digital format examples in Table 25 also apply to the
YA_BIAS_HIGH register, and the digital format examples in
Table 26 apply to the 32-bit combination of the YA_BIAS_LOW
and YA_BIAS_HIGH registers. These registers influence the y-
axis accelerometer measurements in the same manner that the
XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-
axis accelerometer measurements (see Figure 41).
Calibration, Accelerometer Bias (ZA_BIAS_LOW and
ZA_BIAS_HIGH)
Table 94. ZA_BIAS_LOW Register Definition
Addresses Default Access Flash Backup
0x54, 0x55 0x0000 R/W Yes
Table 95. ZA_BIAS_LOW Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction; lower word
Table 96. ZA_BIAS_HIGH Register Definition
Addresses Default Access Flash Backup
0x56, 0x57 0x0000 R/W Yes
Table 97. ZA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction, upper word
The ZA_BIAS_LOW (see Table 94 and Table 95) and ZA_BIAS_
HIGH (see Table 96 and Table 97) registers combine to allow
users to adjust the bias of the z-axis accelerometers. The digital
format examples in Table 25 also apply to the ZA_BIAS_HIGH
register and the digital format examples in Table 26 apply to the
32-bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH
registers. These registers influence the z-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW
and XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 41).
Filter Control Register (FILT_CTRL)
Table 98. FILT_CTRL Register Definition
Addresses Default Access Flash Backup
0x5C, 0x5D 0x0000 R/W Yes
Table 99. FILT_CTRL Bit Definitions
Bits Description
[15:3] Not used
[2:0] Filter Size Variable B
Number of taps in each stage; NB = 2B
The FILT_CTRL register (see Table 98 and Table 99) provides
user controls for the Bartlett window FIR filter (see Figure 18),
which contains two cascaded averaging filters. For example, use
the following sequence to set Register FILT_CTRL, Bits[2:0] =
100, which sets each stage to have 16 taps: 0xCC04, 0xCD00.
Figure 42 provides the frequency response for several settings in
the FILT_CTRL register.
ADIS16470 Data Sheet
Rev. C | Page 26 of 36
0
–20
–40
–60
–80
–100
–120
–140
0.001 0.01 0.1 1
MAGNITUDE (dB)
FREQUENCY (
f
/
f
SM
)
N = 2
N = 4
N = 16
N = 64
15343-043
Figure 42. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
Miscellaneous Control Register (MSC_CTRL)
Table 100. MSC_CTRL Register Definition
Addresses Default Access Flash Backup
0x60, 0x61 0x00C1 R/W Yes
Table 101. MSC_CTRL Bit Definitions
Bits Description
[15:8] Not used
7 Linear g compensation for gyroscopes (1 = enabled)
6 Point of percussion alignment (1 = enabled)
5 Not used, always set to zero
[4:2] SYNC function setting
111 = reserved (do not use)
110 = reserved (do not use)
101 = pulse sync mode
100 = reserved (do not use)
011 = output sync mode
010 = scaled sync mode
001 = direct sync mode
000 = internal clock mode (default)
1 SYNC polarity (input or output)
1 = rising edge triggers sampling
0 = falling edge triggers sampling
0 DR polarity
1 = active high when data is valid
0 = active low when data is valid
Point of Percussion
Register MSC_CTRL, Bit 6 (see Table 101) offers an on/off control
for the point of percussion alignment function, which maps the
accelerometer sensors to the corner of the package that is
closest to Pin A1 (see Figure 43). The factory default setting in
the MSC_CTRL register activates this function. To turn this
function off while retaining the rest of the factory default
settings in the MSC_CTRL register, set Register MSC_CTRL,
Bit 6 = 0, using the following command sequence on the DIN
pin: 0xE081, 0xE100.
PIN A8
POINT OF
PERCUSSION
PIN A1
15343-044
Figure 43. Point of Percussion Reference Point
Linear Acceleration Effect on Gyroscope Bias
Register MSC_CTRL, Bit 7 (see Table 101) provides an on/off
control for the linear g compensation in the signal calibration
routines of the gyroscope. The factory default contents in the
MSC_CTRL register enable this compensation. To turn it off,
set Register MSC_CTRL, Bit 7 = 0, using the following sequence
on the DIN pin: 0xE041, 0xEF00.
Internal Clock Mode
Register MSC_CTRL, Bits[4:2] (see Table 101), provide five
different configuration options for controlling the clock (fSM;
see Figure 15 and Figure 16), which controls data acquisition
and processing for the inertial sensors. The default setting for
Register MSC_CTRL, Bits[4:2] is 000 (binary), which places the
ADIS16470 in the internal clock mode. In this mode, an internal
clock controls inertial sensor data acquisition and processing at a
nominal rate of 2000 Hz. In this mode, each accelerometer data
update comes from an average of two data samples (sample rate
= 4000 Hz).
Output Sync Mode
When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16470
operates in output sync mode, which is the same as internal
clock mode with one exception, the SYNC pin pulses when
the internal processor collects data from the inertial sensors.
Figure 44 provides an example of this signal.
SYNC
250µs
500µs
15343-312
GYROSCOPE AND
ACCELEROMETER
DATA ACQUISITION
ACCELEROMETER
DATA ACQUISITION
Figure 44. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011
Direct Sync Mode
When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16470
operates in direct sync mode. The signal on the SYNC pin
directly controls the sample clock. In this mode, the internal
processor collects gyroscope data samples on the rising edge of
the clock signal (SYNC pin) and collects accelerometer data
samples on both rising and falling edges of the clock signal. The
internal processor averages both accelerometer samples (from
rising and falling edges of the clock signal) together to produce
a single data sample. Therefore, when operating the ADIS16470
in this mode, the clock signal (SYNC pin) must have a duty
cycle of 50% and a frequency that is within the range of 1900 Hz
to 2100 Hz. The ADIS16470 is capable of operating when the
Data Sheet ADIS16470
Rev. C | Page 27 of 36
clock frequency (SYNC pin) is less than 1900 Hz, but with risk
of performance degradation, especially when tracking dynamic
inertial conditions (including vibration).
Pulse Sync Mode
When operating in pulse sync mode (Register MSC_CTRL,
Bits[4:2] = 101), the internal processor only collects accelerometers
samples on the leading edge of the clock signal, which enables
use of a narrow pulse width (see Table 2) in the clock signal on
the SYNC pin. Using pulse sync mode also lowers the bandwidth
on the inertial sensors to 370 Hz. When operating in the pulse
sync mode, the ADIS16470 provides the best performance
when the frequency of the clock signal (SYNC pin) is within the
range of 1000 Hz to 2100 Hz. The ADIS16470 is capable of
operating when the clock frequency (SYNC pin) is less than
1000 Hz, but with risk of performance degradation, especially
when tracking dynamic inertial conditions (including
vibration).
Scaled Sync Mode
When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16470
operates in scaled sync mode that supports a frequency range of
1 Hz to 128 Hz for the clock signal on the SYNC pin. This mode
of operation is particularly useful when synchronizing the data
processing with a PPS signal from a global positioning system
(GPS) receiver or with a synchronization signal from a video
processing system. When operating in scaled sync mode, the
frequency of the sample clock is equal to the product of the
external clock scale factor, KECSF, (from the UP_SCALE register,
see Table 102 and Table 103) and the frequency of the clock
signal on the SYNC pin.
For example, when using a 1 Hz input signal, set UP_SCALE =
0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of
2000 SPS for the inertial sensors and their signal processing.
Use the following sequence on the DIN pin to configure
UP_SCALE for this scenario: 0xE2D0, 0xE307.
Table 102. UP_SCALE Register Definition
Addresses Default Access Flash Backup
0x62, 0x63 0x07D0 R/W Yes
Table 103. UP_SCALE Bit Definitions
Bits Description
[15:0] KECSF; binary format
Decimation Filter (DEC_RATE)
Table 104. DEC_RATE Register Definition
Addresses Default Access Flash Backup
0x64, 0x65 0x0000 R/W Yes
Table 105. DEC_RATE Bit Definitions
Bits Description
[15:11] Don’t care
[10:0] Decimation rate, binary format, maximum = 1999
The DEC_RATE register (see Table 104 and Table 105) provides
user control for the averaging decimating filter, which averages and
decimates the gyroscope and accelerometer data; it also extends
the time that the delta angle and the delta velocity track between
each update. When the ADIS16470 operates in internal clock
mode (see Register MSC_CTRL, Bits [4:2], in Table 101), the
nominal output data rate is equal to 2000/(DEC_RATE + 1).
For example, set DEC_RATE = 0x0013 to reduce the output
sample rate to 100 SPS (2000 ÷ 20), using the following the
DIN pin sequence: 0xE413, 0xE500.
Data Update Rate in External Sync Modes
When using the input sync option, in scaled sync mode
(Register MSC_CTRL, Bits[4:2] = 010, see Table 101), the
output data rate is equal to (fSYNC × KECSF)/(DEC_RATE + 1),
where fSYNC represents the frequency of the clock signal on the
SYNC pin, and KESCF represents the value from the UP_SCALE
register (see Table 103). When using direct sync mode and
pulse sync mode, KESCF equals 1.
Continuous Bias Estimation (NULL_CNFG)
Table 106. NULL_CNFG Register Definition
Addresses Default Access Flash Backup
0x66, 0x67 0x070A R/W Yes
Table 107. NULL_CNFG Bit Definitions
Bits Description
[15:14] Not used
13 Z-axis accelerometer bias correction enable (1 = enabled)
12 Y-axis accelerometer bias correction enable (1 = enabled)
11 X-axis accelerometer bias correction enable (1 = enabled)
10 Z-axis gyroscope bias correction enable (1 = enabled)
9 Y-axis gyroscope bias correction enable (1 = enabled)
8 X-axis gyroscope bias correction enable (1 = enabled)
[7:4] Not used
[3:0] Time base control (TBC), range: 0 to 12 (default = 10);
tB = 2TBC/2000, time base; tA = 64 × tB, average time
The NULL_CNFG register (see Table 106 and Table 107)
provides the configuration controls for the continuous bias
estimator (CBE), which associates with the bias correction
update command in Register GLOB_CMD, Bit 0 (see Table 109).
Register NULL_ CNFG, Bits[3:0] establishes the total average
time (tA) for the bias estimates and Register NULL_CNFG,
Bits[13:8] provide on/off controls for each sensor. The factory
default configuration for the NULL_CNFG register enables the
bias null command for the gyroscopes, disables the bias null
command for the accelerometers, and sets the average time
to ~32 sec.
ADIS16470 Data Sheet
Rev. C | Page 28 of 36
Global Commands (GLOB_CMD)
Table 108. GLOB_CMD Register Definition
Addresses Default Access Flash Backup
0x68, 0x69 Not applicable W No
Table 109. GLOB_CMD Bit Definitions
Bits Description
[15:8] Not used
7 Software reset
[6:5] Not used
4 Flash memory test
3 Flash memory update
2 Sensor self test
1 Factory calibration restore
0 Bias correction update
The GLOB_CMD register (see Table 108 and Table 109)
provides trigger bits for several operations. Write a 1 to the
appropriate bit in GLOB_CMD to start a particular function.
During the execution of these commands, data production
stops, pulsing stops on the DR pin, and the SPI interface does
not respond to requests. Table 1 provides the execution time for
each GLOB_CMD command.
Software Reset
Use the following DIN sequence to set Register GLOB_CMD,
Bit 7 = 1, which triggers a reset: 0xE880, 0xE900. This reset
clears all data, and then restarts data sampling and processing.
This function provides a firmware alternative to toggling the
RST pin (see Table 5, Pin F3).
Flash Memory Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 4 = 1, which tests the flash memory: 0xE810, 0xE900. The
command performs a CRC computation on the flash memory
(excluding user register locations) and compares it with the
original CRC value, which comes from the factory configuration
process. If the current CRC value does not match the original
CRC value, Register DIAG_STAT, Bit 6 (see Table 10) rises to 1,
indicating a failing result.
Flash Memory Update
Use the following DIN sequence to set Register GLOB_CMD,
Bit 3 = 1, which triggers a back up of all user configurable registers
in the flash memory: 0xE808, 0xE900. Register DIAG_STAT,
Bit 2 (see Table 10) identifies success (0) or failure (1) in
completing this process.
Sensor Self Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 2 = 1, which triggers the self test routine for the inertial sensors:
0xE804 and 0xE900. The self test routine uses the following steps
to validate the integrity of each inertial sensor:
1. Measure the output on each sensor.
2. Activate an internal stimulus on the mechanical elements of
each sensor to move them in a predictable manner and
create an observable response in the sensors.
3. Measure the output response on each sensor.
4. Deactivate the internal stimulus on each sensor.
5. Calculate the difference between the sensor measurements
from Step 1 (stimulus is off) and from Step 3 (stimulus is on).
6. Compare the difference with internal pass and fail criteria.
7. Report the pass and fail result to Register DIAG_STAT, Bit 5
(see Table 10).
Motion, during the execution of this test, can indicate a false
failure.
Factory Calibration Restore
Use the following DIN sequence to set Register GLOB_CMD,
Bit 1 = 1 to restore the factory default settings for the
MSC_CTRL, DEC_RATE, and FILT_CTRL registers and to
clear all user configurable bias correction settings: 0xE802,
0xE900. Executing this command results in writing 0x0000 to
the following registers: XG_BIAS_LOW, XG_BIAS_HIGH,
YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_
HIGH, XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW,
YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH.
Bias Correction Update
Use the following DIN pin sequence to set Register GLOB_CMD,
Bit 0 = 1 to trigger a bias correction, using the correction factors
from the CBE (see Table 107): 0xE801, 0xE900.
Firmware Revision (FIRM_REV)
Table 110. FIRM_REV Register Definition
Addresses Default Access Flash Backup
0x6C, 0x6D Not applicable R Yes
Table 111. FIRM_REV Bit Definitions
Bits Description
[15:0] Firmware revision, binary coded decimal (BCD) format
The FIRM_REV register (see Table 110 and Table 111) provides
the firmware revision for the internal firmware. This register
uses a BCD format, where each nibble represents a digit. For
example, if FIRM_REV = 0x0104, the firmware revision is 1.04.
Firmware Revision Day and Month (FIRM_DM)
Table 112. FIRM_DM Register Definition
Addresses Default Access Flash Backup
0x6E, 0x6F Not applicable R Yes
Table 113. FIRM_DM Bit Definitions
Bits Description
[15:8] Factory configuration month, BCD format
[7:0] Factory configuration day, BCD format
The FIRM_DM register (see Table 112 and Table 113)
contains the month and day of the factory configuration date.
Register FIRM_DM, Bits[15:8] contains digits that represent the
Data Sheet ADIS16470
Rev. C | Page 29 of 36
month of the factory configuration. For example, November is the
11th month in a year and is represented by Register FIRM_DM,
Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0] contains the
day of factory configuration. For example, the 27th day of the
month is represented by Register FIRM_DM, Bits[7:0] = 0x27.
Firmware Revision Year (FIRM_Y)
Table 114. FIRM_Y Register Definition
Addresses Default Access Flash Backup
0x70, 0x71 Not applicable R Yes
Table 115. FIRM_Y Bit Definitions
Bits Description
[15:0] Factory configuration year, BCD format
The FIRM_Y register (see Table 114 and Table 115) contains the
year of the factory configuration date. For example, the year,
2017, is represented by FIRM_Y = 0x2017.
Product Identification (PROD_ID)
Table 116. PROD_ID Register Definition
Addresses Default Access Flash Backup
0x72, 0x73 0x4056 R No
Table 117. PROD_ID Bit Definitions
Bits Description
[15:0] Product identification = 0x4056
The PROD_ID register (see Table 116 and Table 117) contains
the numerical portion of the device number (16,470). See Figure 28
for an example of how to use a looping read of this register to
validate the integrity of the communication.
Serial Number (SERIAL_NUM)
Table 118. SERIAL_NUM Register Definition
Addresses Default Access Flash Backup
0x74, 0x75 Not applicable R Yes
Table 119. SERIAL_NUM Bit Definitions
Bits Description
[15:0] Lot specific serial number
Scratch Registers (USER_SCR_1 to USER_SER_3)
Table 120. USER_SCR_1 Register Definition
Addresses Default Access Flash Backup
0x76, 0x77 Not applicable R/W Yes
Table 121. USER_SCR_1 Bit Definitions
Bits Description
[15:0] User defined
Table 122. USER_SCR_2 Register Definition
Addresses Default Access Flash Backup
0x78, 0x79 Not applicable R/W Yes
Table 123. USER_SCR_2 Bit Definitions
Bits Description
[15:0] User defined
Table 124. USER_SCR_3 Register Definition
Addresses Default Access Flash Backup
0x7A, 0x7B Not applicable R/W Yes
Table 125. USER_SCR_3 Bit Definitions
Bits Description
[15:0] User defined
The USER_SCR_1 (see Table 120 and Table 121), USER_SCR_2
(see Table 122 and Table 123), and USER_SCR_3 (see Table 124
and Table 125) registers provide three locations for users to
store information. For nonvolatile storage, use the manual flash
memory update command (Register GLOB_CMD, Bit 3, see
Table 109), after writing information to these registers.
ADIS16470 Data Sheet
Rev. C | Page 30 of 36
Flash Memory Endurance Counter (FLSHCNT_LOW and
FLSHCNT_HIGH)
Table 126. FLSHCNT_LOW Register Definition
Addresses Default Access Flash Backup
0x7C, 0x7D Not applicable R Yes
Table 127. FLSHCNT_LOW Bit Definitions
Bits Description
[15:0] Flash memory write counter, low word
Table 128. FLSHCNT_HIGH Register Definition
Addresses Default Access Flash Backup
0x7E, 0x7F Not applicable R Yes
Table 129. FLSHCNT_HIGH Bit Definitions
Bits Description
[15:0] Flash memory write counter, high word
The FLSHCNT_LOW (see Table 126 and Table 127) and
FLSHCNT_HIGH (see Table 128 and Table 129) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the
number of write cycles, the flash memory has a finite service
lifetime, which depends on the junction temperature. Figure 45
provides guidance for estimating the retention life for the flash
memory at specific junction temperatures. The junction
temperature is approximately 7°C above the case temperature.
600
450
300
150
030 40
RETENTION (Years)
JUNCTION TEMPERATURE (°C)
55 70 85 100 125 135 150
15343-045
Figure 45. Flash Memory Retention
Data Sheet ADIS16470
Rev. C | Page 31 of 36
APPLICATIONS INFORMATION
ASSEMBLY AND HANDLING TIPS
Package Attributes
The ADIS16470 is a multichip module package that has a
44-ball BGA interface. This package has three basic attributes
that influence its handling and assembly to the PCB of the
system: the lid, the substrate, and the BGA pattern. The
material of the lid is a liquid crystal polymer (LCP), and
its nominal thickness is 0.5 mm. The substrate is a laminate
composition that has a nominal thickness of 1.57 mm. The
solder ball material is SAC305, and each ball has a nominal
diameter of 0.75 mm (±0.15 mm). The BGA pattern follows an
8 × 10 array, with 36 unpopulated positions, which simplifies
the escape pattern for the power, ground, and signal traces on
the system PCB.
Assembly Tips
When developing a process to attach the ADIS16470 to a PCB,
consider the following tips and insights:
The ADIS16470 packaging has passed numerous qualification
tests that have exposed it to solder reflow profiles and are
compliant with J-STD-020E, having a peak temperature
of 260°C.
Limit device exposure to one pass through the solder
reflow process (no rework).
The hole in the top of the lid (see Figure 46) provides
venting and pressure relief during the assembly process of
the ADIS16470. Keep this hole clear of obstruction while
attaching the ADIS16470 to a PCB.
OPENING IN
PACKAGE LID
15343-046
Figure 46. Pressure Relief Hole
Use no clean flux to avoid exposing the device to cleaning
solvents, which can penetrate the inside of the ADIS16470
through the hole in the lid and be difficult to remove.
When the assembly process requires the use of liquids that
can reach the hole in the lid, use a temporary seal to
prevent entrapment of those liquids inside of the cavity.
Manage moisture exposure prior to the solder reflow
processing, in accordance with J-STD-033, MSL5.
Avoid exposing the ADIS16470 to mechanical shock
survivability that exceeds the maximum rating of 2000 g
(see Table 3). In standard PCB processing, high speed
handling equipment and panel separation processes often
present the most risk of introducing harmful levels of
mechanical shock survivability.
PCB Layout Suggestions
Figure 47 provides an example of the pad design and layout for
the ADIS16470 on a PCB. This example uses a solder mask
opening, with a diameter of 0.73 mm, around a metal pad that
has a diameter of 0.56 mm. When using a material for the system
PCB, which has similar thermal expansion properties as the
substrate material of the ADIS16470, the system PCB can also
use the solder mask to define the pads that support attachment
to the balls of the ADIS16470. The coefficient of thermal
expansion (CTE) in the substrate of the ADIS16470 is
approximately 14 ppm/°C.
ALL DIMENSIONS IN MILLIMETERS
1.27
1.27
0.73
(MASK OPENING)
0.56
(COPPER PAD)
15343-047
Figure 47. Recommend PCB Pattern, Solder Mask Defined Pads
Underfill
Underfill can be a useful technique in managing certain threats
to the integrity of the solder joints of the ADIS16470, including
peeling stress and extended exposure to vibration. When selecting
underfill material and developing an application and curing
process, ensure that the material fills the gap between each
surface (ADIS16470 substrate and system PCB) and adheres
to both surfaces. The ADIS16470 does not require the use of
underfill materials in applications that do not anticipate
exposure to these types of mechanical stresses and when the
CTE of the system PCB is close to the same value as the CTE
of the substrate of the ADIS16470 (~14 ppm/°C).
Process Validation and Control
These tips and guidelines provide a starting point for
developing a process for attaching the ADIS16470 to a system
PCB. Because each system and situation may present unique
requirements for this attachment process, ensure that the
process supports optimal solder joint integrity, verify that the
final system meets all environmental test requirements, and
establish observation and control strategies for all key process
attributes (peak temperatures, dwell times, ramp rates, and so on).
ADIS16470 Data Sheet
Rev. C | Page 32 of 36
POWER SUPPLY CONSIDERATIONS
The ADIS16470 contains 6 μF of decoupling capacitance across
its VDD and GND pins. When the VDD voltage raises from 0 V
to 3.3 V, the charging current for this capacitor bank imposes
the following current profile (in amperes):
dt
tdVDD
dt
dVDD
CtIDD 6
106
where:
IDD(t)is the current demand on the VDD pin during the initial
power supply ramp, with respect to time.
C is the internal capacitance across the VDD and GND pins (6 μF).
VDD(t) is the voltage on the VDD pin, with respect to time.
For example, if VDD follows a linear ramp from 0 V to 3.3 V, in
66 μs, the charging current is 300 mA for that timeframe. The
ADIS16470 also contains embedded processing functions that
present transient current demands during initialization or reset
recovery operations. During these processes, the peak current
demand reaches 250 mA and occurs at a time that is approximately
40 ms after VDD reaches 3.0 V (or ~40 ms after initiating a
reset sequence).
SERIAL PORT OPERATION
Maximum Throughput
When operating with the maximum output data (DEC_RATE =
0x0000, as described in Table 105), the maximum SCLK rate
(defined in Table 2) and minimum stall time, the SPI port can
support up to 12, 16-bit register reads in between each pulse of
the data ready signal. Attempting to read more than 12 registers
can result in a datapath overrun error in the DIAG_STAT
register (see Table 10). The serial port stall time (tSTALL) to meet
these requirements must be no more than 10% greater than the
minimum specification for tSTALL shown in Table 2.
The number of allowable registers reads between each pulse on
the data ready line increases proportionally with the decimation
rate (set by the DEC_RATE register, see Table 105). For example,
when the decimation rate equals 3 (DEC_RATE = 0x0002), the
SPI is able to support up to 36 register reads, assuming
maximum SCLK rate and minimum stall times in the protocol.
Decreasing the SCLK rate and increasing the stall time lowers
the total number of register reads supported by the ADIS16470
before a datapath overrun error occurs.
This limitation of reading 12, 16-bit registers does not impact
the ability of the user to access the full precision of the
gyroscopes and accelerometers if the factory default settings of
DEC_RATE = 0x0000 and FILT_CTRL = 0x0000 are used. In
this case, the data width for the gyroscope and accelerometer
data is 16 bits, and application processors can acquire all relevant
information through the X_GYRO_OUT, Y_GYRO_OUT,
Z_GYRO_OUT, X_ACCEL_OUT, Y_ACCEL_OUT, and
Z_ACCEL_OUT registers. Thirty-two bit reads of the sensor
data do not provide additional precision in this case. See the
Gyroscope Data Width (Digital Resolution) section and the
Accelerometer Data Width (Digital Resolution) section for
more information.
Serial Port SCLK Underrun/Overrun Conditions
The serial port operates in 16-bit segments, and it is critical that
the number of SCLK cycles be equal to an integer multiple of 16
when the CS pin is low. Failure to meet this condition causes the
serial port controller inside of the ADIS16470 to be unable to
correctly receive and respond to new requests.
If too many SCLK cycles are received before the CS pin is
deasserted, the user can recover serial operation by asserting CS,
providing 17 rising edges on the SCLK line, deasserting CS, and
then attempting to correctly read the PROD_ID (or other read-
only) register on the ADIS16470. The user should repeat these
steps up to a maximum of 15 times until the correct data is read.
If CS is deasserted before enough SCLK cycles are received, the
user must either power cycle or issue a hard reset (using the
RST pin) to regain SPI port access.
DIGITAL RESOLUTION OF GYROSCOPES AND
ACCELEROMETERS
Gyroscope Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 105) and
Bartlett window filter (FILT_CTRL register, see Table 99) have
direct influence over the total number of bits in the output data
registers, which contain relevant information. When using the
factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the gyroscope data width is 16 bits,
which means that application processors can acquire all relevant
information through the X_GYRO_OUT, Y_GYRO_OUT, and
Z_GYRO_OUT registers.
The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_LOW
registers capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the data width increases by one bit
every time the number of summations (in a filter stage)
increases by a factor of two. For example, when DEC_RATE =
0x0007, the decimation filter adds eight (7 + 1 = 8, see Table 105)
successive samples together, which causes the data width to
increase by 3 bits (log28 = 3). When FILT_CTRL = 0x0002, both
stages in the Bartlett window filter use four (22 = 4, see
Table 99) summation operations, which increases the data
width by 2 bits (log24 = 2). When using both DEC_RATE =
0x0007 and FILT_CTRL = 0x0002, the total bit growth is 7 bits,
which increases the overall data width to 23 bits.
Accelerometer Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 105) and
Bartlett window filter (FILT_CTRL register, see Table 99) have
direct influence over the total number of bits in the output data
registers, which contain relevant information. When using the
factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the accelerometer data width is 20 bits.
Data Sheet ADIS16470
Rev. C | Page 33 of 36
The X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_OUT
registers contain the most significant 16 bits of this data, while
the remaining (least significant) bits are in the upper 4 bits of
the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers. Since the total noise (0.6 mg rms, see Table 1) in the
accelerometer data (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) is greater than the 16-bit quantization noise (0.25 mg ÷
120.5 = 0.072 mg), application processors can acquire all relevant
information through the X_ACCL_OUT, Y_ACCL_OUT, and
Z_ACCL_OUT registers. This enables applications to preserve
optimal performance, while using the burst read (see Figure 27),
which only provides 16-bit data for the accelerometers.
The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers also capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the data width increases by one bit
every time the number of summations (in a filter stage)
increases by a factor of two. For example, when DEC_RATE =
0x0001, the decimation filter adds two (1 + 1 = 2, see Table 105)
successive samples together, which causes the data width to
increase by 1 bit (log22 = 1). When FILT_CTRL = 0x0001, both
stages in the Bartlett window filter add two (21 = 2, see Table 99)
successive samples together, which increases the data width by 1
bit (log22 = 1) as well. When using both DEC_RATE = 0x0001
and FILT_CTRL = 0x0001, the total bit growth is 3 bits, which
increases the overall data width to 23 bits.
EVALUATION TOOLS
Breakout Board
The ADIS16470/PCBZ is a breakout board that provides a
simple way to develop a prototype connection between the
ADIS16470 and an existing embedded processor platform.
This breakout board already contains an ADIS16470AMLZ and
a dual row, 2 mm pitch, 16-pin header (J1). Table 130 provides
the J1 pin assignments, which support direction connection
with an embedded processor board, using standard ribbon
cables. As a general guideline, the ADIS16470/PCBZ supports
reliable communications over ribbon cables that are up to 20 cm
in length. Local electromagnetic interference (EMI) conditions
can influence signal integrity, which may require some signal
level observation with an oscilloscope, to assure reliable
communications.
Table 130. J1 Pin Assignments, Breakout Board
J1 Pin Number Signal Function
1 RST Reset
2 SCLK SPI
3 CS SPI
4 DOUT SPI
5 NC Not connect
6 DIN SPI
7 GND Ground
8 GND Ground
9 GND Ground
10 VDD Power, 3.3 V
11 VDD Power, 3.3 V
12 VDD Power, 3.3 V
13 DR Data ready
14 SYNC Input clock
15 NC Not connect
16 NC Not connect
Figure 48 provides a top level view of the breakout board, including
dimensional locations for all the key mechanical features, such
as the mounting holes and the 16-pin header. Figure 49 provides
an electrical schematic for this breakout board.
15343-313
ADIS1647X/PCB
BREAKOUT BOARD
08-045113rA
J1
TFD2
ML/BEL 11/14/16 TFD1
*
5.125mm
5.125mm
3.625mm
6.03mm
33.25mm
16.99mm
16.26mm
30.07mm
Figure 48. Top Level View of the Breakout Board
ADIS16470 Data Sheet
Rev. C | Page 34 of 36
VDD
VDD
VDD
C7
D6
H1
K6
J5
J4
VDD
VDD
ADIS16470AMLZ
DUT1
VDD
VDD
DNCGNDGND
GND SCLK SCLK
GND
RST VDD VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
A2
A3
A4
A5
A6
A7
A8
B3
B4
B5
B6
J6
J3
H3
H6
E3
C3
G3
G6
F6
F3
D3
K8
K3
K1
J7
J2
H8
G7
G2
F8
F1
E7
E6
E2
C6
C2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DIN DOUT DOUTDIN
CS DR DR
SYNC SYNC
CS
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VDD J1
SCLK
DOUT
CS
DIN
GND
DR
DNC
GND
VDD
SYNC
RST
HIROSE
A3-16-PA-2SV(71)
15343-050
Figure 49. Breakout Board Schematic
PC-Based Evaluation, EVAL-ADIS2
In addition to supporting quick prototype connections between
the ADIS16470 and an embedded processing system, J1 on the
ADIS16470/PCBZ also connects directly to J1 on the EVAL-
ADIS2 evaluation system. When used in conjunction with the
IMU Evaluation Software for the EVAL-ADISX Platforms, the
EVAL-ADIS2 provides a simple, functional test platform that
provides users with configuration control and the ability to
collect data from the output data registers of the ADIS16470.
Data Sheet ADIS16470
Rev. C | Page 35 of 36
TRAY DRAWING
The ADIS16470 parts are shipped in the tray shown in Figure 50.
15343-100
NOTES:
1. MATERIAL IS MPPO.
2.
TOLERANCES ARE
x.x =
± 0.25
x.xx
= ± 0.13
UNLESS OTHE RWISE SPECITIED.
3. ESD
–
SURFACE RESISTIVIT Y
10
5
TO 10
11
Ω/SQ.
322.60 REF
11.95 BSC
22.00 BSC
16.00
BSC
315.00
255.30
2.54
34.30 25.40
17.90
21.40
135.90
92.10
12.70
112.25
112.00
111.75
272.05
271.80
271.55
TOP VIEW
SIDE VIEW
14.50 BSC
DETAIL A
DETAIL A
A
A
B
B
7.90
11.10
SECTION A-A
15.43
15.35
15.27
SECTION B-B
11.43
11.35
11.27
DETAIL B
DETAIL C
DETAIL C
DETAIL B
30°
±
1°
3.50
2.00
1.30
2.50 3.80
0.76
R 4.75
C 3.00 × 0.45°
Figure 50. Drawing of Shipping Tray
ADIS16470 Data Sheet
Rev. C | Page 36 of 36
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
06-22-2017-B
PKG-005267
A1 BALL
CORNER INDICATOR
*Including Lable
Thickness
SEATING
PLANE
TOP VIEW
END VIEW
BOTTOM VIEW
11.25
11.00
10.75
15.25
15.00
14.75
11.350
11.000
*10.475
1.055
BSC
1.785
BSC
1.270
BSC
1.270
BSC
0.900
Ø0.750
0.600
0.90
MAX
Figure 51. 44-Ball Ball Grid Array Module [BGA]
(ML-44-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Description Package Option
ADIS16470AMLZ −25°C to +85°C 44-Ball Ball Grid Array Module [BGA] ML-44-1
ADIS16470/PCBZ Breakout Board (Evaluation Board)
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15343-0-4/19(C) www.analog.com/ADIS16470
