HY5DU281622FLTP-D4 - SK Hynix - Datasheet.Directory

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.04 /Jul. 2006 1

128Mb DDR SDRAM

HY5DU281622FTP

Rev. 0.04 /Jul. 2006 2

HY5DU281622FT(P) Series

Revision History

Revision No. History Draft Date Remark

0.01 First version for internal review Feb. 2006

0.02 State Diagram modified Apr. 2006

0.03 Defined : IDD value Apr. 2006

0.04 Insert : 250MHz CL4 Product Apr. 2006

Rev. 0.04 /Jul. 2006 3

HY5DU281622FT(P) Series

DESCRIPTION

The HY5DU281622FT(P) is a 134,217,7 28-bi t CMOS Double D ata R ate (D DR) Synchronous D RAM, ideally su ited for the

main memory applications which requires large memory density and high bandwidth.

This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and contro l inputs ar e latched on th e rising edges of the CK (falling edg es of the /CK), Data,

Data strobes and W rite data mas ks inputs ar e samp led on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All inp ut and ou tput v o lta ge levels are compatible

with SSTL_2.

FEATURES

•VDD, VDDQ = 2.3V min ~ 2.7V max

(Typical 2.5V Operation +/- 0.2V for DDR266, 333)

•V

DD, VDDQ = 2.4V min ~ 2.7V max

(Typical 2.6V Operation +0.1/- 0.2V for DDR400,

400Mbps/pin product and 500Mbps/pin product )

• All inputs and outputs are compatible with SSTL_2

interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous - data transaction aligned to

bidirectional data strobe (DQS)

• x16 device has two bytewide data strobes (UDQS,

LDQS) per each x8 I/O

• Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

• On chip DLL align DQ and DQS transition with CK

transition

• DM mask write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges

of the clock

• Programmable CAS latency 2/2.5 (DDR266, 333)

and 3/4 (DDR400, 400Mbps/pin product and

500Mbps/pin product) supported

• Programmable burst length 2/4/8 with both sequen-

tial and interleave mode

• Internal four bank operations with single pulsed

/RAS

• Auto refresh and self refresh supported

•t

RAS

lock out function supported

• 4096 refresh cycles/64ms

• JEDEC standard 400mil 66pin TSOP-II with 0.65mm

pin pitch

• Lead free (*ROHS Compliant)

ORDERING INFORMATION

* X means speed grade

** Lead-free product

Part No. Configuration Package

HY5DU281622F(L)TP-X* 8Mx16 400mil

66pin

TSOP-II**

OPERATING FREQUENCY

Grade Clock Rate Remark

-4 250MHz@CL4 500Mbps/pin (maxi-

mum Date rate)

-5 200MHz@CL3 400Mbps/pin (maxi-

mum Date rate)

-D43 200MHz@CL3 DDR400B (3-3-3)

-D4 200MHz@CL3 DDR400 (3-4-4)

- J 133MHz@CL2 166MHz @CL2.5

& @CL3 DDR333 (2.5-3-3)

DDR333 (3-3-3)

- K 133MHz@CL2 133MHz@CL2.5 DDR266A (2-3-3)

- H 100MHz@CL2 133MHz@CL2.5 DDR266B (2.5-3-3)

*ROHS (Restriction Of Hazardous Substances)

Rev. 0.04 /Jul. 2006 4

HY5DU281622FT(P) Series

PIN CONFIGURATION

ROW AND COLUMN ADDRESS INFORMATION

• Organization : 2M x 16 x 4banks

• Row Address : A0 - A11

• Column Address : A0 - A8

• Bank Address : BA0, BA1

• Auto Precharge Flag : A10

• Refresh : 4K

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

400m il x 875m il

66pin TSOP-II

0.65m m pin pitch

V

DD

DQ0

V

DDQ

DQ1

DQ2

V

SSQ

DQ3

DQ4

V

DDQ

DQ5

DQ6

V

SSQ

DQ7

NC

V

DDQ

LDQS

NC

V

DD

NC

LDM

/WE

/CAS

/RAS

/CS

NC

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

V

SS

DQ15

V

SSQ

DQ14

DQ13

V

DDQ

DQ12

DQ11

V

SSQ

DQ10

DQ9

V

DDQ

DQ8

NC

V

SSQ

UDQS

NC

VREF

V

SS

UDM

/CK

CK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

V

SS

Rev. 0.04 /Jul. 2006 5

HY5DU281622FT(P) Series

PIN DESCRIPTION

PIN TYPE DESCRIPTION

CK, /CK Input Clock: CK and /CK are diff erential clock inputs. All address and control input signa ls are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivate s internal clock signals, and

device input buf fers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for

SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output dis-

able. CKE must be maintained high throughout READ and WRITE accesses. Input buff-

ers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers,

excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will

detect an LVCMOS LOW level after V

DD

is applied.

/CS Input

Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when Chip Select is registered high. Chip Select provides for exter-

nal bank selection on systems with multiple banks. Chip Select is considered part of the

command code.

BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or

PRECHARGE command is being applied.

A0 ~ A11 Input

Address Inputs: Provide the row address for ACTIVE commands, and the column

address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 is sampled during a precharge

command to determine whether the PRECHARGE applies to one bank (A10 L OW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,

BA1. The address inputs also provide the op code during a MODE REGISTER SET com-

mand. BA0 and BA1 define which mode register is loaded during the MODE REGISTER

SET command (MRS or EMRS).

/RAS, /CAS, /

WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

DM

(LDM,UDM) Input

Input Data Mask: DM is an input mask signal f or write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM cor-

responds to the data on DQ8-Q15.

DQS

(LDQS,UDQS) I/O Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. For the x16, LDQS corresponds to

the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.

DQ I/O Data input / output pin: Data bus

V

DD

/ V

SS

Supply Power supply for internal circuits and input buffers.

V

DDQ

/ V

SSQ

Supply Power supply for output buffers for noise immunity.

V

REF

Supply Reference voltage for inputs for SSTL interface.

NC NC No connection.

Rev. 0.04 /Jul. 2006 6

HY5DU281622FT(P) Series

Functinal Block Diagram (8M x16)

4Banks x 2Mbit x 16I/O Double Data Rate Syncronous DRAM

Sense AMPSense AMP

Sense AMP

Mode

Register

Command

Decoder

CLK

/CLK

CKE

/CS

/RAS

/CAS

/WE

LDM

UDM

Bank

Control

Mode

Register Row

Decoder

2Mx16 BANK 0

2Mx16 BANK 1

2Mx16 BANK 2

2Mx16 BANK 3

Memory

Cell

Array

Sense AMP

Column

Decoder

Address

Buffer

A0

A1

A

max

BA0

BA1

Column Address

Decoder

16

Output Buffer

DQ0

DQ15

Input Buffer

DS

32

2-bit Prefetch Unit

Write Data Register

2-bit Prefetch Unit 16

32

Data Strobe

Transmitter

Data Strobe

Receiver

LDQS,

UDQS

LDQS,

UDQS

DLL

Block

CLK,

/CLK

CLK_DLL

Mode

Register

Rev. 0.04 /Jul. 2006 7

HY5DU281622FT(P) Series

SIMPLIFIED COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE ADDR A10

/AP BA Note

Extended Mode Register

Set H XLLLL OP code 1,2

Mode Register Set H XLLLL OP code 1,2

Device Deselect HX

HXXX X1

No Operation LHHH

Bank Active H X L L H H RA V 1

Read H X LHLHCALV1

Read with Autoprecharge H 1,3

Write HXLHLLCA

LV1

Write with Autoprecharge H 1,4

Precharge All Banks HXLLHLX

HX1,5

Precharge selected Bank LV1

Read Burst Stop H X L H H L X 1

Auto Refresh H HLLLH X 1

Self Refresh

EntryH LLLLH

X

1

Exit L H HXXX 1

LHHH

Precharge

Power Down

Mode

Entry H L HXXX

X

1

LHHH 1

Exit L H HXXX 1

LHHH 1

Active Power

Down Mode Entry H L HXXX

X

1

LVVV 1

Exit L H X 1

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=V alid Data Input, OP Code=Operand Code, NOP=No Operation )

Rev. 0.04 /Jul. 2006 8

HY5DU281622FT(P) Series

WRITE MASK TRUTH TABLE

Function CKEn-1 CKEn /CS, /RAS,

/CAS, /WE DM ADD

RA10/

AP BA Note

Data Write H X X L X 1,2

Data-In Mask H X X H X 1,2

Note :

1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is no t related with read data.

In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.

2. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of

VIHmin ~ VILmax

Note :

1. UDM, LDM states are Don’t Care. Refer to below Write Mask Tru th Ta b le.(note 6)

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before

entering Mode R egi ster Set mode, a ll banks must be in a pr echarg e state and MR S co mmand can be i ssued aft er tRP peri od fr om

Prechagre command.

3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented

to activate bank until CK(n+BL/2+tRP).

4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented

to activate bank until CK(n+BL/2+1+tDPL+t RP). Last Data-In to Prechage delay(tDPL) which is also ca lled Write Recovery

Time(tWR) is neede d to guarantee that the last data have been comp letely written.

5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.

6. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of

VIHmin ~ VILmax

Rev. 0.04 /Jul. 2006 9

HY5DU281622FT(P) Series

SIMPLIFIED STATE DIAGRAM

MRS SREF

SREX

PDEN

PDEX

ACT

AREF

PDEX

PDEN

BST

READWRITE

WRITE

WRITEAP

READ

READAP READAP

PRE(PALL)

Command Input

Automatic Sequence

IDLE

AUTO

REFRESH

PRE-

CHARGE

POWER-UP

POWER APPLIED

MODE

REGISTER

SET

POWER

DOWN

WRITE

WITH

AUTOPRE-

CHARGE

POWER

DOWN

WRITE

READ

WITH

AUTOPRE-

CHARGE

BANK

ACTIVE

READ

SELF

REFRESH

Rev. 0.04 /Jul. 2006 10

HY5DU281622FT(P) Series

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Power must first be applied to V

DD

, then to V

DDQ

, and finally to VREF

(and to the system VTT). VT T must be applie d after V

DDQ

to avoi d device latch-up , which may cause perman ent dam-

age to the device. VREF can be applied anytime after V

DDQ

, but is expected to be nominally coincident with VTT.

Except for CKE, inputs ar e not recogniz ed as valid until after VREF is applied. CKE is an SS TL_2 input, but will detect an

LVCMOS LOW level after V

DD

is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to

guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal oper-

ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR

SDRAM requires a 200us delay prior to applying an executable command.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED

MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE

REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating

parameters. After the DLL r eset, tXSRD(DLL locking time) should be satisfied fo r read command. After the Mode R egis-

ter set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command

for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting

the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - V

DD

, V

DDQ

, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.)

•V

DD

and V

DDQ

are driven from a single power converter output.

• VTT is limited to 1.44V (reflecting V

DDQ

(max)/2 + 50mV VREF variation + 40mV VTT variation.

•V

REF tracks V

DDQ

/2.

• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-

ship must be adhered to during power up.

2. Start clock and maintain stable clock for a minimum of 200usec.

3. After stable power and clock, apply NOP condition and take CKE high.

4. Issue Extended Mode Register Set (EMRS) to enable DLL.

5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles(tXSRD) of clock are required for locking DLL)

6. Issue Precharge commands for all banks of the device.

7. Issue 2 or more Auto Refresh commands.

8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low

Voltage description Sequencing Voltage relationship to avoid latch-up

V

DDQ

After or with V

DD

< V

DD

+ 0.3V

VTT After or with V

DDQ

< V

DDQ

+ 0.3V

VREF After or with V

DDQ

< V

DDQ

+ 0.3V

Rev. 0.04 /Jul. 2006 11

HY5DU281622FT(P) Series

Power-Up Sequence

CODECODE CODE CODECODE

CODE CODECODECODECODE

NOP PRE MRSEMRS PRENOP MRSAREF ACT RD

VDD

VDDQ

VTT

VREF

/CLK

CLK

CKE

CMD

DM

ADDR

A10

BA0, BA1

DQS

DQ'S

LVCMOS Low Level

tIS tIH

tVTD

T=200usec tRP tMRD tRP tRFC tMRD

tXSRD*

READ

Non-Read

Command

Power UP

VDD and CK stable Precharge All EMRS Set MRS Set

Reset DLL

(with A8=H)

Precharge All 2 or more

Auto Refresh

MRS Set

(with A8=L)

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

tMRD

Rev. 0.04 /Jul. 2006 12

HY5DU281622FT(P) Series

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,

burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the

low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and

CKE must be high at least one cycle before the Mode Re gister Set Comm and can be issued. Two cycles are required to

write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is

determined, the information will be held until reset by another MRS command.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 Operating Mode CAS Latency BT Burst Length

A2 A1 A0 Burst Length

Sequential Interleave

0 0 0 Reserved Reserved

001 2 2

010 4 4

011 8 8

1 0 0 Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Reserved Reserved

A3 Burst Type

0Sequential

1Interleave

A6 A5 A4 CAS Latency

000 Reserved

001 Reserved

010 2

011 3

100 4

101 1.5

110 2.5

111 Reserved

BA0 MRS Type

0MRS

1EMRS

A12~A9 A8 A7 A6~A0 Operating Mode

0 0 0 Valid Normal Operation

0 1 0 Valid Normal Operation/ Reset DLL

0 0 1 VS Vendor specific Test Mode

- - - - All other state s reserved

Rev. 0.04 /Jul. 2006 13

HY5DU281622FT(P) Series

BURST DEFINITION

BURST LENGTH & TYPE

Read and write accesses to th e DDR SD RAM are bu rst orien ted, wi th the burst length being programmable. The burst

length determines the maximum number of column locations that can be accessed for a given Read or Write com-

mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length

is set to four and by A3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit

for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location

within the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Burst Definition Table

Burst Length Starting Address

(A2,A1,A0) Sequential Interleave

2XX0 0, 1 0, 1

XX1 1, 0 1, 0

4

X00 0, 1, 2, 3 0, 1, 2, 3

X01 1, 2, 3, 0 1, 0, 3, 2

X10 2, 3, 0, 1 2, 3, 0, 1

X11 3, 0, 1, 2 3, 2, 1, 0

8

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6

010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5

011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4

100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2

110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1

111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

Rev. 0.04 /Jul. 2006 14

HY5DU281622FT(P) Series

CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the

av aila bility of the first burst of output data. The latency can be pr ogrammed 2 or 2.5 clocks for DDR266/3 33 and 3 or

4 clocks for DDR400 and 400Mbps/pin or 500Mbps/pin product.

If a Read comma nd is registered at clock ed ge n, and the latency is m clocks, the data is av aila ble nominally coinciden t

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled f or normal oper ation. DLL enable is requ ired during pow er up init ializa tion, an d upon re turn-

ing to normal operation after having disabled the DLL fo r the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver

option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will

reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver

and the half strength driver are included in this document.

Rev. 0.04 /Jul. 2006 15

HY5DU281622FT(P) Series

EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-

tions include DLL enable/disable, output driver strength se lection(optional). These functions are controlled via the bits

shown below. The Extended Mode Register is programmed via the Mode Register Set command (BA0=1 and BA1=0)

and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register mus t be loaded when all banks are idle and no bursts are in progress, and the controller

must wait the specified time before initiating any subsequent operation. Violating either of these requirements will

result in unspecified operation.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 Operating Mode 0* DS DLL

A0 DLL enable

0Enable

1Disable

BA0 MRS Type

0MRS

1EMRS

A1 Output Driver

Impedance Control

0 Full Strength Driver

1 Half Strength Driver

* This part do not support/QFC function, A2 must be programmed to Zero.

An~A3 A2~A0 Operating Mode

0 Valid Normal Operation

_ _ All other states reserved

Rev. 0.04 /Jul. 2006 16

HY5DU281622FT(P) Series

ABSOLUTE MAXIMUM RATINGS

Note: Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Note:

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. V

REF

is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.

Peak to peak noise on VREF may not exceed ±2% of the DC value.

4. VID is the magnitude of the difference between the input level on CK and the input level on /CK.

Parameter Symbol Rating Unit

Operating Temperature (Ambient) TA0 ~ 70 oC

Storage Temperature TSTG -55 ~ 150 oC

Voltage on VDD relative to VSS VDD -1.0 ~ 3.6 V

Voltage on VDDQ relative to VSS VDDQ -1.0 ~ 3.6 V

Voltage on inputs relative to VSS VINPUT -1.0 ~ 3.6 V

Voltage on I/O pins relative to VSS VIO -0.5 ~3.6 V

Output Short Circuit Current IOS 50 mA

Soldering Temper atur e ⋅ Time TSOLDER 260 ⋅ 10 oC ⋅ Sec

Parameter Symbol Min Typ. Max Unit

Power Supply Voltage (DDR200, 266, 333) VDD 2.3 2.5 2.7 V

Power Supply Voltage (DDR200, 266, 333)1VDDQ 2.3 2.5 2.7 V

Power Supply Voltage (DDR400, 400Mbps/pin or

500Mbps/pin product) VDD 2.4 2.6 2.7 V

Power Supply Voltage (DDR400, 400Mbps/pin or

500Mbps/pin product)1VDDQ 2.4 2.6 2.7 V

Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V

Input Low Voltage2VIL -0.3 - VREF - 0.15 V

Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V

Reference Volta ge3VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V

Input Voltage Level, CK and CK inputs VIN(DC) -0.3 - VDDQ+0.3 V

Input Differential Voltage, CK and CK inputs4VID(DC) 0.36 - VDDQ+0.6 V

V-I Matching: Pullup to Pulldown Current Ratio5VI(RATIO) 0.71 - 1.4 -

Input Leakage Current6ILI -2 - 2 uA

Output Leakage Current7ILO -5 - 5 uA

Normal Strength

Output Driver

(VOUT=VTT ±

0.84)

Output High Current

(min VDDQ, min VREF, min

VTT)IOH -16.8 - - mA

Output Low Current

(min VDDQ, max VREF, max

VTT)IOL 16.8 - - mA

Half Strength

Output Driver

(VOUT=VTT ±

0.68)

Output High Current

(min VDDQ, min VREF, min

VTT)IOH -13.6 - - mA

Output Low Current

(min VDDQ, max VREF, max

VTT)IOL 13.6 - - mA

Rev. 0.04 /Jul. 2006 17

HY5DU281622FT(P) Series

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-

ature and voltage r ange, f or devi ce dr ain to source v oltages from 0.25V to 1.0V. F or a giv en outp ut, it r epr esents the m aximum dif-

ference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum

pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

6. VIN=0 to VDD, All other pins are no t tested under VIN =0V.

7. DQs are disabl ed, VOUT=0 to VDDQ

IDD SPECIFICATION AND CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Test Conditions

Test Condition Symbol

Operating Current:

One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice

per clock cycle; address and control inputs changing once per clock cycle IDD0

Operating Current:

One bank; Active - Read - Precharge;

Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock

cycle

IDD1

Precharge Power Down Standby Current:

All banks idle; Power down mode; CKE=Low, tCK=tCK(min) IDD2P

Idle Standby Current:

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing once per clock cycle.

VIN=VREF for DQ, DQS and DM

IDD2F

Idle Quiet Standby Current:

/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref

for DQ, DQS and DM IDD2Q

Active Power Down Standby Current:

One bank active; Power down mode; CKE=Low, tCK=tCK(min) IDD3P

Active Standby Current:

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min);

DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing

once per clock cycle

IDD3N

Operating Current:

Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per

clock cycle; tCK=tCK(min); IOUT=0mA IDD4R

Operating Current:

Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per

clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle IDD4W

Auto Refresh Current:

tRC=tRFC(min) - 8* tCK for DDR200 at 100Mhz, 10*tCK f or DDR266A & DDR266B at 133 Mhz; distributed

refresh

tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz

IDD5

Self Refresh Current:

CKE =< 0.2V; External clock on; tCK=tCK(min) IDD6

Operating Current - Four Bank Operation:

Four bank interleaving with BL=4, Refer to the following page for detailed test condition IDD7

Rev. 0.04 /Jul. 2006 18

HY5DU281622FT(P) Series

DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

8Mx16 (2M x4Bank x16I/O)

Parameter Symbol Test Condition

Speed Unit Note45/ D43/ D4

250 200 MHz

Operating

Current IDD0

One bank; Active - Precharge ; tRC=tRC(min);

tCK=tCK(min) ; DQ,DM and DQS inputs changing twice

per clock cycle; address and control inputs changing

once per clock cycle

TBD 120 mA

Operating

Current IDD1 One bank; Active - Read - Precharge;

Burst Length=2; tRC=tRC(min); tCK=tCK(min); address

and control inputs changing once per clock cycle TBD 120 mA

Precharge

Power Down

Standby

Current

IDD2P All banks idle; Power down mode; CKE=Low,

tCK=tCK(min) TBD 10 mA

Idle Standby

Current IDD2N VIN>=VIH(min) or VIN=<VIL(max) for DQ, DQS and

DM TBD 60 mA

Idle Standby

Current IDD2F

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing once

per clock cycle.

VIN=VREF for DQ, DQS and DM

TBD 60 mA

Idle Quiet

Standby

Current IDD2Q /CS>=VIH(min); All banks idle; CKE>=VIH(min);

Addresses and other control inputs sta ble, VIN=Vref for

DQ, DQS and DM TBD 60 mA

Active Power

Down

Standby

Current

IDD3P One bank active; Power down mode; CKE=Low,

tCK=tCK(min) TBD 20 mA

Active

Standby

Current IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;

tRC=tRAS(max); tCK=tCK(min);

DQ, DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing once

per clock cycle

TBD 70 mA

Rev. 0.04 /Jul. 2006 19

HY5DU281622FT(P) Series

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Parameter Symbol Test Condition

Speed Unit Note45/ D43/ D4

250 200 MHz

Operating

Current IDD4R Burst=2; Reads; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); IOUT=0mA TBD 200

mA

Operating

Current IDD4W

Burst=2; Writes; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); DQ , DM and DQS inputs changing

twice per clock cycle

TBD 200

Auto Refresh

Current IDD5 tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz TBD 200

Self Refresh

Current IDD6 CKE =< 0.2V; External clock on; tCK=tCK(min) TBD 3 mA

Operating

Current -

Four Bank

Operation

IDD7 Four bank interleaving with BL=4, Refer to the

following page for detailed test condition TBD 300 mA

Random Read

Current IDD7A

4banks active read with activate every 20ns, AP(Auto

Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0

mA, 100% DQ , DM and DQS in puts changing twice per

clock cycle; 100% addresses changing once per clock

cycle

TBD 300 mA

Rev. 0.04 /Jul. 2006 20

HY5DU281622FT(P) Series

DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

8Mx16 (2M x4Bank x16I/O)

Parameter Symbol Test Condition

Speed Unit NoteJ K H

133 133 100 MHz

Operating

Current IDD0

One bank; Active - Precharge ; tRC=tRC(min);

tCK=tCK(min) ; DQ,DM and DQS inputs changing twice

per clock cycle; address and control inputs changing

once per clock cycle

110 100 100 mA

Operating

Current IDD1 One bank; Active - Read - Precharge;

Burst Length=2; tRC=tRC(min); tCK=tCK(min); address

and control inputs changing once per clock cycle 110 100 100 mA

Precharge

Power Down

Standby

Current

IDD2P All banks idle; Power down mode; CKE=Low,

tCK=tCK(min) 20 mA

Idle Standby

Current IDD2N VIN>=VIH(min) or VIN=<VIL(max) for DQ, DQS and

DM -mA

Idle Standby

Current IDD2F

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing once

per clock cycle.

VIN=VREF for DQ, DQS and DM

50 45 mA

Idle Quiet

Standby

Current IDD2Q /CS>=VIH(min); All banks idle; CKE>=VIH(min);

Addresses and other control inp uts stable, VIN=Vr ef for

DQ, DQS and DM -mA

Active Power

Down

Standby

Current

IDD3P One bank active; Power down mode; CKE=Low,

tCK=tCK(min) 20 mA

Active

Standby

Current IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;

tRC=tRAS(max); tCK=tCK(min);

DQ, DM and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per

clock cycle

60 50 mA

Rev. 0.04 /Jul. 2006 21

HY5DU281622FT(P) Series

- Continue

Parameter Symbol Test Condition

Speed Unit NoteJ K H

133 133 100 MHz

Operating

Current IDD4R Burst=2; Reads; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); IOUT=0mA 160 150

mA

Operating

Current IDD4W

Burst=2; Writes; Continuous burst; One bank active;

Address and control inputs changing once per clock

cycle; tCK=tCK(min); DQ, DM and DQS inputs

changing twice per clock cycle

160 150

Auto Refresh

Current IDD5 tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz 180 170

Self Refresh

Current IDD6 CKE =< 0.2V; External clock on; tCK=tCK(min) 2 mA

Operating

Current -

Four Bank

Operation

IDD7 Four bank interleaving with BL=4, Refer to the

following page for detailed test condition 250 230 mA

Random Read

Current IDD7A

4banks active read with activate every 20ns, AP(Auto

Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0

mA, 100% DQ, DM and DQS inputs changing twice

per clock cycle; 100% addresses changing once per

clock cycle

-mA

Rev. 0.04 /Jul. 2006 22

HY5DU281622FT(P) Series

DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7

IDD1 : Operating current: One bank operation

1. Typical Case : VDD = 2.6V, T=25 oC

2. Worst Case : VDD = 2.7V, T= 0 oC

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are

changing once per clock cycle. lout = 0mA

4. Timing patterns

- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK

Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random add

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

IDD7 : Operating current: Four bank operation

1. Typical Case : VDD = 2.6V, T=25 oC

2. Worst Case : VDD= 2.7V, T= 0 oC

3. Four banks are being interleaved with tRC(min), Burst Mode, Address an d Control inputs on NOP edge are not

changing. lout = 0mA

4. Timing patterns

- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 3, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Rev. 0.04 /Jul. 2006 23

HY5DU281622FT(P) Series

AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage refere nced t o VSS = 0V)

Note:

1. V

ID

is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

*For more information about AC Overshoot/Undershoot Specifications, refer to “Device Operation” section in hynix website.

AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Parameter Symbol Min Max Unit

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 - V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) - VREF - 0.31 V

Input Differential Voltage, CK and /CK inputs1VID(AC) 0.7 VDDQ + 0.6 V

Input Crossing Point Voltage, CK and /CK inputs2VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V

Parameter Value Unit

Reference Volta ge VDDQ x 0.5 V

Termination Voltage VDDQ x 0.5 V

AC Input High Level Voltage (VIH, min) VREF + 0.31 V

AC Input Low Level Voltage (VIL, max) VREF - 0.31 V

Input Timing Measurement Reference Level Voltage VREF V

Output Timing Measurement Reference Level Voltage VTT V

Input Signal maximum peak swing 1.5 V

Input minimum Signal Slew Rate 1 V/ns

Termination Resistor (RT) 50 Ω

Series Resistor (RS) 25 W

Output Load Capacitance for Access Time Measurement (CL) 30 pF

Rev. 0.04 /Jul. 2006 24

HY5DU281622FT(P) Series

AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)

Parameter Symbol -4 -5 / D43 D4 UNIT

Min Max Min Max Min Max

Row Cycle Time tRC 60 - 55 - 60 - ns

Auto Refresh Row Cycle Time tRFC 72 - 70 - 70 - ns

Row Active Time tRAS 40 70K 40 70K 40 70K ns

Active to R ead with Auto Precharge

Delay tRAP tRCD or

tRAS(min) -tRCD or

tRAS(min) -ns

Row Address to Column Address

Delay tRCD 12 - 15 - 18 - ns

Row Active to Row Active Delay tRRD 12 - 10 - 10 - ns

Column Address to Column

Address Delay tCCD 1-1-1-tCK

Row Precharge Time tRP 20 - 15 - 18 - ns

Write Recovery Time tWR 15 - 15 - 15 - ns

Internal Write to Read Command

Delay tWTR 2-2-2-tCK

Auto Precharge Write Recovery +

Precharge Time22 tDAL (tWR/tCK)

+

(tRP/tCK)-(tWR/tCK)

+

(tRP/tCK)-(tWR/tCK)

+

(tRP/tCK)-t

CK

System Clock

Cycle Time24 CL = 4 tCK 410----

CL = 3 - - 510510ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock Low Level Wid th tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Data-Out edge to Clock edge Skew tAC -0.6 0.6 -0.7 0.7 -0.7 0.7 ns

DQS-Out edge to Clock edge Skew tDQSCK -0.6 0.6 -0.55 0.55 -0.65 0.65 ns

DQS-Out edge to Data-Out edge

Skew21 tDQSQ - 0.4 - 0.4 - 0.4 ns

Data-Out hold time from DQS20 tQH tHP

-tQHS -tHP

-tQHS -ns

Clock Half Period19,20 tHP min

(tCL,tCH)-min

(tCL,tCH)-ns

Data Hold Skew Factor20 tQHS - 0.5 - 0.5 - 0.5 ns

Valid Data Output Window tDV tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns

Rev. 0.04 /Jul. 2006 25

HY5DU281622FT(P) Series

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Parameter Symbol J K H UNIT

Min Max Min Max Min Max

Row Cycle Time tRC 60 - 65 - 65 - ns

Auto Refresh Row Cycle Time tRFC 72 - 75 - 75 - ns

Row Active Time tRAS 42 70K 45 120K 50 120K ns

Active to Read with Auto

Precharge Delay tRAP tRCD or

tRAS(min) -tRCD or

tRAS(min) -ns

Row Address to Column

Address Delay tRCD 18 - 20 - 20 - ns

Row Active to Row Active Delay tRRD 12 - 15 - 15 - ns

Column Address to Column

Address Delay tCCD 1-1-1-t

CK

Row Precharge Time tRP 18 - 20 - 20 - ns

Write Recovery Time tWR 15 - 15 - 15 - ns

Internal Write to Read

Command Delay tWTR 1-1-1-t

CK

Auto Precharge Write Recovery

+ Precharge Time22 tDAL (tWR/tCK)

+

(tRP/tCK)-(tWR/tCK)

+

(tRP/tCK)-(tWR/tCK)

+

(tRP/tCK)-t

CK

System Clock

Cycle Time24

CL = 3

tCK

612----

CL = 2.5 6 12 7.5 12 7.5 12 ns

CL = 2 7.5127.5121012ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock Low Level Wid th tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Data-Out edge to Clock edge

Skew tAC -0.7 0.7 -0.75 0.75 -0.75 0.75 ns

DQS-Out edge to Clock edge

Skew tDQSCK -0.6 0.6 -0.75 0.75 -0.75 0.75 ns

DQS-Out edge to Data-Out

edge Skew21 tDQSQ -0.45- 0.5 - 0.5ns

Data-Out hold time from

DQS20 tQH t

HP

-t

QHS

-t

HP

-t

QHS

-t

HP

-t

QHS

-ns

Clock Half Period19,20 tHP min

(tCL,tCH)-min

(tCL,tCH)-ns

Data Hold Skew Factor20 tQHS - 0.55 - 0.75 - 0.75 ns

Valid Data Output Window tDV tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns

Rev. 0.04 /Jul. 2006 26

HY5DU281622FT(P) Series

- Continue

Parameter Symbol -4 -5 / -D43 -D4 UNIT

Min Max Min Max Min Max

Data-out high-impedance window from CK,/CK10 tHZ -tAC

(Max) -tAC

(Max) ns

Data-out low-impedance window from CK, /CK10 tLZ -0.70.7-0.70.7-0.70.7 ns

Input Setup Time (fast slew rate)14,16-18 tIS 0.75 - 0.6 - 0.6 - ns

Input Hold Time (fast slew rate)14,16-18 tIH 0.75 - 0.6 - 0.6 - ns

Input Setup Time (slow slew rate)15-18 tIS 0.7 - 0.7 - 0.7 - ns

Input Hold Time (slow slew rate)15-18 tIH 0.7 - 0.7 - 0.7 - ns

Input Pulse Width17 tIPW 2.2 -2.2 -2.2 -ns

Write DQS High Level Width tDQSH 0.4 0.6 0.35 -0.35 -tCK

Write DQS Low Level Width tDQSL 0.4 0.6 0.35 -0.35 -tCK

Clock to First Rising edge of DQS-In tDQSS 0.85 1.15 0.72 1.25 0.72 1.25 tCK

DQS falling edge to CK setup time tDSS 0.3 -0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.3 -0.2 -0.2 -tCK

DQ & DM input setup time25 tDS 0.4 -0.4 -0.4 -ns

DQ & DM input hold time25 tDH 0.4 -0.4 -0.4 -ns

DQ & DM Input Pulse Width17 tDIPW 1.75 -1.75 -1.75 -ns

Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Write DQS Preamble Setup Time12 tWPRES 0 - 0 - 0 -ns

Write DQS Preamble Hold Time tWPREH 0.35 -0.25 -0.25 -tCK

Write DQS Postamble Time11 tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Mode Register Set Delay tMRD 2 - 2 - 2 -tCK

Exit Self Refresh to non-Read command23 tXSNR 75 -75 -75 -ns

Exit Self Refresh to Read command tXSRD 200 -200 -200 -tCK

Average Periodic Refresh Interval13,25 tREFI -15.6 -15.6 -15.6 us

Rev. 0.04 /Jul. 2006 27

HY5DU281622FT(P) Series

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Parameter Symbol J K H UNIT

Min Max Min Max Min Max

Data-out high-impedance window from CK,/

CK10 tHZ -t

AC

(Max) -t

AC

(Max) -t

AC

(Max) ns

Data-out low-impedance window from CK, /

CK10 tLZ -0.7 0.7 -0.75 0.75 -0.75 0.75 ns

Input Setup Time (fast slew rate)14,16-18 tIS 0.75 - 0.9 - 0.9 - ns

Input Hold Time (fast slew rate)14,16-18 tIH 0.75 - 0.9 - 0.9 - ns

Input Setup Time (slow slew rate)15-18 tIS 0.8 - 1.0 - 1.0 - ns

Input Hold Time (slow slew rate)15-18 tIH 0.8 - 1.0 - 1.0 - ns

Input Pulse Width17 tIPW 2.2 - 2.2 - 2.2 - ns

Write DQS High Level Width tDQSH 0.35 - 0.35 - 0.35 - tCK

Write DQS Low Level Width tDQSL 0.35 - 0.35 - 0.35 - tCK

Clock to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2-0.2-tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2-0.2-tCK

DQ & DM input setup time25 tDS 0.45 - 0.5 - 0.5 - ns

DQ & DM input hold time25 tDH 0.45 - 0.5 - 0.5 - ns

DQ & DM Input Pulse Width17 tDIPW 1.75 - 1.75 - 1.75 - ns

Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Write DQS Preamble Setup Time12 tWPRES 0-0-0-ns

Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - 0.25 - tCK

Write DQS Postamble Time11 tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Mode Register Set Delay tMRD 2-2-2-tCK

Exit Self Refresh to non-Read command23 tXSNR 75 - 75 - 75 - ns

Exit Self Refresh to Read command tXSRD 200 - 200 - 200 - tCK

Average Periodic Refresh Interval13,25 tREFI - 15.6 - 15.6 - 15.6 us

Rev. 0.04 /Jul. 2006 28

HY5DU281622FT(P) Series

Note:

1. All voltages referenced to Vss.

2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,

but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to

be either a precise representation of the typical system environm ent nor a depiction o f the actual load p resented by a producti on

tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.

Manufactur ers will correlat e to their product ion test conditio ns (generall y a coaxial tr ansmission line terminated at the tester elec-

tronics).

4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to

VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under

normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).

5. The ac and dc input level sp ecifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result

of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the

dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is

recognized as LOW.

7. The CK, /CK input referen ce leve l (for ti ming referenced to C K, /CK) is the point at which CK and /CK cross; the input reference

level for signals other than CK, /CK is VREF.

8. The output timing reference voltage level is VTT.

9. Oper at ion or timin g that i s not s pecif ied is illegal and after such an event, in order to guarantee proper operation, the DRAM must

be powered down and then restarted through the specified initialization sequence before normal operation ca n co ntinue.

10. tHZ and tLZ tr an siti ons oc cur in the same acc ess time win dows as v ali d data transitions. These parameters are not r eferenced to

a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

11. The maximum limit for this parameter is not a device limit. The d evice will operate with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is de fined as monotonic and meet ing the inpu t slew rate specifications of the device. When no writes were previ-

ously in progress on the bus, DQ S will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitionin g from HIGH to LOW at this time, depending on tDQSS.

13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

14. For command/address input slew rate ≥1.0 V/ns.

15. For command/address input slew rate ≥0.5 V/ns and ＜1.0 V/ns

16. For CK & /CK slew rate ≥1.0 V/ns (single-ended)

17. These parameters guarantee device timing, but they are not nec e ssarily tested on each device.

They may be guaranteed by device design or tester correlation.

18. Slew Rate is measured between VOH(ac) and VOL(ac).

19. Min (tCL, tCH) r ef ers to th e smaller of the ac tual clo ck l ow time an d the actu al cl ock hi gh t ime as pr ov ided t o the dev ice (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

For example, tCL and tCH are = 50% o f the period , less the half perio d jitter (tJIT(HP)) of the clock source, and less the half

period jitter due to crosst alk (tJIT(crosstalk)) into the clock traces.

Figure: Timing Referen ce Lo ad

VDDQ

50

Output

(VOUT)

30 pF

Ω

Rev. 0.04 /Jul. 2006 29

HY5DU281622FT(P) Series

20.tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The

pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the

worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,

and p-channel to n-channel variation of the output drivers.

21. tDQSQ:

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given

cycle.

22. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For DDR266B at CL=2.5 and tCK=7.5 ns

tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks

= ((2) + (3)) clocks

= 5 clocks

23. In all circumstances, tXSNR can be satisfied us ing

tXSNR = tRFCmin + 1*tCK

24. The only time that the clock frequency is allowed to change is durin g self-refresh mode.

25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-writ ten with valid data before a valid

READ can be executed.

Rev. 0.04 /Jul. 2006 30

HY5DU281622FT(P) Series

SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS

The following tables are described specification parameters that required in systems using DDR devices to ensure

proper performannce. These characteristics are for system simulation purposes and are guaranteed by design.

Input Slew Rate for DQ/DM/DQS (Table a.)

Address & Control Input Setup & Hold Time Derating (Table b.)

DQ & DM Input Setup & Hold Time Derating (Table c.)

DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate (Table d.)

Output Slew Rate Characteristics (for x16 Device) (Table e.)

Output Slew Rate Matching Ratio Characteristics (Table f.)

AC CHARACTERISTICS DDR400 DDR333 DDR266 UNIT Note

PARAMETER Symbol min max min max min max

DQ/DM/DQS inpu t slew rate

measured between VIH(DC),

VIL(DC) and VIL(DC), VIH(DC) DCSLEW 0.5 4.0 0.5 4.0 0.5 4.0 V/ns 1,12

Input Slew Rate Delta tIS Delta tIH UNIT Note

0.5 V/ns 0 0 ps 9

0.4 V/ns +50 0 ps 9

0.3 V/ns +100 0 ps 9

Input Slew Rate Delta tDS Delta tDH UNIT Note

0.5 V/ns 0 0 ps 11

0.4 V/ns +75 0 ps 11

0.3 V/ns +150 0 ps 11

Input Slew Rate Delta tDS Delta tDH UNIT Note

±0.0 ns/V 00ps10

±0.25 ns/V +50 +50 ps 10

±0.5 ns/V +100 +100 ps 10

Slew Rate Characteristic Typical Range (V/

ns) Minimum (V/

ns) Maximum (V/

ns) Note

Pullup Slew Rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8

Pulldown Slew Rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8

Slew Rate Characteristic DDR266A DDR266B Note

Parameter min max min max

Output Slew Rate Matching Ratio (Pullup to

Pulldown) - --- 5,12

Rev. 0.04 /Jul. 2006 31

HY5DU281622FT(P) Series

Note:

1. Pullup slew rate is characterized under the te st conditions as shown in below Figure.

2. Pulldown slew rate is measured under the test conditions sho w n in below Figure.

3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ±250mV)

Pulldown slew rate is measured between (VDDQ/2 + 320mV ±250mV)

Pullup and Pulldown slew r ate c onditions are to be met fo r any pat tern of d ata, inclu ding all outp uts switch ing and on ly on e output

switching.

Example: For typical slew, DQ0 is switching

For minimum slew rate, all DQ bits are switching worst case pattern

For maximum slew rate, only one DQ is switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

4. Evaluation condit io ns

Typical: 25 oC (Ambient), VDDQ = nominal, typical process

Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process

Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process

5. The ratio of pullup sl ew r a te to pulldown slew r ate is spec ified f or the same temperature and voltage, over the entire tempe rature

and voltage range. F or a giv en output, it r epresents th e maximum differ ence between pullup and pulldown drivers due to process

variation.

6. Verified under typical conditions for qualification purposes.

7. TSOP-II package devices only.

8. Only intended for operation up to 256 Mbps per pin.

9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.

The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), sim-

ilarly for rising transitions.

10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c

& d. Input sl ew r ate is bas ed on the lar ger of AC - AC delta rise , fall r ate an d DC -DC delta rise, fall r ate . Input sl ew rat e is bas ed on

the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The

delta rise/fall rate is calculated as:

{1/(Slew Rate1)} - {1/(slew Rate2)}

For example:

If Slew Rate 1 is 0.5 V/ ns and Slew Rate 2 is 0.4 V/ns, then the d elta rise, fall rate is -0.5 ns/V. Using the table given, this would

result in the need for an increase in tDS and tDH of 100ps.

11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the

lesser of the AC- AC slew r ate and the DC -DC slew r ate. The input slew rate is based on the lesser of the slew rates determined by

either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.

12. DQS, DM, and DQ input sl ew rate is spec ified to prevent doub le clocking of d a ta a nd preserve setup and hold times. Si gnal tran-

sitions through the DC region must be monotonic.

50

Output

(VOUT)

VSSQ

Test Point

Figure: Pullup Slew rate

Ω

VDDQ

50

Test Point

Output

(VOUT)

Figure: Pulldown Slew rate

Ω

Rev. 0.04 /Jul. 2006 32

HY5DU281622FT(P) Series

CAPACITANCE (TA=25oC, f=100MHz)

Note:

1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V

2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

Parameter Pin Symbol Min Max Unit

Input Clock Capacitance CK, /CK CI1 2.0 3.0 pF

Delta Input Clock Capacitance CK, /CK Delta CI1 - 0.25 pF

Input Capacitance All other input-only pins CI1 2.0 3.0 pF

Delta Input Capacitance All other input-only pins Delta CI2 - 0.5 pF

Input / Output Capacitance DQ, DQS, DM CIO 4.0 5.0 pF

Delta Input / Output Capacitance DQ, DQS, DM Delta CIO - 0.5 pF

V

REF

V

TT

C

L

= 30pF

Z

O

= 50 Ohm

Out put

R

T

= 50 Ohm

Rev. 0.04 /Jul. 2006 33

HY5DU281622FT(P) Series

PACKAGE INFORMATION

400mil 66pin Thin Small Outline Package

10.26 (0.404)

10.05 (0.396)

11.94 (0.470)

11.79 (0.462)

22.33 (0.879)

22.12 (0.871)

1.194 (0.0470)

0.991 (0.0390)

0.65 (0.0256) BSC 0.35 (0.0138)

0.25 (0.0098)

0.15 (0.0059)

0.05 (0.0020)

BASE PLANE

SEATING PLANE

0.597 (0.0235)

0.406 (0.0160) 0.210 (0.0083)

0.120 (0.0047)

0 ~ 5 Deg.

Unit : m m(Inch)