19-4138; Rev 0; 10/08 KIT ATION EVALU LE B A IL A AV Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers Features The MAX4810/MAX4811/MAX4812 integrated circuits generate high-voltage, high-frequency, unipolar or bipolar pulses from low-voltage logic inputs. These dual pulsers feature independent logic inputs, independent high-voltage pulser outputs with active clamps and independent high-voltage supply inputs. The MAX4810/MAX4811/MAX4812 feature a 9 output impedance for the high-voltage outputs, and a 27 impedance for the active clamp. The high-voltage outputs are guaranteed to provide 1.3A output current. Highly Integrated, High-Voltage, High-Frequency Unipolar/Bipolar Pulser All devices use three logic inputs per channel to control the positive and negative pulses and active clamp. Also included are two independent enable inputs. Disabling EN ensures the output MOSFETs are not accidentally turned on during fast power-supply ramping. This allows for faster ramp times and smaller delays between pulsing modes. A low-power shutdown mode reduces power consumption to less than 1A. All digital inputs are CMOS compatible. The MAX4810 includes clamp output overvoltage protection, while the MAX4811 features both pulser output and clamp output overvoltage protection. The MAX4812 does not provide overvoltage protection. See the Ordering Information/Selector Guide. The MAX4810/MAX4811/MAX4812 are available in a 56-pin (7mm x 7mm), TQFN exposed-pad package and are specified over the 0C to +70C commercial temperature range. Matched Rise/Fall Times and Matched Propagation Delays Piezoelectric Drivers Test Instruments Ordering Information/ Selector Guide 0 to +220V Unipolar or 110V Bipolar Outputs CMOS-Compatible Logic Inputs 56-Pin, 7mm x 7mm, TQFN Package Pin Configuration 27 VCC2 VCC2 45 26 INN2 CGC2 46 25 INC2 CDC2 47 24 INP2 VEE2 48 23 EN2 22 AGND VDD 49 MAX4810 MAX4811 MAX4812 VSS 50 VEE1 51 CDC1 52 21 SHDN 20 EN1 19 INP1 18 INC1 CGC1 53 17 INN1 1.3 56 TQFN-EP** Note: All devices are specified over the 0C to +70C operating temperature range. +Denotes a lead-free/RoHS-compliant package. *Future product--contact factory for availability. **EP = Exposed pad. 7 8 9 10 11 12 13 14 VNN1 None 6 N.C. MAX4812CTN+* 5 ON1 56 TQFN-EP** 4 OCN1 1.3 3 GND OCP_, OCN_, OP_, ON_ 2 OCP1 MAX4811CTN+ 15 GND 1 OP1 56 TQFN-EP** 16 VCC1 CDP1 56 N.C. 1.3 *EP + VPP1 OCP_, OCN_ GND 55 VPP1 MAX4810CTN+ CDN2 28 GND GND 44 CGP1 PART PINPACKAGE CGN2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CDP2 43 VCC1 54 OUTPUT PROTECTED CURRENT OUTPUTS (A) VNN2 VNN2 N.C. ON2 OCN2 GND OCP2 OP2 N.C. VPP2 VPP2 CGP2 TOP VIEW CDN1 Cleaning Equipment Flaw Detection Pulser and Clamp Overvoltage Protection (MAX4810/MAX4811) CGN1 Ultrasound Medical Imaging 27 Active Clamp VNN1 Applications 9 Output Impedance and 1.3A (min) Output Current TQFN 7mm x 7mm *EP = EXPOSED PAD, CONNECT EP TO VSS. Warning: The MAX4810/MAX4811/MAX4812 are designed to operate with high voltages. Exercise caution. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX4810/MAX4811/MAX4812 General Description MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VDD Logic Supply Voltage........................................-0.3V to +6V VCC_ Output Driver Positive Supply Voltage ..........-0.3V to +15V VEE_ Output Driver Negative Supply Voltage.........-15V to +0.3V VPP_ High Positive Supply Voltage.......................-0.3V to +230V VNN_ High Negative Supply Voltage ....................-230V to +0.3V VSS Voltage ................................................(VPP_ - 250V) to VNN_ VPP1 - VNN1, VPP2 - VNN2 Supply Voltage............-0.6V to +250V INP_, INN_, INC_, EN_, SHDN Logic Input...-0.3V to VDD + 0.3V OP_, OCP_, OLN_, ON_ ..............(-0.3V + VNN_) to (-0.3V to VPP_) CGN_ Voltage............................(-0.3V + VNN_) to (+15V + VNN_) CGP_ Voltage .............................(+0.3V + VPP_) to (-15V + VPP_) CGC_ Voltage...........................................................-15V to +15V CDC_, CDP_, CDN_ Voltage......................................-0.3V to VCC_ Peak Current per Output Channel ........................................3.0A Continuous Power Dissipation (TA = +70C) (Note 1) 56-Pin TQFN (derate 40mW/C above +70C) ..........3200mW Thermal Resistance (Note 2) JA ................................................................................25C/W JC ...............................................................................0.8C/W Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Note 1: This specification is based on the thermal characteristic of the package, the maximum junction temperature, and the setup described by JEDEC 51. The maximum power dissipation for the MAX4810/MAX4811/MAX4812 might be limited by the thermal protection included in the device. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +6V, VCC_ = +4.75V to +12.6V, VEE_ = -12.6V to -4.75V, VNN_ = -200V to 0, VPP_ = 0 to (VNN_ + 200V), VSS the lower of VNN1 or VNN2, TA = TJ = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 3) (See Figures 8, 9, and 10.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY (VDD, VCC_, VEE_, VPP_, VNN_) Logic Supply Voltage VDD +2.7 +3 +6 V Positive Drive Supply Voltage VCC_ +4.75 +12 +12.6 V Negative Drive Supply Voltage VEE_ -12.6 -12 -4.75 V VNN_ + 220 V High-Side Supply Voltage VPP_ 0 Low-Side Supply Voltage VNN_ -200 0 V 0 +220 V VPP_ - VNN_ Supply Voltage SUPPLY CURRENT (Single Channel) VINN_/VINP_ = 0 , VSHDN = 0 VDD Supply Current IDD VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz 1 100 200 VEN_ = VDD, VSHDN = VDD, CH1 and CH2 130 200 VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz, VCC_ = 5V, VDD = 3V, only one channel switching 15 VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz, VCC_ = 12V, VDD = 3V, only one channel switching 36 VSHDN = 0, CH1 and CH2 VCC_ Supply Current 2 ICC_ 1 A A mA _______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers (VDD = +2.7V to +6V, VCC_ = +4.75V to +12.6V, VEE_ = -12.6V to -4.75V, VNN_ = -200V to 0, VPP_ = 0 to (VNN_ + 200V), VSS the lower of VNN1 or VNN2, TA = TJ = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 3) (See Figures 8, 9, and 10.) PARAMETER VEE_ Supply Current SYMBOL IEE_ CONDITIONS MIN TYP 25 VEN_ = VDD, VSHDN = VDD, CH1 and CH2 1 VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz, VEE_ = -5V, only one channel switching 200 VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz, VEE_ = -12V, only one channel switching 200 VSHDN = 0, CH1 and CH2 VPP_ Supply Current IPP_ 1 VEN_ = VDD, VSHDN = VDD, CH1 and CH2 90 VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz, VPP_ = +5V, VNN_ = -5V, no load, only one channel switching 9 A A 0.6 VSHDN = 0, CH1 and CH2 INN_ 160 UNITS mA VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VPP_ = +80V, VNN_ = -80V, pulse repetition frequency = 10kHz, f = 10MHz, 4 periods, no load, only one channel switching VNN_ Supply Current MAX VSHDN = 0, CH1 and CH2 1 VEN_ = VDD, VSHDN = VDD, CH1 and CH2 40 VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VINN_ = VINP_, f = 5MHz, VNN_ = -5V, VPP_ = +5V, no load, only one channel switching 9 80 A mA VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD, VPP_ = +80V, VNN_ = -80V, pulse repetition frequency = 10kHz, f = 10MHz, 4 periods, no load, only one channel switching 0.6 LOGIC INPUTS (EN_, SHDN, INN_, INP_, INC_) Low-Level Input Voltage VIL High-Level Input Voltage VIH Logic-Input Capacitance CIN Logic-Input Leakage IIN 0.25 x VDD 0.75 x VDD V V 5 VIN = 0 or VDD pF 1 A OUTPUT (OUT_) No load at OUT_ OUT_ Output-Voltage Range Low-Side Small-Signal Output Impedance VOUT_ ROLS VNN_ VPP_ Unprotected outputs (see the Ordering Information/Selector Guide), 100mA load VNN_ + 1.5 VPP_ 1.5 Protected outputs (see the Ordering Information/Selector Guide), 100mA load VNN_ + 2.5 VPP_ 2.5 IOP_ = -100mA, VCC_ = +12V 5%, DC-coupled 9 17 IOP_ = -100mA, VCC_ = +5V 5%, DC-coupled 9.5 18 V _______________________________________________________________________________________ 3 MAX4810/MAX4811/MAX4812 ELECTRICAL CHARACTERISTICS (continued) MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +6V, VCC_ = +4.75V to +12.6V, VEE_ = -12.6V to -4.75V, VNN_ = -200V to 0, VPP_ = 0 to (VNN_ + 200V), VSS the lower of VNN1 or VNN2, TA = TJ = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 3) (See Figures 8, 9, and 10.) PARAMETER High-Side Small-Signal Output Impedance SYMBOL ROHS TYP MAX IOP_ = -100mA, VCC_ = +12V 5%, DC-coupled CONDITIONS MIN 10.5 17 IOP_ = -100mA, VCC_ = +5V 5%, DC-coupled 12 18 UNITS Low-Side Output Current IOL VCC_ = +12V 5%, VOUT_ - VNN_ = 100V 1.3 A High-Side Output Current IOH VCC_ = +12V 5%, VOUT_ - VPP_ = 100V 1.3 A Off-Output Capacitance Off-Output Leakage Current Low-Side Signal-Clamp Output Impedance High-Side Signal-Clamp Output Impedance Low-Side Gate Short Impedance High-Side Gate Short Impedance CO(OFF) ILK RCLS RCHS OP_, ON_, OCP_ and OCN_ connected together, VPP_ = +100V, VNN_ = -100V MAX4810 45 MAX4811 75 pF VNN_ = -100V, VPP_ = 100V, EN_ = 0, OUT = -100V to +100V -1 +1 IOCN_ = -100mA, DC-coupled, VCC_ = +12V 5%, VEE_ = -VCC_ 22 IOCN_ = -100mA, DC-coupled, VCC_ = +5V 5%, VEE_ = -VCC_ 24 65 IOCP_ = -100mA, DC-coupled, VCC_ = +12V 5%, VEE_ = -VCC_ 28 50 IOCP_ = -100mA, DC-coupled, VCC_ = +5V 5%, VEE_ = -VCC_ 38 VCC_ = +12V 5%, VEE_ = -VCC_, ICGN = 10mA, EN_ = VDD 5 7.5 VCC_ = +12V 5%, VEE_ = -VCC_, ICGN = 10mA, EN_ = 0 RHSH VCC_ = +12V 5%, VEE_ = -VCC_, ICGN = 10mA, EN_ = VDD 50 VCC_ = +12V 5%, VEE_ = -VCC_, ICGN = 10mA, EN_ = 0 RLSH A 5 7.5 65 100 10 k 100 10 k THERMAL SHUTDOWN Thermal Shutdown TSHDN Junction temperature rising Thermal-Shutdown Hysteresis 150 C 20 C DYNAMIC CHARACTERISTICS (RL = 100, CL = 100pF, unless otherwise noted) Logic Input to Output Rise Propagation Delay tPLH VCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 4 15 ns Logic Input to Output Fall Propagation Delay tPHL VCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 4 15 ns Logic Input to Output Rise Propagation Delay tPOH VCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 4 15 ns Logic Input to Output Fall Propagation Delay tPOL VCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 4 15 ns Logic Input to Output-Rise Propagation Delay Clamp tPLO VCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 4 15 ns 4 _______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers (VDD = +2.7V to +6V, VCC_ = +4.75V to +12.6V, VEE_ = -12.6V to -4.75V, VNN_ = -200V to 0, VPP_ = 0 to (VNN_ + 200V), VSS the lower of VNN1 or VNN2, TA = TJ = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 3) (See Figures 8, 9, and 10.) SYMBOL CONDITIONS Logic Input to Output-Fall Propagation Delay Clamp PARAMETER tPHO VCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 4 15 OUT_ Rise Time (GND to VPP_) tR0P VPP_ = +100V, VNN_ = -100V, VCC_ = +12V 5%, VEE_ = -VCC_, Figure 4 9 20 ns OUT_ Rise Time (VNN_ to GND) tRN0 VPP_ = +100V, VNN_ = -100V, VCC_ = +12V 5%, VEE_ = -VCC_, Figure 4 17 35 ns OUT_ Rise Time (VNN_ to VPP_) tRNP VPP_ = +100V, VNN_ = -100V, VCC_ = +12V 5%, VEE_ = -VCC_, Figure 4 10.5 35 ns OUT_ Fall Time (GND to VNN_) tF0N VPP_ = +100V, VNN_ = -100V, VCC_ = +12V 5%, VEE_ = -VCC_, Figure 4 9 20 ns OUT_ Fall Time (VPP_ to GND) tFP0 VPP_ = +100V, VNN_ = -100V, VCC_ = +12V 5%, VEE_ = -VCC_, Figure 4 17 35 ns OUT_ Fall Time (VPP_ to VNN_) tFPN VPP_ = +100V, VNN_ = -100V, VCC_ = +12V 5%, VEE_ = -VCC_, Figure 4 10.5 35 ns OUT Enable Time from EN (Figure 5) tEN OUT Disable Time from EN (Figure 5) tDI Clamp Enable Time from INC (Figure 6) tEN-CL Clamp Disable Time from INC (Figure 6) tDI-CL Short Enable Time from EN (Figure 7) Short Disable Time from EN (Figure 7) tEN_SH tDI_SH 2nd Harmonic Distortion RMS Output Jitter 2HD tJ TYP MAX UNITS ns VCC_ = +12V 5%, VEE_ = -VCC_ 100 VCC_ = +5V 5%, VEE_ = -VCC_ 150 VCC_ = +12V 5%, VEE_ = -VCC_ 100 VCC_ = +5V 5%, VEE_ = -VCC_ 150 VCC_ = +12V 5%, VEE_ = -VCC_ 150 VCC_ = +5V 5%, VEE_ = -VCC_ 180 VCC_ = +12V 5%, VEE_ = -VCC_ 150 VCC_ = +5V 5%, VEE_ = -VCC_ 150 VPP_ = 12V, VNN_ = 0, VCC_ = +12V 5%, VEE_ = -VCC_ 1000 VPP_ = 5V, VNN_ = 0, VCC_ = +5V 5%, VEE_ = -VCC_ 1000 VPP_ = 12V, VNN_ = 0, VCC_ = +12V 5%, VEE_ = -VCC_ 250 VPP_ = 5V, VNN_ = 0, VCC_ = +5V 5%, VEE_ = -VCC_ 250 INP_ to INN_ Overlap Tolerance Crosstalk MIN ns ns ns ns ns ns |3| ns VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, f = 5MHz 69 dB VPP_ = VNN_ = 100V, fOUT = 5MHz, VCC_ = 12V -48 dB 9 ps VCC_ = 12V Note 3: Specifications are guaranteed for the stated global conditions, unless otherwise noted and are 100% production tested at TA = +25C and TA = +70C. Specifications at TA = 0C are guaranteed by design. Note 4: 100% production tested at TA = +25C. Specifications over temperature are guaranteed by design. _______________________________________________________________________________________ 5 MAX4810/MAX4811/MAX4812 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = +3.3V, VCC_ = +12V, VEE_ = -12V, VSS = -100V, VPP_ = +100V, VNN_ = -100V, fOUT = 5MHz, TA = +25C, unless otherwise noted.) 0.46 0.44 0.38 20 15 0.36 0.32 0.30 0 3 5 7 9 11 13 1 15 2 3 4 9 10 0 8 6 20 30 40 50 60 4 PULSES, PRF = 10kHz 0.72 18 16 0.60 0.56 8 6 0.48 4 0.44 2 0 1 3 5 7 9 11 13 1 15 MAX4810/11/12 toc07 10 6 IPP (mA) 0.64 0.60 0.56 0.80 5 4 0.48 0.44 1 0.44 0.40 0 TEMPERATURE (C) 70 9 10 13 15 4 PULSES, PRF = 10kHz 0.56 0.52 60 8 0.60 2 50 7 0.64 0.48 40 6 0.68 3 30 5 0.72 0.52 20 4 0.76 INN (mA) 8 7 10 3 INN vs. OUTPUT FREQUENCY CONTINUOUS SWITCHING, fOUT = 2.5MHz, VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, VDD = +3.3V, NO LOAD 9 0.68 0 2 FREQUENCY (MHz) IPP vs. TEMPERATURE 0.72 70 10 0.52 IPP vs. TEMPERATURE 4 PULSES AT 10MHz, PRF = 10kHz 60 12 FREQUENCY (MHz) 0.76 50 14 0.64 TEMPERATURE (C) 0.80 40 CONTINUOUS SWITCHING, VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, VDD = +3.3V, NO LOAD 20 0.68 70 30 IPP vs. OUTPUT FREQUENCY MAX4810/11/12 toc08 10 20 22 0.40 5 0 10 TEMPERATURE (C) IPP (mA) 9 7 6 8 0.76 IPP (mA) ICC (mA) 0.80 MAX4810/11/12 toc04 CONTINUOUS SWITCHING, fOUT = 2.5MHz, VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, VDD = +3.3V, NO LOAD 10 7 IPP vs. OUTPUT FREQUENCY ICC vs. TEMPERATURE 11 6 FREQUENCY (MHz) FREQUENCY (MHz) 12 5 MAX4810/11/12 toc05 1 0.38 0.34 5 0.30 0.40 0.36 10 0.34 0.32 0.42 MAX4810/11/12 toc06 0.40 ICC (A) 25 ICC (mA) ICC (mA) 0.44 0.42 MAX4810/11/12 toc03 30 4 PULSES AT 10MHz, PRF = 10kHz 0.48 MAX4810/11/12 toc09 0.46 CONTINUOUS SWITCHING, VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, VDD = +3.3V, NO LOAD 35 0.50 MAX4810/11/12 toc02 40 MAX4810/11/12 toc01 4 PULSES, PRF = 10kHz 0.48 ICC vs. TEMPERATURE ICC vs. OUTPUT FREQUENCY ICC vs. OUTPUT FREQUENCY 0.50 IPP (mA) MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers 0.40 0 10 20 30 40 50 TEMPERATURE (C) 60 70 1 3 5 7 9 11 FREQUENCY (MHz) _______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers 0.72 INN (mA) 12 10 7 0.64 6 0.60 4 0.56 6 0.52 3 4 0.48 2 2 0.44 1 0 0.40 2 3 4 5 6 7 8 9 10 0 0 10 20 30 40 50 60 0 70 10 20 30 40 50 60 70 TEMPERATURE (C) TEMPERATURE (C) OUT RISE TIME (GND TO VPP_) vs. VCC_/VEE_ SUPPLY VOLTAGE OUT FALL TIME (GND TO VNN_) vs. VCC_/VEE_ SUPPLY VOLTAGE INP-TO-OUT RISE PROPAGATION DELAY vs. VCC_/VEE_ SUPPLY VOLTAGE RL = 100, CL = 100pF 20 22 18 16 20 RL = 100, CL = 100pF 18 16 MAX4810/11/12 toc14 FREQUENCY (MHz) 22 tFON (ns) 12 10 tPLH (ns) 14 14 12 10 8 8 6 6 4 4 2 2 0 0 22 21 20 19 18 17 16 15 14 13 12 11 10 RL = 100, CL = 100pF +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 VCC_/VEE_ SUPPLY VOLTAGE (V) INP-TO-OUT RISE PROPAGATION DELAY vs. TEMPERATURE INP-TO-OUT FALL PROPAGATION DELAY vs. VCC_/VEE_ SUPPLY VOLTAGE INP-TO-OUT FALL PROPAGATION DELAY vs. TEMPERATURE RL = 100, CL = 100pF 18 16 14 tPHL (ns) 12 10 8 6 4 2 22 21 20 19 18 17 16 15 14 13 12 RL = 100, CL = 100pF 0 10 20 30 40 50 TEMPERATURE (C) 60 70 RL = 100, CL = 100pF 18 16 14 12 10 8 6 4 2 11 10 0 20 tPHL (ns) 20 MAX4810/11/12 toc18 +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 VCC_/VEE_ SUPPLY VOLTAGE (V) MAX4810/11/12 toc16 +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 VCC_/VEE_ SUPPLY VOLTAGE (V) MAX4810/11/12 toc17 tROP (ns) 5 8 1 tPLH (ns) 8 0.68 MAX4810/11/12 toc13 INN (mA) 14 CONTINUOUS SWITCHING, fOUT = 2.5MHz, VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, VDD = +3.3V, NO LOAD 9 MAX4810/11/12 toc15 16 4 PULSES AT 10MHz, PRF = 10kHz 0.76 INN (mA) 18 10 MAX4810/11/12 toc11 MAX4810/11/12 toc10 CONTINUOUS SWITCHING, VPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V, VDD = +3.3V, NO LOAD 20 INN vs. TEMPERATURE INN vs. TEMPERATURE 0.80 MAX4810/11/12 toc12 INN vs. OUTPUT FREQUENCY 22 0 +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 VCC_/VEE_ SUPPLY VOLTAGE (V) 0 10 20 30 40 50 60 70 TEMPERATURE (C) _______________________________________________________________________________________ 7 MAX4810/MAX4811/MAX4812 Typical Operating Characteristics (continued) (VDD = +3.3V, VCC_ = +12V, VEE_ = -12V, VSS = -100V, VPP_ = +100V, VNN_ = -100V, fOUT = 5MHz, TA = +25C, unless otherwise noted.) Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers MAX4810/MAX4811/MAX4812 Pin Description PIN 8 NAME FUNCTION 1 CGP1 Channel 1 High-Side Gate Input. Connect a 1nF to 10nF capacitor between CDP1 and CGP1 as close as possible to the device. 2,3 VPP1 Channel 1 High-Side Positive Supply Voltage Input. Bypass VPP1 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 4, 10, 33, 39 N.C. No Connection. Not connected internally. 5 OP1 Channel 1 High-Side Drain Output 6 OCP1 Channel 1 High-Side Clamp Output 7, 15, 28, 36, 44, 55 GND Ground 8 OCN1 Channel 1 Low-Side Clamp Output 9 ON1 Channel 1 Low-Side Drain Output 11, 12 VNN1 Channel 1 High-Side Negative Supply Voltage Input. Bypass VNN1 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 13 CGN1 Channel 1 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between CDN1 and CGN1 as close as possible to the device. 14 CDN1 Channel 1 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between CDN1 and CGN1 as close as possible to the device. 16, 54 VCC1 Channel 1 Gate-Drive Supply Voltage Input. Bypass VCC1 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 17 INN1 Channel 1 Low-Side Logic Input (Table 1) 18 INC1 Channel 1 Clamp Logic Input. Clamps OCP1 and OCN1 are turned on when INC1 is high and when INP1 and INN1 are low (see Table 1). 19 INP1 Channel 1 High-Side Logic Input (Table 1) 20 EN1 Channel 1 Enable Logic Input. Drive EN1 high to enable OP1 and ON1. Pull EN1 low to turn on the gatesource short circuit (see Table 1). 21 SHDN 22 AGND Shutdown Logic Input (Table 1) Analog Ground. Must be connected to common GND. 23 EN2 Channel 2 Enable Logic Input. Drive EN2 high to enable OP2 and ON2. Pull EN2 low to turn on the gatesource short circuit. See Table 1. 24 INP2 Channel 2 High-Side Logic Input (Table 1) 25 INC2 Channel 2 Clamp Logic Input. Clamps OCP2 and OCN2 are turned on when INC2 is high and when INP2 and INN2 are low. See Table 1. 26 INN2 Channel 2 Low-Side Logic Input (Table 1) 27, 45 VCC2 Channel 2 Gate-Drive Supply Voltage Input. Bypass VCC2 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 29 CDN2 Channel 2 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between CDN2 and CGN2 as close as possible to the device. 30 CGN2 Channel 2 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between CDN2 and CGN2 as close as possible to the device. _______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers PIN NAME FUNCTION 31, 32 VNN2 Channel 2 High-Side Negative Supply Voltage Input. Bypass VNN2 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 34 ON2 Channel 2 Low-Side Drain Output 35 OCN2 Channel 2 Low-Side Clamp Output 37 OCP2 Channel 2 High-Side Clamp Output 38 OP2 Channel 2 High-Side Drain Output 40, 41 VPP2 Channel 2 High-Side Supply Voltage Input. Bypass VPP2 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 42 CGP2 Channel 2 High-Side Gate Input. Connect a 1nF to 10nF capacitor between CDP2 and CGP2 as close as possible to the device. 43 CDP2 Channel 2 High-Side Driver Output. Connect a 1nF to 10nF capacitor between CDP2 and CGP2 as close as possible to the device. 46 CGC2 Channel 2 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between CDC2 and CGC2 as close as possible to the device. 47 CDC2 Channel 2 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between CDC2 and CGC2 as close as possible to the device. 48 VEE2 Channel 2 Negative Supply Input. |VEE2| VCC2. Gate Drive Supply Voltage for the OCP clamp. Bypass VEE2 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 49 VDD Logic Supply Voltage Input. Bypass VDD to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 50 VSS Substrate Voltage. Connect VSS to a voltage equal to or more negative than the more negative of VNN1 or VNN2. 51 VEE1 Channel 1 Negative Supply Input. |VEE1| VCC1. Gate Drive Supply Voltage for the OCP clamp. Bypass VEE1 to GND with a 0.1F as close as possible to the device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing may be required. 52 CDC1 Channel 1 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between CDC1 and CGC1 as close as possible to the device. 53 CGC1 Channel 1 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between CDC1 and CGC1 as close as possible to the device. 56 CDP1 Channel 1 High-Side Driver Output. Connect a 1nF to 10nF capacitor between CDP1 and CGP1 as close as possible to the device. -- EP Exposed Pad. EP must be connected to VSS. Do not use EP as the only VSS connection for the device. Detailed Description The MAX4810/MAX4811/MAX4812 are dual high-voltage, high-speed pulsers that can be independently configured for either unipolar or bipolar pulse outputs. These devices have independent logic inputs for full pulse control and independent active clamps. The clamp input, INC_, can be set high to activate the clamp automatically when the device is not pulsing to the positive or negative high-voltage supplies. Logic Inputs (INP_, INN_, INC_, EN_, SHDN) The MAX4810/MAX4811/MAX4812 have a total of nine logic input signals. SHDN controls power-up and powerdown of the device. There are two sets of INP_, INN_, INC_, and EN_ signals: one for each channel. INP_ _______________________________________________________________________________________ 9 MAX4810/MAX4811/MAX4812 Pin Description (continued) MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers Table 1. Truth Table INPUTS OUTPUTS SDHN EN_ 0 X X X 0 X X 1 0 1 INP_ INN_ INC_ OCP_, OCN_ STATE OP_ ON_ 0 High impedance High impedance X 1 High impedance High impedance X X 0 High impedance High impedance 0 X X 1 High impedance High impedance 1 1 0 0 0 High impedance High impedance 1 1 0 0 1 High impedance High impedance 1 1 0 1 X High impedance VNN_ High Powered up, all inputs enabled, gate-source short impedance disabled 1 1 1 0 X VPP_ High impedance High Powered up, all inputs enabled, gate-source short impedance disabled 1 1 1 1 X VPP_ VNN_ High Powered down, INP_/INN_ disabled, gate-source impedance short disabled GND Powered down, INP_/INN_ disabled, gate-source short disabled High Powered up, INP_/INN_ disabled, gate-source short impedance enabled GND Powered up, INP_/INN_ disabled, gate-source short enabled High Powered up, all inputs enabled, gate-source short impedance disabled GND Powered up, all inputs enabled, gate-source short disabled High Not allowed (3ns maximum overlap) impedance X = Don't care. 0 = Logic-low. 1 = Logic-high. controls the on and off states of the high side FET, INN_ controls the on and off states of the low side FET, INC_ controls the active clamp and EN_ controls the gate to source short. These signals give complete control of the output stage of each driver (see Table 1 for all logic combinations). The MAX4810/MAX4811/MAX4812 logic inputs are CMOS logic compatible and the logic level are referenced to VDD for maximum flexibility. The low 5pF (typ) input capacitance of the logic inputs reduces loading and increases switching speed. High-Voltage Output Protection (MAX4811 Only) The high-voltage outputs of the MAX4811 feature an integrated overvoltage protection circuit that allows the user to implement multilevel pulsing by connecting the outputs of multiple pulser channels in parallel. Internal diodes in series with the ON_ and OP_ outputs prevent the body diode of the high-side and low-side FETs from switching on when a voltage greater than VNN_ or VPP_ is present on the output. See Figure 2. 10 Active Clamps The MAX4810/MAX4811/MAX4812 feature an active clamp circuit to improve pulse quality and reduce 2nd harmonic output. The clamp circuit consists of an Nchannel (DC-coupled) and a P-channel (AC and DC delay coupled) high-voltage FETs that are switched on or off by the logic clamp input (INC_). The MAX4810/ MAX4811 feature protected clamp devices, allowing the clamp circuit to be used in bipolar pulsing circuits (see Figures 1 and 2). A diode in series with the OCN_ output prevents the body diode of the low-side FET from turning on when a voltage lower than GND is present. Another diode in series with the OCP_ output prevents the body diode of the high-side FET from turning on when a voltage higher than ground is present. The MAX4812 does not have diode protection on the clamp outputs. Thus, the device is suitable for use in circuits where only unipolar pulsing is required. The user can connect the active clamp input (INC_) to a logic-high voltage and drive only the INP_ and INN_ inputs to minimize the number of signals used to drive the ______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers PVNN_) must be kept below the maximum power-dissipation limit. See the Typical Operating Characteristics section for more information on typical supply currents versus switching frequencies. Power-Supply Ramping and Gate-Source Short Circuit The device consumes most of the supply current from VCC_ supply to charge and discharge internal nodes such as the gate capacitance of the high-side FET (CP) and the low-side FET (CN). Neglecting the small quiescent supply current and a small amount of current used to charge and discharge the capacitances at the internal gate clamp FETs, the power consumption can be estimated as follows: The MAX4810/MAX4811/MAX4812 include a gatesource short circuit that is controlled by the enable input (EN_). When SHDN is high and EN is low, a 60 switch shorts together the gate and source of the high-side output FET. At the same time, a similar switch shorts the gate and source of the low-side output FET (Table 1). The gate-source short circuit prevents accidental turnon of the output FETs due to the ramping voltage on VPP_ and VNN_, and allows for faster ramping rates and smaller delay times between pulsing modes. Shutdown Mode SHDN is common to both channel 1 and channel 2 and powers up or down the device. Drive SHDN low to power down all internal circuits (except the clamp circuits). When SHDN is low, the device is in the lowest power state (1A) and the gate-source short circuit is disabled. The device takes 1s (typ) to become active when SHDN is disabled. Thermal Protection A thermal shutdown circuit with a typical threshold of +150C prevents damage due to excessive power dissipation. When the junction temperature exceeds TJ = +150C, all outputs are disabled. Normal operation typically resumes after the IC's junction temperature drops below +130C. Applications Information AC-Coupling Capacitor Selection The value of all AC-coupling capacitors (between CDP_ and CGP, and between CDN_ and CGN_) should be between 1nF to 10nF. The voltage rating of the capacitor should be at least as high as VPP_. The capacitors should be placed as close as possible to the device. Because INP_ and part of INC_ are AC-coupled to the output devices, they cannot be driven high indefinitely when the device is active. Power Dissipation The power dissipation of the MAX4810/MAX4811/ MAX4812 consists of three major components caused by the current consumption from VCC_, VPP_, and VNN_. The sum of these components (P VCC_ , P VPP_ and ( ) ( ) PVCC = CN x VCC _ 2 x fIN + CP x VCC _ 2 x fIN x (BRF x BTD) fIN = fINN + fINP Where fINN and fINP are the switching frequency of the inputs INN, INP respectively, and where BRF is the burst repitition frequency and BTD is the burst time duration. The typical value of the gate capacitances of the power FET are CN = 0.2nF, CP = 0.4nF. For an output load that has a resistance of R L and capacitance of CL, the MAX4810/MAX4811/MAX4812 power dissipation can be estimated as follows (assume square wave output and neglect the resistance of the switches): 2 1 2 V PVPP = (CO + CL ) x fIN x ( VPP _ - VNN _ ) + PP _ x x (BRF x BTD) RL 2 where CO is the output capacitance of the device. Power Supplies and Bypassing The MAX4810/MAX4811/MAX4812 operate from independent supply voltage sets (only VDD and VSS are common to both channels). The logic input circuit operates from a +2.7V to +6V single supply (V DD ). The level-shift driver dual supplies, VCC_/VEE_ operate from 4.75V to 12.6V. The VPP_/VNN_ high-side and low-side supplies are driven from a single positive supply up to +220V, from a single negative supply up to -200V, or from 110V dual supplies. Either VPP_ or VNN_ can be set at 0. Bypass each supply input to ground with a 0.1F capacitor as close as possible to the device. Depending on the load of the input, additional bypassing may be needed to keep the output of VNN_ and VPP_ stable during output transitions. For example, with ______________________________________________________________________________________ 11 MAX4810/MAX4811/MAX4812 device. In this case, whenever both the INP_ and INN_ inputs are low and the INC_ input is high, the active clamp circuit pulls the output to GND through the OCP_ and OCN_ outputs (see Table 1 for more information). MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers VDD VCC_ CDP_ CGP_ VPP_ VDD VCC_ LEVEL SHIFTER INP_ CDP_ CGP_ OP_ VSS GND_ VDD LEVEL SHIFTER INC_ VEE_ CDC_ CGC_ OCP_ SHDN VSS SHORT CIRCUIT EN_ MAX4810 VSS VDD VSS OCN_ VCC_ LEVEL SHIFTER GND VSS VDD ON_ VCC_ CGN_ LEVEL SHIFTER INN_ CDN_ VNN_ GND VEE_ CDC_ CGC_ CDN_ CGN_ Figure 1. MAX4810 Simplified Functional Diagram for One Channel COUT = 100pF and ROUT = 100 load, additional 10F (typ) capacitor is recommended. VSS is the substrate voltage and must be connected to a voltage equal to or more negative than the more negative voltage of VNN1 or VNN2. Exposed Pad and Layout Concerns The MAX4810/MAX4811/MAX4812 provide an exposed pad (EP) underneath the TQFN package for improved thermal performance. EP is internally connected to VSS. Connect EP to VSS externally and do not run traces 12 under the package to avoid possible short circuits. To aid heat dissipation, connect EP to a similarly sized pad on the component side of the PCB. This pad should be connected through to the solder-side copper by several plated holes to a large heat spreading copper area to conduct heat away from the device. The MAX4810/MAX4811/MAX4812 high-speed pulsers require low-inductance bypass capacitors to their supply inputs. High-speed PCB trace design practices are recommended. Pay particular attention to minimize ______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers VCC_ CDP_ MAX4810/MAX4811/MAX4812 VDD CGP_ VPP_ VDD VCC_ LEVEL SHIFTER INP_ CDP_ CGP_ OP_ VSS GND_ VDD LEVEL SHIFTER INC_ VEE_ CDC_ CGC_ OCP_ SHDN VSS SHORT CIRCUIT EN_ MAX4811 VSS VSS VDD OCN_ VCC_ LEVEL SHIFTER GND VSS VDD ON_ VCC_ CGN_ LEVEL SHIFTER INN_ CDN_ VNN_ GND VEE_ CDC_ CGC_ CDN_ CGN_ Figure 2. MAX4811 Simplified Functional Diagram for One Channel trace lengths and use sufficient trace width to reduce inductance. Use of surface-mount components is recommended. Supply Sequencing VSS must be lower than or equal to the more negative voltage of VNN1 or VNN2 at all times. No other powersupply sequencing is required for the MAX4810/ MAX4811/MAX4812. Typical Application Circuits Figures 8, 9, and 10 show typical applications for the MAX4810/MAX4811/MAX4812. Figure 8 shows the MAX4810 used in a bipolar pulsing connection. Figure 9 shows the MAX4811 in a five-level pulsing application, and Figure 10 shows the MAX4812 used in a unipolar application. ______________________________________________________________________________________ 13 MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers VDD VCC_ CDP_ CGP_ VPP_ VDD VCC_ LEVEL SHIFTER INP_ CDP_ CGP_ OP_ VSS GND_ VDD LEVEL SHIFTER INC_ VEE_ CDC_ CGC_ OCP_ SHDN VSS SHORT CIRCUIT EN_ MAX4812 VSS VDD VSS OCN_ VCC_ LEVEL SHIFTER GND VSS VDD ON_ VCC_ CGN_ LEVEL SHIFTER INN_ CDN_ VNN_ GND VEE_ CDC_ CGC_ CDN_ CGN_ Figure 3. MAX4812 Simplified Functional Diagram for One Channel 14 ______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers MAX4810/MAX4811/MAX4812 tFPN 90% 90% 10% VPP_ 10% tFON OUT_ tRNO 90% 10% 10% tROP 90% tFPO 90% 10% tPOH INP_ tPHO 50% GND 10% VNN_ tRNP 50% 50% 50% tPLH tPHL tPOL tPLO VDD 50% INN_ 50% 50% 50% GND INC_ = HIGH Figure 4. Detailed Timing (RL = 100, CL = 100pF) OUT_ (INP_ = HIGH) GND 10% OUT_ (INN_ = HIGH) 10% tDI EN 50% tEN 50% INC_ = HIGH Figure 5. Enable Timing (RL = 100, CL = 100pF) ______________________________________________________________________________________ 15 MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers OUT_ (VPP_) 1k PULLUP RESISTOR TO VPP_ GND 10% 10% 1k PULLDOWN RESISTOR TO VNN_ 10% OUT_ (VNN_) tEN-CL tDI-CL INC_ Figure 6. Active Clamp Timing +12V 90% CGN_ GND 10% 10% GND CGP_ -12V tDI-SH EN 10% tEN-SH 50% 1k PULLUP RESISTOR BETWEEN CGN_ AND +12V. 1k PULLDOWN RESISTOR BETWEEN CGP_ AND -12V. Figure 7. Short-Circuit Timing 16 ______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers MAX4810/MAX4811/MAX4812 -100V -12V +3V -12V +12V +12V GND CDP2 VCC2 CGC2 VEE2 CDC2 VSS VDD VEE1 CDC1 CGC1 GND CGP2 42 VPP1 VPP2 41 3 VPP1 VPP2 40 4 N.C. N.C. 39 5 OP1 OP2 38 6 OCP1 OCP2 37 7 GND 8 OCN1 9 ON1 GND 36 MAX4810 +100V OUT2 OCN2 35 ON2 34 -100V GND VCC2 INN2 INC2 CDN2 29 INP2 CGN2 30 14 CDN1 EN2 13 CGN1 AGND VNN2 31 SHDN 12 VNN1 EN1 VNN2 32 INP1 N.C. 33 11 VNN1 INC1 10 N.C. GND -100V CGP1 2 INN1 OUT1 1 VCC1 +100V VCC1 CDP1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 +12V VDD VDD +12V Figure 8. MAX4810: Dual Bipolar Pulsing, 100V, GND ______________________________________________________________________________________ 17 MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers -100V -12V +3V -12V +12V +12V GND CDP2 VCC2 CGC2 VEE2 CDC2 VSS VDD VEE1 CDC1 CGC1 GND VPP1 VPP2 41 3 VPP1 VPP2 40 4 N.C. N.C. 39 5 OP1 OP2 38 6 OCP1 OCP2 37 7 GND 8 OCN1 9 ON1 GND 36 MAX4811 +100V OUT1 OCN2 35 ON2 34 -100V GND VCC2 INN2 INC2 CDN2 29 INP2 CGN2 30 14 CDN1 EN2 13 CGN1 AGND VNN2 31 SHDN 12 VNN1 EN1 VNN2 32 INP1 N.C. 33 11 VNN1 INC1 10 N.C. GND -100V CGP1 2 INN1 OUT1 CGP2 42 1 VCC1 +100V VCC1 CDP1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 +12V +12V Figure 9. MAX4811: Five-Level Pulsing, 100V, 50V, GND 18 ______________________________________________________________________________________ Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers MAX4810/MAX4811/MAX4812 +3V +12V GND CDP2 VCC2 CGC2 VEE2 CDC2 VSS VDD VEE1 CDC1 CGC1 GND CDP1 CAC CGP2 42 1 CGP1 2 VPP1 VPP2 41 3 VPP1 VPP2 40 4 N.C. N.C. 39 5 OP1 OP2 38 6 OCP1 OCP2 37 7 GND GND 36 8 OCN1 9 ON1 MAX4812 +100V CPP OUT2 OCN2 35 ON2 34 10 N.C. N.C. 33 11 VNN1 VNN2 32 GND VCC2 INN2 INC2 INP2 EN2 AGND SHDN EN1 CDN2 29 INP1 14 CDN1 INC1 CGN2 30 INN1 VNN2 31 13 CGN1 VCC1 12 VNN1 GND OUT1 VCC1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 CAC +100V CPP +12V 15 16 17 18 19 20 21 22 23 24 25 26 27 28 +12V +12V Figure 10. MAX4812: Dual Unipolar Pulsing, +100V, GND ______________________________________________________________________________________ 19 MAX4810/MAX4811/MAX4812 Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 56 TQFN T5677-1 21-0144 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.