LTC2368-18
1
236818f
18-Bit, 1Msps, Pseudo-
Differential Unipolar SAR
ADC with 97dB SNR
TYPICAL APPLICATION
FEATURES DESCRIPTION
The LTC
®
2368-18 is a low noise, low power, high speed
18-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2368-18 has a 0V
to VREF pseudo-differential unipolar input range with VREF
ranging from 2.5V to 5.1V. The LTC2368-18 consumes
only 13.5mW and achieves ±2.5LSB INL maximum, no
missing codes at 18 bits with 97dB SNR.
The LTC2368-18 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic while
also featuring a daisy-chain mode. The fast 1Msps through-
put with no cycle latency makes the LTC2368-18 ideally
suited for a wide variety of high speed applications. An
internal oscillator sets the conversion time, easing external
timing considerations. The LTC2368-18 automatically pow-
ers down between conversions, leading to reduced power
dissipation that scales with the sampling rate.
32k Point FFT fS = 1Msps, fIN = 2kHz
APPLICATIONS
n 1Msps Throughput Rate
n ±2.5LSB INL (Max)
n Guaranteed 18-Bit No Missing Codes
n Low Power: 13.5mW at 1Msps, 13.5µW at 1ksps
n 97dB SNR (Typ) at fIN = 2kHz
n –120dB THD (Typ) at fIN = 2kHz
n Guaranteed Operation to 125°C
n 2.5V Supply
n Pseudo-Differential Unipolar Input Range: 0V to VREF
n VREF Input Range from 2.5V to 5.1V
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7705765.
10Ω
VREF
0V
10nF
–
+
SAMPLE CLOCK
236818 TA01a
10µF 0.1µF
2.5V
REF
1.8V TO 5V
2.5V TO 5.1V 47µF
(X5R, 0805 SIZE)
REF GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
LTC2368-18
LT®6202
VDD OVDD
IN+
IN–
FREQUENCY (kHz)
0 100 200 300 400 500
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
236818 TA01b
SNR = 97.2dB
THD = –120dB
SINAD = 97.1dB
SFDR = 120dB
LTC2368-18
2
236818f
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF) ................................................. 6V
Analog Input Voltage (Note 3)
IN+, IN– .........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
TOP VIEW
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2368CMS-18#PBF LTC2368CMS-18#TRPBF 236818 16-Lead Plastic MSOP 0°C to 70°C
LTC2368IMS-18#PBF LTC2368IMS-18#TRPBF 236818 16-Lead Plastic MSOP –40°C to 85°C
LTC2368HMS-18#PBF LTC2368HMS-18#TRPBF 236818 16-Lead Plastic MSOP –40°C to 125°C
LTC2368CDE-18#PBF LTC2368CDE-18#TRPBF 23688 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2368IDE-18#PBF LTC2368IDE-18#TRPBF 23688 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2368C ................................................ 0°C to 70°C
LTC2368I .............................................–40°C to 85°C
LTC2368H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
LTC2368-18
3
236818f
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2kHz, VREF = 5V l93.8 97 dB
fIN = 2kHz, VREF = 5V, (H-Grade) l93.3 97 dB
SNR Signal-to-Noise Ratio fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
l
94.3
88.5
97
91.5
dB
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l
l
93.8
88
97
91.5
dB
dB
THD Total Harmonic Distortion fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
l
–120
–116
–103
–103
dB
dB
SFDR Spurious Free Dynamic Range fIN = 2kHz, VREF = 5V l104 120 dB
–3dB Input Bandwidth 34 MHz
Aperture Delay 500 ps
Aperture Jitter 4 ps
Transient Response Full-Scale Step 460 ns
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (IN+) (Note 5) l–0.1 VREF + 0.1 V
VIN– Absolute Input Range (IN–) (Note 5) l–0.1 0.1 V
VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN–l0 VREF V
IIN Analog Input Leakage Current l±1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
45
5
pF
pF
CMRR Input Common Mode Rejection Ratio fIN = 500kHz 80 dB
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
CONVERTER CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l18 Bits
No Missing Codes l18 Bits
Transition Noise 1.3 LSBRMS
INL Integral Linearity Error (Note 6) l–2.5 ±0.5 2.5 LSB
DNL Differential Linearity Error l–0.5 ±0.1 0.5 LSB
ZSE Zero-Scale Error (Note 7) l–11 0 11 LSB
Zero-Scale Error Drift 0.02 LSB/°C
FSE Full-Scale Error (Note 7) l–50 ±7 50 LSB
Full-Scale Error Drift ±0.15 ppm/°C
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2368-18
4
236818f
ADC TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l1 Msps
tCONV Conversion Time l460 527 ns
tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 10) l460 ns
tCYC Time Between Conversions l1 µs
tCNVH CNV High Time l20 ns
tBUSYLH CNV↑ to BUSY Delay CL = 20pF l13 ns
tCNVL Minimum Low Time for CNV (Note 11) l20 ns
tQUIET SCK Quiet Time from CNV↑(Note 10) l20 ns
tSCK SCK Period (Notes 11, 12) l10 ns
tSCKH SCK High Time l4 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l2.375 2.5 2.625 V
OVDD Supply Voltage l1.71 5.25 V
IVDD
IOVDD
IPD
IPD
Supply Current
Supply Current
Power Down Mode
Power Down Mode
1Msps Sample Rate
1Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
l
l
l
5.4
0.7
0.9
0.9
6.3
90
140
mA
mA
µA
µA
PDPower Dissipation
Power Down Mode
Power Down Mode
1Msps Sample Rate
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
13.5
2.25
2.25
15.8
225
315
mW
µW
µW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
REFERENCE INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Reference Voltage (Note 5) l2.5 5.1 V
IREF Reference Input Current (Note 9) l0.5 0.7 mA
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IO = –500µA lOVDD – 0.2 V
VOL Low Level Output Voltage IO = 500µA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 µA
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2368-18
5
236818f
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCKL SCK Low Time l4 ns
tSSDISCK SDI Setup Time From SCK↑(Note 11) l4 ns
tHSDISCK SDI Hold Time From SCK↑(Note 11) l1 ns
tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l13.5 ns
tDSDO SDO Data Valid Delay from SCK↑CL = 20pF (Note 11) l9.5 ns
tHSDO SDO Data Remains Valid Delay from SCK↑CL = 20pF (Note 10) l1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓CL = 20pF (Note 10) l5 ns
tEN Bus Enable Time After RDL↓(Note 11) l16 ns
tDIS Bus Relinquish Time After RDL↑ (Note 11) l13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and
00 0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: fSMPL = 1MHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
Figure 1. Voltage Levels for Timing Specifications
0.8*OVDD
0.2*OVDD
50% 50%
236818 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
LTC2368-18
6
236818f
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT fS = 1Msps,
fIN = 2kHz SNR, SINAD vs Input Frequency
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input level,
fIN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V,
fSMPL = 1Msps, unless otherwise noted.
OUTPUT CODE
0 65536 131072 196608 262144
–2.0
INL ERROR (LSB)
0.0
0.5
1.0
1.5
–0.5
–1.0
–1.5
2.0
236818 G01
OUTPUT CODE
–0.5
DNL ERROR (LSB)
0.4
0.3
0.2
0.1
0.0
–0.4
–0.3
–0.2
–0.1
0.5
236818 G02
0 65536 131072 196608 262144
FREQUENCY (kHz)
0 100 200 300 400 500
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
236818 G04
SNR = 97.2dB
THD = –120dB
SINAD = 97.1dB
SFDR = 120dB
FREQUENCY (kHz)
0
70
SNR, SINAD (dBFS)
75
80
85
90
50 100 150 200
236818 G05
95
100
SNR
25 75 125 175
SINAD
FREQUENCY (kHz)
0
–160
HARMONICS, THD (dBFS)
–150
–130
–120
–110
–60
THD
2ND
3RD
–90
50 100 125
236818 G06
–140
–80
–70
–100
25 75 150 175 200
INPUT LEVEL (dB)
–40
95.0
SNR, SINAD (dBFS)
95.5
96.0
96.5
97.0
97.5 SNR
SINAD
98.0
–30 –20 –10 0
236818 G07
REFERENCE VOLTAGE (V)
2.5
95
96
98
97
SNR
SINAD
4.5
236818 G08
94
93
3 3.5 4 5
92
91
90
SNR, SINAD (dBFS)
REFERENCE VOLTAGE (V)
2.5
HARMONICS, THD (dBFS)
–120
–110
THD
3RD
–100
4.5
236818 G09
–130
–140
–125
–115
–105
–135
–145
–150 33.5 45
2ND
CODE
COUNTS
25000
30000
35000
236818 G03
15000
0131067 131069 131071 131073 131075 131077
40000
σ = 1.3
20000
10000
5000
LTC2368-18
7
236818f
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature
Shutdown Current vs Temperature CMRR vs Input Frequency
Reference Current
vs Reference Voltage
INL/DNL vs Temperature
Full-Scale Error vs Temperature Offset Error vs Temperature
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V,
fSMPL = 1Msps, unless otherwise noted.
TEMPERATURE (°C)
–55
SNR, SINAD (dBFS)
97.0
97.5
98.0
105
236818 G10
96.5
96.0
95.0 –15 25 65
–35 125
545 85
95.5
99.0
98.5
SNR
SINAD
TEMPERATURE (°C)
–55
–145
HARMONICS, THD (dBFS)
–140
–130
–125
–120
–110
–35 45 85
236818 G11
–135
–115
25 125
–15 565 105
2ND
3RD
THD
TEMPERATURE (°C)
–55
–1.0
INL/DNL ERROR (LSB)
–0.5
0
0.5
1.0
–35 –15 5 25
236818 G12
45 65 85 105 125
MAX INL
MAX DNL
MIN DNL
MIN INL
TEMPERATURE (°C)
–55
POWER SUPPLY CURRENT (mA)
4
5
6
105
236818 G15
3
2
0–15 25 65
–35 125
545 85
1
IVDD
IREF IOVDD
TEMPERATURE (°C)
POWER-DOWN CURRENT (µA)
45
40
35
30
236818 G16
0
5
10
15
20
25
–55 –35 –15 5 25 45 65 85 105 125
IVDD + IOVDD + IREF
FREQUENCY (kHz)
0 100 200 300 500400
70
CMRR (dB)
85
80
75
100
95
90
236818 G17
REFERENCE VOLTAGE (V)
2.5
0
REFERENCE CURRENT (mA)
0.1
0.3
0.4
0.6
0.5
3.5 4.5 5
236818 G18
0.2
3 4
TEMPERATURE (°C)
–55
–20
FULL-SCALE ERROR (LSB)
–10
10
20
–15 25 45 125
236818 G13
0
–15
5
15
–5
–35 5 65 85 105
TEMPERATURE (°C)
–55
–10
OFFSET ERROR (LSB)
–8
–4
–2
0
–15 25 45 125
236818 G14
–6
–35 5 65 85 105
10
2
4
6
8
LTC2368-18
8
236818f
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2368-18 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2368-18 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by OVDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+ (Pin 4): Analog Input. IN+ operates differential with
respect to IN– with an IN+-IN– range of 0V to VREF.
IN– (Pin 5): Analog Ground Sense. IN– has an input range
of ±100mV with respect to GND and must be tied to the
ground plane or a remote ground sense.
REF (Pins 7, 8): Reference Inputs. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47µF ceramic capacitor
(X5R, 0805 size).
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result
or daisy-chain data is output on this pin on each rising
edge of SCK MSB first. The output data is in straight binary
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17, DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
PIN FUNCTIONS
LTC2368-18
9
236818f
FUNCTIONAL BLOCK DIAGRAM
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
REF = 5V
IN+
VDD = 2.5V
OVDD = 1.8V to 5V
IN–
CHAIN
CNV
GND
BUSY
SDO
SCK
RDL/SDI
CONTROL LOGIC
18-BIT SAMPLING ADC SPI
PORT
+
–
236818 BD
POWER-DOWN AND ACQUIRE
CONVERT
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
SCK
CNV
CHAIN, RDL/SDI = 0
BUSY
236818 TD01
LTC2368-18
10
236818f
OVERVIEW
The LTC2368-18 is a low noise, low power, high speed 18-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2368-18 supports a
0V to VREF pseudo-differential unipolar input range with
VREF ranging from 2.5V to 5.1V, making it ideal for high
performance applications which require a wide dynamic
range. The LTC2368-18 achieves ±2.5LSB INL max, no
missing codes at 18 bits and 97dB SNR.
Fast 1Msps throughput with no cycle latency makes the
LTC2368-18 ideally suited for a wide variety of high speed
applications. An internal oscillator sets the conversion time,
easing external timing considerations. The LTC2368-18 dis-
sipates only 13.5mW at 1Msps, while an auto power-down
feature is provided to further reduce power dissipation
during inactive periods.
CONVERTER OPERATION
The LTC2368-18 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins to
sample the pseudo-differential analog input voltage. A ris-
ing edge on the CNV pin initiates a conversion. During the
conversion phase, the 18-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/262144)
using the differential comparator. At the end of conver-
sion, the CDAC output approximates the sampled analog
input. The ADC control logic then prepares the 18-bit
digital output code for serial transfer.
TRANSFER FUNCTION
The LTC2368-18 digitizes the full-scale voltage of REF
into 218 levels, resulting in an LSB size of 19µV with
REF = 5V. The ideal transfer function is shown in Figure2.
The output data is in straight binary format.
APPLICATIONS INFORMATION
Figure 2. LTC2368-18 Transfer Function
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2368-18
ANALOG INPUT
The analog inputs of the LTC2368-18 are pseudo-differential
in order to reduce any unwanted signal that is common
to both inputs. The analog inputs can be modeled by the
equivalent circuit shown in Figure 3. The diodes at the input
provide ESD protection. In the acquisition phase, each
input sees approximately 45pF (CIN) from the sampling
CDAC in series with 40Ω (RON) from the on-resistance
of the sampling switch. The IN+ input draws a current
spike while charging the CIN capacitor during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
INPUT VOLTAGE (V)
0V
OUTPUT CODE
236818 F02
111...111
111...110
111...101
111...100
000...001
000...000
000...010
000...011
1
LSB
UNIPOLAR
ZERO
FS – 1LSB
1LSB = FS/262144
RON
40Ω
CIN
45pF
RON
40Ω
REF
REF
CIN
45pF
IN+
IN–
BIAS
VOLTAGE
236818 F03
LTC2368-18
11
236818f
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance input of the LTC2368-18 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC input
draws a current spike when entering acquisition.
For best performance, a buffer amplifier should be used
to drive the analog input of the LTC2368-18. The ampli-
fier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC input draws.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Pseudo-Differential Unipolar Inputs
For most applications, we recommend the low power
LT6202 ADC driver to drive the LTC2368-18. With a low
noise density of 1.9nV/√Hz and a low supply current of
3mA, the LT6202 is flexible and may be configured to
convert signals of various amplitudes to the 0V to 5V input
range of the LTC2368-18.
To achieve the full distortion performance of the
LTC2368-18, a low distortion single-ended signal source
driven through the LT6202 configured as a unity-gain buf-
fer as shown in Figure 4 can be used to get the full data
sheet THD specification of –120dB.
The LT6202 can also be used to buffer and convert large
true bipolar signals which swing below ground to the 0V
to 5V input range of the LTC2368-18. Figure 5a shows the
LT6202 being used to convert a ±10V true bipolar signal
for use by the LTC2368-18. In this case, the LT6202 is
configured as an inverting amplifier stage, which acts to
attenuate and level shift the input signal to the 0V to 5V input
range of the LTC2368-18. In the inverting configuration, the
single-ended input signal source no longer directly drives
a high impedance input. The input impedance is instead
set by resistor RIN. RIN must be chosen carefully based on
the source impedance of the signal source. Higher values
of RIN tend to degrade both the noise and distortion of
the LT6202 and LTC2368-18 as a system. Table 1 shows
the resulting SNR and THD for several values of RIN, R1,
R2, R3 and R4 in this configuration. Figure 5b shows the
resulting FFT when using the LT6202 as shown in Figure 5a.
Figure 4. Input Signal Chain
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noise contribution of the buffer and to help minimize distur-
bances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
10Ω
10nF
66nF
50Ω LPF2
LPF1
BW = 1.6MHz
BW = 48kHz LTC2368-18
IN+
IN–
236818 F04
–
+
LT6202
V
REF
0V
LTC2368-18
12
236818f
Table 1. SNR, THD vs RIN for ±10V Input Signal
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k 499 499 2k 402 96.9 –99.3
10k 2.49k 2.49k 10k 2k 96.8 –94
100k 24.9k 24.9k 100k 20k 94.8 –93.8
APPLICATIONS INFORMATION
ADC REFERENCE
The LTC2368-18 requires an external reference to define
its input range. A low noise, low temperature drift refer-
ence is critical to achieving the full datasheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and
high accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2368-18. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2368-18 up to 125°C. We recommend bypassing the
LTC6655-5 with a 47µF ceramic capacitor (X5R, 0805 size)
close to the REF pin.
The REF pin of the LTC2368-18 draws charge (QCONV) from
the 47µF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
IREF = QCONV/tCYC. The DC current draw of the REF pin,
IREF, depends on the sampling rate and output code. If
the LTC2368-18 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSBs.
When idling, the REF pin on the LTC2368-18 draws only
a small leakage current (< 1µA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 6, IREF quickly goes from approximately
0µA to a maximum of 0.7mA at 1Msps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the refer-
ence output voltage will affect the accuracy of the output
Figure 6. CNV Waveform Showing Burst Sampling
Figure 5a. LT6202 Converting a ±10V Bipolar Signal
to a 0V to 5V Input Signal
Figure 5b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
–
+
1
3
4
LT6202
R4
402Ω
R1
499Ω
RIN
2k
R3
2k
R2
499Ω
10µF
10V
–10V
0V
200pF
200pF
VCM = VREF/2
5V
0V
236818 F05a
FREQUENCY (kHz)
0
AMPLITUDE (dBFS)
–80
–60
–40
236818 F05b
–100
–120
–180
–160
200 400100 300 500
–140
0
–20 SNR = 96.9dB
THD = –99.3dB
SINAD = 93.9dB
SFDR = 99.8dB
CNV
IDLE
PERIOD
IDLE
PERIOD
236818 F06
LTC2368-18
13
236818f
APPLICATIONS INFORMATION
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-5 refer-
ence is also recommended.
In applications where power management is critical and
the external reference may be powered down, it is rec-
ommended that REF is kept greater than 2V in order to
guarantee a maximum shutdown current of 140µA. In such
applications, a Schottky diode can be placed between REF
and VDD, as shown in Figure 7.
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 8 shows
that the LTC2368-18 achieves a typical SNR of 97.2dB at
a 1MHz sampling rate with a 2kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD=20log V22+V32+V42+…+ VN
2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2368-18 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2368-18 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Figure 8. 32k Point FFT with fIN = 2kHz of the LTC2368-18
REF
236818 F07
LTC2368-18
VDD
Figure 7. A Schottky Diode Between REF and VDD Maintains
REF > 2V for Applications Where the Reference May Be
Powered Down
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2368-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 8 shows that the LTC2368-18 achieves
a typical SINAD of 97.1dB at a 1MHz sampling rate with
a 2kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
FREQUENCY (kHz)
0 100 200 300 400 500
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
236818 F08
SNR = 97.2dB
THD = –120dB
SINAD = 97.1dB
SFDR = 120dB
LTC2368-18
14
236818f
APPLICATIONS INFORMATION
Power Supply Sequencing
The LTC2368-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2368-18
has a power-on-reset (POR) circuit that will reset the
LTC2368-18 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2368-18 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up the
LTC2368-18. Once a conversion has been initiated, it cannot
be restarted until the conversion is complete. For optimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2368-18 powers down and begins acquiring the
input signal.
Internal Conversion Clock
The LTC2368-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 527ns. With a min-
imum acquisition time of 460ns, throughput performance
of 1Msps is guaranteed without any external adjustments.
Auto Power-Down
The LTC2368-18 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2368-18 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2368-18 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 9.
DIGITAL INTERFACE
The LTC2368-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2368-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
100MHz, a 1Msps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2368-18 is simple and
straightforward to use. The following sections describe the
operation of the LTC2368-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
Figure 9. Power Supply Current of the LTC2368-18
Versus Sampling Rate
SAMPLING RATE (kHz)
1
0
POWER SUPPLY CURRENT (mA)
1
2
3
4
5
6
200 400 600 800
IVDD
IREF
IOVDD
236818 F09
1000
LTC2368-18
15
236818f
TIMING DIAGRAMS
Normal Mode, Single Device
When CHAIN = 0, the LTC2368-18 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven.
Figure 10 shows a single LTC2368-18 operated in normal
mode with CHAIN and RDL/SDI tied to ground. With
RDL/SDI grounded, SDO is enabled and the MSB(D17) of
the new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2368-18.
Figure 10. Using a Single LTC2368-18 in Normal Mode
236818 F10
CONVERT CONVERT
tACQ
tACQ = tCYC – tCONV – tBUSYLH
POWER-DOWN AND ACQUIRE
POWER-DOWN
AND ACQUIRE
CNV
CHAIN = 0
BUSY
SCK
SDO
RDL/SDI = 0
tBUSYLH
tDSDOBUSYL
tSCK
tHSDO
tSCKH tQUIET
tSCKL
tDSDO
tCONV
tCNVH
tCYC
tCNVL
D17 D16 D15 D1 D0
1 2 3 16 17 18
CNV
LTC2368-18
BUSY
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
SDO
SCK
RDL/SDI
CHAIN
LTC2368-18
16
236818f
TIMING DIAGRAMS
Figure 11. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
Normal Mode, Multiple Devices
Figure 11 shows multiple LTC2368-18 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2368-18 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 11,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
236818 F11
D17A
SDO
SCK
CNV
BUSY
CHAIN = 0
RDL/SDIB
RDL/SDIA
D17BD16BD1BD0B
D15B
D16AD15AD1AD0A
Hi-Z Hi-ZHi-Z
tEN
tHSDO
tDSDO tDIS
tSCKL
tSCKH
tCNVL
1 2 3 16 17 18 19 20 21 34 35 36
tSCK
CONVERT
CONVERT
tQUIET
tCONV
tBUSYLH
POWER-DOWN AND ACQUIRE
POWER-DOWN
AND ACQUIRE
RDLB
RDLA
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2368-18 SDO
A
SCK
RDL/SDI
CNV
LTC2368-18 SDO
B
SCK
RDL/SDI
CHAIN BUSY
CHAIN
LTC2368-18
17
236818f
TIMING DIAGRAMS
Chain Mode, Multiple Devices
When CHAIN = OVDD, the LTC2368-18 operates in
chain mode. In chain mode, SDO is always enabled and
RDL/SDI serves as the serial data input pin (SDI) where
daisy-chain data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 12 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 18 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
Figure 12. Chain Mode Timing Diagram
236818 F12
D0A
D1A
D16A
D17A
D15B
D16B
D17B
SDOB
SDOA = RDL/SDIB
RDL/SDIA = 0
D0B
D1B
D15A
D16A
D17AD0A
D1A
1 2 3 16 17 18 19 20 34 35 36
tDSDOBUSYL
tSSDISCK
tHSDISCK
tBUSYLH
tCONV
tHSDO
tDSDO
tSCKL
tSCKH
tSCKCH
tCNVL
tCYC
CONVERT
CONVERT
SCK
CNV
BUSY
CHAIN = OVDD
tQUIET
POWER-DOWN AND ACQUIRE
POWER-DOWN
AND ACQUIRE
OVDD
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2368-18
BUSY
SDO
B
SCK
RDL/SDI
CNV
LTC2368-18
SDO
A
SCK
RDL/SDI
CHAIN
OVDD
CHAIN
LTC2368-18
18
236818f
BOARD LAYOUT
To obtain the best performance from the LTC2368-18
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital clocks
or signals alongside analog signals or underneath the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1813A, the
evaluation kit for the LTC2368-18.
Partial Top Silkscreen
LTC2368-18
19
236818f
BOARD LAYOUT
Partial Layer 1 Component Side
Partial Layer 2 Ground Plane
LTC2368-18
20
236818f
BOARD LAYOUT
Partial Layer 3 PWR Plane
Partial Layer 4 Bottom Layer
LTC2368-18
21
236818f
BOARD LAYOUT
Partial Schematic of Demoboard
U6
NC7SZ66P5X
C13
0.1µF
4
12
9
CNV
SCK
C20
47µF
6.3V
0805
C56
0.1µF
CNV
REF
GND
GND
GND
GND
REF
VDD
VREF
0.8VREF
OVDD
SCK
SDO
BUSY
RDL/SDI
SDO
BUSY
RD
LTC2368-18
IN–
IN+
5
413
14
11
12
B A
5
3
GND
VCC
OE
+3.3V
R5
49.9Ω
1206
R6
1k
U8
NC7SZ04P5X
U2
NC7SVU04P5X
U20
LTC6655AHMS8-5
U3
NL17SZ74
U4
NC7SVU04P5X
CNVST_33
FROM CPLD
CLK
TO CPLD
C5
0.1µF
C1
0.1µF
C11
0.1µF
SHDN
GND
GND
OUT_F
GND
GND
9V TO 10V 1
2
3
4
8
7
6
5
+3.3V +3.3V +3.3V
3
42
5
3
42
5
C2
0.1µF
R3
33Ω
R2
1k
R1
33Ω
+3.3V
+3.3V
3
1
4
6
2
8
7
5
R8
33Ω
C3
0.1µF
R4
33Ω
C4
0.1µF
VIN OUT_S GND VCC
CLR\
Q\
CP
Q
D
PR\
3
4 2
5
+3.3V
DC590 DETECT
TO CPLD
+3.3V
C58
OPT
U9
NC7SZ04P5X C15
0.1µF
C16
0.1µF
3
42
5
+3.3V
R13
1k
R17
2k
R10
4.99k
U7
24LC025-I/ST R11
4.99k
R12
4.99k
C14
0.1µF
6
8
4
236818 BL
5
7
3
2
1
SCL
SDA
ARRAY
EEPROM
WP
A2
A1
A0
VSS
VCC
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J3
DC590
SDO
SCK
CNV
9V TO
10V
R7
1k
10
16
6
3
1
15
7
2
8
JP6
FS
1
2
3
HD1X3-100
OPT
C7
0.1µF
C6
10µF
6.3V
+2.5V
C10
0.1µF
C39
0.01µF
NPO
C65
OPT
0805 NPO
R38
OPT
R58
ØΩ
R35
OPT
R45
ØΩ
C40
OPT
NPO
C9
10µF
6.3V
R16
0Ω
R32
10Ω
OUT1
V+
V–
V+
4
1
–IN1
+IN13
5
2
R19
0Ω
R46
ØΩ
R31
OPT
U15
LT6202CS5
R32
0Ω
C42
15pF
C55
1µF V+
V–
C57
0.1µF
R9
OPT
C61
10µF
6.3V
C63
10µF
6.3V
C43
0.1µF
R15
OPT
C18
OPT
C17
10µF
JP2
CM
E7
EXT_CM
1
+2.5V
2
3
VREF/2
EXT
HD1X3-100
C8
1µF
C46
1µF
R40
OPT
R39
0Ω
1
2
3
COUPLING
AC DC
JP1
HD1X3-100
C44
1µF
C49
OPT
C48
10µF
6.3V
C47
OPT
R41
OPT
C59
1µF
C60
0.1µF
1
2
3
JP5
HD1X3-100
COUPLING
AC DC
DB16
DB17
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
CLKOUT
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J2
CON-EDGE 40-100
CLKIN
J1
J4
J8
R14
0Ω
AIN+
AIN–
–
+
LTC2368-18
22
236818f
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ± 0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ± 0.05
0.45 BSC
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2368-18
23
236818f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MSOP (MS16) 1107 REV Ø
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
0.1016 ± 0.0508
(.004 ± .002)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.280 ± 0.076
(.011 ± .003)
REF
4.90 ± 0.152
(.193 ± .006)
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2368-18
24
236818f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012
LT 0112 • PRINTED IN USA
1
5
2
3
LTC2368-18
IN+REF VDD
2.5V
IN–
10nF
47µF
10Ω
R4
402Ω
R1
499Ω
RIN
2k
R3
2k
R2
3k
10µF
200pF
8V
5V
LT6202
V+
V–
–3V
236818 TA02
VOUT_S
VOUT_F
VIN LTC6655-5
5V
0V
4–
+
220pF
10V
–10V
0V
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2379-18/LTC2378-18
LTC2377-18/LTC2376-18
18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low
Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range,
DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16
Packages
LTC2380-16/LTC2378-16
LTC2377-16/LTC2376-16
16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low
Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range,
DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16
Packages
LTC2383-16/LTC2382-16/
LTC2381-16
16-Bit, 1Msps/500ksps/250ksps Serial, Low Power ADC 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin-
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2393-16/LTC2392-16/
LTC2391-16
16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, Pin-
Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages
LTC2365 12-Bit, 1Msps Serial ADC 2.35V to 3.6V Supply, 6- and 8-Lead TSOT-23 Packages
LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC 3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package
DACS
LTC2757 18-Bit, Single Parallel IOUT SoftSpan™ DAC ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm
LQFP-48 Package
LTC2641 16-Bit/14-Bit/12-Bit Single Serial VOUT DACs ±1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output
LTC2630 12-Bit/10-Bit/8-Bit Single VOUT DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
References
LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT6202/LT6203 Single/Dual 100MHz Rail-to-Rail Input/Output Noise Low
Power Amplifiers
1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth
LT6200/LT6200-5/
LT6200-10
165MHz/800MHz/1.6GHz Op Amp with
Unity Gain/AV = 5/AV = 10
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at
1MHz, TSOT23-6 Package
RELATED PARTS
TYPICAL APPLICATION
LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal Into the LTC2368-18
